RISC-V: Add testcases for unsigned .SAT_ADD vector form 7

RISC-V: Add testcases for unsigned .SAT_ADD vector form 7

After the middle-end support the form 7 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 7.

Form 7:
  #define DEF_VEC_SAT_U_ADD_FMT_7(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_add_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        out[i] = (T)(x + y) < x ? -1 : (x + y);                        \
      }                                                                \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
	macro for testing.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-25.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-26.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-27.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-28.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>