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(parent: 0c6f7cd) | patch
x86: Only align destination to 1x VEC_SIZE in memset 4x loop
authorNoah Goldstein <goldstein.w.n@gmail.com>
Wed, 1 Nov 2023 20:30:26 +0000 (15:30 -0500)
committerSunil K Pandey <skpgkp2@gmail.com>
Fri, 10 Jan 2025 05:25:24 +0000 (21:25 -0800)
commitf0c2fcce5f3b2776a6da7b1274463b60d2b9a655
tree2b993548edef1ff425059076cea39dc1ecb57e89tree
parent0c6f7cd550a1852a8828d773623fc6256c6afcc4commit | diff
x86: Only align destination to 1x VEC_SIZE in memset 4x loop

Current code aligns to 2x VEC_SIZE. Aligning to 2x has no affect on
performance other than potentially resulting in an additional
iteration of the loop.
1x maintains aligned stores (the only reason to align in this case)
and doesn't incur any unnecessary loop iterations.
Reviewed-by: Sunil K Pandey <skpgkp2@gmail.com>
(cherry picked from commit 9469261cf1924d350feeec64d2c80cafbbdcdd4d)
sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S diff | blob | blame | history
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