]> git.ipfire.org Git - thirdparty/qemu.git/commit
trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
authorDaniel Henrique Barboza <dbarboza@ventanamicro.com>
Tue, 16 Apr 2024 23:04:37 +0000 (20:04 -0300)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 3 Jun 2024 01:12:12 +0000 (11:12 +1000)
commitf15af01740efb95d1dccdac763011dcba144c1fe
tree0461373696f8d4258b78477b6a4f9a115ea6ea38
parent0099f6053410f5611796213b723e908cfc8055eb
trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint

Privileged spec section 4.1.9 mentions:

"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)

If stval is written with a nonzero value when a breakpoint,
address-misaligned, access-fault, or page-fault exception occurs on an
instruction fetch, load, or store, then stval will contain the faulting
virtual address."

A similar text is found for mtval in section 3.1.16.

Setting mtval/stval in this scenario is optional, but some softwares read
these regs when handling ebreaks.

Write 'badaddr' in all ebreak breakpoints to write the appropriate
'tval' during riscv_do_cpu_interrrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn_trans/trans_privileged.c.inc