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(parent: 704bc36) | patch
drm/amdgpu: Use correct gfx deferred error count
authorXiang Liu <xiang.liu@amd.com>
Fri, 21 Mar 2025 12:47:23 +0000 (20:47 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 26 Mar 2025 21:44:27 +0000 (17:44 -0400)
commitf3f05a0ec584855c53f2d95024e23259f3ee101d
treeb5ff3f79915614f0b1721332d92fb312263da20atree
parent704bc361e3a4ead1c0eb40acc255b636b788dc89commit | diff
drm/amdgpu: Use correct gfx deferred error count

In the case of parsing GFX deferred error from SMU corrected error
channel, the error count should be set to 1 instead of parsing from
MISC0 register, which is 0.

Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c diff | blob | blame | history
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