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sve: Fix fcmuo combine patterns [PR106524]
authorTamar Christina <tamar.christina@arm.com>
Fri, 12 Aug 2022 11:28:41 +0000 (12:28 +0100)
committerTamar Christina <tamar.christina@arm.com>
Fri, 12 Aug 2022 11:28:41 +0000 (12:28 +0100)
commitf4ff20d464f90c85919ce2e7fa63e204dcda4e40
tree179246fd5aa1757653a451341bcea38cdf3d0198tree | snapshot
parent7e3b45befdbbf1a1f9ff728fa2bac31b4756907ccommit | diff
sve: Fix fcmuo combine patterns [PR106524]

There's no encoding for fcmuo with zero.  This restricts the combine patterns
from accepting zero registers.

gcc/ChangeLog:

PR target/106524
* config/aarch64/aarch64-sve.md (*fcmuo<mode>_nor_combine,
*fcmuo<mode>_bic_combine): Don't accept comparisons against zero.

gcc/testsuite/ChangeLog:

PR target/106524
* gcc.target/aarch64/sve/pr106524.c: New test.
gcc/config/aarch64/aarch64-sve.md diff | blob | blame | history
gcc/testsuite/gcc.target/aarch64/sve/pr106524.c [new file with mode: 0644] blob
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