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(parent: b925965) | patch
net: xilinx_axienet.c: Add phy soft reset bit clearing
authorNathan Rossi <nathan.rossi@xilinx.com>
Wed, 9 Apr 2014 01:52:39 +0000 (18:52 -0700)
committerStefan Hajnoczi <stefanha@redhat.com>
Fri, 25 Apr 2014 11:40:10 +0000 (13:40 +0200)
commitf663faac3e2e9d9134415f75d429ae30432e6038
tree74af6becd3675ca3f88aad100c07244da59600e7tree | snapshot
parentb925965294e8cf370a922ca0504c21877e748e70commit | diff
net: xilinx_axienet.c: Add phy soft reset bit clearing

Clear the BMCR Reset when writing to registers.

Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
[ PC:
 * Trivial style fixes to commit message
]
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
hw/net/xilinx_axienet.c diff | blob | blame | history
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