mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115611]

mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115611]

This patch fixes the backend pattern that was printing the wrong input
scalar register pair when inserting into lane 1.

Added a new test to force float-abi=hard so we can use scan-assembler to check
correct codegen.

gcc/ChangeLog:

	PR target/115611
	* config/arm/mve.md (mve_vec_setv2di_internal): Fix printing of input
	scalar register pair when lane = 1.

gcc/testsuite/ChangeLog:

	* gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c: New test.

(cherry picked from commit 7c11fdd2cc11a7058e9643b6abf27831970ad2c9)