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(parent: 321f211) | patch
target-mips: fix DSP loads with rd = 0
authorAurelien Jarno <aurelien@aurel32.net>
Tue, 1 Jan 2013 17:02:22 +0000 (18:02 +0100)
committerAurelien Jarno <aurelien@aurel32.net>
Thu, 31 Jan 2013 22:29:27 +0000 (23:29 +0100)
commitf7d2072e25d3592acec4657dae8862facf298e9f
tree7d799c17404cbb21d8c7cc292e0ba825b6afbe49tree | snapshot
parent321f211707822b4c87f0bb89e4f46586fff43163commit | diff
target-mips: fix DSP loads with rd = 0

When rd is 0, which still need to do the actually load to possibly
generate a TLB exception.

Reviewed-by: Eric Johnson <ericj@mips.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips/translate.c diff | blob | blame | history
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