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target/mips/mxu: Add D32SARL D32SARW instructions
authorSiarhei Volkau <lis8215@gmail.com>
Thu, 8 Jun 2023 10:42:13 +0000 (13:42 +0300)
committerPhilippe Mathieu-Daudé <philmd@linaro.org>
Mon, 10 Jul 2023 21:33:38 +0000 (23:33 +0200)
commitf900da7691db16b534d5b4abcab2fdb29673aaa9
tree17d5e605e6d7fad63f0c28781d4e18b28e0164d5tree | snapshot
parent5925963476d65ce1a74651bbf48865977ff0c1b0commit | diff
target/mips/mxu: Add D32SARL D32SARW instructions

These instructions are dual 32-bit arithmetic shift right and
pack LSBs to 2x 16-bit into a MXU register.
The difference is the shift amount source: immediate or GP reg.

Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-25-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
target/mips/tcg/mxu_translate.c diff | blob | blame | history
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