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(parent: 68db9a3) | patch
[riscv] Add support for the RISC-V CPU architecture 1307/head
authorMichael Brown <mcb30@ipxe.org>
Sun, 15 Sep 2024 09:54:04 +0000 (10:54 +0100)
committerMichael Brown <mcb30@ipxe.org>
Sun, 15 Sep 2024 21:34:10 +0000 (22:34 +0100)
commitc215048ddaac75969c22c018871295a5748a47e8
tree1e47dce485579135c16c130778a810aaeb912d9ctree
parent68db9a3cb3d73aae83ee4b7a0cbe9c69d7f32482commit | diff
[riscv] Add support for the RISC-V CPU architecture

Add support for building iPXE as a 64-bit or 32-bit RISC-V binary, for
either UEFI or Linux userspace platforms.  For example:

  # RISC-V 64-bit UEFI
  make CROSS=riscv64-linux-gnu- bin-riscv64-efi/ipxe.efi

  # RISC-V 32-bit UEFI
  make CROSS=riscv64-linux-gnu- bin-riscv32-efi/ipxe.efi

  # RISC-V 64-bit Linux
  make CROSS=riscv64-linux-gnu- bin-riscv64-linux/tests.linux
  qemu-riscv64 -L /usr/riscv64-linux-gnu/sys-root \
               ./bin-riscv64-linux/tests.linux

  # RISC-V 32-bit Linux
  make CROSS=riscv64-linux-gnu- SYSROOT=/usr/riscv32-linux-gnu/sys-root \
       bin-riscv32-linux/tests.linux
  qemu-riscv32 -L /usr/riscv32-linux-gnu/sys-root \
               ./bin-riscv32-linux/tests.linux

Signed-off-by: Michael Brown <mcb30@ipxe.org>
42 files changed:
src/arch/riscv/Makefile [new file with mode: 0644] blob
src/arch/riscv/Makefile.efi [new file with mode: 0644] blob
src/arch/riscv/Makefile.linux [new file with mode: 0644] blob
src/arch/riscv/core/riscv_bigint.c [new file with mode: 0644] blob
src/arch/riscv/core/riscv_io.c [new file with mode: 0644] blob
src/arch/riscv/core/riscv_string.c [new file with mode: 0644] blob
src/arch/riscv/core/riscv_strings.S [new file with mode: 0644] blob
src/arch/riscv/core/setjmp.S [new file with mode: 0644] blob
src/arch/riscv/include/bits/bigint.h [new file with mode: 0644] blob
src/arch/riscv/include/bits/bitops.h [new file with mode: 0644] blob
src/arch/riscv/include/bits/byteswap.h [new file with mode: 0644] blob
src/arch/riscv/include/bits/compiler.h [new file with mode: 0644] blob
src/arch/riscv/include/bits/endian.h [new file with mode: 0644] blob
src/arch/riscv/include/bits/errfile.h [new file with mode: 0644] blob
src/arch/riscv/include/bits/io.h [new file with mode: 0644] blob
src/arch/riscv/include/bits/nap.h [new file with mode: 0644] blob
src/arch/riscv/include/bits/setjmp.h [new file with mode: 0644] blob
src/arch/riscv/include/bits/stdint.h [new file with mode: 0644] blob
src/arch/riscv/include/bits/string.h [new file with mode: 0644] blob
src/arch/riscv/include/bits/strings.h [new file with mode: 0644] blob
src/arch/riscv/include/ipxe/riscv_io.h [new file with mode: 0644] blob
src/arch/riscv32/Makefile [new file with mode: 0644] blob
src/arch/riscv32/Makefile.efi [new file with mode: 0644] blob
src/arch/riscv32/Makefile.linux [new file with mode: 0644] blob
src/arch/riscv32/core/riscv32_byteswap.S [new file with mode: 0644] blob
src/arch/riscv32/include/bits/profile.h [new file with mode: 0644] blob
src/arch/riscv32/include/ipxe/efi/dhcparch.h [new file with mode: 0644] blob
src/arch/riscv32/include/limits.h [new file with mode: 0644] blob
src/arch/riscv32/libgcc/llshift.S [new file with mode: 0644] blob
src/arch/riscv64/Makefile [new file with mode: 0644] blob
src/arch/riscv64/Makefile.efi [new file with mode: 0644] blob
src/arch/riscv64/Makefile.linux [new file with mode: 0644] blob
src/arch/riscv64/core/riscv64_byteswap.S [new file with mode: 0644] blob
src/arch/riscv64/include/bits/profile.h [new file with mode: 0644] blob
src/arch/riscv64/include/ipxe/efi/dhcparch.h [new file with mode: 0644] blob
src/arch/riscv64/include/limits.h [new file with mode: 0644] blob
src/config/defaults/efi.h diff | blob | blame | history
src/include/ipxe/efi/ProcessorBind.h diff | blob | blame | history
src/include/ipxe/efi/RiscV64/ProcessorBind.h [new file with mode: 0644] blob
src/util/efirom.c diff | blob | blame | history
src/util/elf2efi.c diff | blob | blame | history
src/util/genfsimg diff | blob | blame | history
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