realtek: dsa: rtl931x: Fix port L2 table flushing

realtek: dsa: rtl931x: Fix port L2 table flushing

The DSA driver must flush the HW FDB when a port changes from
learning/forwarding to disabled/blocking/listening.

But the implementation for RTL931x was writing the port information
starting at bit 11 (bit 11 of the second 32-bit L2_TBL_FLUSH_CTRL
register). But this offset is the AGG_VID and not the port. The actual
position is 43 (bit 11 of the first register).

As result, the FDB was always only flushed for the port 0 and not for the
selected port.

Fixes: 9ed609705481 ("realtek: Add HW support for RTL931X for PIE, L2 and STP aging")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20422
Signed-off-by: Robert Marko <robimarko@gmail.com>