aarch64: fp8 convert and scale - Add advsimd insn variants

aarch64: fp8 convert and scale - Add advsimd insn variants

Add the advanced SIMD variant of the FP8 convert and scale
instructions, enabled at assembly-time using the `+fp8'
architectural extension flag.  More specifically, support is
added for the following instructions:

FP8 convert to BFloat16 (vector):
---------------------------------

  - bf1cvtl V<d>.8H, V<n>.8B
  - bf2cvtl V<d>.8H, V<n>.8B
  - bf1cvtl2 V<d>.8H, V<n>.16B
  - bf2cvtl2 V<d>.8H, V<n>.16B

FP8 convert to half-precision (vector):
---------------------------------------

  - f1cvtl V<d>.8H, V<n>.8B
  - f2cvtl V<d>.8H, V<n>.8B
  - f1cvtl2 V<d>.8H, V<n>.16B
  - f2cvtl2 V<d>.8H, V<n>.16B

Single-precision to FP8 convert and narrow (vector):
----------------------------------------------------

  - fcvtn V<d>.8B, V<n>.4S, V<m>.4S
  - fcvtn2 V<d>.16B, V<n>.4S, V<m>.4S

Half-precision to FP8 convert and narrow (vector):
--------------------------------------------------

  - fcvtn V<d>.8B, V<n>.4H, V<m>.4H
  - fcvtn V<d>.16B, V<n>.8H, V<m>.8H

Floating-point adjust exponent by vector:
-----------------------------------------

  - fscale V<d>.4H, V<n>.4H, V<m>.4H
  - fscale V<d>.8H, V<n>.8H, V<m>.8H
  - fscale V<d>.2S, V<n>.2S, V<m>.2S
  - fscale V<d>.4S, V<n>.4S, V<m>.4S
  - fscale V<d>.2d, V<n>.2d, V<m>.2d