If VEX.vvvv and EVEX.vvvv are reserved, they must be all 1s, which are
all 0s in inverted form. Add check for unused VEX.vvvv and EVEX.vvvv
when disassembling VEX and EVEX instructions.
gas/
PR binutils/24626
* testsuite/gas/i386/disassem.s: Add tests for reserved VEX.vvvv
and EVEX.vvvv.
* testsuite/gas/i386/x86-64-disassem.s: Likewise.
* testsuite/gas/i386/disassem.d: Updated.
* testsuite/gas/i386/x86-64-disassem.d: Likewise.
opcodes/
PR binutils/24626
* i386-dis.c (print_insn): Check for unused VEX.vvvv and
EVEX.vvvv when disassembling VEX and EVEX instructions.
(OP_VEX): Set vex.register_specifier to 0 after readding
vex.register_specifier.
(OP_Vex_2src_1): Likewise.
(OP_Vex_2src_2): Likewise.
(OP_LWP_E): Likewise.
(OP_EX_Vex): Don't check vex.register_specifier.
(OP_XMM_Vex): Likewise.
+2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/24626
+ * testsuite/gas/i386/disassem.s: Add tests for reserved VEX.vvvv
+ and EVEX.vvvv.
+ * testsuite/gas/i386/x86-64-disassem.s: Likewise.
+ * testsuite/gas/i386/disassem.d: Updated.
+ * testsuite/gas/i386/x86-64-disassem.d: Likewise.
+
2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
Lili Cui <lili.cui@intel.com>
2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
Lili Cui <lili.cui@intel.com>
[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\)
[ ]*[a-f0-9]+:[ ]*c4 e1 f9 93[ ]*\(bad\)[ ]*
[ ]*[a-f0-9]+:[ ]*3f[ ]*aas[ ]*
[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\)
[ ]*[a-f0-9]+:[ ]*c4 e1 f9 93[ ]*\(bad\)[ ]*
[ ]*[a-f0-9]+:[ ]*3f[ ]*aas[ ]*
+[ ]*[a-f0-9]+:[ ]*c4 e2 01 1c[ ]*\(bad\)[ ]*
+[ ]*[a-f0-9]+:[ ]*41[ ]*inc[ ]*%ecx
+[ ]*[a-f0-9]+:[ ]*37[ ]*aaa[ ]*
+[ ]*[a-f0-9]+:[ ]*62 f2 ad 08 1c[ ]*\(bad\)[ ]*
+[ ]*[a-f0-9]+:[ ]*01[ ]*.byte[ ]*0x1
.byte 0xC4, 0xE1, 0xF9, 0x93, 0x9B
.byte 0xC4, 0xE1, 0xF9, 0x93, 0x6F
.byte 0xC4, 0xE1, 0xF9, 0x93, 0x3F
.byte 0xC4, 0xE1, 0xF9, 0x93, 0x9B
.byte 0xC4, 0xE1, 0xF9, 0x93, 0x6F
.byte 0xC4, 0xE1, 0xF9, 0x93, 0x3F
+.byte 0xc4, 0xe2, 0x1, 0x1c, 0x41, 0x37
+.byte 0x62, 0xf2, 0xad, 0x08, 0x1c, 0x01
[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\)
[ ]*[a-f0-9]+:[ ]*c4 e1 f9 93[ ]*\(bad\)[ ]*
[ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\)[ ]*
[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\)
[ ]*[a-f0-9]+:[ ]*c4 e1 f9 93[ ]*\(bad\)[ ]*
[ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\)[ ]*
+[ ]*[a-f0-9]+:[ ]*c4 62 01 1c[ ]*\(bad\)[ ]*
+[ ]*[a-f0-9]+:[ ]*41 37[ ]*rex.B \(bad\)[ ]*
+[ ]*[a-f0-9]+:[ ]*62 72 ad 08 1c[ ]*\(bad\)[ ]*
+[ ]*[a-f0-9]+:[ ]*01[ ]*.byte[ ]*0x1
.byte 0xC4, 0xE1, 0xF9, 0x93, 0x9B
.byte 0xC4, 0xE1, 0xF9, 0x93, 0x6F
.byte 0xC4, 0xE1, 0xF9, 0x93, 0x3F
.byte 0xC4, 0xE1, 0xF9, 0x93, 0x9B
.byte 0xC4, 0xE1, 0xF9, 0x93, 0x6F
.byte 0xC4, 0xE1, 0xF9, 0x93, 0x3F
+.byte 0xc4, 0x62, 0x1, 0x1c, 0x41, 0x37
+.byte 0x62, 0x72, 0xad, 0x08, 0x1c, 0x01
+2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/24626
+ * i386-dis.c (print_insn): Check for unused VEX.vvvv and
+ EVEX.vvvv when disassembling VEX and EVEX instructions.
+ (OP_VEX): Set vex.register_specifier to 0 after readding
+ vex.register_specifier.
+ (OP_Vex_2src_1): Likewise.
+ (OP_Vex_2src_2): Likewise.
+ (OP_LWP_E): Likewise.
+ (OP_EX_Vex): Don't check vex.register_specifier.
+ (OP_XMM_Vex): Likewise.
+
2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
Lili Cui <lili.cui@intel.com>
2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
Lili Cui <lili.cui@intel.com>
+ /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
+ are all 0s in inverted form. */
+ if (need_vex && vex.register_specifier != 0)
+ {
+ (*info->fprintf_func) (info->stream, "(bad)");
+ return end_codep - priv.the_buffer;
+ }
+
/* Check if the REX prefix is used. */
if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
all_prefixes[last_rex_prefix] = 0;
/* Check if the REX prefix is used. */
if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
all_prefixes[last_rex_prefix] = 0;
return;
reg = vex.register_specifier;
return;
reg = vex.register_specifier;
+ vex.register_specifier = 0;
if (address_mode != mode_64bit)
reg &= 7;
else if (vex.evex && !vex.v)
if (address_mode != mode_64bit)
reg &= 7;
else if (vex.evex && !vex.v)
if (vex.w)
{
unsigned int reg = vex.register_specifier;
if (vex.w)
{
unsigned int reg = vex.register_specifier;
+ vex.register_specifier = 0;
if (address_mode != mode_64bit)
reg &= 7;
if (address_mode != mode_64bit)
reg &= 7;
else
{
unsigned int reg = vex.register_specifier;
else
{
unsigned int reg = vex.register_specifier;
+ vex.register_specifier = 0;
if (address_mode != mode_64bit)
reg &= 7;
if (address_mode != mode_64bit)
reg &= 7;
OP_EX_Vex (int bytemode, int sizeflag)
{
if (modrm.mod != 3)
OP_EX_Vex (int bytemode, int sizeflag)
{
if (modrm.mod != 3)
- {
- if (vex.register_specifier != 0)
- BadOp ();
- need_vex_reg = 0;
- }
OP_EX (bytemode, sizeflag);
}
OP_EX (bytemode, sizeflag);
}
OP_XMM_Vex (int bytemode, int sizeflag)
{
if (modrm.mod != 3)
OP_XMM_Vex (int bytemode, int sizeflag)
{
if (modrm.mod != 3)
- {
- if (vex.register_specifier != 0)
- BadOp ();
- need_vex_reg = 0;
- }
OP_XMM (bytemode, sizeflag);
}
OP_XMM (bytemode, sizeflag);
}
{
const char **names;
unsigned int reg = vex.register_specifier;
{
const char **names;
unsigned int reg = vex.register_specifier;
+ vex.register_specifier = 0;
if (rex & REX_W)
names = names64;
if (rex & REX_W)
names = names64;