]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
ASoC: SOF: amd: update conditional check for cache register update
authorVijendar Mukunda <Vijendar.Mukunda@amd.com>
Wed, 7 Aug 2024 05:13:17 +0000 (10:43 +0530)
committerMark Brown <broonie@kernel.org>
Thu, 8 Aug 2024 08:17:17 +0000 (09:17 +0100)
Instead of desc->rev, use acp pci revision id(pci_rev) for cache register
conditional check.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://patch.msgid.link/20240807051341.1616925-5-Vijendar.Mukunda@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/sof/amd/acp-loader.c

index 2d5e58846499d2e261b972931be5f7a58c7fa42b..19f10dd77e4ba3bf17f54dfb368c52865a36214c 100644 (file)
@@ -219,7 +219,7 @@ int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev)
                        dev_err(sdev->dev, "acp dma transfer status: %d\n", ret);
        }
 
-       if (desc->rev > 3) {
+       if (adata->pci_rev > ACP_RN_PCI_ID) {
                /* Cache Window enable */
                snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DSP0_CACHE_OFFSET0, desc->sram_pte_offset);
                snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DSP0_CACHE_SIZE0, SRAM1_SIZE | BIT(31));