R: Sumit Garg <sumit.garg@linaro.org>
S: Maintained
F: arch/arm/mach-snapdragon/
+F: drivers/button/button-qcom-pmic.c
+F: drivers/clk/qcom/
F: drivers/gpio/msm_gpio.c
F: drivers/mmc/msm_sdhci.c
F: drivers/phy/msm8916-usbh-phy.c
+F: drivers/pinctrl/qcom/
F: drivers/serial/serial_msm.c
F: drivers/serial/serial_msm_geni.c
F: drivers/smem/msm_smem.c
@find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
\( -name '*.[oas]' -o -name '*.ko' -o -name '.*.cmd' \
-o -name '*.ko.*' -o -name '*.su' -o -name '*.pyc' \
+ -o -name '*.dtb' -o -name '*.dtbo' \
+ -o -name '*.dtb.S' -o -name '*.dtbo.S' \
-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
-o -name '*.lex.c' -o -name '*.tab.[ch]' \
-o -name '*.asn1.[ch]' \
Configuration Settings:
-----------------------
-- MEM_SUPPORT_64BIT_DATA: Defined automatically if compiled as 64-bit.
- Optionally it can be defined to support 64-bit memory commands.
-
- CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
undefine this when you're short of memory.
depends on SPL
bool
+config SPL_USE_SEPARATE_FAULT_HANDLERS
+ bool "Use separate fault handlers instead of a single common one"
+ depends on !SPL_SYS_NO_VECTOR_TABLE && !ARM64 && !CPU_V7M
+ help
+ Instead of a common fault handler, generate a separate one for
+ undefined_instruction, software_interrupt, prefetch_abort etc.
+ This is for debugging purposes, when you want to set breakpoints
+ on them separately.
+
config LINUX_KERNEL_IMAGE_HEADER
depends on ARM64
bool
select CLK
select SMEM
select OF_CONTROL
+ select CLK_QCOM_IPQ4019
+ select PINCTRL_QCOM_IPQ4019
imply CMD_DM
config ARCH_KEYSTONE
select DM
select DM_GPIO
select DM_SERIAL
+ select DM_RESET
select GPIO_EXTRA_HEADER
select MSM_SMEM
select OF_CONTROL
Support for pomelo platform.
It has 8GB Sdram, uart and pcie.
+config TARGET_PE2201
+ bool "Support Phytium PE2201 Platform"
+ select ARM64
+ help
+ Support for pe2201 platform.It has 2GB Sdram, uart and pcie.
+
config TARGET_PRESIDIO_ASIC
bool "Support Cortina Presidio ASIC Platform"
select ARM64
source "board/vscom/baltos/Kconfig"
source "board/phytium/durian/Kconfig"
source "board/phytium/pomelo/Kconfig"
+source "board/phytium/pe2201/Kconfig"
source "board/xen/xenguest_arm64/Kconfig"
source "arch/arm/Kconfig.debug"
imx8mm-mx8menlo.dtb \
imx8mm-phg.dtb \
imx8mm-phyboard-polis-rdk.dtb \
+ imx8mm-phygate-tauri-l.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \
k3-am625-beagleplay.dtb \
k3-am625-r5-beagleplay.dtb \
k3-am625-verdin-wifi-dev.dtb \
- k3-am625-verdin-r5.dtb
+ k3-am625-verdin-r5.dtb \
+ k3-am625-phyboard-lyra-rdk.dtb \
+ k3-am625-r5-phycore-som-2gb.dtb
dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-sk.dtb \
k3-am62a7-r5-sk.dtb
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb
+dtb-$(CONFIG_TARGET_PE2201) += phytium-pe2201.dtb
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
bootph-all;
};
-ð0 {
- /* G.hn does not work without additional configuration */
- status = "disabled";
-};
-
ð1 {
fixed-link {
speed = <1000>;
full-duplex;
};
};
+
+/*
+ * eDPU v2 has a MV88E6361 switch on the MDIO bus and U-boot is used
+ * to patch the Linux DTS if its found so enable MDIO by default.
+ */
+&mdio {
+ status = "okay";
+};
ð0 {
phy-mode = "2500base-x";
};
+
+/*
+ * External MV88E6361 switch is only available on v2 of the board.
+ * U-Boot will enable the MDIO bus and switch nodes.
+ */
+&mdio {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&smi_pins>;
+
+ /* Actual device is MV88E6361 */
+ switch: switch@0 {
+ compatible = "marvell,mv88e6190";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "cpu";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ ethernet = <ð0>;
+ };
+
+ port@9 {
+ reg = <9>;
+ label = "downlink";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ };
+
+ port@a {
+ reg = <10>;
+ label = "uplink";
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ sfp = <&sfp_eth1>;
+ };
+ };
+ };
+};
gpios = <&pm8916_gpios 3 0>;
};
};
-
-
-&pm8916_pon {
- key_vol_down {
- gpios = <&pm8916_pon 1 0>;
- };
-
- key_power {
- gpios = <&pm8916_pon 0 0>;
- };
-};
#address-cells = <0x1>;
#size-cells = <0x1>;
- pm8916_pon: pm8916_pon@800 {
- compatible = "qcom,pm8916-pwrkey";
- reg = <0x800 0x96>;
- #gpio-cells = <2>;
- gpio-controller;
+ pon@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x800 0x100>;
+ mode-bootloader = <0x2>;
+ mode-recovery = <0x1>;
+
+ pwrkey {
+ compatible = "qcom,pm8941-pwrkey";
+ debounce = <15625>;
+ bias-pull-up;
+ };
+
+ pm8916_resin: resin {
+ compatible = "qcom,pm8941-resin";
+ debounce = <15625>;
+ bias-pull-up;
+ };
};
pm8916_gpios: pm8916_gpios@c000 {
compatible = "qcom,pm8916-gpio";
reg = <0xc000 0x400>;
gpio-controller;
- gpio-count = <4>;
+ gpio-ranges = <&pm8916_gpios 0 0 4>;
#gpio-cells = <2>;
- gpio-bank-name="pmic";
};
};
};
};
};
-
-&pm8994_pon {
- key_vol_down {
- gpios = <&pm8994_pon 1 0>;
- label = "key_vol_down";
- };
-
- key_power {
- gpios = <&pm8994_pon 0 0>;
- label = "key_power";
- };
-};
#address-cells = <0x1>;
#size-cells = <0x1>;
- pm8994_pon: pm8994_pon@800 {
- compatible = "qcom,pm8994-pwrkey";
- reg = <0x800 0x96>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-bank-name="pm8994_key.";
+ pm8994_pon: pon@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x800 0x100>;
+ mode-bootloader = <0x2>;
+ mode-recovery = <0x1>;
+
+ pwrkey {
+ compatible = "qcom,pm8941-pwrkey";
+ debounce = <15625>;
+ bias-pull-up;
+ };
+
+ pm8994_resin: resin {
+ compatible = "qcom,pm8941-resin";
+ debounce = <15625>;
+ bias-pull-up;
+ };
};
pm8994_gpios: pm8994_gpios@c000 {
compatible = "qcom,pm8994-gpio";
reg = <0xc000 0x400>;
gpio-controller;
- gpio-count = <24>;
+ gpio-ranges = <&pm8994_gpios 0 0 22>;
#gpio-cells = <2>;
- gpio-bank-name="pm8994.";
};
};
bootph-all;
};
- pinctrl_north@3900000 {
+ pinctrl@3400000 {
bootph-all;
};
};
};
-
-&pm8998_pon {
- key_vol_down {
- gpios = <&pm8998_pon 1 0>;
- label = "key_vol_down";
- };
- key_power {
- gpios = <&pm8998_pon 0 0>;
- label = "key_power";
- };
-};
};
};
+&pm8998_resin {
+ status = "okay";
+};
+
#include "dragonboard845c-uboot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ */
+
+#include "imx8mm-u-boot.dtsi"
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ bootph-pre-ram;
+ };
+};
+
+&pinctrl_uart3 {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2 {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc3 {
+ bootph-pre-ram;
+};
+
+&pinctrl_wdog {
+ bootph-pre-ram;
+};
+
+&gpio1 {
+ bootph-pre-ram;
+};
+
+&gpio2 {
+ bootph-pre-ram;
+};
+
+&gpio3 {
+ bootph-pre-ram;
+};
+
+&gpio4 {
+ bootph-pre-ram;
+};
+
+&gpio5 {
+ bootph-pre-ram;
+};
+
+&uart3 {
+ bootph-pre-ram;
+};
+
+&usdhc2 {
+ bootph-pre-ram;
+};
+
+&usdhc3 {
+ bootph-pre-ram;
+};
+
+&wdog1 {
+ bootph-pre-ram;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 PHYTEC Messtechnik GmbH
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
+#include "imx8mm-phycore-som.dtsi"
+
+/ {
+ model = "PHYTEC phyGATE-Tauri-L-iMX8MM";
+ compatible = "phytec,imx8mm-phygate-tauri-l",
+ "phytec,imx8mm-phycore-som", "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ can_osc_40m: clock-can {
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ clock-output-names = "can_osc_40m";
+ #clock-cells = <0>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiokeys>;
+
+ key {
+ gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ label = "KEY-A";
+ linux,code = <KEY_A>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_leds>;
+
+ led-1 {
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "none";
+ };
+
+ led-2 {
+ color = <LED_COLOR_ID_YELLOW>;
+ gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "none";
+ };
+ };
+
+ usdhc1_pwrseq: pwr-seq {
+ compatible = "mmc-pwrseq-simple";
+ post-power-on-delay-ms = <100>;
+ power-off-delay-us = <60>;
+ reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_usb_hub_vbus: regulator-hub-otg1 {
+ compatible = "regulator-fixed";
+ gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbhubpwr>;
+ regulator-name = "usb_hub_vbus";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1 {
+ compatible = "regulator-fixed";
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1pwr>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ off-on-delay-us = <20000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "VSD_3V3";
+ };
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
+ <&gpio5 13 GPIO_ACTIVE_LOW>,
+ <&gpio5 2 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ /* CAN MCP251XFD */
+ can0: can@0 {
+ compatible = "microchip,mcp251xfd";
+ reg = <0>;
+ clocks = <&can_osc_40m>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can_int>;
+ spi-max-frequency = <10000000>;
+ };
+
+ tpm: tpm@1 {
+ compatible = "tcg,tpm_tis-spi";
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm>;
+ reg = <1>;
+ spi-max-frequency = <38000000>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ temp_sense0: temperature-sensor@49 {
+ compatible = "ti,tmp102";
+ reg = <0x49>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tempsense>;
+ #thermal-sensor-cells = <1>;
+ };
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+/* PCIe */
+&pcie0 {
+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
+ <&clk IMX8MM_CLK_PCIE1_PHY>,
+ <&clk IMX8MM_CLK_PCIE1_CTRL>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
+ <&clk IMX8MM_SYS_PLL2_100M>,
+ <&clk IMX8MM_SYS_PLL2_250M>;
+ assigned-clock-rates = <10000000>, <100000000>, <250000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "okay";
+};
+
+/* RTC */
+&rv3028 {
+ trickle-resistor-ohms = <3000>;
+};
+
+&uart1 {
+ assigned-clocks = <&clk IMX8MM_CLK_UART1>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+/* UART2 - RS232 */
+&uart2 {
+ assigned-clocks = <&clk IMX8MM_CLK_UART2>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+/* UART - console */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+/* USB */
+&usbotg1 {
+ adp-disable;
+ dr_mode = "otg";
+ over-current-active-low;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
+ srp-disable;
+ vbus-supply = <®_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ disable-over-current;
+ dr_mode = "host";
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ vbus-supply = <®_usb_hub_vbus>;
+ status = "okay";
+};
+
+/* SD-Card */
+&usdhc2 {
+ assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
+ assigned-clock-rates = <200000000>;
+ bus-width = <4>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ vqmmc-supply = <®_nvcc_sd2>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_can_int: can-intgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
+ >;
+ };
+
+ pinctrl_ecspi1_cs: ecspi1csgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00
+ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x00
+ >;
+ };
+
+ pinctrl_gpiokeys: keygrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1e0
+ MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1e0
+ >;
+ };
+
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e0
+ MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e0
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c4_gpio: i2c4gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e0
+ MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e0
+ >;
+ };
+
+ pinctrl_leds: leds1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x00
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x00
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ /* COEX2 */
+ MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x00
+ /* COEX1 */
+ MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x40
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x40
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x40
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
+ >;
+ };
+
+ pinctrl_tempsense: tempsensegrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00
+ >;
+ };
+
+ pinctrl_tpm: tpmgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x00
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x00
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usbhubpwr: usbhubpwrgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x00
+ >;
+ };
+
+ pinctrl_usbotg1pwr: usbotg1pwrgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x80
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * This file was generated with the
+ * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.05
+ * Fri Feb 03 2023 10:59:20 GMT+0100 (Mitteleuropäische Normalzeit)
+ * DDR Type: DDR4
+ * Frequency = 800MHz (1600MTs)
+ * Density: 16Gb
+ * Number of Ranks: 1
+*/
+
+#define DDRSS_PLL_FHS_CNT 6
+#define DDRSS_PLL_FREQUENCY_1 400000000
+#define DDRSS_PLL_FREQUENCY_2 400000000
+
+
+#define DDRSS_CTL_0_DATA 0x00000A00
+#define DDRSS_CTL_1_DATA 0x00000000
+#define DDRSS_CTL_2_DATA 0x00000000
+#define DDRSS_CTL_3_DATA 0x00000000
+#define DDRSS_CTL_4_DATA 0x00000000
+#define DDRSS_CTL_5_DATA 0x00000000
+#define DDRSS_CTL_6_DATA 0x00000000
+#define DDRSS_CTL_7_DATA 0x000890B8
+#define DDRSS_CTL_8_DATA 0x00000000
+#define DDRSS_CTL_9_DATA 0x00000000
+#define DDRSS_CTL_10_DATA 0x00000000
+#define DDRSS_CTL_11_DATA 0x000890B8
+#define DDRSS_CTL_12_DATA 0x00000000
+#define DDRSS_CTL_13_DATA 0x00000000
+#define DDRSS_CTL_14_DATA 0x00000000
+#define DDRSS_CTL_15_DATA 0x000890B8
+#define DDRSS_CTL_16_DATA 0x00000000
+#define DDRSS_CTL_17_DATA 0x00000000
+#define DDRSS_CTL_18_DATA 0x00000000
+#define DDRSS_CTL_19_DATA 0x01010100
+#define DDRSS_CTL_20_DATA 0x01000100
+#define DDRSS_CTL_21_DATA 0x01000110
+#define DDRSS_CTL_22_DATA 0x02010002
+#define DDRSS_CTL_23_DATA 0x00027100
+#define DDRSS_CTL_24_DATA 0x00061A80
+#define DDRSS_CTL_25_DATA 0x02550255
+#define DDRSS_CTL_26_DATA 0x00000255
+#define DDRSS_CTL_27_DATA 0x00000000
+#define DDRSS_CTL_28_DATA 0x00000000
+#define DDRSS_CTL_29_DATA 0x00000000
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x00000000
+#define DDRSS_CTL_35_DATA 0x00000000
+#define DDRSS_CTL_36_DATA 0x00000000
+#define DDRSS_CTL_37_DATA 0x00000000
+#define DDRSS_CTL_38_DATA 0x0400091C
+#define DDRSS_CTL_39_DATA 0x1C1C1C1C
+#define DDRSS_CTL_40_DATA 0x0400091C
+#define DDRSS_CTL_41_DATA 0x1C1C1C1C
+#define DDRSS_CTL_42_DATA 0x0400091C
+#define DDRSS_CTL_43_DATA 0x1C1C1C1C
+#define DDRSS_CTL_44_DATA 0x05050404
+#define DDRSS_CTL_45_DATA 0x00002706
+#define DDRSS_CTL_46_DATA 0x0602001D
+#define DDRSS_CTL_47_DATA 0x05001D0B
+#define DDRSS_CTL_48_DATA 0x00270605
+#define DDRSS_CTL_49_DATA 0x0602001D
+#define DDRSS_CTL_50_DATA 0x05001D0B
+#define DDRSS_CTL_51_DATA 0x00270605
+#define DDRSS_CTL_52_DATA 0x0602001D
+#define DDRSS_CTL_53_DATA 0x07001D0B
+#define DDRSS_CTL_54_DATA 0x00180807
+#define DDRSS_CTL_55_DATA 0x04006DB0
+#define DDRSS_CTL_56_DATA 0x07070009
+#define DDRSS_CTL_57_DATA 0x00001808
+#define DDRSS_CTL_58_DATA 0x04006DB0
+#define DDRSS_CTL_59_DATA 0x07070009
+#define DDRSS_CTL_60_DATA 0x00001808
+#define DDRSS_CTL_61_DATA 0x04006DB0
+#define DDRSS_CTL_62_DATA 0x03000009
+#define DDRSS_CTL_63_DATA 0x0D0C0002
+#define DDRSS_CTL_64_DATA 0x0D0C0D0C
+#define DDRSS_CTL_65_DATA 0x01010000
+#define DDRSS_CTL_66_DATA 0x03191919
+#define DDRSS_CTL_67_DATA 0x0B0B0B0B
+#define DDRSS_CTL_68_DATA 0x00000B0B
+#define DDRSS_CTL_69_DATA 0x00000101
+#define DDRSS_CTL_70_DATA 0x00000000
+#define DDRSS_CTL_71_DATA 0x01000000
+#define DDRSS_CTL_72_DATA 0x01180803
+#define DDRSS_CTL_73_DATA 0x00000C30
+#define DDRSS_CTL_74_DATA 0x00000118
+#define DDRSS_CTL_75_DATA 0x00000C30
+#define DDRSS_CTL_76_DATA 0x00000118
+#define DDRSS_CTL_77_DATA 0x00000C30
+#define DDRSS_CTL_78_DATA 0x00000005
+#define DDRSS_CTL_79_DATA 0x00000000
+#define DDRSS_CTL_80_DATA 0x00000000
+#define DDRSS_CTL_81_DATA 0x00000000
+#define DDRSS_CTL_82_DATA 0x00000000
+#define DDRSS_CTL_83_DATA 0x00000000
+#define DDRSS_CTL_84_DATA 0x00000000
+#define DDRSS_CTL_85_DATA 0x00000000
+#define DDRSS_CTL_86_DATA 0x00000000
+#define DDRSS_CTL_87_DATA 0x00090009
+#define DDRSS_CTL_88_DATA 0x00000009
+#define DDRSS_CTL_89_DATA 0x00000000
+#define DDRSS_CTL_90_DATA 0x00000000
+#define DDRSS_CTL_91_DATA 0x00000000
+#define DDRSS_CTL_92_DATA 0x00000000
+#define DDRSS_CTL_93_DATA 0x00000000
+#define DDRSS_CTL_94_DATA 0x00010001
+#define DDRSS_CTL_95_DATA 0x00025501
+#define DDRSS_CTL_96_DATA 0x02550120
+#define DDRSS_CTL_97_DATA 0x02550120
+#define DDRSS_CTL_98_DATA 0x01200120
+#define DDRSS_CTL_99_DATA 0x01200120
+#define DDRSS_CTL_100_DATA 0x00000000
+#define DDRSS_CTL_101_DATA 0x00000000
+#define DDRSS_CTL_102_DATA 0x00000000
+#define DDRSS_CTL_103_DATA 0x00000000
+#define DDRSS_CTL_104_DATA 0x00000000
+#define DDRSS_CTL_105_DATA 0x00000000
+#define DDRSS_CTL_106_DATA 0x03010000
+#define DDRSS_CTL_107_DATA 0x00010000
+#define DDRSS_CTL_108_DATA 0x00000000
+#define DDRSS_CTL_109_DATA 0x01000000
+#define DDRSS_CTL_110_DATA 0x80104002
+#define DDRSS_CTL_111_DATA 0x00040003
+#define DDRSS_CTL_112_DATA 0x00040005
+#define DDRSS_CTL_113_DATA 0x00030000
+#define DDRSS_CTL_114_DATA 0x00050004
+#define DDRSS_CTL_115_DATA 0x00000004
+#define DDRSS_CTL_116_DATA 0x00040003
+#define DDRSS_CTL_117_DATA 0x00040005
+#define DDRSS_CTL_118_DATA 0x00000000
+#define DDRSS_CTL_119_DATA 0x00030C00
+#define DDRSS_CTL_120_DATA 0x00030C00
+#define DDRSS_CTL_121_DATA 0x00030C00
+#define DDRSS_CTL_122_DATA 0x00030C00
+#define DDRSS_CTL_123_DATA 0x00030C00
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x00005550
+#define DDRSS_CTL_126_DATA 0x00030C00
+#define DDRSS_CTL_127_DATA 0x00030C00
+#define DDRSS_CTL_128_DATA 0x00030C00
+#define DDRSS_CTL_129_DATA 0x00030C00
+#define DDRSS_CTL_130_DATA 0x00030C00
+#define DDRSS_CTL_131_DATA 0x00000000
+#define DDRSS_CTL_132_DATA 0x00005550
+#define DDRSS_CTL_133_DATA 0x00030C00
+#define DDRSS_CTL_134_DATA 0x00030C00
+#define DDRSS_CTL_135_DATA 0x00030C00
+#define DDRSS_CTL_136_DATA 0x00030C00
+#define DDRSS_CTL_137_DATA 0x00030C00
+#define DDRSS_CTL_138_DATA 0x00000000
+#define DDRSS_CTL_139_DATA 0x00005550
+#define DDRSS_CTL_140_DATA 0x00000000
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x00000000
+#define DDRSS_CTL_149_DATA 0x00000000
+#define DDRSS_CTL_150_DATA 0x00000000
+#define DDRSS_CTL_151_DATA 0x00000000
+#define DDRSS_CTL_152_DATA 0x00000000
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00000000
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x080C0000
+#define DDRSS_CTL_157_DATA 0x080C080C
+#define DDRSS_CTL_158_DATA 0x08000000
+#define DDRSS_CTL_159_DATA 0x00000808
+#define DDRSS_CTL_160_DATA 0x000E0000
+#define DDRSS_CTL_161_DATA 0x00080808
+#define DDRSS_CTL_162_DATA 0x0E000000
+#define DDRSS_CTL_163_DATA 0x08080800
+#define DDRSS_CTL_164_DATA 0x00000000
+#define DDRSS_CTL_165_DATA 0x0000080E
+#define DDRSS_CTL_166_DATA 0x00040003
+#define DDRSS_CTL_167_DATA 0x00000007
+#define DDRSS_CTL_168_DATA 0x00000000
+#define DDRSS_CTL_169_DATA 0x00000000
+#define DDRSS_CTL_170_DATA 0x00000000
+#define DDRSS_CTL_171_DATA 0x00000000
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x01000000
+#define DDRSS_CTL_175_DATA 0x00000000
+#define DDRSS_CTL_176_DATA 0x00001500
+#define DDRSS_CTL_177_DATA 0x0000100E
+#define DDRSS_CTL_178_DATA 0x00000000
+#define DDRSS_CTL_179_DATA 0x00000000
+#define DDRSS_CTL_180_DATA 0x00000001
+#define DDRSS_CTL_181_DATA 0x00000002
+#define DDRSS_CTL_182_DATA 0x00000C00
+#define DDRSS_CTL_183_DATA 0x00001000
+#define DDRSS_CTL_184_DATA 0x00000C00
+#define DDRSS_CTL_185_DATA 0x00001000
+#define DDRSS_CTL_186_DATA 0x00000C00
+#define DDRSS_CTL_187_DATA 0x00001000
+#define DDRSS_CTL_188_DATA 0x00000000
+#define DDRSS_CTL_189_DATA 0x00000000
+#define DDRSS_CTL_190_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x00000000
+#define DDRSS_CTL_193_DATA 0x00000000
+#define DDRSS_CTL_194_DATA 0x00000000
+#define DDRSS_CTL_195_DATA 0x00000000
+#define DDRSS_CTL_196_DATA 0x00000000
+#define DDRSS_CTL_197_DATA 0x00000000
+#define DDRSS_CTL_198_DATA 0x00000000
+#define DDRSS_CTL_199_DATA 0x00000000
+#define DDRSS_CTL_200_DATA 0x00000000
+#define DDRSS_CTL_201_DATA 0x00000000
+#define DDRSS_CTL_202_DATA 0x00000000
+#define DDRSS_CTL_203_DATA 0x00000000
+#define DDRSS_CTL_204_DATA 0x00042400
+#define DDRSS_CTL_205_DATA 0x00000301
+#define DDRSS_CTL_206_DATA 0x000000C0
+#define DDRSS_CTL_207_DATA 0x00000424
+#define DDRSS_CTL_208_DATA 0x00000301
+#define DDRSS_CTL_209_DATA 0x000000C0
+#define DDRSS_CTL_210_DATA 0x00000424
+#define DDRSS_CTL_211_DATA 0x00000301
+#define DDRSS_CTL_212_DATA 0x000000C0
+#define DDRSS_CTL_213_DATA 0x00000424
+#define DDRSS_CTL_214_DATA 0x00000301
+#define DDRSS_CTL_215_DATA 0x000000C0
+#define DDRSS_CTL_216_DATA 0x00000424
+#define DDRSS_CTL_217_DATA 0x00000301
+#define DDRSS_CTL_218_DATA 0x000000C0
+#define DDRSS_CTL_219_DATA 0x00000424
+#define DDRSS_CTL_220_DATA 0x00000301
+#define DDRSS_CTL_221_DATA 0x000000C0
+#define DDRSS_CTL_222_DATA 0x00000000
+#define DDRSS_CTL_223_DATA 0x00000000
+#define DDRSS_CTL_224_DATA 0x00000000
+#define DDRSS_CTL_225_DATA 0x00000000
+#define DDRSS_CTL_226_DATA 0x00000000
+#define DDRSS_CTL_227_DATA 0x00000000
+#define DDRSS_CTL_228_DATA 0x00000000
+#define DDRSS_CTL_229_DATA 0x00000000
+#define DDRSS_CTL_230_DATA 0x0000000C
+#define DDRSS_CTL_231_DATA 0x0000000C
+#define DDRSS_CTL_232_DATA 0x0000000C
+#define DDRSS_CTL_233_DATA 0x0000000C
+#define DDRSS_CTL_234_DATA 0x0000000C
+#define DDRSS_CTL_235_DATA 0x0000000C
+#define DDRSS_CTL_236_DATA 0x00001401
+#define DDRSS_CTL_237_DATA 0x00001401
+#define DDRSS_CTL_238_DATA 0x00001401
+#define DDRSS_CTL_239_DATA 0x00001401
+#define DDRSS_CTL_240_DATA 0x00001401
+#define DDRSS_CTL_241_DATA 0x00001401
+#define DDRSS_CTL_242_DATA 0x00000493
+#define DDRSS_CTL_243_DATA 0x00000493
+#define DDRSS_CTL_244_DATA 0x00000493
+#define DDRSS_CTL_245_DATA 0x00000493
+#define DDRSS_CTL_246_DATA 0x00000493
+#define DDRSS_CTL_247_DATA 0x00000493
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x00000000
+#define DDRSS_CTL_255_DATA 0x00000000
+#define DDRSS_CTL_256_DATA 0x00000000
+#define DDRSS_CTL_257_DATA 0x00000000
+#define DDRSS_CTL_258_DATA 0x00000000
+#define DDRSS_CTL_259_DATA 0x00000000
+#define DDRSS_CTL_260_DATA 0x00000000
+#define DDRSS_CTL_261_DATA 0x00000000
+#define DDRSS_CTL_262_DATA 0x00000000
+#define DDRSS_CTL_263_DATA 0x00000000
+#define DDRSS_CTL_264_DATA 0x00000000
+#define DDRSS_CTL_265_DATA 0x00000000
+#define DDRSS_CTL_266_DATA 0x00000000
+#define DDRSS_CTL_267_DATA 0x00000000
+#define DDRSS_CTL_268_DATA 0x00000000
+#define DDRSS_CTL_269_DATA 0x00000000
+#define DDRSS_CTL_270_DATA 0x00000000
+#define DDRSS_CTL_271_DATA 0x00000000
+#define DDRSS_CTL_272_DATA 0x00000000
+#define DDRSS_CTL_273_DATA 0x00000000
+#define DDRSS_CTL_274_DATA 0x00000000
+#define DDRSS_CTL_275_DATA 0x00000000
+#define DDRSS_CTL_276_DATA 0x00000000
+#define DDRSS_CTL_277_DATA 0x00010000
+#define DDRSS_CTL_278_DATA 0x00000000
+#define DDRSS_CTL_279_DATA 0x00000000
+#define DDRSS_CTL_280_DATA 0x00000000
+#define DDRSS_CTL_281_DATA 0x00000101
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000000
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00000000
+#define DDRSS_CTL_287_DATA 0x00000000
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x0C181511
+#define DDRSS_CTL_291_DATA 0x00000304
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x00000000
+#define DDRSS_CTL_297_DATA 0x00000000
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00040000
+#define DDRSS_CTL_306_DATA 0x00800200
+#define DDRSS_CTL_307_DATA 0x00000000
+#define DDRSS_CTL_308_DATA 0x02000400
+#define DDRSS_CTL_309_DATA 0x00000080
+#define DDRSS_CTL_310_DATA 0x00040000
+#define DDRSS_CTL_311_DATA 0x00800200
+#define DDRSS_CTL_312_DATA 0x00000000
+#define DDRSS_CTL_313_DATA 0x00000000
+#define DDRSS_CTL_314_DATA 0x00000000
+#define DDRSS_CTL_315_DATA 0x00000100
+#define DDRSS_CTL_316_DATA 0x01010000
+#define DDRSS_CTL_317_DATA 0x00000000
+#define DDRSS_CTL_318_DATA 0x3FFF0000
+#define DDRSS_CTL_319_DATA 0x000FFF00
+#define DDRSS_CTL_320_DATA 0xFFFFFFFF
+#define DDRSS_CTL_321_DATA 0x00FFFF00
+#define DDRSS_CTL_322_DATA 0x0A000000
+#define DDRSS_CTL_323_DATA 0x0001FFFF
+#define DDRSS_CTL_324_DATA 0x01010101
+#define DDRSS_CTL_325_DATA 0x01010101
+#define DDRSS_CTL_326_DATA 0x00000118
+#define DDRSS_CTL_327_DATA 0x00000C01
+#define DDRSS_CTL_328_DATA 0x00000000
+#define DDRSS_CTL_329_DATA 0x00000000
+#define DDRSS_CTL_330_DATA 0x00000000
+#define DDRSS_CTL_331_DATA 0x01000000
+#define DDRSS_CTL_332_DATA 0x00000100
+#define DDRSS_CTL_333_DATA 0x00010000
+#define DDRSS_CTL_334_DATA 0x00000000
+#define DDRSS_CTL_335_DATA 0x00000000
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x00000000
+#define DDRSS_CTL_339_DATA 0x00000000
+#define DDRSS_CTL_340_DATA 0x00000000
+#define DDRSS_CTL_341_DATA 0x00000000
+#define DDRSS_CTL_342_DATA 0x00000000
+#define DDRSS_CTL_343_DATA 0x00000000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x00000000
+#define DDRSS_CTL_361_DATA 0x00000000
+#define DDRSS_CTL_362_DATA 0x00000000
+#define DDRSS_CTL_363_DATA 0x00000000
+#define DDRSS_CTL_364_DATA 0x00000000
+#define DDRSS_CTL_365_DATA 0x00000000
+#define DDRSS_CTL_366_DATA 0x00000000
+#define DDRSS_CTL_367_DATA 0x00000000
+#define DDRSS_CTL_368_DATA 0x00000000
+#define DDRSS_CTL_369_DATA 0x00000000
+#define DDRSS_CTL_370_DATA 0x0C000000
+#define DDRSS_CTL_371_DATA 0x060C0606
+#define DDRSS_CTL_372_DATA 0x06060C06
+#define DDRSS_CTL_373_DATA 0x00010101
+#define DDRSS_CTL_374_DATA 0x02000000
+#define DDRSS_CTL_375_DATA 0x05020101
+#define DDRSS_CTL_376_DATA 0x00000505
+#define DDRSS_CTL_377_DATA 0x02020200
+#define DDRSS_CTL_378_DATA 0x02020202
+#define DDRSS_CTL_379_DATA 0x02020202
+#define DDRSS_CTL_380_DATA 0x02020202
+#define DDRSS_CTL_381_DATA 0x00000000
+#define DDRSS_CTL_382_DATA 0x00000000
+#define DDRSS_CTL_383_DATA 0x04000100
+#define DDRSS_CTL_384_DATA 0x1E000004
+#define DDRSS_CTL_385_DATA 0x00001860
+#define DDRSS_CTL_386_DATA 0x00000200
+#define DDRSS_CTL_387_DATA 0x00000200
+#define DDRSS_CTL_388_DATA 0x00000200
+#define DDRSS_CTL_389_DATA 0x00000200
+#define DDRSS_CTL_390_DATA 0x00006DB0
+#define DDRSS_CTL_391_DATA 0x0000F3C0
+#define DDRSS_CTL_392_DATA 0x0C0D0302
+#define DDRSS_CTL_393_DATA 0x001E090A
+#define DDRSS_CTL_394_DATA 0x00001860
+#define DDRSS_CTL_395_DATA 0x00000200
+#define DDRSS_CTL_396_DATA 0x00000200
+#define DDRSS_CTL_397_DATA 0x00000200
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x00006DB0
+#define DDRSS_CTL_400_DATA 0x0000F3C0
+#define DDRSS_CTL_401_DATA 0x0C0D0302
+#define DDRSS_CTL_402_DATA 0x001E090A
+#define DDRSS_CTL_403_DATA 0x00001860
+#define DDRSS_CTL_404_DATA 0x00000200
+#define DDRSS_CTL_405_DATA 0x00000200
+#define DDRSS_CTL_406_DATA 0x00000200
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x00006DB0
+#define DDRSS_CTL_409_DATA 0x0000F3C0
+#define DDRSS_CTL_410_DATA 0x0C0D0302
+#define DDRSS_CTL_411_DATA 0x0000090A
+#define DDRSS_CTL_412_DATA 0x00000000
+#define DDRSS_CTL_413_DATA 0x0302000A
+#define DDRSS_CTL_414_DATA 0x01000500
+#define DDRSS_CTL_415_DATA 0x01010001
+#define DDRSS_CTL_416_DATA 0x00010001
+#define DDRSS_CTL_417_DATA 0x01010001
+#define DDRSS_CTL_418_DATA 0x02010000
+#define DDRSS_CTL_419_DATA 0x00000200
+#define DDRSS_CTL_420_DATA 0x02000201
+#define DDRSS_CTL_421_DATA 0x00000000
+#define DDRSS_CTL_422_DATA 0x00202020
+#define DDRSS_PI_0_DATA 0x00000A00
+#define DDRSS_PI_1_DATA 0x00000000
+#define DDRSS_PI_2_DATA 0x00000000
+#define DDRSS_PI_3_DATA 0x01000000
+#define DDRSS_PI_4_DATA 0x00000001
+#define DDRSS_PI_5_DATA 0x00010064
+#define DDRSS_PI_6_DATA 0x00000000
+#define DDRSS_PI_7_DATA 0x00000000
+#define DDRSS_PI_8_DATA 0x00000000
+#define DDRSS_PI_9_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000000
+#define DDRSS_PI_12_DATA 0x00000000
+#define DDRSS_PI_13_DATA 0x00010001
+#define DDRSS_PI_14_DATA 0x00000000
+#define DDRSS_PI_15_DATA 0x00010001
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00000000
+#define DDRSS_PI_24_DATA 0x280D0001
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x00010000
+#define DDRSS_PI_27_DATA 0x00003200
+#define DDRSS_PI_28_DATA 0x00000000
+#define DDRSS_PI_29_DATA 0x00000000
+#define DDRSS_PI_30_DATA 0x00060602
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x00000000
+#define DDRSS_PI_34_DATA 0x00000001
+#define DDRSS_PI_35_DATA 0x00000055
+#define DDRSS_PI_36_DATA 0x000000AA
+#define DDRSS_PI_37_DATA 0x000000AD
+#define DDRSS_PI_38_DATA 0x00000052
+#define DDRSS_PI_39_DATA 0x0000006A
+#define DDRSS_PI_40_DATA 0x00000095
+#define DDRSS_PI_41_DATA 0x00000095
+#define DDRSS_PI_42_DATA 0x000000AD
+#define DDRSS_PI_43_DATA 0x00000000
+#define DDRSS_PI_44_DATA 0x00000000
+#define DDRSS_PI_45_DATA 0x00010100
+#define DDRSS_PI_46_DATA 0x00000014
+#define DDRSS_PI_47_DATA 0x000007D0
+#define DDRSS_PI_48_DATA 0x00000300
+#define DDRSS_PI_49_DATA 0x00000000
+#define DDRSS_PI_50_DATA 0x00000000
+#define DDRSS_PI_51_DATA 0x01000000
+#define DDRSS_PI_52_DATA 0x00010101
+#define DDRSS_PI_53_DATA 0x01000000
+#define DDRSS_PI_54_DATA 0x00000000
+#define DDRSS_PI_55_DATA 0x00010000
+#define DDRSS_PI_56_DATA 0x00000000
+#define DDRSS_PI_57_DATA 0x00000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x00000000
+#define DDRSS_PI_60_DATA 0x00001400
+#define DDRSS_PI_61_DATA 0x00000000
+#define DDRSS_PI_62_DATA 0x01000000
+#define DDRSS_PI_63_DATA 0x00000404
+#define DDRSS_PI_64_DATA 0x00000001
+#define DDRSS_PI_65_DATA 0x0001010E
+#define DDRSS_PI_66_DATA 0x02040100
+#define DDRSS_PI_67_DATA 0x00010000
+#define DDRSS_PI_68_DATA 0x00000034
+#define DDRSS_PI_69_DATA 0x00000000
+#define DDRSS_PI_70_DATA 0x00000000
+#define DDRSS_PI_71_DATA 0x00000000
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00000000
+#define DDRSS_PI_74_DATA 0x00000000
+#define DDRSS_PI_75_DATA 0x00000005
+#define DDRSS_PI_76_DATA 0x01000000
+#define DDRSS_PI_77_DATA 0x04000100
+#define DDRSS_PI_78_DATA 0x00020000
+#define DDRSS_PI_79_DATA 0x00010002
+#define DDRSS_PI_80_DATA 0x00000001
+#define DDRSS_PI_81_DATA 0x00020001
+#define DDRSS_PI_82_DATA 0x00020002
+#define DDRSS_PI_83_DATA 0x00000000
+#define DDRSS_PI_84_DATA 0x00000000
+#define DDRSS_PI_85_DATA 0x00000000
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000300
+#define DDRSS_PI_92_DATA 0x0A090B0C
+#define DDRSS_PI_93_DATA 0x04060708
+#define DDRSS_PI_94_DATA 0x01000005
+#define DDRSS_PI_95_DATA 0x00000800
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x00010008
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x0000AA00
+#define DDRSS_PI_100_DATA 0x00000000
+#define DDRSS_PI_101_DATA 0x00010000
+#define DDRSS_PI_102_DATA 0x00000000
+#define DDRSS_PI_103_DATA 0x00000000
+#define DDRSS_PI_104_DATA 0x00000000
+#define DDRSS_PI_105_DATA 0x00000000
+#define DDRSS_PI_106_DATA 0x00000000
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x00000000
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00000000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000008
+#define DDRSS_PI_125_DATA 0x00000000
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00010100
+#define DDRSS_PI_134_DATA 0x00000000
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x00027100
+#define DDRSS_PI_137_DATA 0x00061A80
+#define DDRSS_PI_138_DATA 0x00000100
+#define DDRSS_PI_139_DATA 0x00000000
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x01000000
+#define DDRSS_PI_145_DATA 0x00010003
+#define DDRSS_PI_146_DATA 0x02000101
+#define DDRSS_PI_147_DATA 0x01030001
+#define DDRSS_PI_148_DATA 0x00010400
+#define DDRSS_PI_149_DATA 0x06000105
+#define DDRSS_PI_150_DATA 0x01070001
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00010000
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x00000000
+#define DDRSS_PI_157_DATA 0x00000000
+#define DDRSS_PI_158_DATA 0x00000000
+#define DDRSS_PI_159_DATA 0x00010000
+#define DDRSS_PI_160_DATA 0x00000004
+#define DDRSS_PI_161_DATA 0x00000000
+#define DDRSS_PI_162_DATA 0x00000000
+#define DDRSS_PI_163_DATA 0x00000000
+#define DDRSS_PI_164_DATA 0x00007800
+#define DDRSS_PI_165_DATA 0x00780078
+#define DDRSS_PI_166_DATA 0x00141414
+#define DDRSS_PI_167_DATA 0x0000003A
+#define DDRSS_PI_168_DATA 0x0000003A
+#define DDRSS_PI_169_DATA 0x0004003A
+#define DDRSS_PI_170_DATA 0x04000400
+#define DDRSS_PI_171_DATA 0xC8040009
+#define DDRSS_PI_172_DATA 0x0400091C
+#define DDRSS_PI_173_DATA 0x00091CC8
+#define DDRSS_PI_174_DATA 0x001CC804
+#define DDRSS_PI_175_DATA 0x00000118
+#define DDRSS_PI_176_DATA 0x00000C30
+#define DDRSS_PI_177_DATA 0x00000118
+#define DDRSS_PI_178_DATA 0x00000C30
+#define DDRSS_PI_179_DATA 0x00000118
+#define DDRSS_PI_180_DATA 0x04000C30
+#define DDRSS_PI_181_DATA 0x01010404
+#define DDRSS_PI_182_DATA 0x00001901
+#define DDRSS_PI_183_DATA 0x00190019
+#define DDRSS_PI_184_DATA 0x010C010C
+#define DDRSS_PI_185_DATA 0x0000010C
+#define DDRSS_PI_186_DATA 0x00000000
+#define DDRSS_PI_187_DATA 0x05000000
+#define DDRSS_PI_188_DATA 0x01010505
+#define DDRSS_PI_189_DATA 0x01010101
+#define DDRSS_PI_190_DATA 0x00181818
+#define DDRSS_PI_191_DATA 0x00000000
+#define DDRSS_PI_192_DATA 0x00000000
+#define DDRSS_PI_193_DATA 0x0D000000
+#define DDRSS_PI_194_DATA 0x0A0A0D0D
+#define DDRSS_PI_195_DATA 0x0303030A
+#define DDRSS_PI_196_DATA 0x00000000
+#define DDRSS_PI_197_DATA 0x00000000
+#define DDRSS_PI_198_DATA 0x00000000
+#define DDRSS_PI_199_DATA 0x00000000
+#define DDRSS_PI_200_DATA 0x00000000
+#define DDRSS_PI_201_DATA 0x00000000
+#define DDRSS_PI_202_DATA 0x00000000
+#define DDRSS_PI_203_DATA 0x00000000
+#define DDRSS_PI_204_DATA 0x00000000
+#define DDRSS_PI_205_DATA 0x00000000
+#define DDRSS_PI_206_DATA 0x00000000
+#define DDRSS_PI_207_DATA 0x00000000
+#define DDRSS_PI_208_DATA 0x00000000
+#define DDRSS_PI_209_DATA 0x0D090000
+#define DDRSS_PI_210_DATA 0x0D09000D
+#define DDRSS_PI_211_DATA 0x0D09000D
+#define DDRSS_PI_212_DATA 0x0000000D
+#define DDRSS_PI_213_DATA 0x00000000
+#define DDRSS_PI_214_DATA 0x00000000
+#define DDRSS_PI_215_DATA 0x00000000
+#define DDRSS_PI_216_DATA 0x00000000
+#define DDRSS_PI_217_DATA 0x16000000
+#define DDRSS_PI_218_DATA 0x001600C8
+#define DDRSS_PI_219_DATA 0x001600C8
+#define DDRSS_PI_220_DATA 0x010100C8
+#define DDRSS_PI_221_DATA 0x00001B01
+#define DDRSS_PI_222_DATA 0x1F0F0053
+#define DDRSS_PI_223_DATA 0x05000001
+#define DDRSS_PI_224_DATA 0x001B0A0D
+#define DDRSS_PI_225_DATA 0x1F0F0053
+#define DDRSS_PI_226_DATA 0x05000001
+#define DDRSS_PI_227_DATA 0x001B0A0D
+#define DDRSS_PI_228_DATA 0x1F0F0053
+#define DDRSS_PI_229_DATA 0x05000001
+#define DDRSS_PI_230_DATA 0x00010A0D
+#define DDRSS_PI_231_DATA 0x0C0B0700
+#define DDRSS_PI_232_DATA 0x000D0605
+#define DDRSS_PI_233_DATA 0x000062B8
+#define DDRSS_PI_234_DATA 0x0000001D
+#define DDRSS_PI_235_DATA 0x180A0800
+#define DDRSS_PI_236_DATA 0x0B071C1C
+#define DDRSS_PI_237_DATA 0x0D06050C
+#define DDRSS_PI_238_DATA 0x000062B8
+#define DDRSS_PI_239_DATA 0x0000001D
+#define DDRSS_PI_240_DATA 0x180A0800
+#define DDRSS_PI_241_DATA 0x0B071C1C
+#define DDRSS_PI_242_DATA 0x0D06050C
+#define DDRSS_PI_243_DATA 0x000062B8
+#define DDRSS_PI_244_DATA 0x0000001D
+#define DDRSS_PI_245_DATA 0x180A0800
+#define DDRSS_PI_246_DATA 0x00001C1C
+#define DDRSS_PI_247_DATA 0x00001860
+#define DDRSS_PI_248_DATA 0x0000F3C0
+#define DDRSS_PI_249_DATA 0x00001860
+#define DDRSS_PI_250_DATA 0x0000F3C0
+#define DDRSS_PI_251_DATA 0x00001860
+#define DDRSS_PI_252_DATA 0x0000F3C0
+#define DDRSS_PI_253_DATA 0x02550255
+#define DDRSS_PI_254_DATA 0x03030255
+#define DDRSS_PI_255_DATA 0x00025503
+#define DDRSS_PI_256_DATA 0x02550255
+#define DDRSS_PI_257_DATA 0x0C080C08
+#define DDRSS_PI_258_DATA 0x00000C08
+#define DDRSS_PI_259_DATA 0x000890B8
+#define DDRSS_PI_260_DATA 0x00000000
+#define DDRSS_PI_261_DATA 0x00000000
+#define DDRSS_PI_262_DATA 0x00000000
+#define DDRSS_PI_263_DATA 0x00000120
+#define DDRSS_PI_264_DATA 0x000890B8
+#define DDRSS_PI_265_DATA 0x00000000
+#define DDRSS_PI_266_DATA 0x00000000
+#define DDRSS_PI_267_DATA 0x00000000
+#define DDRSS_PI_268_DATA 0x00000120
+#define DDRSS_PI_269_DATA 0x000890B8
+#define DDRSS_PI_270_DATA 0x00000000
+#define DDRSS_PI_271_DATA 0x00000000
+#define DDRSS_PI_272_DATA 0x00000000
+#define DDRSS_PI_273_DATA 0x02000120
+#define DDRSS_PI_274_DATA 0x00000080
+#define DDRSS_PI_275_DATA 0x00020000
+#define DDRSS_PI_276_DATA 0x00000080
+#define DDRSS_PI_277_DATA 0x00020000
+#define DDRSS_PI_278_DATA 0x00000080
+#define DDRSS_PI_279_DATA 0x00000000
+#define DDRSS_PI_280_DATA 0x00000000
+#define DDRSS_PI_281_DATA 0x00040404
+#define DDRSS_PI_282_DATA 0x00000000
+#define DDRSS_PI_283_DATA 0x02010102
+#define DDRSS_PI_284_DATA 0x67676767
+#define DDRSS_PI_285_DATA 0x00000202
+#define DDRSS_PI_286_DATA 0x00000000
+#define DDRSS_PI_287_DATA 0x00000000
+#define DDRSS_PI_288_DATA 0x00000000
+#define DDRSS_PI_289_DATA 0x00000000
+#define DDRSS_PI_290_DATA 0x00000000
+#define DDRSS_PI_291_DATA 0x0D100F00
+#define DDRSS_PI_292_DATA 0x0003020E
+#define DDRSS_PI_293_DATA 0x00000001
+#define DDRSS_PI_294_DATA 0x01000000
+#define DDRSS_PI_295_DATA 0x00020201
+#define DDRSS_PI_296_DATA 0x00000000
+#define DDRSS_PI_297_DATA 0x00000424
+#define DDRSS_PI_298_DATA 0x00000301
+#define DDRSS_PI_299_DATA 0x000000C0
+#define DDRSS_PI_300_DATA 0x00000000
+#define DDRSS_PI_301_DATA 0x0000000C
+#define DDRSS_PI_302_DATA 0x00001401
+#define DDRSS_PI_303_DATA 0x00000493
+#define DDRSS_PI_304_DATA 0x00000000
+#define DDRSS_PI_305_DATA 0x00000424
+#define DDRSS_PI_306_DATA 0x00000301
+#define DDRSS_PI_307_DATA 0x000000C0
+#define DDRSS_PI_308_DATA 0x00000000
+#define DDRSS_PI_309_DATA 0x0000000C
+#define DDRSS_PI_310_DATA 0x00001401
+#define DDRSS_PI_311_DATA 0x00000493
+#define DDRSS_PI_312_DATA 0x00000000
+#define DDRSS_PI_313_DATA 0x00000424
+#define DDRSS_PI_314_DATA 0x00000301
+#define DDRSS_PI_315_DATA 0x000000C0
+#define DDRSS_PI_316_DATA 0x00000000
+#define DDRSS_PI_317_DATA 0x0000000C
+#define DDRSS_PI_318_DATA 0x00001401
+#define DDRSS_PI_319_DATA 0x00000493
+#define DDRSS_PI_320_DATA 0x00000000
+#define DDRSS_PI_321_DATA 0x00000424
+#define DDRSS_PI_322_DATA 0x00000301
+#define DDRSS_PI_323_DATA 0x000000C0
+#define DDRSS_PI_324_DATA 0x00000000
+#define DDRSS_PI_325_DATA 0x0000000C
+#define DDRSS_PI_326_DATA 0x00001401
+#define DDRSS_PI_327_DATA 0x00000493
+#define DDRSS_PI_328_DATA 0x00000000
+#define DDRSS_PI_329_DATA 0x00000424
+#define DDRSS_PI_330_DATA 0x00000301
+#define DDRSS_PI_331_DATA 0x000000C0
+#define DDRSS_PI_332_DATA 0x00000000
+#define DDRSS_PI_333_DATA 0x0000000C
+#define DDRSS_PI_334_DATA 0x00001401
+#define DDRSS_PI_335_DATA 0x00000493
+#define DDRSS_PI_336_DATA 0x00000000
+#define DDRSS_PI_337_DATA 0x00000424
+#define DDRSS_PI_338_DATA 0x00000301
+#define DDRSS_PI_339_DATA 0x000000C0
+#define DDRSS_PI_340_DATA 0x00000000
+#define DDRSS_PI_341_DATA 0x0000000C
+#define DDRSS_PI_342_DATA 0x00001401
+#define DDRSS_PI_343_DATA 0x00000493
+#define DDRSS_PI_344_DATA 0x00000000
+#define DDRSS_PHY_0_DATA 0x04C00000
+#define DDRSS_PHY_1_DATA 0x00000000
+#define DDRSS_PHY_2_DATA 0x00000200
+#define DDRSS_PHY_3_DATA 0x00000000
+#define DDRSS_PHY_4_DATA 0x00000000
+#define DDRSS_PHY_5_DATA 0x00000000
+#define DDRSS_PHY_6_DATA 0x00000000
+#define DDRSS_PHY_7_DATA 0x00000000
+#define DDRSS_PHY_8_DATA 0x00000001
+#define DDRSS_PHY_9_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x010101FF
+#define DDRSS_PHY_12_DATA 0x00010000
+#define DDRSS_PHY_13_DATA 0x00C00004
+#define DDRSS_PHY_14_DATA 0x00CC0008
+#define DDRSS_PHY_15_DATA 0x00660201
+#define DDRSS_PHY_16_DATA 0x00000000
+#define DDRSS_PHY_17_DATA 0x00000000
+#define DDRSS_PHY_18_DATA 0x00000000
+#define DDRSS_PHY_19_DATA 0x0000AAAA
+#define DDRSS_PHY_20_DATA 0x00005555
+#define DDRSS_PHY_21_DATA 0x0000B5B5
+#define DDRSS_PHY_22_DATA 0x00004A4A
+#define DDRSS_PHY_23_DATA 0x00005656
+#define DDRSS_PHY_24_DATA 0x0000A9A9
+#define DDRSS_PHY_25_DATA 0x0000B7B7
+#define DDRSS_PHY_26_DATA 0x00004848
+#define DDRSS_PHY_27_DATA 0x00000000
+#define DDRSS_PHY_28_DATA 0x00000000
+#define DDRSS_PHY_29_DATA 0x08000000
+#define DDRSS_PHY_30_DATA 0x0F000008
+#define DDRSS_PHY_31_DATA 0x00000F0F
+#define DDRSS_PHY_32_DATA 0x00E4E400
+#define DDRSS_PHY_33_DATA 0x00070820
+#define DDRSS_PHY_34_DATA 0x000C0020
+#define DDRSS_PHY_35_DATA 0x00062000
+#define DDRSS_PHY_36_DATA 0x00000000
+#define DDRSS_PHY_37_DATA 0x55555555
+#define DDRSS_PHY_38_DATA 0xAAAAAAAA
+#define DDRSS_PHY_39_DATA 0x55555555
+#define DDRSS_PHY_40_DATA 0xAAAAAAAA
+#define DDRSS_PHY_41_DATA 0x00005555
+#define DDRSS_PHY_42_DATA 0x01000100
+#define DDRSS_PHY_43_DATA 0x00800180
+#define DDRSS_PHY_44_DATA 0x00000000
+#define DDRSS_PHY_45_DATA 0x00000000
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000004
+#define DDRSS_PHY_66_DATA 0x00000000
+#define DDRSS_PHY_67_DATA 0x00000000
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x041F07FF
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x01CCB001
+#define DDRSS_PHY_75_DATA 0x2000CCB0
+#define DDRSS_PHY_76_DATA 0x20000140
+#define DDRSS_PHY_77_DATA 0x07FF0200
+#define DDRSS_PHY_78_DATA 0x0000DD01
+#define DDRSS_PHY_79_DATA 0x10100303
+#define DDRSS_PHY_80_DATA 0x10101010
+#define DDRSS_PHY_81_DATA 0x10101010
+#define DDRSS_PHY_82_DATA 0x00021010
+#define DDRSS_PHY_83_DATA 0x00100010
+#define DDRSS_PHY_84_DATA 0x00100010
+#define DDRSS_PHY_85_DATA 0x00100010
+#define DDRSS_PHY_86_DATA 0x00100010
+#define DDRSS_PHY_87_DATA 0x02020010
+#define DDRSS_PHY_88_DATA 0x51515041
+#define DDRSS_PHY_89_DATA 0x31804000
+#define DDRSS_PHY_90_DATA 0x04BF0340
+#define DDRSS_PHY_91_DATA 0x01008080
+#define DDRSS_PHY_92_DATA 0x04050001
+#define DDRSS_PHY_93_DATA 0x00000504
+#define DDRSS_PHY_94_DATA 0x42100010
+#define DDRSS_PHY_95_DATA 0x010C053E
+#define DDRSS_PHY_96_DATA 0x000F0C14
+#define DDRSS_PHY_97_DATA 0x01000140
+#define DDRSS_PHY_98_DATA 0x007A0120
+#define DDRSS_PHY_99_DATA 0x00000C00
+#define DDRSS_PHY_100_DATA 0x000001CC
+#define DDRSS_PHY_101_DATA 0x20100200
+#define DDRSS_PHY_102_DATA 0x00000005
+#define DDRSS_PHY_103_DATA 0x76543210
+#define DDRSS_PHY_104_DATA 0x00000008
+#define DDRSS_PHY_105_DATA 0x02800280
+#define DDRSS_PHY_106_DATA 0x02800280
+#define DDRSS_PHY_107_DATA 0x02800280
+#define DDRSS_PHY_108_DATA 0x02800280
+#define DDRSS_PHY_109_DATA 0x00000280
+#define DDRSS_PHY_110_DATA 0x00008000
+#define DDRSS_PHY_111_DATA 0x00800080
+#define DDRSS_PHY_112_DATA 0x00800080
+#define DDRSS_PHY_113_DATA 0x00800080
+#define DDRSS_PHY_114_DATA 0x00800080
+#define DDRSS_PHY_115_DATA 0x00800080
+#define DDRSS_PHY_116_DATA 0x00800080
+#define DDRSS_PHY_117_DATA 0x00800080
+#define DDRSS_PHY_118_DATA 0x00800080
+#define DDRSS_PHY_119_DATA 0x01000080
+#define DDRSS_PHY_120_DATA 0x01000000
+#define DDRSS_PHY_121_DATA 0x00000000
+#define DDRSS_PHY_122_DATA 0x00000000
+#define DDRSS_PHY_123_DATA 0x00080200
+#define DDRSS_PHY_124_DATA 0x00000000
+#define DDRSS_PHY_125_DATA 0x00000000
+#define DDRSS_PHY_126_DATA 0x00000000
+#define DDRSS_PHY_127_DATA 0x00000000
+#define DDRSS_PHY_128_DATA 0x00000000
+#define DDRSS_PHY_129_DATA 0x00000000
+#define DDRSS_PHY_130_DATA 0x00000000
+#define DDRSS_PHY_131_DATA 0x00000000
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x00000000
+#define DDRSS_PHY_134_DATA 0x00000000
+#define DDRSS_PHY_135_DATA 0x00000000
+#define DDRSS_PHY_136_DATA 0x00000000
+#define DDRSS_PHY_137_DATA 0x00000000
+#define DDRSS_PHY_138_DATA 0x00000000
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x04C00000
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00000200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x00000000
+#define DDRSS_PHY_262_DATA 0x00000000
+#define DDRSS_PHY_263_DATA 0x00000000
+#define DDRSS_PHY_264_DATA 0x00000001
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x010101FF
+#define DDRSS_PHY_268_DATA 0x00010000
+#define DDRSS_PHY_269_DATA 0x00C00004
+#define DDRSS_PHY_270_DATA 0x00CC0008
+#define DDRSS_PHY_271_DATA 0x00660201
+#define DDRSS_PHY_272_DATA 0x00000000
+#define DDRSS_PHY_273_DATA 0x00000000
+#define DDRSS_PHY_274_DATA 0x00000000
+#define DDRSS_PHY_275_DATA 0x0000AAAA
+#define DDRSS_PHY_276_DATA 0x00005555
+#define DDRSS_PHY_277_DATA 0x0000B5B5
+#define DDRSS_PHY_278_DATA 0x00004A4A
+#define DDRSS_PHY_279_DATA 0x00005656
+#define DDRSS_PHY_280_DATA 0x0000A9A9
+#define DDRSS_PHY_281_DATA 0x0000B7B7
+#define DDRSS_PHY_282_DATA 0x00004848
+#define DDRSS_PHY_283_DATA 0x00000000
+#define DDRSS_PHY_284_DATA 0x00000000
+#define DDRSS_PHY_285_DATA 0x08000000
+#define DDRSS_PHY_286_DATA 0x0F000008
+#define DDRSS_PHY_287_DATA 0x00000F0F
+#define DDRSS_PHY_288_DATA 0x00E4E400
+#define DDRSS_PHY_289_DATA 0x00070820
+#define DDRSS_PHY_290_DATA 0x000C0020
+#define DDRSS_PHY_291_DATA 0x00062000
+#define DDRSS_PHY_292_DATA 0x00000000
+#define DDRSS_PHY_293_DATA 0x55555555
+#define DDRSS_PHY_294_DATA 0xAAAAAAAA
+#define DDRSS_PHY_295_DATA 0x55555555
+#define DDRSS_PHY_296_DATA 0xAAAAAAAA
+#define DDRSS_PHY_297_DATA 0x00005555
+#define DDRSS_PHY_298_DATA 0x01000100
+#define DDRSS_PHY_299_DATA 0x00800180
+#define DDRSS_PHY_300_DATA 0x00000000
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000004
+#define DDRSS_PHY_322_DATA 0x00000000
+#define DDRSS_PHY_323_DATA 0x00000000
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x041F07FF
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x01CCB001
+#define DDRSS_PHY_331_DATA 0x2000CCB0
+#define DDRSS_PHY_332_DATA 0x20000140
+#define DDRSS_PHY_333_DATA 0x07FF0200
+#define DDRSS_PHY_334_DATA 0x0000DD01
+#define DDRSS_PHY_335_DATA 0x10100303
+#define DDRSS_PHY_336_DATA 0x10101010
+#define DDRSS_PHY_337_DATA 0x10101010
+#define DDRSS_PHY_338_DATA 0x00021010
+#define DDRSS_PHY_339_DATA 0x00100010
+#define DDRSS_PHY_340_DATA 0x00100010
+#define DDRSS_PHY_341_DATA 0x00100010
+#define DDRSS_PHY_342_DATA 0x00100010
+#define DDRSS_PHY_343_DATA 0x02020010
+#define DDRSS_PHY_344_DATA 0x51515041
+#define DDRSS_PHY_345_DATA 0x31804000
+#define DDRSS_PHY_346_DATA 0x04BF0340
+#define DDRSS_PHY_347_DATA 0x01008080
+#define DDRSS_PHY_348_DATA 0x04050001
+#define DDRSS_PHY_349_DATA 0x00000504
+#define DDRSS_PHY_350_DATA 0x42100010
+#define DDRSS_PHY_351_DATA 0x010C053E
+#define DDRSS_PHY_352_DATA 0x000F0C14
+#define DDRSS_PHY_353_DATA 0x01000140
+#define DDRSS_PHY_354_DATA 0x007A0120
+#define DDRSS_PHY_355_DATA 0x00000C00
+#define DDRSS_PHY_356_DATA 0x000001CC
+#define DDRSS_PHY_357_DATA 0x20100200
+#define DDRSS_PHY_358_DATA 0x00000005
+#define DDRSS_PHY_359_DATA 0x76543210
+#define DDRSS_PHY_360_DATA 0x00000008
+#define DDRSS_PHY_361_DATA 0x02800280
+#define DDRSS_PHY_362_DATA 0x02800280
+#define DDRSS_PHY_363_DATA 0x02800280
+#define DDRSS_PHY_364_DATA 0x02800280
+#define DDRSS_PHY_365_DATA 0x00000280
+#define DDRSS_PHY_366_DATA 0x00008000
+#define DDRSS_PHY_367_DATA 0x00800080
+#define DDRSS_PHY_368_DATA 0x00800080
+#define DDRSS_PHY_369_DATA 0x00800080
+#define DDRSS_PHY_370_DATA 0x00800080
+#define DDRSS_PHY_371_DATA 0x00800080
+#define DDRSS_PHY_372_DATA 0x00800080
+#define DDRSS_PHY_373_DATA 0x00800080
+#define DDRSS_PHY_374_DATA 0x00800080
+#define DDRSS_PHY_375_DATA 0x01000080
+#define DDRSS_PHY_376_DATA 0x01000000
+#define DDRSS_PHY_377_DATA 0x00000000
+#define DDRSS_PHY_378_DATA 0x00000000
+#define DDRSS_PHY_379_DATA 0x00080200
+#define DDRSS_PHY_380_DATA 0x00000000
+#define DDRSS_PHY_381_DATA 0x00000000
+#define DDRSS_PHY_382_DATA 0x00000000
+#define DDRSS_PHY_383_DATA 0x00000000
+#define DDRSS_PHY_384_DATA 0x00000000
+#define DDRSS_PHY_385_DATA 0x00000000
+#define DDRSS_PHY_386_DATA 0x00000000
+#define DDRSS_PHY_387_DATA 0x00000000
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x00000000
+#define DDRSS_PHY_390_DATA 0x00000000
+#define DDRSS_PHY_391_DATA 0x00000000
+#define DDRSS_PHY_392_DATA 0x00000000
+#define DDRSS_PHY_393_DATA 0x00000000
+#define DDRSS_PHY_394_DATA 0x00000000
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x00000100
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00000000
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x00000100
+#define DDRSS_PHY_518_DATA 0x00000000
+#define DDRSS_PHY_519_DATA 0x00000000
+#define DDRSS_PHY_520_DATA 0x00000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x00000000
+#define DDRSS_PHY_524_DATA 0x00000000
+#define DDRSS_PHY_525_DATA 0x00DCBA98
+#define DDRSS_PHY_526_DATA 0x00000000
+#define DDRSS_PHY_527_DATA 0x00000000
+#define DDRSS_PHY_528_DATA 0x00000000
+#define DDRSS_PHY_529_DATA 0x00000000
+#define DDRSS_PHY_530_DATA 0x00000000
+#define DDRSS_PHY_531_DATA 0x00000000
+#define DDRSS_PHY_532_DATA 0x00000000
+#define DDRSS_PHY_533_DATA 0x00000000
+#define DDRSS_PHY_534_DATA 0x00000000
+#define DDRSS_PHY_535_DATA 0x00000000
+#define DDRSS_PHY_536_DATA 0x00000000
+#define DDRSS_PHY_537_DATA 0x00000000
+#define DDRSS_PHY_538_DATA 0x00000000
+#define DDRSS_PHY_539_DATA 0x00000000
+#define DDRSS_PHY_540_DATA 0x0A418820
+#define DDRSS_PHY_541_DATA 0x103F0000
+#define DDRSS_PHY_542_DATA 0x000F0100
+#define DDRSS_PHY_543_DATA 0x0000000F
+#define DDRSS_PHY_544_DATA 0x020002CC
+#define DDRSS_PHY_545_DATA 0x00030000
+#define DDRSS_PHY_546_DATA 0x00000300
+#define DDRSS_PHY_547_DATA 0x00000300
+#define DDRSS_PHY_548_DATA 0x00000300
+#define DDRSS_PHY_549_DATA 0x00000300
+#define DDRSS_PHY_550_DATA 0x00000300
+#define DDRSS_PHY_551_DATA 0x42080010
+#define DDRSS_PHY_552_DATA 0x0000003E
+#define DDRSS_PHY_553_DATA 0x00000000
+#define DDRSS_PHY_554_DATA 0x00000000
+#define DDRSS_PHY_555_DATA 0x00000000
+#define DDRSS_PHY_556_DATA 0x00000000
+#define DDRSS_PHY_557_DATA 0x00000000
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000000
+#define DDRSS_PHY_579_DATA 0x00000000
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x00000000
+#define DDRSS_PHY_587_DATA 0x00000000
+#define DDRSS_PHY_588_DATA 0x00000000
+#define DDRSS_PHY_589_DATA 0x00000000
+#define DDRSS_PHY_590_DATA 0x00000000
+#define DDRSS_PHY_591_DATA 0x00000000
+#define DDRSS_PHY_592_DATA 0x00000000
+#define DDRSS_PHY_593_DATA 0x00000000
+#define DDRSS_PHY_594_DATA 0x00000000
+#define DDRSS_PHY_595_DATA 0x00000000
+#define DDRSS_PHY_596_DATA 0x00000000
+#define DDRSS_PHY_597_DATA 0x00000000
+#define DDRSS_PHY_598_DATA 0x00000000
+#define DDRSS_PHY_599_DATA 0x00000000
+#define DDRSS_PHY_600_DATA 0x00000000
+#define DDRSS_PHY_601_DATA 0x00000000
+#define DDRSS_PHY_602_DATA 0x00000000
+#define DDRSS_PHY_603_DATA 0x00000000
+#define DDRSS_PHY_604_DATA 0x00000000
+#define DDRSS_PHY_605_DATA 0x00000000
+#define DDRSS_PHY_606_DATA 0x00000000
+#define DDRSS_PHY_607_DATA 0x00000000
+#define DDRSS_PHY_608_DATA 0x00000000
+#define DDRSS_PHY_609_DATA 0x00000000
+#define DDRSS_PHY_610_DATA 0x00000000
+#define DDRSS_PHY_611_DATA 0x00000000
+#define DDRSS_PHY_612_DATA 0x00000000
+#define DDRSS_PHY_613_DATA 0x00000000
+#define DDRSS_PHY_614_DATA 0x00000000
+#define DDRSS_PHY_615_DATA 0x00000000
+#define DDRSS_PHY_616_DATA 0x00000000
+#define DDRSS_PHY_617_DATA 0x00000000
+#define DDRSS_PHY_618_DATA 0x00000000
+#define DDRSS_PHY_619_DATA 0x00000000
+#define DDRSS_PHY_620_DATA 0x00000000
+#define DDRSS_PHY_621_DATA 0x00000000
+#define DDRSS_PHY_622_DATA 0x00000000
+#define DDRSS_PHY_623_DATA 0x00000000
+#define DDRSS_PHY_624_DATA 0x00000000
+#define DDRSS_PHY_625_DATA 0x00000000
+#define DDRSS_PHY_626_DATA 0x00000000
+#define DDRSS_PHY_627_DATA 0x00000000
+#define DDRSS_PHY_628_DATA 0x00000000
+#define DDRSS_PHY_629_DATA 0x00000000
+#define DDRSS_PHY_630_DATA 0x00000000
+#define DDRSS_PHY_631_DATA 0x00000000
+#define DDRSS_PHY_632_DATA 0x00000000
+#define DDRSS_PHY_633_DATA 0x00000000
+#define DDRSS_PHY_634_DATA 0x00000000
+#define DDRSS_PHY_635_DATA 0x00000000
+#define DDRSS_PHY_636_DATA 0x00000000
+#define DDRSS_PHY_637_DATA 0x00000000
+#define DDRSS_PHY_638_DATA 0x00000000
+#define DDRSS_PHY_639_DATA 0x00000000
+#define DDRSS_PHY_640_DATA 0x00000000
+#define DDRSS_PHY_641_DATA 0x00000000
+#define DDRSS_PHY_642_DATA 0x00000000
+#define DDRSS_PHY_643_DATA 0x00000000
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x00000000
+#define DDRSS_PHY_646_DATA 0x00000000
+#define DDRSS_PHY_647_DATA 0x00000000
+#define DDRSS_PHY_648_DATA 0x00000000
+#define DDRSS_PHY_649_DATA 0x00000000
+#define DDRSS_PHY_650_DATA 0x00000000
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x00000100
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00000000
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x00000100
+#define DDRSS_PHY_774_DATA 0x00000000
+#define DDRSS_PHY_775_DATA 0x00000000
+#define DDRSS_PHY_776_DATA 0x00000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x00000000
+#define DDRSS_PHY_780_DATA 0x00000000
+#define DDRSS_PHY_781_DATA 0x00DCBA98
+#define DDRSS_PHY_782_DATA 0x00000000
+#define DDRSS_PHY_783_DATA 0x00000000
+#define DDRSS_PHY_784_DATA 0x00000000
+#define DDRSS_PHY_785_DATA 0x00000000
+#define DDRSS_PHY_786_DATA 0x00000000
+#define DDRSS_PHY_787_DATA 0x00000000
+#define DDRSS_PHY_788_DATA 0x00000000
+#define DDRSS_PHY_789_DATA 0x00000000
+#define DDRSS_PHY_790_DATA 0x00000000
+#define DDRSS_PHY_791_DATA 0x00000000
+#define DDRSS_PHY_792_DATA 0x00000000
+#define DDRSS_PHY_793_DATA 0x00000000
+#define DDRSS_PHY_794_DATA 0x00000000
+#define DDRSS_PHY_795_DATA 0x00000000
+#define DDRSS_PHY_796_DATA 0x16A4A0E6
+#define DDRSS_PHY_797_DATA 0x103F0000
+#define DDRSS_PHY_798_DATA 0x000F0000
+#define DDRSS_PHY_799_DATA 0x0000000F
+#define DDRSS_PHY_800_DATA 0x020002CC
+#define DDRSS_PHY_801_DATA 0x00030000
+#define DDRSS_PHY_802_DATA 0x00000300
+#define DDRSS_PHY_803_DATA 0x00000300
+#define DDRSS_PHY_804_DATA 0x00000300
+#define DDRSS_PHY_805_DATA 0x00000300
+#define DDRSS_PHY_806_DATA 0x00000300
+#define DDRSS_PHY_807_DATA 0x42080010
+#define DDRSS_PHY_808_DATA 0x0000003E
+#define DDRSS_PHY_809_DATA 0x00000000
+#define DDRSS_PHY_810_DATA 0x00000000
+#define DDRSS_PHY_811_DATA 0x00000000
+#define DDRSS_PHY_812_DATA 0x00000000
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000000
+#define DDRSS_PHY_835_DATA 0x00000000
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x00000000
+#define DDRSS_PHY_843_DATA 0x00000000
+#define DDRSS_PHY_844_DATA 0x00000000
+#define DDRSS_PHY_845_DATA 0x00000000
+#define DDRSS_PHY_846_DATA 0x00000000
+#define DDRSS_PHY_847_DATA 0x00000000
+#define DDRSS_PHY_848_DATA 0x00000000
+#define DDRSS_PHY_849_DATA 0x00000000
+#define DDRSS_PHY_850_DATA 0x00000000
+#define DDRSS_PHY_851_DATA 0x00000000
+#define DDRSS_PHY_852_DATA 0x00000000
+#define DDRSS_PHY_853_DATA 0x00000000
+#define DDRSS_PHY_854_DATA 0x00000000
+#define DDRSS_PHY_855_DATA 0x00000000
+#define DDRSS_PHY_856_DATA 0x00000000
+#define DDRSS_PHY_857_DATA 0x00000000
+#define DDRSS_PHY_858_DATA 0x00000000
+#define DDRSS_PHY_859_DATA 0x00000000
+#define DDRSS_PHY_860_DATA 0x00000000
+#define DDRSS_PHY_861_DATA 0x00000000
+#define DDRSS_PHY_862_DATA 0x00000000
+#define DDRSS_PHY_863_DATA 0x00000000
+#define DDRSS_PHY_864_DATA 0x00000000
+#define DDRSS_PHY_865_DATA 0x00000000
+#define DDRSS_PHY_866_DATA 0x00000000
+#define DDRSS_PHY_867_DATA 0x00000000
+#define DDRSS_PHY_868_DATA 0x00000000
+#define DDRSS_PHY_869_DATA 0x00000000
+#define DDRSS_PHY_870_DATA 0x00000000
+#define DDRSS_PHY_871_DATA 0x00000000
+#define DDRSS_PHY_872_DATA 0x00000000
+#define DDRSS_PHY_873_DATA 0x00000000
+#define DDRSS_PHY_874_DATA 0x00000000
+#define DDRSS_PHY_875_DATA 0x00000000
+#define DDRSS_PHY_876_DATA 0x00000000
+#define DDRSS_PHY_877_DATA 0x00000000
+#define DDRSS_PHY_878_DATA 0x00000000
+#define DDRSS_PHY_879_DATA 0x00000000
+#define DDRSS_PHY_880_DATA 0x00000000
+#define DDRSS_PHY_881_DATA 0x00000000
+#define DDRSS_PHY_882_DATA 0x00000000
+#define DDRSS_PHY_883_DATA 0x00000000
+#define DDRSS_PHY_884_DATA 0x00000000
+#define DDRSS_PHY_885_DATA 0x00000000
+#define DDRSS_PHY_886_DATA 0x00000000
+#define DDRSS_PHY_887_DATA 0x00000000
+#define DDRSS_PHY_888_DATA 0x00000000
+#define DDRSS_PHY_889_DATA 0x00000000
+#define DDRSS_PHY_890_DATA 0x00000000
+#define DDRSS_PHY_891_DATA 0x00000000
+#define DDRSS_PHY_892_DATA 0x00000000
+#define DDRSS_PHY_893_DATA 0x00000000
+#define DDRSS_PHY_894_DATA 0x00000000
+#define DDRSS_PHY_895_DATA 0x00000000
+#define DDRSS_PHY_896_DATA 0x00000000
+#define DDRSS_PHY_897_DATA 0x00000000
+#define DDRSS_PHY_898_DATA 0x00000000
+#define DDRSS_PHY_899_DATA 0x00000000
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x00000000
+#define DDRSS_PHY_902_DATA 0x00000000
+#define DDRSS_PHY_903_DATA 0x00000000
+#define DDRSS_PHY_904_DATA 0x00000000
+#define DDRSS_PHY_905_DATA 0x00000000
+#define DDRSS_PHY_906_DATA 0x00000000
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000100
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000000
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00000000
+#define DDRSS_PHY_1036_DATA 0x00000000
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x00000000
+#define DDRSS_PHY_1039_DATA 0x00000000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x00000000
+#define DDRSS_PHY_1045_DATA 0x00000000
+#define DDRSS_PHY_1046_DATA 0x00000000
+#define DDRSS_PHY_1047_DATA 0x00000000
+#define DDRSS_PHY_1048_DATA 0x00000000
+#define DDRSS_PHY_1049_DATA 0x00000000
+#define DDRSS_PHY_1050_DATA 0x00000000
+#define DDRSS_PHY_1051_DATA 0x00000000
+#define DDRSS_PHY_1052_DATA 0x2307B9AC
+#define DDRSS_PHY_1053_DATA 0x10030000
+#define DDRSS_PHY_1054_DATA 0x000F0000
+#define DDRSS_PHY_1055_DATA 0x0000000F
+#define DDRSS_PHY_1056_DATA 0x020002CC
+#define DDRSS_PHY_1057_DATA 0x00030000
+#define DDRSS_PHY_1058_DATA 0x00000300
+#define DDRSS_PHY_1059_DATA 0x00000300
+#define DDRSS_PHY_1060_DATA 0x00000300
+#define DDRSS_PHY_1061_DATA 0x00000300
+#define DDRSS_PHY_1062_DATA 0x00000300
+#define DDRSS_PHY_1063_DATA 0x42080010
+#define DDRSS_PHY_1064_DATA 0x0000003E
+#define DDRSS_PHY_1065_DATA 0x00000000
+#define DDRSS_PHY_1066_DATA 0x00000000
+#define DDRSS_PHY_1067_DATA 0x00000000
+#define DDRSS_PHY_1068_DATA 0x00000000
+#define DDRSS_PHY_1069_DATA 0x00000000
+#define DDRSS_PHY_1070_DATA 0x00000000
+#define DDRSS_PHY_1071_DATA 0x00000000
+#define DDRSS_PHY_1072_DATA 0x00000000
+#define DDRSS_PHY_1073_DATA 0x00000000
+#define DDRSS_PHY_1074_DATA 0x00000000
+#define DDRSS_PHY_1075_DATA 0x00000000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00000100
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00000000
+#define DDRSS_PHY_1285_DATA 0x00000000
+#define DDRSS_PHY_1286_DATA 0x00050000
+#define DDRSS_PHY_1287_DATA 0x04000100
+#define DDRSS_PHY_1288_DATA 0x00000055
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00000000
+#define DDRSS_PHY_1292_DATA 0x00000000
+#define DDRSS_PHY_1293_DATA 0x01002000
+#define DDRSS_PHY_1294_DATA 0x00004001
+#define DDRSS_PHY_1295_DATA 0x00020028
+#define DDRSS_PHY_1296_DATA 0x00010100
+#define DDRSS_PHY_1297_DATA 0x00000001
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x0F0F0E06
+#define DDRSS_PHY_1300_DATA 0x00010101
+#define DDRSS_PHY_1301_DATA 0x010F0004
+#define DDRSS_PHY_1302_DATA 0x00000000
+#define DDRSS_PHY_1303_DATA 0x00000000
+#define DDRSS_PHY_1304_DATA 0x00000064
+#define DDRSS_PHY_1305_DATA 0x00000000
+#define DDRSS_PHY_1306_DATA 0x00000000
+#define DDRSS_PHY_1307_DATA 0x01020103
+#define DDRSS_PHY_1308_DATA 0x0F020102
+#define DDRSS_PHY_1309_DATA 0x03030303
+#define DDRSS_PHY_1310_DATA 0x03030303
+#define DDRSS_PHY_1311_DATA 0x00040000
+#define DDRSS_PHY_1312_DATA 0x00005201
+#define DDRSS_PHY_1313_DATA 0x00000000
+#define DDRSS_PHY_1314_DATA 0x00000000
+#define DDRSS_PHY_1315_DATA 0x00000000
+#define DDRSS_PHY_1316_DATA 0x00000000
+#define DDRSS_PHY_1317_DATA 0x00000000
+#define DDRSS_PHY_1318_DATA 0x00000000
+#define DDRSS_PHY_1319_DATA 0x07070001
+#define DDRSS_PHY_1320_DATA 0x00005400
+#define DDRSS_PHY_1321_DATA 0x000040A2
+#define DDRSS_PHY_1322_DATA 0x00024410
+#define DDRSS_PHY_1323_DATA 0x00004410
+#define DDRSS_PHY_1324_DATA 0x00004410
+#define DDRSS_PHY_1325_DATA 0x00004410
+#define DDRSS_PHY_1326_DATA 0x00004410
+#define DDRSS_PHY_1327_DATA 0x00004410
+#define DDRSS_PHY_1328_DATA 0x00004410
+#define DDRSS_PHY_1329_DATA 0x00004410
+#define DDRSS_PHY_1330_DATA 0x00004410
+#define DDRSS_PHY_1331_DATA 0x00004410
+#define DDRSS_PHY_1332_DATA 0x00000000
+#define DDRSS_PHY_1333_DATA 0x00000046
+#define DDRSS_PHY_1334_DATA 0x00000400
+#define DDRSS_PHY_1335_DATA 0x00000008
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x00000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x03000000
+#define DDRSS_PHY_1342_DATA 0x00000000
+#define DDRSS_PHY_1343_DATA 0x00000000
+#define DDRSS_PHY_1344_DATA 0x00000000
+#define DDRSS_PHY_1345_DATA 0x04102006
+#define DDRSS_PHY_1346_DATA 0x00041020
+#define DDRSS_PHY_1347_DATA 0x01C98C98
+#define DDRSS_PHY_1348_DATA 0x3F400000
+#define DDRSS_PHY_1349_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1350_DATA 0x0000001F
+#define DDRSS_PHY_1351_DATA 0x00000000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000001
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x00000000
+#define DDRSS_PHY_1357_DATA 0x00000000
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x76543210
+#define DDRSS_PHY_1360_DATA 0x00000098
+#define DDRSS_PHY_1361_DATA 0x00000000
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00040700
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000000
+#define DDRSS_PHY_1368_DATA 0x00000002
+#define DDRSS_PHY_1369_DATA 0x00000100
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x00000FC3
+#define DDRSS_PHY_1372_DATA 0x00020002
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00001142
+#define DDRSS_PHY_1375_DATA 0x03020400
+#define DDRSS_PHY_1376_DATA 0x00000080
+#define DDRSS_PHY_1377_DATA 0x03900390
+#define DDRSS_PHY_1378_DATA 0x03900390
+#define DDRSS_PHY_1379_DATA 0x03900390
+#define DDRSS_PHY_1380_DATA 0x03900390
+#define DDRSS_PHY_1381_DATA 0x03900390
+#define DDRSS_PHY_1382_DATA 0x03900390
+#define DDRSS_PHY_1383_DATA 0x00000300
+#define DDRSS_PHY_1384_DATA 0x00000300
+#define DDRSS_PHY_1385_DATA 0x00000300
+#define DDRSS_PHY_1386_DATA 0x00000300
+#define DDRSS_PHY_1387_DATA 0x31823FC7
+#define DDRSS_PHY_1388_DATA 0x00000000
+#define DDRSS_PHY_1389_DATA 0x0C000D3F
+#define DDRSS_PHY_1390_DATA 0x30000D3F
+#define DDRSS_PHY_1391_DATA 0x300D3F11
+#define DDRSS_PHY_1392_DATA 0x01990000
+#define DDRSS_PHY_1393_DATA 0x000D3FCC
+#define DDRSS_PHY_1394_DATA 0x00000C11
+#define DDRSS_PHY_1395_DATA 0x300D3F11
+#define DDRSS_PHY_1396_DATA 0x01990000
+#define DDRSS_PHY_1397_DATA 0x300C3F11
+#define DDRSS_PHY_1398_DATA 0x01990000
+#define DDRSS_PHY_1399_DATA 0x300C3F11
+#define DDRSS_PHY_1400_DATA 0x01990000
+#define DDRSS_PHY_1401_DATA 0x300D3F11
+#define DDRSS_PHY_1402_DATA 0x01990000
+#define DDRSS_PHY_1403_DATA 0x300D3F11
+#define DDRSS_PHY_1404_DATA 0x01990000
+#define DDRSS_PHY_1405_DATA 0x20040004
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ *
+ * Product homepage:
+ * https://www.phytec.com/product/phycore-am62x
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ model = "PHYTEC phyCORE-AM62x";
+ compatible = "phytec,am62-phycore-som", "ti,am625";
+
+ aliases {
+ ethernet0 = &cpsw_port1;
+ gpio0 = &main_gpio0;
+ gpio1 = &main_gpio1;
+ i2c0 = &main_i2c0;
+ mmc0 = &sdhci0;
+ rtc0 = &i2c_som_rtc;
+ rtc1 = &wkup_rtc0;
+ spi0 = &ospi0;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ramoops@9ca00000 {
+ compatible = "ramoops";
+ reg = <0x00 0x9ca00000 0x00 0x00100000>;
+ record-size = <0x8000>;
+ console-size = <0x8000>;
+ ftrace-size = <0x00>;
+ pmsg-size = <0x8000>;
+ };
+
+ secure_tfa_ddr: tfa@9e780000 {
+ reg = <0x00 0x9e780000 0x00 0x80000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+ alignment = <0x1000>;
+ no-map;
+ };
+
+ wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9db00000 0x00 0x00c00000>;
+ no-map;
+ };
+ };
+
+ vcc_5v0_som: regulator-vcc-5v0-som {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_5V0_SOM";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v8: regulator-vdd-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_5v0_som>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_pins_default>;
+
+ led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&main_gpio0 13 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ function = LED_FUNCTION_HEARTBEAT;
+ };
+ };
+};
+
+&main_pmx0 {
+ leds_pins_default: leds-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x034, PIN_OUTPUT, 7) /* (H21) OSPI0_CSN2.GPIO0_13 */
+ >;
+ };
+
+ main_i2c0_pins_default: main-i2c0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
+ AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
+ >;
+ };
+
+ main_mdio1_pins_default: main-mdio1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
+ AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
+ >;
+ };
+
+ main_mmc0_pins_default: main-mmc0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (Y3) MMC0_CMD */
+ AM62X_IOPAD(0x218, PIN_INPUT_PULLDOWN, 0) /* (AB1) MMC0_CLK */
+ AM62X_IOPAD(0x214, PIN_INPUT_PULLUP, 0) /* (AA2) MMC0_DAT0 */
+ AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */
+ AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */
+ AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */
+ AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */
+ AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
+ AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
+ AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
+ >;
+ };
+
+ main_rgmii1_pins_default: main-rgmii1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
+ AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
+ AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
+ AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
+ AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
+ AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
+ AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
+ AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
+ AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
+ AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
+ AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
+ AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
+ >;
+ };
+
+ ospi0_pins_default: ospi0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
+ AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
+ AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
+ AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
+ AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
+ AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
+ AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
+ AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
+ AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
+ AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
+ AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
+ >;
+ };
+
+ pmic_irq_pins_default: pmic-irq-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */
+ >;
+ };
+};
+
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_rgmii1_pins_default>;
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy1>;
+};
+
+&cpsw3g_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mdio1_pins_default>;
+ status = "okay";
+
+ cpsw3g_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&main_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ pmic@30 {
+ compatible = "ti,tps65219";
+ reg = <0x30>;
+ buck1-supply = <&vcc_5v0_som>;
+ buck2-supply = <&vcc_5v0_som>;
+ buck3-supply = <&vcc_5v0_som>;
+ ldo1-supply = <&vdd_3v3>;
+ ldo2-supply = <&vdd_1v8>;
+ ldo3-supply = <&vcc_5v0_som>;
+ ldo4-supply = <&vcc_5v0_som>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins_default>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ ti,power-button;
+ system-power-controller;
+
+ regulators {
+ vdd_core: buck1 {
+ regulator-name = "VDD_CORE";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd_3v3: buck2 {
+ regulator-name = "VDD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd_ddr4: buck3 {
+ regulator-name = "VDD_DDR4";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vddshv5_sdio: ldo1 {
+ regulator-name = "VDDSHV5_SDIO";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-allow-bypass;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vddr_core: ldo2 {
+ regulator-name = "VDDR_CORE";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdda_1v8: ldo3 {
+ regulator-name = "VDDA_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd_2v5: ldo4 {
+ regulator-name = "VDD_2V5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ pagesize = <32>;
+ reg = <0x50>;
+ };
+
+ i2c_som_rtc: rtc@52 {
+ compatible = "microcrystal,rv3028";
+ reg = <0x52>;
+ };
+};
+
+&ospi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ospi0_pins_default>;
+ status = "okay";
+
+ serial_flash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <25000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <0>;
+ };
+};
+
+&sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc0_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+ non-removable;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * phyCORE-AM62x dts file for SPLs
+ * Copyright (C) 2022 - 2023 Phytec Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ *
+ * Product homepage:
+ * https://www.phytec.com/product/phyboard-am62x
+ */
+
+#include "k3-am625-phycore-som-binman.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &main_timer0;
+ };
+
+ aliases {
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ };
+
+ memory@80000000 {
+ bootph-all;
+ };
+};
+
+&cpsw3g {
+ bootph-all;
+};
+
+&cpsw_port1 {
+ bootph-all;
+};
+
+&cpsw_port2 {
+ status = "disabled";
+};
+
+&cpsw3g_phy1 {
+ bootph-all;
+};
+
+&dmsc {
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ bootph-all;
+ };
+};
+
+&fss {
+ bootph-all;
+};
+
+&main_bcdma {
+ bootph-all;
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
+ "ringrt" , "cfg", "tchan", "rchan";
+};
+
+&main_gpio0 {
+ bootph-all;
+};
+
+&main_mdio1_pins_default {
+ bootph-all;
+};
+
+&main_i2c0 {
+ bootph-all;
+};
+
+&main_i2c0_pins_default {
+ bootph-all;
+};
+
+&main_mmc0_pins_default {
+ bootph-all;
+};
+
+&main_mmc1_pins_default {
+ bootph-all;
+};
+
+&main_pktdma {
+ bootph-all;
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x20000>,
+ <0x00 0x4b800000 0x00 0x200000>,
+ <0x00 0x485e0000 0x00 0x10000>,
+ <0x00 0x484a0000 0x00 0x2000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x1000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+ "cfg", "tchan", "rchan", "rflow";
+};
+
+&main_rgmii1_pins_default {
+ bootph-all;
+};
+
+&main_timer0 {
+ clock-frequency = <25000000>;
+};
+
+&main_uart0 {
+ bootph-all;
+};
+
+&main_uart0_pins_default {
+ bootph-all;
+};
+
+&main_uart1 {
+ bootph-all;
+};
+
+&main_uart1_pins_default {
+ bootph-all;
+};
+
+&ospi0 {
+ bootph-all;
+
+ flash@0 {
+ bootph-all;
+ };
+};
+
+&ospi0_pins_default {
+ bootph-all;
+};
+
+&sdhci0 {
+ bootph-all;
+};
+
+&sdhci1 {
+ bootph-all;
+};
+
+&vcc_3v3_mmc {
+ bootph-all;
+};
+
+&vcc_5v0_som {
+ bootph-all;
+};
+
+&vddshv5_sdio {
+ bootph-all;
+};
+
+&wkup_uart0 {
+ bootph-all;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ *
+ * Product homepage:
+ * https://www.phytec.com/product/phyboard-am62x
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include "k3-am625.dtsi"
+#include "k3-am62-phycore-som.dtsi"
+
+/ {
+ compatible = "phytec,am625-phyboard-lyra-rdk",
+ "phytec,am62-phycore-som", "ti,am625";
+ model = "PHYTEC phyBOARD-Lyra AM625";
+
+ aliases {
+ serial2 = &main_uart0;
+ serial3 = &main_uart1;
+ mmc1 = &sdhci1;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ ethernet1 = &cpsw_port2;
+ };
+
+ can_tc1: can-phy0 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ standby-gpios = <&gpio_exp 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_pins_default>;
+
+ key-home {
+ label = "home";
+ linux,code = <KEY_HOME>;
+ gpios = <&main_gpio1 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ key-menu {
+ label = "menu";
+ linux,code = <KEY_MENU>;
+ gpios = <&gpio_exp 4 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>;
+
+ led-1 {
+ gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ };
+
+ led-2 {
+ gpios = <&gpio_exp 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ };
+ };
+
+ vcc_3v3_mmc: regulator-vcc-3v3-mmc {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3_MMC";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&main_pmx0 {
+ gpio_keys_pins_default: gpio-keys-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x1d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
+ >;
+ };
+
+ gpio_exp_int_pins_default: gpio-exp-int-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x244, PIN_INPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
+ AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
+ >;
+ };
+
+ main_mcan0_pins_default: main-mcan0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */
+ AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x23c, PIN_INPUT_PULLUP, 0) /* (A21) MMC1_CMD */
+ AM62X_IOPAD(0x234, PIN_INPUT_PULLDOWN, 0) /* (B22) MMC1_CLK */
+ AM62X_IOPAD(0x230, PIN_INPUT_PULLUP, 0) /* (A22) MMC1_DAT0 */
+ AM62X_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (B21) MMC1_DAT1 */
+ AM62X_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (C21) MMC1_DAT2 */
+ AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */
+ AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */
+ >;
+ };
+
+ main_rgmii2_pins_default: main-rgmii2-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
+ AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
+ AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
+ AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
+ AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
+ AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
+ AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
+ AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
+ AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
+ AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
+ AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
+ AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
+ >;
+ };
+
+ main_uart0_pins_default: main-uart0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
+ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
+ >;
+ };
+
+ main_uart1_pins_default: main-uart1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */
+ AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
+ AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
+ AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
+ >;
+ };
+
+ main_usb1_pins_default: main-usb1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */
+ >;
+ };
+
+ user_leds_pins_default: user-leds-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x084, PIN_OUTPUT, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */
+ >;
+ };
+};
+
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
+};
+
+&cpsw_port2 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy3>;
+};
+
+&cpsw3g_mdio {
+ cpsw3g_phy3: ethernet-phy@3 {
+ compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ gpio_exp: gpio-expander@21 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_exp_int_pins_default>;
+ compatible = "nxp,pcf8574";
+ reg = <0x21>;
+ interrupt-parent = <&main_gpio1>;
+ interrupts = <49 0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-line-names = "GPIO0_HDMI_RST", "GPIO1_CAN0_nEN",
+ "GPIO2_LED2", "GPIO3_LVDS_GPIO",
+ "GPIO4_BUT2", "GPIO5_LVDS_BKLT_EN",
+ "GPIO6_ETH1_USER_RESET", "GPIO7_AUDIO_USER_RESET";
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ pagesize = <16>;
+ reg = <0x51>;
+ };
+};
+
+&main_mcan0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan0_pins_default>;
+ phys = <&can_tc1>;
+ status = "okay";
+};
+
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+ status = "okay";
+};
+
+&main_uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
+ /* Main UART1 may be used by TIFS firmware */
+ status = "okay";
+};
+
+&sdhci1 {
+ vmmc-supply = <&vcc_3v3_mmc>;
+ vqmmc-supply = <&vddshv5_sdio>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+ no-1-8-v;
+ status = "okay";
+};
+
+&usbss0 {
+ ti,vbus-divider;
+ status = "okay";
+};
+
+&usbss1 {
+ ti,vbus-divider;
+ status = "okay";
+};
+
+&usb0 {
+ dr_mode = "peripheral";
+};
+
+&usb1 {
+ dr_mode = "host";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usb1_pins_default>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Based on k3-am625-sk-binman.dtsi
+ *
+ * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ */
+
+#include "k3-binman.dtsi"
+
+#ifdef CONFIG_TARGET_PHYCORE_AM62X_R5
+&binman {
+ tiboot3-am62x-hs-phycore-som.bin {
+ filename = "tiboot3-am62x-hs-phycore-som.bin";
+ ti-secure-rom {
+ content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
+ <&combined_dm_cfg>, <&sysfw_inner_cert>;
+ combined;
+ dm-data;
+ sysfw-inner-cert;
+ keyfile = "custMpk.pem";
+ sw-rev = <1>;
+ content-sbl = <&u_boot_spl>;
+ content-sysfw = <&ti_fs_enc>;
+ content-sysfw-data = <&combined_tifs_cfg>;
+ content-sysfw-inner-cert = <&sysfw_inner_cert>;
+ content-dm-data = <&combined_dm_cfg>;
+ load = <0x43c00000>;
+ load-sysfw = <0x40000>;
+ load-sysfw-data = <0x67000>;
+ load-dm-data = <0x43c3a800>;
+ };
+ u_boot_spl: u-boot-spl {
+ no-expanded;
+ };
+ ti_fs_enc: ti-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-firmware-am62x-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_tifs_cfg: combined-tifs-cfg.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+ sysfw_inner_cert: sysfw-inner-cert {
+ filename = "ti-sysfw/ti-fs-firmware-am62x-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_dm_cfg: combined-dm-cfg.bin {
+ filename = "combined-dm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+};
+
+&binman {
+ tiboot3-am62x-hs-fs-phycore-som.bin {
+ filename = "tiboot3-am62x-hs-fs-phycore-som.bin";
+ symlink = "tiboot3.bin";
+ ti-secure-rom {
+ content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
+ <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
+ combined;
+ dm-data;
+ sysfw-inner-cert;
+ keyfile = "custMpk.pem";
+ sw-rev = <1>;
+ content-sbl = <&u_boot_spl_fs>;
+ content-sysfw = <&ti_fs_enc_fs>;
+ content-sysfw-data = <&combined_tifs_cfg_fs>;
+ content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
+ content-dm-data = <&combined_dm_cfg_fs>;
+ load = <0x43c00000>;
+ load-sysfw = <0x40000>;
+ load-sysfw-data = <0x67000>;
+ load-dm-data = <0x43c3a800>;
+ };
+ u_boot_spl_fs: u-boot-spl {
+ no-expanded;
+ };
+ ti_fs_enc_fs: ti-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_tifs_cfg_fs: combined-tifs-cfg.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+ sysfw_inner_cert_fs: sysfw-inner-cert {
+ filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_dm_cfg_fs: combined-dm-cfg.bin {
+ filename = "combined-dm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+};
+
+&binman {
+ tiboot3-am62x-gp-phycore-som.bin {
+ filename = "tiboot3-am62x-gp-phycore-som.bin";
+ ti-secure-rom {
+ content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
+ <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
+ combined;
+ dm-data;
+ content-sbl = <&u_boot_spl_unsigned>;
+ load = <0x43c00000>;
+ content-sysfw = <&ti_fs_gp>;
+ load-sysfw = <0x40000>;
+ content-sysfw-data = <&combined_tifs_cfg_gp>;
+ load-sysfw-data = <0x67000>;
+ content-dm-data = <&combined_dm_cfg_gp>;
+ load-dm-data = <0x43c3a800>;
+ sw-rev = <1>;
+ keyfile = "ti-degenerate-key.pem";
+ };
+ u_boot_spl_unsigned: u-boot-spl {
+ no-expanded;
+ };
+ ti_fs_gp: ti-fs-gp.bin {
+ filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+ combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
+ filename = "combined-dm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+};
+#endif /* CONFIG_TARGET_PHYCORE_AM62X_R5 */
+
+#ifdef CONFIG_TARGET_PHYCORE_AM62X_A53
+#define SPL_AM625_PHYBOARD_LYRA_DTB "spl/dts/k3-am625-phyboard-lyra-rdk.dtb"
+#define AM625_PHYBOARD_LYRA_DTB "u-boot.dtb"
+
+&binman {
+ ti-dm {
+ filename = "ti-dm.bin";
+ blob-ext {
+ filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ };
+ };
+ ti-spl {
+ insert-template = <&ti_spl_template>;
+
+ fit {
+
+ images {
+ dm {
+ ti-secure {
+ content = <&dm>;
+ keyfile = "custMpk.pem";
+ };
+ dm: blob-ext {
+ filename = "ti-dm.bin";
+ };
+ };
+
+ fdt-0 {
+ description = "k3-am625-phyboard-lyra-rdk";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <&spl_am625_phyboard_lyra_dtb>;
+ keyfile = "custMpk.pem";
+ };
+ spl_am625_phyboard_lyra_dtb: blob-ext {
+ filename = SPL_AM625_PHYBOARD_LYRA_DTB;
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-am625-phyboard-lyra-rdk";
+ firmware = "atf";
+ loadables = "tee", "dm", "spl";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+};
+
+&binman {
+ u-boot {
+ insert-template = <&u_boot_template>;
+
+ fit {
+ images {
+ uboot {
+ description = "U-Boot for phyCORE-AM62x";
+ };
+
+ fdt-0 {
+ description = "k3-am625-phyboard-lyra-rdk";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <&am625_phyboard_lyra_dtb>;
+ keyfile = "custMpk.pem";
+ };
+ am625_phyboard_lyra_dtb: blob-ext {
+ filename = AM625_PHYBOARD_LYRA_DTB;
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-am625-phyboard-lyra-rdk";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+};
+
+&binman {
+ ti-spl_unsigned {
+ insert-template = <&ti_spl_unsigned_template>;
+
+ fit {
+ images {
+ dm {
+ blob-ext {
+ filename = "ti-dm.bin";
+ };
+ };
+
+ fdt-0 {
+ description = "k3-am625-phyboard-lyra-rdk";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ spl_am625_phyboard_lyra_dtb_unsigned: blob {
+ filename = SPL_AM625_PHYBOARD_LYRA_DTB;
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-am625-phyboard-lyra-rdk";
+ firmware = "atf";
+ loadables = "tee", "dm", "spl";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+};
+
+&binman {
+ u-boot_unsigned {
+ insert-template = <&u_boot_unsigned_template>;
+
+ fit {
+ images {
+ uboot {
+ description = "U-Boot for phyCORE-AM62x";
+ };
+
+ fdt-0 {
+ description = "k3-am625-phyboard-lyra-rdk";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ am625_phyboard_lyra_dtb_unsigned: blob {
+ filename = AM625_PHYBOARD_LYRA_DTB;
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-am625-phyboard-lyra-rdk";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+};
+#endif /* CONFIG_TARGET_PHYCORE_AM62X_A53 */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * phyCORE-AM62x dts file for R5 SPL with 2GB RAM
+ * Copyright (C) 2022 - 2023 Phytec Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ */
+
+#include "k3-am625-phyboard-lyra-rdk.dts"
+#include "k3-am62-phycore-som-ddr4-2gb.dtsi"
+#include "k3-am62-ddr.dtsi"
+
+#include "k3-am625-phyboard-lyra-rdk-u-boot.dtsi"
+
+/ {
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a53_0;
+ serial0 = &wkup_uart0;
+ serial3 = &main_uart1;
+ };
+
+ a53_0: a53@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x00 0x00a90000 0x00 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 135 0>;
+ clocks = <&k3_clks 61 0>;
+ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ assigned-clock-parents = <&k3_clks 61 2>;
+ assigned-clock-rates = <200000000>, <1200000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ bootph-pre-ram;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <36>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_main 22>,
+ <&secure_proxy_main 23>;
+ bootph-pre-ram;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 2G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+ bootph-pre-ram;
+ };
+};
+
+&secure_proxy_sa3 {
+ /* We require this for boot handshake */
+ status = "okay";
+};
+
+&cbass_main {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
+ mbox-names = "tx", "rx", "boot_notify";
+ bootph-pre-ram;
+ };
+};
+
+&dmsc {
+ mboxes= <&secure_proxy_main 0>,
+ <&secure_proxy_main 1>,
+ <&secure_proxy_main 0>;
+ mbox-names = "rx", "tx", "notify";
+ ti,host-id = <35>;
+ ti,secure-host;
+};
+
+&main_bcdma {
+ ti,sci = <&dm_tifs>;
+};
+
+&main_pktdma {
+ ti,sci = <&dm_tifs>;
+};
+
+/* Main UART1 is used for TIFS firmware logs */
+&main_uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
+ status = "okay";
+ bootph-pre-ram;
+};
+
+&mcu_pmx0 {
+ wkup_uart0_pins_default: wkup-uart0-pins-default {
+ pinctrl-single,pins = <
+ AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */
+ AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */
+ AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */
+ AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */
+ >;
+ bootph-pre-ram;
+ };
+};
+
+&ospi0 {
+ reg = <0x00 0x0fc40000 0x00 0x100>,
+ <0x00 0x60000000 0x00 0x08000000>;
+};
+
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+ status = "okay";
+ bootph-pre-ram;
+};
no-expanded;
};
};
+
+ tiboot3-j721e_sr2-hs-evm.bin {
+ filename = "tiboot3-j721e_sr2-hs-evm.bin";
+ ti-secure-rom {
+ content = <&u_boot_spl_sr2>;
+ core = "public";
+ load = <CONFIG_SPL_TEXT_BASE>;
+ keyfile = "custMpk.pem";
+ };
+ u_boot_spl_sr2: u-boot-spl {
+ no-expanded;
+ };
+ };
+
sysfw {
filename = "sysfw.bin";
ti-secure-rom {
optional;
};
};
+
+ sysfw_sr2 {
+ filename = "sysfw.bin_sr2";
+ ti-secure-rom {
+ content = <&ti_fs_cert_sr2>;
+ core = "secure";
+ load = <0x40000>;
+ keyfile = "custMpk.pem";
+ countersign;
+ };
+ ti_fs_cert_sr2: ti-fs-cert.bin {
+ filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ ti-fs-firmware-j721e_sr2-hs-enc.bin {
+ filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ };
+
itb {
filename = "sysfw-j721e_sr1_1-hs-evm.itb";
insert-template = <&itb_template>;
};
+
+ itb_sr2 {
+ filename = "sysfw-j721e_sr2-hs-evm.itb";
+ insert-template = <&itb_template>;
+ fit {
+ images {
+ sysfw.bin {
+ blob-ext {
+ filename = "sysfw.bin_sr2";
+ };
+ };
+ board-cfg.bin {
+ ti-secure {
+ content = <&board_cfg_sr2>;
+ };
+ board_cfg_sr2: board-cfg {
+ filename = "board-cfg.bin";
+ };
+ };
+ pm-cfg.bin {
+ ti-secure {
+ content = <&pm_cfg_sr2>;
+ };
+ pm_cfg_sr2: pm-cfg {
+ filename = "pm-cfg.bin";
+ };
+ };
+ rm-cfg.bin {
+ ti-secure {
+ content = <&rm_cfg_sr2>;
+ };
+ rm_cfg_sr2: rm-cfg {
+ filename = "rm-cfg.bin";
+ };
+ };
+ sec-cfg.bin {
+ ti-secure {
+ content = <&sec_cfg_sr2>;
+ };
+ sec_cfg_sr2: sec-cfg {
+ filename = "sec-cfg.bin";
+ };
+ };
+
+ };
+ };
+ };
};
&binman {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Phytium pe2201 board
+ * Copyright (C) 2023, Phytium Technology Co., Ltd.
+ * lixinde <lixinde@phytium.com.cn>
+ * weichangzheng <weichangzheng@phytium.com.cn>
+ */
+/dts-v1/;
+
+/ {
+ model = "Phytium pe2201 Board";
+ compatible = "phytium,pe2201";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ uart0: serial@2800c000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x2800c000 0x0 0x1000>;
+ clock = <100000000>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ pcie@40000000 {
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0x0 0x40000000 0x0 0x10000000>;
+ ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00F00000>,
+ <0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>,
+ <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>;
+ };
+ };
+};
status = "disabled";
};
- reset: gcc-reset@1800000 {
- compatible = "qcom,gcc-reset-ipq4019";
- reg = <0x1800000 0x60000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- bootph-all;
- };
-
soc_gpios: pinctrl@1000000 {
compatible = "qcom,ipq4019-pinctrl";
reg = <0x1000000 0x300000>;
#phy-cells = <0>;
reg = <0x9a000 0x800>;
reg-names = "phy_base";
- resets = <&reset USB3_UNIPHY_PHY_ARES>;
+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
reset-names = "por_rst";
status = "disabled";
};
#phy-cells = <0>;
reg = <0xa6000 0x40>;
reg-names = "phy_base";
- resets = <&reset USB3_HSPHY_POR_ARES>, <&reset USB3_HSPHY_S_ARES>;
+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
reset-names = "por_rst", "srif_rst";
status = "disabled";
};
#phy-cells = <0>;
reg = <0xa8000 0x40>;
reg-names = "phy_base";
- resets = <&reset USB2_HSPHY_POR_ARES>, <&reset USB2_HSPHY_S_ARES>;
+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
reset-names = "por_rst", "srif_rst";
status = "disabled";
};
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <1>;
- };
-
- reset: gcc-reset@1800000 {
- compatible = "qcom,gcc-reset-qcs404";
- reg = <0x1800000 0x80000>;
#reset-cells = <1>;
};
clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB3_PHY_PIPE_CLK>;
clock-names = "ahb", "pipe";
- resets = <&reset GCC_USB3_PHY_BCR>,
- <&reset GCC_USB3PHY_PHY_BCR>;
+ resets = <&gcc GCC_USB3_PHY_BCR>,
+ <&gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "com", "phy";
};
clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB2A_PHY_SLEEP_CLK>;
clock-names = "ahb", "sleep";
- resets = <&reset GCC_USB_HS_PHY_CFG_AHB_BCR>,
- <&reset GCC_USB2A_PHY_BCR>;
+ resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
+ <&gcc GCC_USB2A_PHY_BCR>;
reset-names = "phy", "por";
};
clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB2A_PHY_SLEEP_CLK>;
clock-names = "ahb", "sleep";
- resets = <&reset GCC_QUSB2_PHY_BCR>,
- <&reset GCC_USB2_HS_PHY_ONLY_BCR>;
+ resets = <&gcc GCC_QUSB2_PHY_BCR>,
+ <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
reset-names = "phy", "por";
};
<&gcc GCC_ETH_PTP_CLK>,
<&gcc GCC_ETH_RGMII_CLK>;
- resets = <&reset GCC_EMAC_BCR>;
+ resets = <&gcc GCC_EMAC_BCR>;
reset-names = "emac";
snps,tso;
spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
- reg = <0x200f000 0x1000
- 0x2400000 0x400000
- 0x2c00000 0x400000>;
+ reg = <0x200f000 0x001000>,
+ <0x2400000 0x800000>,
+ <0x2c00000 0x800000>;
+ reg-names = "core", "chnls", "obsrvr";
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "qcom,pms405-gpio";
reg = <0xc000 0x400>;
gpio-controller;
- gpio-count = <12>;
+ gpio-ranges = <&pms405_gpios 0 0 12>;
#gpio-cells = <2>;
- gpio-bank-name="pmic";
};
};
};
};
keyboard_pins: keyboard {
- pins = "GP_3_10", "GP_3_11", "GP_3_12", "GP_3_15", "GP_11_02";
+ pins = "GP_3_10", "GP_3_11", "GP_3_12", "GP_3_15", "GP_11_2";
bias-pull-up;
};
status = "okay";
clock-frequency = <400000>;
- hdmi@39{
+ hdmi@39 {
compatible = "adi,adv7511w";
#sound-dai-cells = <0>;
reg = <0x39>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
dynamic-power-coefficient = <277>;
- clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
+ clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
next-level-cache = <&L2_CA53>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
- clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
+ clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
-// SPDX-License-Identifier: (GPL-2.0 or MIT)
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree Source for the Spider CPU board
*
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
#include "r8a779f0.dtsi"
/ {
stdout-path = "serial0:1843200n8";
};
+ leds {
+ compatible = "gpio-leds";
+
+ led-7 {
+ gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_INDICATOR;
+ function-enumerator = <7>;
+ };
+
+ led-8 {
+ gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_INDICATOR;
+ function-enumerator = <8>;
+ };
+ };
+
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
-// SPDX-License-Identifier: (GPL-2.0 or MIT)
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree Source for the Spider CPU and BreakOut boards
*
-// SPDX-License-Identifier: (GPL-2.0 or MIT)
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
*
#thermal-sensor-cells = <1>;
};
+ intc_ex: interrupt-controller@e61c0000 {
+ compatible = "renesas,intc-ex-r8a779f0", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_CORE R8A779F0_CLK_CL16M>;
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ };
+
tmu0: timer@e61e0000 {
compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
reg = <0 0xe61e0000 0 0x30>;
#power-domain-cells = <1>;
};
- gpio_north: gpio_north@3900000 {
- #gpio-cells = <2>;
- compatible = "qcom,sdm845-pinctrl";
- reg = <0x3900000 0x400000>;
- gpio-count = <150>;
- gpio-controller;
- gpio-ranges = <&gpio_north 0 0 150>;
- gpio-bank-name = "soc_north.";
- };
-
- tlmm_north: pinctrl_north@3900000 {
+ tlmm: pinctrl@3400000 {
compatible = "qcom,sdm845-pinctrl";
- reg = <0x3900000 0x400000>;
+ reg = <0x3400000 0xc00000>;
gpio-count = <150>;
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&tlmm_north 0 0 150>;
+ gpio-ranges = <&tlmm 0 0 150>;
/* DEBUG UART */
qup_uart9: qup-uart9-default {
reg = <0xc440000 0x1100>,
<0xc600000 0x2000000>,
<0xe600000 0x100000>;
- reg-names = "cnfg", "core", "obsrvr";
+ reg-names = "core", "chnls", "obsrvr";
#address-cells = <0x1>;
#size-cells = <0x1>;
#address-cells = <0x1>;
#size-cells = <0x1>;
- pm8998_pon: pm8998_pon@800 {
- compatible = "qcom,pm8998-pwrkey";
+ pm8998_pon: pon@800 {
+ compatible = "qcom,pm8998-pon";
+
reg = <0x800 0x100>;
- #gpio-cells = <2>;
- gpio-controller;
- gpio-bank-name = "pm8998_key.";
+ mode-bootloader = <0x2>;
+ mode-recovery = <0x1>;
+
+ pm8998_pwrkey: pwrkey {
+ compatible = "qcom,pm8941-pwrkey";
+ debounce = <15625>;
+ bias-pull-up;
+ };
+
+ pm8998_resin: resin {
+ compatible = "qcom,pm8941-resin";
+ debounce = <15625>;
+ bias-pull-up;
+ status = "disabled";
+ };
};
pm8998_gpios: pm8998_gpios@c000 {
compatible = "qcom,pm8998-gpio";
reg = <0xc000 0x1a00>;
gpio-controller;
- gpio-count = <21>;
+ gpio-ranges = <&pm8998_gpios 0 0 26>;
#gpio-cells = <2>;
- gpio-bank-name = "pm8998.";
};
};
clock-controller@100000 {
bootph-all;
};
- gpio_north@3900000 {
- bootph-all;
- };
- pinctrl_north@3900000 {
+ pinctrl@3400000 {
bootph-all;
};
};
};
-&pm8998_pon {
- key_vol_down {
- gpios = <&pm8998_pon 1 0>;
- label = "key_vol_down";
- };
- key_power {
- gpios = <&pm8998_pon 0 0>;
- label = "key_power";
- };
-};
format = "a8r8g8b8";
};
- gpio-keys {
- compatible = "gpio-keys";
-
- key-pwr {
- label = "Power";
- linux,code = <KEY_ENTER>;
- gpios = <&pm8998_pon 0 GPIO_ACTIVE_LOW>;
- };
-
- key-vol-down {
- label = "Volume Down";
- linux,code = <KEY_DOWN>;
- gpios = <&pm8998_pon 1 GPIO_ACTIVE_LOW>;
- };
- };
-
soc: soc {
serial@a84000 {
status = "okay";
};
+ };
+};
- pinctrl_north@3900000 {
- muic_i2c: muic_i2c {
- pins = "GPIO_33", "GPIO_34";
- drive-strength = <0x2>;
- function = "gpio";
- bias-disable;
- };
- };
+&pm8998_resin {
+ status = "okay";
+};
+
+&tlmm {
+ muic_i2c: muic-i2c-n {
+ pins = "GPIO_33", "GPIO_34";
+ drive-strength = <0x2>;
+ function = "gpio";
+ bias-disable;
};
};
#ifndef __ASSEMBLY__
/* Function prototypes */
-void mem_init(void);
+void omap3_mem_init(void);
u32 is_mem_sdr(void);
u32 mem_ok(u32 cs);
#if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE)
.align 5
undefined_instruction:
+#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS)
+ b undefined_instruction
+#endif
software_interrupt:
+#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS)
+ b software_interrupt
+#endif
prefetch_abort:
+#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS)
+ b prefetch_abort
+#endif
data_abort:
+#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS)
+ b data_abort
+#endif
not_used:
+#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS)
+ b not_used
+#endif
irq:
+#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS)
+ b irq
+#endif
fiq:
1:
b 1b /* hang and never return */
config IMX8M
bool
+ select BINMAN
select GICV3 if ARMV8_PSCI
select HAS_CAAM
select ROM_UNIFIED_SECTIONS
config TARGET_IMX8MQ_CM
bool "Ronetix iMX8MQ-CM SoM"
- select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
config TARGET_IMX8MQ_EVK
bool "imx8mq_evk"
- select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
select FSL_CAAM
config TARGET_IMX8MQ_PHANBELL
bool "imx8mq_phanbell"
- select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
config TARGET_IMX8MQ_REFORM2
bool "imx8mq_reform2"
- select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
bool "Data Modul eDM SBC i.MX8M Mini"
- select BINMAN
select IMX8MM
select IMX8M_LPDDR4
select SUPPORT_SPL
config TARGET_IMX8MM_EVK
bool "imx8mm LPDDR4 EVK board"
- select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_ICORE_MX8MM
bool "Engicam i.Core MX8M Mini SOM"
- select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_MX8MENLO
bool "Support i.MX8M Mini MX8Menlo board based on Toradex Verdin SoM"
- select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_PHG
bool "i.MX8MM PHG board"
- select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_VENICE
bool "Support Gateworks Venice iMX8M Mini module"
- select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_KONTRON_MX8MM
bool "Kontron Electronics N80xx"
- select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MN_BSH_SMM_S2
bool "imx8mn-bsh-smm-s2"
- select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR3L
config TARGET_IMX8MN_BSH_SMM_S2PRO
bool "imx8mn-bsh-smm-s2pro"
- select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR3L
config TARGET_IMX8MN_EVK
bool "imx8mn LPDDR4 EVK board"
- select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MN_DDR4_EVK
bool "imx8mn DDR4 EVK board"
- select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR4
config TARGET_IMX8MN_VENICE
bool "Support Gateworks Venice iMX8M Nano module"
- select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MP_DATA_MODUL_EDM_SBC
bool "Data Modul eDM SBC i.MX8M Plus"
- select BINMAN
select IMX8MP
select IMX8M_LPDDR4
select SUPPORT_SPL
config TARGET_IMX8MP_BEACON
bool "imx8mm Beacon Embedded devkit"
- select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MP_DEBIX_MODEL_A
bool "Polyhex i.MX8M Plus Debix Model A SBC"
- select BINMAN
select IMX8MP
select IMX8M_LPDDR4
select SUPPORT_SPL
config TARGET_IMX8MP_DH_DHCOM_PDK2
bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus"
- select BINMAN
select IMX8MP
select IMX8M_LPDDR4
select SUPPORT_SPL
config TARGET_IMX8MP_ICORE_MX8MP
bool "Engicam i.Core MX8M Plus SOM"
- select BINMAN
select IMX8MP
select IMX8M_LPDDR4
select SUPPORT_SPL
config TARGET_IMX8MP_EVK
bool "imx8mp LPDDR4 EVK board"
- select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MP_VENICE
bool "Support Gateworks Venice iMX8M Plus module"
- select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_PICO_IMX8MQ
bool "Support Technexion Pico iMX8MQ"
- select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
config TARGET_IMX8MN_VAR_SOM
bool "Variscite imx8mn_var_som"
- select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR4
config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"
- select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
config TARGET_VERDIN_IMX8MM
bool "Support Toradex Verdin iMX8M Mini module"
- select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_VERDIN_IMX8MP
bool "Support Toradex Verdin iMX8M Plus module"
- select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_BEACON
bool "imx8mm Beacon Embedded devkit"
- select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MN_BEACON
bool "imx8mn Beacon Embedded devkit"
- select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_PHYCORE_IMX8MM
bool "PHYTEC PHYCORE i.MX8MM"
- select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_PHYCORE_IMX8MP
bool "PHYTEC PHYCORE i.MX8MP"
- select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_CL_IOT_GATE
bool "CompuLab iot-gate-imx8"
- select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_CL_IOT_GATE_OPTEE
bool "CompuLab iot-gate-imx8 with optee support"
- select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MP_RSB3720A1_4G
bool "Support i.MX8MP RSB3720A1 4G"
- select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MP_RSB3720A1_6G
bool "Support i.MX8MP RSB3720A1 6G"
- select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_MSC_SM2S_IMX8MP
bool "MSC SMARC2 i.MX8MPLUS"
- select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_LIBREM5
bool "Purism Librem5 Phone"
- select BINMAN
select IMX8MQ
select SUPPORT_SPL
select IMX8M_LPDDR4
config IMX9
bool
+ select BINMAN
select HAS_CAAM
select ROM_UNIFIED_SECTIONS
config TARGET_IMX93_11X11_EVK
bool "imx93_11x11_evk"
- select BINMAN
select IMX93
config TARGET_IMX93_VAR_SOM
bool "imx93_var_som"
- select BINMAN
select IMX93
select IMX9_LPDDR4X
return 0;
}
+static int fixup_thermal_trips(void *blob, const char *name)
+{
+ int minc, maxc;
+ int node, trip;
+
+ node = fdt_path_offset(blob, "/thermal-zones");
+ if (node < 0)
+ return node;
+
+ node = fdt_subnode_offset(blob, node, name);
+ if (node < 0)
+ return node;
+
+ node = fdt_subnode_offset(blob, node, "trips");
+ if (node < 0)
+ return node;
+
+ get_cpu_temp_grade(&minc, &maxc);
+
+ fdt_for_each_subnode(trip, blob, node) {
+ const char *type;
+ int temp, ret;
+
+ type = fdt_getprop(blob, trip, "type", NULL);
+ if (!type)
+ continue;
+
+ temp = 0;
+ if (!strcmp(type, "critical"))
+ temp = 1000 * (maxc - 5);
+ else if (!strcmp(type, "passive"))
+ temp = 1000 * (maxc - 10);
+ if (temp) {
+ ret = fdt_setprop_u32(blob, trip, "temperature", temp);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
int ft_system_setup(void *blob, struct bd_info *bd)
{
+ if (fixup_thermal_trips(blob, "cpu-thermal"))
+ printf("Failed to update cpu-thermal trip(s)");
+
return 0;
}
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2019 Sartura Ltd.
-#
-# Author: Robert Marko <robert.marko@sartura.hr>
-
-obj-y += clock-ipq4019.o
-obj-y += pinctrl-snapdragon.o
-obj-y += pinctrl-ipq4019.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Clock drivers for Qualcomm IPQ40xx
- *
- * Copyright (c) 2020 Sartura Ltd.
- *
- * Author: Robert Marko <robert.marko@sartura.hr>
- *
- */
-
-#include <clk-uclass.h>
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-
-#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
-
-struct msm_clk_priv {
- phys_addr_t base;
-};
-
-ulong msm_set_rate(struct clk *clk, ulong rate)
-{
- switch (clk->id) {
- case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
- /* This clock is already initialized by SBL1 */
- return 0;
- default:
- return -EINVAL;
- }
-}
-
-static int msm_clk_probe(struct udevice *dev)
-{
- struct msm_clk_priv *priv = dev_get_priv(dev);
-
- priv->base = dev_read_addr(dev);
- if (priv->base == FDT_ADDR_T_NONE)
- return -EINVAL;
-
- return 0;
-}
-
-static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
-{
- return msm_set_rate(clk, rate);
-}
-
-static int msm_enable(struct clk *clk)
-{
- switch (clk->id) {
- case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/
- /* This clock is already initialized by SBL1 */
- return 0;
- case GCC_PRNG_AHB_CLK: /*PRNG*/
- /* This clock is already initialized by SBL1 */
- return 0;
- case GCC_USB3_MASTER_CLK:
- case GCC_USB3_SLEEP_CLK:
- case GCC_USB3_MOCK_UTMI_CLK:
- case GCC_USB2_MASTER_CLK:
- case GCC_USB2_SLEEP_CLK:
- case GCC_USB2_MOCK_UTMI_CLK:
- /* These clocks is already initialized by SBL1 */
- return 0;
- default:
- return -EINVAL;
- }
-}
-
-static struct clk_ops msm_clk_ops = {
- .set_rate = msm_clk_set_rate,
- .enable = msm_enable,
-};
-
-static const struct udevice_id msm_clk_ids[] = {
- { .compatible = "qcom,gcc-ipq4019" },
- { }
-};
-
-U_BOOT_DRIVER(clk_msm) = {
- .name = "clk_msm",
- .id = UCLASS_CLK,
- .of_match = msm_clk_ids,
- .ops = &msm_clk_ops,
- .priv_auto = sizeof(struct msm_clk_priv),
- .probe = msm_clk_probe,
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * TLMM driver for Qualcomm IPQ40xx
- *
- * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
- *
- * Copyright (c) 2020 Sartura Ltd.
- *
- * Author: Robert Marko <robert.marko@sartura.hr>
- *
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <dm/device_compat.h>
-#include <dm/lists.h>
-#include <dm/pinctrl.h>
-#include <linux/bitops.h>
-#include "pinctrl-snapdragon.h"
-
-struct msm_pinctrl_priv {
- phys_addr_t base;
- struct msm_pinctrl_data *data;
-};
-
-#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000)
-#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
-#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
-#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
-#define TLMM_GPIO_DISABLE BIT(9)
-
-static const struct pinconf_param msm_conf_params[] = {
- { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },
- { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
- { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 2 },
-};
-
-static int msm_get_functions_count(struct udevice *dev)
-{
- struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
- return priv->data->functions_count;
-}
-
-static int msm_get_pins_count(struct udevice *dev)
-{
- struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
- return priv->data->pin_count;
-}
-
-static const char *msm_get_function_name(struct udevice *dev,
- unsigned int selector)
-{
- struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
- return priv->data->get_function_name(dev, selector);
-}
-
-static int msm_pinctrl_probe(struct udevice *dev)
-{
- struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
- priv->base = devfdt_get_addr(dev);
- priv->data = (struct msm_pinctrl_data *)dev->driver_data;
-
- return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
-}
-
-static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector)
-{
- struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
- return priv->data->get_pin_name(dev, selector);
-}
-
-static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
- unsigned int func_selector)
-{
- struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
- clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
- TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
- priv->data->get_function_mux(func_selector) << 2);
- return 0;
-}
-
-static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
- unsigned int param, unsigned int argument)
-{
- struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
- switch (param) {
- case PIN_CONFIG_DRIVE_STRENGTH:
- clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
- TLMM_DRV_STRENGTH_MASK, argument << 6);
- break;
- case PIN_CONFIG_BIAS_DISABLE:
- clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
- TLMM_GPIO_PULL_MASK);
- break;
- case PIN_CONFIG_BIAS_PULL_UP:
- clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
- TLMM_GPIO_PULL_MASK, argument);
- break;
- default:
- return 0;
- }
-
- return 0;
-}
-
-static int msm_pinctrl_bind(struct udevice *dev)
-{
- ofnode node = dev_ofnode(dev);
- const char *name;
- int ret;
-
- ofnode_get_property(node, "gpio-controller", &ret);
- if (ret < 0)
- return 0;
-
- /* Get the name of gpio node */
- name = ofnode_get_name(node);
- if (!name)
- return -EINVAL;
-
- /* Bind gpio node */
- ret = device_bind_driver_to_node(dev, "gpio_msm",
- name, node, NULL);
- if (ret)
- return ret;
-
- dev_dbg(dev, "bind %s\n", name);
-
- return 0;
-}
-
-static struct pinctrl_ops msm_pinctrl_ops = {
- .get_pins_count = msm_get_pins_count,
- .get_pin_name = msm_get_pin_name,
- .set_state = pinctrl_generic_set_state,
- .pinmux_set = msm_pinmux_set,
- .pinconf_num_params = ARRAY_SIZE(msm_conf_params),
- .pinconf_params = msm_conf_params,
- .pinconf_set = msm_pinconf_set,
- .get_functions_count = msm_get_functions_count,
- .get_function_name = msm_get_function_name,
-};
-
-static const struct udevice_id msm_pinctrl_ids[] = {
- { .compatible = "qcom,ipq4019-pinctrl", .data = (ulong)&ipq4019_data },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_snapdraon) = {
- .name = "pinctrl_msm",
- .id = UCLASS_PINCTRL,
- .of_match = msm_pinctrl_ids,
- .priv_auto = sizeof(struct msm_pinctrl_priv),
- .ops = &msm_pinctrl_ops,
- .probe = msm_pinctrl_probe,
- .bind = msm_pinctrl_bind,
-};
select BINMAN
imply SYS_K3_SPL_ATF
+config TARGET_PHYCORE_AM62X_A53
+ bool "PHYTEC phyCORE-AM62x running on A53"
+ select ARM64
+ select BINMAN
+
+config TARGET_PHYCORE_AM62X_R5
+ bool "PHYTEC phyCORE-AM62x running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+
config TARGET_VERDIN_AM62_A53
bool "Toradex Verdin AM62 running on A53"
select ARM64
endchoice
source "board/beagle/beagleplay/Kconfig"
+source "board/phytec/phycore_am62x/Kconfig"
source "board/ti/am62x/Kconfig"
source "board/toradex/verdin-am62/Kconfig"
case BOOT_DEVICE_EMMC:
return BOOT_DEVICE_MMC1;
+ case BOOT_DEVICE_NAND:
+ return BOOT_DEVICE_NAND;
+
case BOOT_DEVICE_MMC:
if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
#define BOOT_DEVICE_USB 0x2A
#define BOOT_DEVICE_DFU 0x0A
+#define BOOT_DEVICE_NAND 0x0B
#define BOOT_DEVICE_GPMC_NOR 0x0C
#define BOOT_DEVICE_PCIE 0x0D
#define BOOT_DEVICE_XSPI 0x0E
select SUPPORT_SPL
select SYS_L2_PL310 if !SYS_L2CACHE_OFF
select TRANSLATION_OFFSET
+ select TOOLS_KWBIMAGE if SPL
select SPL_SYS_NO_VECTOR_TABLE if SPL
select ARCH_VERY_EARLY_INIT
DECLARE_GLOBAL_DATA_PTR;
-#define RAM_SIZE SZ_1G
+#define AC5_PTE_BLOCK_DEVICE \
+ (PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | \
+ PTE_BLOCK_NON_SHARE | \
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN)
static struct mm_region ac5_mem_map[] = {
{
.phys = 0x00000000,
.virt = 0xa0000000,
.size = 0x100000,
-
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ .attrs = AC5_PTE_BLOCK_DEVICE,
},
{
/* MMIO regions */
.phys = 0x100000,
.virt = 0x100000,
.size = 0x3ff00000,
-
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ .attrs = AC5_PTE_BLOCK_DEVICE,
},
{
- /* MMIO regions */
.phys = 0x7F000000,
.virt = 0x7F000000,
- .size = 0x21000000,
-
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ .size = SZ_8M,
+ .attrs = AC5_PTE_BLOCK_DEVICE,
+ },
+ {
+ .phys = 0x7F800000,
+ .virt = 0x7F800000,
+ .size = SZ_4M,
+ .attrs = AC5_PTE_BLOCK_DEVICE,
+ },
+ {
+ .phys = 0x7FC00000,
+ .virt = 0x7FC00000,
+ .size = SZ_512K,
+ .attrs = AC5_PTE_BLOCK_DEVICE,
+ },
+ {
+ .phys = 0x7FC80000,
+ .virt = 0x7FC80000,
+ .size = SZ_512K,
+ .attrs = AC5_PTE_BLOCK_DEVICE,
+ },
+ {
+ .phys = 0x7FD00000,
+ .virt = 0x7FD00000,
+ .size = SZ_512K,
+ .attrs = AC5_PTE_BLOCK_DEVICE,
+ },
+ /* ATF region 0x7FE00000-0x7FE20000 not mapped */
+ {
+ .phys = 0x7FE80000,
+ .virt = 0x7FE80000,
+ .size = SZ_512K,
+ .attrs = AC5_PTE_BLOCK_DEVICE,
+ },
+ {
+ .phys = 0x7FFF0000,
+ .virt = 0x7FFF0000,
+ .size = SZ_1M,
+ .attrs = AC5_PTE_BLOCK_DEVICE,
+ },
+ {
+ .phys = 0x80000000,
+ .virt = 0x80000000,
+ .size = SZ_2G,
+ .attrs = AC5_PTE_BLOCK_DEVICE,
},
{
0,
void board_init_f(ulong dummy)
{
early_system_init();
- mem_init();
+ omap3_mem_init();
/*
* Save the boot parameters passed from romcode.
* We cannot delay the saving further than this,
}
/*
- * mem_init() -
+ * omap3_mem_init() -
* - Initialize memory subsystem
*/
-void mem_init(void)
+void omap3_mem_init(void)
{
do_emif4_init();
}
*
* This file has been created after exctracting and consolidating
* the SDRC related content from mem.c and board.c, also created
- * generic init function (mem_init).
+ * generic init function (omap3_mem_init).
*
* Copyright (C) 2004-2010
* Texas Instruments Incorporated - https://www.ti.com/
}
/*
- * mem_init -
+ * omap3_mem_init -
* - Init the sdrc chip,
* - Selects CS0 and CS1,
*/
-void mem_init(void)
+void omap3_mem_init(void)
{
/* only init up first bank here */
do_sdrc_init(CS0, EARLY_INIT);
config SDM845
bool "Qualcomm Snapdragon 845 SoC"
select LINUX_KERNEL_IMAGE_HEADER
+ imply CLK_QCOM_SDM845
+ imply PINCTRL_QCOM_SDM845
+ imply BUTTON_QCOM_PMIC
config LNX_KRNL_IMG_TEXT_OFFSET_BASE
default 0x80000000
bool "96Boards Dragonboard 410C"
select BOARD_LATE_INIT
select ENABLE_ARM_SOC_BOOT0_HOOK
+ imply CLK_QCOM_APQ8016
+ imply PINCTRL_QCOM_APQ8016
+ imply BUTTON_QCOM_PMIC
help
Support for 96Boards Dragonboard 410C. This board complies with
96Board Open Platform Specifications. Features:
config TARGET_DRAGONBOARD820C
bool "96Boards Dragonboard 820C"
+ imply CLK_QCOM_APQ8096
+ imply PINCTRL_QCOM_APQ8096
+ imply BUTTON_QCOM_PMIC
help
Support for 96Boards Dragonboard 820C. This board complies with
96Board Open Platform Specifications. Features:
config TARGET_QCS404EVB
bool "Qualcomm Technologies, Inc. QCS404 EVB"
select LINUX_KERNEL_IMAGE_HEADER
+ imply CLK_QCOM_QCS404
+ imply PINCTRL_QCOM_QCS404
help
Support for Qualcomm Technologies, Inc. QCS404 evaluation board.
Features:
#
# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
-obj-$(CONFIG_SDM845) += clock-sdm845.o
obj-$(CONFIG_SDM845) += sysmap-sdm845.o
obj-$(CONFIG_SDM845) += init_sdm845.o
-obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o
obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
-obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o
obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
obj-y += misc.o
-obj-y += clock-snapdragon.o
obj-y += dram.o
-obj-y += pinctrl-snapdragon.o
-obj-y += pinctrl-apq8016.o
-obj-y += pinctrl-apq8096.o
-obj-y += pinctrl-qcs404.o
-obj-y += pinctrl-sdm845.o
-obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o
obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
+++ /dev/null
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Clock drivers for Qualcomm SDM845
- *
- * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
- * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
- *
- * Based on Little Kernel driver, simplified
- */
-
-#include <common.h>
-#include <clk-uclass.h>
-#include <dm.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-#include <dt-bindings/clock/qcom,gcc-sdm845.h>
-#include "clock-snapdragon.h"
-
-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-
-struct freq_tbl {
- uint freq;
- uint src;
- u8 pre_div;
- u16 m;
- u16 n;
-};
-
-static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
- F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
- F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
- F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
- F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
- F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
- F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
- F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
- F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
- F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
- F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
- F(102400000, CFG_CLK_SRC_GPLL0_EVEN, 1, 128, 375),
- F(112000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75),
- F(117964800, CFG_CLK_SRC_GPLL0_EVEN, 1, 6144, 15625),
- F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
- F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75),
- { }
-};
-
-static const struct bcr_regs uart2_regs = {
- .cfg_rcgr = SE9_UART_APPS_CFG_RCGR,
- .cmd_rcgr = SE9_UART_APPS_CMD_RCGR,
- .M = SE9_UART_APPS_M,
- .N = SE9_UART_APPS_N,
- .D = SE9_UART_APPS_D,
-};
-
-const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate)
-{
- if (!f)
- return NULL;
-
- if (!f->freq)
- return f;
-
- for (; f->freq; f++)
- if (rate <= f->freq)
- return f;
-
- /* Default to our fastest rate */
- return f - 1;
-}
-
-static int clk_init_uart(struct msm_clk_priv *priv, uint rate)
-{
- const struct freq_tbl *freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
-
- clk_rcg_set_rate_mnd(priv->base, &uart2_regs,
- freq->pre_div, freq->m, freq->n, freq->src);
-
- return 0;
-}
-
-ulong msm_set_rate(struct clk *clk, ulong rate)
-{
- struct msm_clk_priv *priv = dev_get_priv(clk->dev);
-
- switch (clk->id) {
- case GCC_QUPV3_WRAP1_S1_CLK: /*UART2*/
- return clk_init_uart(priv, rate);
- default:
- return 0;
- }
-}
-
-int msm_enable(struct clk *clk)
-{
- return 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Clock drivers for Qualcomm APQ8016, APQ8096
- *
- * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
- *
- * Based on Little Kernel driver, simplified
- */
-
-#include <common.h>
-#include <clk-uclass.h>
-#include <dm.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-#include "clock-snapdragon.h"
-
-/* CBCR register fields */
-#define CBCR_BRANCH_ENABLE_BIT BIT(0)
-#define CBCR_BRANCH_OFF_BIT BIT(31)
-
-extern ulong msm_set_rate(struct clk *clk, ulong rate);
-extern int msm_enable(struct clk *clk);
-
-/* Enable clock controlled by CBC soft macro */
-void clk_enable_cbc(phys_addr_t cbcr)
-{
- setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT);
-
- while (readl(cbcr) & CBCR_BRANCH_OFF_BIT)
- ;
-}
-
-void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0)
-{
- if (readl(base + gpll0->status) & gpll0->status_bit)
- return; /* clock already enabled */
-
- setbits_le32(base + gpll0->ena_vote, gpll0->vote_bit);
-
- while ((readl(base + gpll0->status) & gpll0->status_bit) == 0)
- ;
-}
-
-#define BRANCH_ON_VAL (0)
-#define BRANCH_NOC_FSM_ON_VAL BIT(29)
-#define BRANCH_CHECK_MASK GENMASK(31, 28)
-
-void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk)
-{
- u32 val;
-
- setbits_le32(base + vclk->ena_vote, vclk->vote_bit);
- do {
- val = readl(base + vclk->cbcr_reg);
- val &= BRANCH_CHECK_MASK;
- } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL));
-}
-
-#define APPS_CMD_RCGR_UPDATE BIT(0)
-
-/* Update clock command via CMD_RCGR */
-void clk_bcr_update(phys_addr_t apps_cmd_rcgr)
-{
- setbits_le32(apps_cmd_rcgr, APPS_CMD_RCGR_UPDATE);
-
- /* Wait for frequency to be updated. */
- while (readl(apps_cmd_rcgr) & APPS_CMD_RCGR_UPDATE)
- ;
-}
-
-#define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */
-
-#define CFG_MASK 0x3FFF
-
-#define CFG_DIVIDER_MASK 0x1F
-
-/* root set rate for clocks with half integer and MND divider */
-void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
- int div, int m, int n, int source)
-{
- u32 cfg;
- /* M value for MND divider. */
- u32 m_val = m;
- /* NOT(N-M) value for MND divider. */
- u32 n_val = ~((n) - (m)) * !!(n);
- /* NOT 2D value for MND divider. */
- u32 d_val = ~(n);
-
- /* Program MND values */
- writel(m_val, base + regs->M);
- writel(n_val, base + regs->N);
- writel(d_val, base + regs->D);
-
- /* setup src select and divider */
- cfg = readl(base + regs->cfg_rcgr);
- cfg &= ~CFG_MASK;
- cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
-
- /* Set the divider; HW permits fraction dividers (+0.5), but
- for simplicity, we will support integers only */
- if (div)
- cfg |= (2 * div - 1) & CFG_DIVIDER_MASK;
-
- if (n_val)
- cfg |= CFG_MODE_DUAL_EDGE;
-
- writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
-
- /* Inform h/w to start using the new config. */
- clk_bcr_update(base + regs->cmd_rcgr);
-}
-
-/* root set rate for clocks with half integer and mnd_width=0 */
-void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
- int source)
-{
- u32 cfg;
-
- /* setup src select and divider */
- cfg = readl(base + regs->cfg_rcgr);
- cfg &= ~CFG_MASK;
- cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
-
- /*
- * Set the divider; HW permits fraction dividers (+0.5), but
- * for simplicity, we will support integers only
- */
- if (div)
- cfg |= (2 * div - 1) & CFG_DIVIDER_MASK;
-
- writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
-
- /* Inform h/w to start using the new config. */
- clk_bcr_update(base + regs->cmd_rcgr);
-}
-
-static int msm_clk_probe(struct udevice *dev)
-{
- struct msm_clk_priv *priv = dev_get_priv(dev);
-
- priv->base = dev_read_addr(dev);
- if (priv->base == FDT_ADDR_T_NONE)
- return -EINVAL;
-
- return 0;
-}
-
-static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
-{
- return msm_set_rate(clk, rate);
-}
-
-static int msm_clk_enable(struct clk *clk)
-{
- return msm_enable(clk);
-}
-
-static struct clk_ops msm_clk_ops = {
- .set_rate = msm_clk_set_rate,
- .enable = msm_clk_enable,
-};
-
-static const struct udevice_id msm_clk_ids[] = {
- { .compatible = "qcom,gcc-msm8916" },
- { .compatible = "qcom,gcc-apq8016" },
- { .compatible = "qcom,gcc-msm8996" },
- { .compatible = "qcom,gcc-apq8096" },
- { .compatible = "qcom,gcc-sdm845" },
- { .compatible = "qcom,gcc-qcs404" },
- { }
-};
-
-U_BOOT_DRIVER(clk_msm) = {
- .name = "clk_msm",
- .id = UCLASS_CLK,
- .of_match = msm_clk_ids,
- .ops = &msm_clk_ops,
- .priv_auto = sizeof(struct msm_clk_priv),
- .probe = msm_clk_probe,
-};
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Qualcomm APQ8016, APQ8096, SDM845
- *
- * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
- */
-#ifndef _CLOCK_SNAPDRAGON_H
-#define _CLOCK_SNAPDRAGON_H
-
-#define CFG_CLK_SRC_CXO (0 << 8)
-#define CFG_CLK_SRC_GPLL0 (1 << 8)
-#define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
-#define CFG_CLK_SRC_MASK (7 << 8)
-
-struct pll_vote_clk {
- uintptr_t status;
- int status_bit;
- uintptr_t ena_vote;
- int vote_bit;
-};
-
-struct vote_clk {
- uintptr_t cbcr_reg;
- uintptr_t ena_vote;
- int vote_bit;
-};
-struct bcr_regs {
- uintptr_t cfg_rcgr;
- uintptr_t cmd_rcgr;
- uintptr_t M;
- uintptr_t N;
- uintptr_t D;
-};
-
-struct msm_clk_priv {
- phys_addr_t base;
-};
-
-void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0);
-void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
-void clk_enable_cbc(phys_addr_t cbcr);
-void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk);
-void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
- int div, int m, int n, int source);
-void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
- int source);
-
-#endif
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Empty gpio.h
+ * Qualcomm common pin control data.
*
- * This file must stay as arch/arm/include/asm/gpio.h requires it.
- *
- * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ * Copyright (C) 2023 Linaro Ltd.
*/
+#ifndef _QCOM_GPIO_H_
+#define _QCOM_GPIO_H_
+
+#include <asm/types.h>
+#include <stdbool.h>
+
+struct msm_pin_data {
+ int pin_count;
+ const unsigned int *pin_offsets;
+};
+
+static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector)
+{
+ u32 out = (selector * 0x1000);
+
+ if (offs)
+ return out + offs[selector];
+
+ return out;
+}
+
+#endif /* _QCOM_GPIO_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Qualcomm APQ8916 sysmap
- *
- * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
- */
-#ifndef _MACH_SYSMAP_APQ8016_H
-#define _MACH_SYSMAP_APQ8016_H
-
-#define GICD_BASE (0x0b000000)
-#define GICC_BASE (0x0b002000)
-
-/* Clocks: (from CLK_CTL_BASE) */
-#define GPLL0_STATUS (0x2101C)
-#define APCS_GPLL_ENA_VOTE (0x45000)
-#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
-
-#define SDCC_BCR(n) ((n * 0x1000) + 0x41000)
-#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004)
-#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008)
-#define SDCC_M(n) ((n * 0x1000) + 0x4100C)
-#define SDCC_N(n) ((n * 0x1000) + 0x41010)
-#define SDCC_D(n) ((n * 0x1000) + 0x41014)
-#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018)
-#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C)
-
-/* BLSP1 AHB clock (root clock for BLSP) */
-#define BLSP1_AHB_CBCR 0x1008
-
-/* Uart clock control registers */
-#define BLSP1_UART2_BCR (0x3028)
-#define BLSP1_UART2_APPS_CBCR (0x302C)
-#define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
-#define BLSP1_UART2_APPS_CFG_RCGR (0x3038)
-#define BLSP1_UART2_APPS_M (0x303C)
-#define BLSP1_UART2_APPS_N (0x3040)
-#define BLSP1_UART2_APPS_D (0x3044)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Qualcomm APQ8096 sysmap
- *
- * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
- */
-#ifndef _MACH_SYSMAP_APQ8096_H
-#define _MACH_SYSMAP_APQ8096_H
-
-#define TLMM_BASE_ADDR (0x1010000)
-
-/* Strength (sdc1) */
-#define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000)
-
-/* Clocks: (from CLK_CTL_BASE) */
-#define GPLL0_STATUS (0x0000)
-#define APCS_GPLL_ENA_VOTE (0x52000)
-#define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004)
-
-#define SDCC2_BCR (0x14000) /* block reset */
-#define SDCC2_APPS_CBCR (0x14004) /* branch control */
-#define SDCC2_AHB_CBCR (0x14008)
-#define SDCC2_CMD_RCGR (0x14010)
-#define SDCC2_CFG_RCGR (0x14014)
-#define SDCC2_M (0x14018)
-#define SDCC2_N (0x1401C)
-#define SDCC2_D (0x14020)
-
-#define BLSP2_AHB_CBCR (0x25004)
-#define BLSP2_UART2_APPS_CBCR (0x29004)
-#define BLSP2_UART2_APPS_CMD_RCGR (0x2900C)
-#define BLSP2_UART2_APPS_CFG_RCGR (0x29010)
-#define BLSP2_UART2_APPS_M (0x29014)
-#define BLSP2_UART2_APPS_N (0x29018)
-#define BLSP2_UART2_APPS_D (0x2901C)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Qualcomm QCS404 sysmap
- *
- * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
- */
-#ifndef _MACH_SYSMAP_QCS404_H
-#define _MACH_SYSMAP_QCS404_H
-
-#define GICD_BASE (0x0b000000)
-#define GICC_BASE (0x0b002000)
-
-/* Clocks: (from CLK_CTL_BASE) */
-#define GPLL0_STATUS (0x21000)
-#define GPLL1_STATUS (0x20000)
-#define APCS_GPLL_ENA_VOTE (0x45000)
-#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
-
-/* BLSP1 AHB clock (root clock for BLSP) */
-#define BLSP1_AHB_CBCR 0x1008
-
-/* Uart clock control registers */
-#define BLSP1_UART2_BCR (0x3028)
-#define BLSP1_UART2_APPS_CBCR (0x302C)
-#define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
-#define BLSP1_UART2_APPS_CFG_RCGR (0x3038)
-#define BLSP1_UART2_APPS_M (0x303C)
-#define BLSP1_UART2_APPS_N (0x3040)
-#define BLSP1_UART2_APPS_D (0x3044)
-
-/* I2C controller clock control registerss */
-#define BLSP1_QUP0_I2C_APPS_CBCR (0x6028)
-#define BLSP1_QUP0_I2C_APPS_CMD_RCGR (0x602C)
-#define BLSP1_QUP0_I2C_APPS_CFG_RCGR (0x6030)
-#define BLSP1_QUP1_I2C_APPS_CBCR (0x2008)
-#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x200C)
-#define BLSP1_QUP1_I2C_APPS_CFG_RCGR (0x2010)
-#define BLSP1_QUP2_I2C_APPS_CBCR (0x3010)
-#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x3000)
-#define BLSP1_QUP2_I2C_APPS_CFG_RCGR (0x3004)
-#define BLSP1_QUP3_I2C_APPS_CBCR (0x4020)
-#define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x4000)
-#define BLSP1_QUP3_I2C_APPS_CFG_RCGR (0x4004)
-#define BLSP1_QUP4_I2C_APPS_CBCR (0x5020)
-#define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x5000)
-#define BLSP1_QUP4_I2C_APPS_CFG_RCGR (0x5004)
-
-/* SD controller clock control registers */
-#define SDCC_BCR(n) (((n) * 0x1000) + 0x41000)
-#define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x41004)
-#define SDCC_CFG_RCGR(n) (((n) * 0x1000) + 0x41008)
-#define SDCC_M(n) (((n) * 0x1000) + 0x4100C)
-#define SDCC_N(n) (((n) * 0x1000) + 0x41010)
-#define SDCC_D(n) (((n) * 0x1000) + 0x41014)
-#define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018)
-#define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C)
-
-/* USB-3.0 controller clock control registers */
-#define SYS_NOC_USB3_CBCR (0x26014)
-#define USB30_BCR (0x39000)
-#define USB3PHY_BCR (0x39008)
-#define USB30_MASTER_CBCR (0x3900C)
-#define USB30_SLEEP_CBCR (0x39010)
-#define USB30_MOCK_UTMI_CBCR (0x39014)
-#define USB30_MOCK_UTMI_CMD_RCGR (0x3901C)
-#define USB30_MOCK_UTMI_CFG_RCGR (0x39020)
-#define USB30_MASTER_CMD_RCGR (0x39028)
-#define USB30_MASTER_CFG_RCGR (0x3902C)
-#define USB30_MASTER_M (0x39030)
-#define USB30_MASTER_N (0x39034)
-#define USB30_MASTER_D (0x39038)
-#define USB2A_PHY_SLEEP_CBCR (0x4102C)
-#define USB_HS_PHY_CFG_AHB_CBCR (0x41030)
-
-/* ETH controller clock control registers */
-#define ETH_PTP_CBCR (0x4e004)
-#define ETH_RGMII_CBCR (0x4e008)
-#define ETH_SLAVE_AHB_CBCR (0x4e00c)
-#define ETH_AXI_CBCR (0x4e010)
-#define EMAC_PTP_CMD_RCGR (0x4e014)
-#define EMAC_PTP_CFG_RCGR (0x4e018)
-#define EMAC_CMD_RCGR (0x4e01c)
-#define EMAC_CFG_RCGR (0x4e020)
-#define EMAC_M (0x4e024)
-#define EMAC_N (0x4e028)
-#define EMAC_D (0x4e02c)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Qualcomm SDM845 sysmap
- *
- * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
- */
-#ifndef _MACH_SYSMAP_SDM845_H
-#define _MACH_SYSMAP_SDM845_H
-
-#define TLMM_BASE_ADDR (0x1010000)
-
-/* Strength (sdc1) */
-#define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000)
-
-/* Clocks: (from CLK_CTL_BASE) */
-#define GPLL0_STATUS (0x0000)
-#define APCS_GPLL_ENA_VOTE (0x52000)
-#define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004)
-
-#define SDCC2_BCR (0x14000) /* block reset */
-#define SDCC2_APPS_CBCR (0x14004) /* branch control */
-#define SDCC2_AHB_CBCR (0x14008)
-#define SDCC2_CMD_RCGR (0x1400c)
-#define SDCC2_CFG_RCGR (0x14010)
-#define SDCC2_M (0x14014)
-#define SDCC2_N (0x14018)
-#define SDCC2_D (0x1401C)
-
-#define RCG2_CFG_REG 0x4
-#define M_REG 0x8
-#define N_REG 0xc
-#define D_REG 0x10
-
-#define SE9_AHB_CBCR (0x25004)
-#define SE9_UART_APPS_CBCR (0x29004)
-#define SE9_UART_APPS_CMD_RCGR (0x18148)
-#define SE9_UART_APPS_CFG_RCGR (0x1814C)
-#define SE9_UART_APPS_M (0x18150)
-#define SE9_UART_APPS_N (0x18154)
-#define SE9_UART_APPS_D (0x18158)
-
-#endif
* (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
*/
+#include <button.h>
#include <init.h>
#include <env.h>
#include <common.h>
/* Check for vol- and power buttons */
__weak int misc_init_r(void)
{
- struct udevice *pon;
- struct gpio_desc resin;
- int node, ret;
+ struct udevice *btn;
+ int ret;
+ enum button_state_t state;
- ret = uclass_get_device_by_name(UCLASS_GPIO, "pm8998_pon@800", &pon);
+ ret = button_get_by_label("pwrkey", &btn);
if (ret < 0) {
- printf("Failed to find PMIC pon node. Check device tree\n");
- return 0;
+ printf("Couldn't find power button!\n");
+ return ret;
}
- node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
- "key_vol_down");
- if (node < 0) {
- printf("Failed to find key_vol_down node. Check device tree\n");
- return 0;
- }
- if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
- &resin, 0)) {
- printf("Failed to request key_vol_down button.\n");
- return 0;
- }
- if (dm_gpio_get_value(&resin)) {
- env_set("key_vol_down", "1");
- printf("Volume down button pressed\n");
- } else {
- env_set("key_vol_down", "0");
- }
-
- node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
- "key_power");
- if (node < 0) {
- printf("Failed to find key_power node. Check device tree\n");
- return 0;
- }
- if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
- &resin, 0)) {
- printf("Failed to request key_power button.\n");
- return 0;
- }
- if (dm_gpio_get_value(&resin)) {
+ state = button_get_state(btn);
+ if (state == BUTTON_ON) {
env_set("key_power", "1");
printf("Power button pressed\n");
} else {
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm SDM845 pinctrl
- *
- * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
- *
- */
-
-#include "pinctrl-snapdragon.h"
-#include <common.h>
-
-#define MAX_PIN_NAME_LEN 32
-static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
-
-static const struct pinctrl_function msm_pinctrl_functions[] = {
- {"qup9", 1},
- {"gpio", 0},
-};
-
-static const char *sdm845_get_function_name(struct udevice *dev,
- unsigned int selector)
-{
- return msm_pinctrl_functions[selector].name;
-}
-
-static const char *sdm845_get_pin_name(struct udevice *dev,
- unsigned int selector)
-{
- snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
- return pin_name;
-}
-
-static unsigned int sdm845_get_function_mux(unsigned int selector)
-{
- return msm_pinctrl_functions[selector].val;
-}
-
-struct msm_pinctrl_data sdm845_data = {
- .pin_count = 150,
- .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
- .get_function_name = sdm845_get_function_name,
- .get_function_mux = sdm845_get_function_mux,
- .get_pin_name = sdm845_get_pin_name,
-};
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Qualcomm Pin control
- *
- * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
- *
- */
-#ifndef _PINCTRL_SNAPDRAGON_H
-#define _PINCTRL_SNAPDRAGON_H
-
-struct udevice;
-
-struct msm_pinctrl_data {
- int pin_count;
- int functions_count;
- const char *(*get_function_name)(struct udevice *dev,
- unsigned int selector);
- unsigned int (*get_function_mux)(unsigned int selector);
- const char *(*get_pin_name)(struct udevice *dev,
- unsigned int selector);
-};
-
-struct pinctrl_function {
- const char *name;
- int val;
-};
-
-extern struct msm_pinctrl_data apq8016_data;
-extern struct msm_pinctrl_data apq8096_data;
-extern struct msm_pinctrl_data sdm845_data;
-extern struct msm_pinctrl_data qcs404_data;
-
-#endif
#ifndef __ASSEMBLY__
#include <asm/types.h>
-enum endianness {
- LITTLE_ENDIAN = 0,
- BIG_ENDIAN,
- UNKNOWN_ENDIANNESS
-};
-
int socfpga_get_handoff_size(void *handoff_address);
int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len);
#endif
#include <errno.h>
#include "log.h"
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+enum endianness {
+ LITTLE_ENDIAN = 0,
+ BIG_ENDIAN,
+ UNKNOWN_ENDIANNESS
+};
+#endif
+
static enum endianness check_endianness(u32 handoff)
{
switch (handoff) {
strerror(errno));
return -errno;
}
- return retval;
+ return 0;
}
int sandbox_eth_raw_os_recv(void *packet, int *length,
spmi_gpios: gpios@c000 {
compatible = "qcom,pm8916-gpio";
reg = <0xc000 0x400>;
+ gpio-ranges = <&spmi_gpios 0 0 4>;
gpio-controller;
gpio-count = <4>;
#gpio-cells = <2>;
- gpio-bank-name="spmi";
};
};
};
#ifdef CONFIG_GENERATE_ACPI_TABLE
{ "acpi", write_acpi_tables, BLOBLISTT_ACPI_TABLES, 0x10000, 0x1000},
#endif
-#ifdef CONFIG_GENERATE_SMBIOS_TABLE
+#if defined(CONFIG_GENERATE_SMBIOS_TABLE) && !defined(CONFIG_QFW_SMBIOS)
{ "smbios", write_smbios_table, BLOBLISTT_SMBIOS_TABLES, 0x1000, 0x100},
#endif
};
#include <mmc.h>
#include <miiphy.h>
#include <phy.h>
+#include <fdt_support.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
/* Single-chip mode */
/* Switch Port Registers */
#define MVEBU_SW_LINK_CTRL_REG (1)
+#define MVEBU_SW_PORT_SWITCH_ID (3)
#define MVEBU_SW_PORT_CTRL_REG (4)
#define MVEBU_SW_PORT_BASE_VLAN (6)
#define MVEBU_G2_SMI_PHY_CMD_REG (24)
#define MVEBU_G2_SMI_PHY_DATA_REG (25)
+#define SWITCH_88E6361_PRODUCT_NUMBER 0x2610
+
/*
* Memory Controller Registers
*
#define A3700_MC_CTRL2_SDRAM_TYPE_DDR3 2
#define A3700_MC_CTRL2_SDRAM_TYPE_DDR4 3
+static bool is_edpu_plus(void)
+{
+ struct udevice *bus;
+ ofnode node;
+ int val;
+
+ if (!CONFIG_IS_ENABLED(DM_MDIO))
+ return false;
+
+ node = ofnode_by_compatible(ofnode_null(), "marvell,orion-mdio");
+ if (!ofnode_valid(node) ||
+ uclass_get_device_by_ofnode(UCLASS_MDIO, node, &bus) ||
+ device_probe(bus)) {
+ printf("Cannot find MDIO bus\n");
+ return -ENODEV;
+ }
+
+ val = dm_mdio_read(bus, 0x0, MDIO_DEVAD_NONE, MVEBU_SW_PORT_SWITCH_ID);
+ if (val == SWITCH_88E6361_PRODUCT_NUMBER)
+ return true;
+ else
+ return false;
+}
+
int board_early_init_f(void)
{
return 0;
return 0;
}
-/* Bring-up board-specific network stuff */
-static int last_stage_init(void)
+static int espressobin_last_stage_init(void)
{
struct udevice *bus;
ofnode node;
- if (!CONFIG_IS_ENABLED(DM_MDIO) ||
- !of_machine_is_compatible("globalscale,espressobin"))
+ if (!CONFIG_IS_ENABLED(DM_MDIO))
return 0;
node = ofnode_by_compatible(ofnode_null(), "marvell,orion-mdio");
return 0;
}
-EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
+static int edpu_plus_last_stage_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (is_edpu_plus()) {
+ ret = uclass_get_device_by_name(UCLASS_ETH,
+ "ethernet@40000",
+ &dev);
+ if (!ret) {
+ device_remove(dev, DM_REMOVE_NORMAL);
+ device_unbind(dev);
+ }
+
+ /* Currently no networking support on the eDPU+ board */
+ ret = uclass_get_device_by_name(UCLASS_ETH,
+ "ethernet@30000",
+ &dev);
+ if (!ret) {
+ device_remove(dev, DM_REMOVE_NORMAL);
+ device_unbind(dev);
+ }
+ } else {
+ ret = uclass_get_device_by_name(UCLASS_ETH,
+ "ethernet@30000",
+ &dev);
+ if (!ret) {
+ device_remove(dev, DM_REMOVE_NORMAL);
+ device_unbind(dev);
+ }
+ }
+
+ return 0;
+}
+
+/* Bring-up board-specific network stuff */
+static int last_stage_init(void)
+{
+
+ if (of_machine_is_compatible("globalscale,espressobin"))
+ return espressobin_last_stage_init();
+
+ if (of_machine_is_compatible("methode,edpu"))
+ return edpu_plus_last_stage_init();
+
+ return 0;
+}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
#endif
#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, struct bd_info *bd)
+static int espressobin_fdt_setup(void *blob)
{
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
int ret;
int spi_off;
int parts_off;
int part_off;
/* Fill SPI MTD partitions for Linux kernel on Espressobin */
- if (!of_machine_is_compatible("globalscale,espressobin"))
- return 0;
-
spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
if (spi_off < 0)
return 0;
return 0;
}
+ return 0;
+}
+
+static int edpu_plus_fdt_setup(void *blob)
+{
+ const char *ports[] = { "downlink", "uplink" };
+ uint8_t mac[ETH_ALEN];
+ const char *path;
+ int i, ret;
+
+ if (is_edpu_plus()) {
+ ret = fdt_set_status_by_compatible(blob,
+ "marvell,orion-mdio",
+ FDT_STATUS_OKAY);
+ if (ret)
+ printf("Failed to enable MDIO!\n");
+
+ ret = fdt_set_status_by_alias(blob,
+ "ethernet1",
+ FDT_STATUS_DISABLED);
+ if (ret)
+ printf("Failed to disable ethernet1!\n");
+
+ path = fdt_get_alias(blob, "ethernet0");
+ if (path)
+ do_fixup_by_path_string(blob, path, "phy-mode", "2500base-x");
+ else
+ printf("Failed to update ethernet0 phy-mode to 2500base-x!\n");
+
+ ret = fdt_set_status_by_compatible(blob,
+ "marvell,mv88e6190",
+ FDT_STATUS_OKAY);
+ if (ret)
+ printf("Failed to enable MV88E6361!\n");
+
+ /*
+ * MAC-s for Uplink and Downlink ports are stored under
+ * non standard variable names, so lets manually fixup the
+ * switch port nodes to have the desired MAC-s.
+ */
+ for (i = 0; i < 2; i++) {
+ if (eth_env_get_enetaddr(ports[i], mac)) {
+ do_fixup_by_prop(blob,
+ "label",
+ ports[i],
+ strlen(ports[i]) + 1,
+ "mac-address",
+ mac, ARP_HLEN, 1);
+
+ do_fixup_by_prop(blob,
+ "label",
+ ports[i],
+ strlen(ports[i]) + 1,
+ "local-mac-address",
+ mac, ARP_HLEN, 1);
+ }
+ }
+ }
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+ if (of_machine_is_compatible("globalscale,espressobin"))
+ return espressobin_fdt_setup(blob);
#endif
+ if (of_machine_is_compatible("methode,edpu"))
+ return edpu_plus_fdt_setup(blob);
+
return 0;
}
#endif
imply NVME_PCI
imply PCIE_ECAM_GENERIC
imply DM_RNG
+ imply DM_RTC
+ imply RTC_GOLDFISH
imply SCSI
imply SYS_NS16550
imply SIFIVE_SERIAL
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Struct for boot image source description for placing in last
+ * two SPI NOR flash sectors on legcom.
+ */
+
+struct boot_img_src {
+ u8 magic; /* Must be 'B' = 0x42 */
+ u8 flags; /* flags to specify mmcblk[0|1] boot[0|1] */
+ u8 crc8; /* CRC-8 over above two bytes */
+} __packed;
+
+/*
+ * Bit definition in boot_img_src.flags:
+ * Bit 0: mmcblk device 0 or 1 (1 - if this bit set)
+ * Bit 1: mmcblk boot partition 0 or 1.
+ * for eMMC: boot0 if this bit is cleared, boot1 - if set
+ * for SD-card the boot partition value will always be 0
+ * (independent of the value of this bit)
+ *
+ */
+#define BOOT_SRC_MMC1 BIT(0)
+#define BOOT_SRC_PART1 BIT(1)
+
+/* Offset of the first boot image source descriptor in SPI NOR */
+#define SPI_FLASH_BOOT_SRC_OFFS 0xFE0000
+#define SPI_FLASH_SECTOR_SIZE 0x10000
#include <errno.h>
#include <usb.h>
#include <serial.h>
+#include <u-boot/crc.h>
+#include "boot_img_scr.h"
+
+#include <spi.h>
+#include <spi_flash.h>
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
preloader_console_init();
}
+static struct boot_img_src img_src[2];
+static int spi_load_boot_info(void)
+{
+ struct spi_flash *flash;
+ int err;
+
+ flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
+ CONFIG_SF_DEFAULT_CS,
+ CONFIG_SF_DEFAULT_SPEED,
+ CONFIG_SF_DEFAULT_MODE);
+ if (!flash) {
+ printf("%s: SPI probe err\n", __func__);
+ return -ENODEV;
+ }
+
+ /*
+ * Load both boot info structs from SPI flash
+ */
+ err = spi_flash_read(flash, SPI_FLASH_BOOT_SRC_OFFS,
+ sizeof(img_src[0]),
+ (void *)&img_src[0]);
+ if (err) {
+ debug("%s: First boot info NOR sector read error %d\n",
+ __func__, err);
+ return err;
+ }
+
+ err = spi_flash_read(flash,
+ SPI_FLASH_BOOT_SRC_OFFS + SPI_FLASH_SECTOR_SIZE,
+ sizeof(img_src[0]),
+ (void *)&img_src[1]);
+ if (err) {
+ debug("%s: First boot info NOR sector read error %d\n",
+ __func__, err);
+ return err;
+ }
+
+ debug("%s: BI0 0x%x 0x%x 0x%x\n", __func__,
+ img_src[0].magic, img_src[0].flags, img_src[0].crc8);
+
+ debug("%s: BI1 0x%x 0x%x 0x%x\n", __func__,
+ img_src[1].magic, img_src[1].flags, img_src[1].crc8);
+
+ return 0;
+}
+
static int boot_tiva0, boot_tiva1;
/* Check if TIVAs request booting via U-Boot proper */
boot_tiva1 = dm_gpio_get_value(&btiva1);
}
+int spl_mmc_emmc_boot_partition(struct mmc *mmc)
+{
+ int i, src_idx = -1, ret;
+
+ ret = spi_load_boot_info();
+ if (ret) {
+ printf("%s: Cannot read XEA boot info! [%d]\n", __func__, ret);
+ /* To avoid bricking board - by default boot from boot0 eMMC */
+ return 1;
+ }
+
+ for (i = 0; i < 2; i++) {
+ if (img_src[i].magic == 'B' &&
+ img_src[i].crc8 == crc8(0, &img_src[i].magic, 2)) {
+ src_idx = i;
+ break;
+ }
+ }
+
+ debug("%s: src idx: %d\n", __func__, src_idx);
+
+ if (src_idx < 0)
+ /*
+ * Always use eMMC (mmcblkX) boot0 if no
+ * valid image source description found
+ */
+ return 1;
+
+ if (img_src[src_idx].flags & BOOT_SRC_PART1)
+ return 2;
+
+ return 1;
+}
+
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = BOOT_DEVICE_MMC1;
--- /dev/null
+bootmode=update
+bootpri=mmc_mmc
+bootsec=sf_swu
+consdev=ttyAMA0
+baudrate=115200
+dtbfile=imx28-xea.dtb
+rootdev=/dev/mmcblk0p2
+netdev=eth0
+swufile=swupdate-image-xea-upd.itb
+sf_kernel_offset=0xA0000
+sf_swu_size=0xF40000
+ethact=FEC
+arch=xea
+lwe_env=
+ if dhcp ${loadaddr} ${hostname}/${lwe_uenv} ; then
+ source ${loadaddr};
+ fi
+lwe_uenv=env_uboot_xea.bin
+do_update_mmc=
+ if mmc rescan ; then
+ mmc dev 0 ${update_mmc_part} ;
+ if dhcp ${hostname}/${update_filename} ; then
+ setexpr fw_sz ${filesize} / 0x200 ;
+ setexpr fw_sz ${fw_sz} + 1 ;
+ mmc write ${loadaddr} ${update_offset} ${fw_sz} ;
+ fi ;
+ fi
+do_update_sf=
+ if sf probe ; then
+ if dhcp ${hostname}/${update_filename} ; then
+ sf erase ${update_offset} +${filesize} ;
+ sf write ${loadaddr} ${update_offset} ${filesize} ;
+ fi ;
+ fi
+factory_reset=
+ if sf probe ; then
+ run update_swu ;
+ setenv bootmode update ;
+ saveenv ;
+ fi
+update_spl_filename=u-boot.sb
+update_spl=
+ setenv update_filename ${update_spl_filename} ;
+ setenv update_offset 0 ;
+ run do_update_sf
+update_uboot_filename=u-boot.img
+update_uboot=
+ setenv update_filename ${update_uboot_filename} ;
+ setenv update_offset 0x10000 ;
+ run do_update_sf ;
+ setenv update_mmc_part 1 ;
+ setenv update_offset 0 ;
+ run do_update_mmc ;
+ setenv update_mmc_part 2 ;
+ run do_update_mmc
+update_kernel_filename=uImage
+update_kernel=
+ setenv update_mmc_part 1 ;
+ setenv update_filename ${update_kernel_filename} ;
+ setenv update_offset 0x800 ;
+ run do_update_mmc ;
+ setenv update_filename ${dtbfile} ;
+ setenv update_offset 0x400 ;
+ run do_update_mmc
+update_swu=
+ setenv update_filename ${swufile} ;
+ setenv update_offset ${sf_kernel_offset} ;
+ run do_update_sf
+addcons=
+ setenv bootargs ${bootargs}
+ console=${consdev},${baudrate}
+addip=
+ setenv bootargs ${bootargs}
+ ip=${ipaddr}:${serverip}:${gatewayip}:
+ ${netmask}:${hostname}:${netdev}:off
+addmisc=
+ setenv bootargs ${bootargs} ${miscargs}
+addargs=run addcons addmisc
+mmcload=
+ mmc rescan ;
+ mmc dev 0 1 ;
+ mmc read ${loadaddr} 0x800 0x2000 ;
+ mmc read ${dtbaddr} 0x400 0x80
+netload=
+ dhcp ${loadaddr} ${hostname}/${bootfile} ;
+ tftp ${dtbaddr} ${hostname}/${dtbfile}
+usbload=
+ usb start ;
+ load usb 0:1 ${loadaddr} ${bootfile}
+miscargs=panic=1
+mmcargs=setenv bootargs root=${rootdev} rw rootwait
+nfsargs=
+ setenv bootargs root=/dev/nfs rw
+ nfsroot=${serverip}:${rootpath},v3,tcp
+mmc_mmc=
+ if run mmcload mmcargs addargs ; then
+ bootm ${loadaddr} - ${dtbaddr} ;
+ fi
+mmc_nfs=
+ if run mmcload nfsargs addip addargs ; then
+ bootm ${loadaddr} - ${dtbaddr} ;
+ fi
+sf_mmc=
+ if run sfload mmcargs addargs ; then
+ bootm ${loadaddr} - ${dtbaddr} ;
+ fi
+sf_swu=
+ if sf probe ; then
+ sf read ${loadaddr} ${sf_kernel_offset} ${sf_swu_size} ;
+ setenv bootargs root=/dev/ram0 rw ;
+ run addargs ;
+ bootm ${loadaddr} ;
+ fi
+net_mmc=
+ if run netload mmcargs addargs ; then
+ bootm ${loadaddr} - ${dtbaddr} ;
+ fi
+net_nfs=
+ if run netload nfsargs addip addargs ; then
+ bootm ${loadaddr} - ${dtbaddr} ;
+ fi
+prebootcmd=
+ if test ${envsaved} != y ; then ;
+ setenv envsaved y ;
+ saveenv ;
+ fi ;
+ if test ${bootmode} = normal ; then
+ setenv bootdelay 0 ;
+ setenv bootpri mmc_mmc ;
+ elif test ${bootmode} = devel ; then
+ setenv bootdelay 3 ;
+ setenv bootpri net_mmc ;
+ else
+ if test ${bootmode} != update ; then
+ echo Warning: unknown bootmode ${bootmode} ;
+ fi ;
+ setenv bootdelay 1 ;
+ setenv bootpri sf_swu ;
+ fi
obj- := __dummy__.o
endif
-obj-$(CONFIG_PHYTEC_SOM_DETECTION) += phytec_som_detection.o
-obj-$(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) += imx8m_som_detection.o
+obj-y += phytec_som_detection.o
+obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o
*/
#include <common.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/arch/sys_proto.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <i2c.h>
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH
+# Author: Wadim Egorov <w.egorov@phytec.de>
+
+if TARGET_PHYCORE_AM62X_A53
+
+config SYS_BOARD
+ default "phycore_am62x"
+
+config SYS_VENDOR
+ default "phytec"
+
+config SYS_CONFIG_NAME
+ default "phycore_am62x"
+
+endif
+
+if TARGET_PHYCORE_AM62X_R5
+
+config SYS_BOARD
+ default "phycore_am62x"
+
+config SYS_VENDOR
+ default "phytec"
+
+config SYS_CONFIG_NAME
+ default "phycore_am62x"
+
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+endif
--- /dev/null
+phyCORE-AM62x
+M: Wadim Egorov <w.egorov@phytec.de>
+W: https://www.phytec.com/product/phycore-am62x
+S: Maintained
+F: arch/arm/dts/k3-am62-phycore-som-ddr4-2gb.dtsi
+F: arch/arm/dts/k3-am62-phycore-som.dtsi
+F: arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
+F: arch/arm/dts/k3-am625-phyboard-lyra-rdk.dts
+F: arch/arm/dts/k3-am625-phycore-som-binman.dtsi
+F: arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts
+F: board/phytec/phycore_am62x/
+F: configs/phycore_am62x_a53_defconfig
+F: configs/phycore_am62x_r5_defconfig
+F: include/configs/phycore_am62x.h
+F: doc/board/phytec/phycore-am62x.rst
--- /dev/null
+#
+# Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH
+# Author: Wadim Egorov <w.egorov@phytec.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += phycore-am62x.o
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for AM62
+#
+
+---
+
+board-cfg:
+ rev:
+ boardcfg_abi_maj : 0x0
+ boardcfg_abi_min : 0x1
+ control:
+ subhdr:
+ magic: 0xC1D3
+ size: 7
+ main_isolation_enable : 0x5A
+ main_isolation_hostid : 0x2
+ secproxy:
+ subhdr:
+ magic: 0x1207
+ size: 7
+ scaling_factor : 0x1
+ scaling_profile : 0x1
+ disable_main_nav_secure_proxy : 0
+ msmc:
+ subhdr:
+ magic: 0xA5C3
+ size: 5
+ msmc_cache_size : 0x0
+ debug_cfg:
+ subhdr:
+ magic: 0x020C
+ size: 8
+ trace_dst_enables : 0x00
+ trace_src_enables : 0x00
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ */
+
+#include <asm/io.h>
+#include <env.h>
+#include <env_internal.h>
+#include <spl.h>
+#include <fdt_support.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+#define CTRLMMR_USB0_PHY_CTRL 0x43004008
+#define CTRLMMR_USB1_PHY_CTRL 0x43004018
+#define CORE_VOLTAGE 0x80000000
+
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+ u32 val;
+
+ /* Set USB0 PHY core voltage to 0.85V */
+ val = readl(CTRLMMR_USB0_PHY_CTRL);
+ val &= ~(CORE_VOLTAGE);
+ writel(val, CTRLMMR_USB0_PHY_CTRL);
+
+ /* Set USB1 PHY core voltage to 0.85V */
+ val = readl(CTRLMMR_USB1_PHY_CTRL);
+ val &= ~(CORE_VOLTAGE);
+ writel(val, CTRLMMR_USB1_PHY_CTRL);
+
+ /* We have 32k crystal, so lets enable it */
+ val = readl(MCU_CTRL_LFXOSC_CTRL);
+ val &= ~(MCU_CTRL_LFXOSC_32K_DISABLE_VAL);
+ writel(val, MCU_CTRL_LFXOSC_CTRL);
+ /* Add any TRIM needed for the crystal here.. */
+ /* Make sure to mux up to take the SoC 32k from the crystal */
+ writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL,
+ MCU_CTRL_DEVICE_CLKOUT_32K_CTRL);
+}
+#endif
--- /dev/null
+fdtaddr=0x88000000
+loadaddr=0x82000000
+scriptaddr=0x80000000
+fdt_addr_r=0x88000000
+kernel_addr_r=0x82000000
+ramdisk_addr_r=0x88080000
+fdtoverlay_addr_r=0x89000000
+
+fdtfile=CONFIG_DEFAULT_FDT_FILE
+mmcdev=1
+mmcroot=2
+mmcpart=1
+console=ttyS2,115200n8
+mmcargs=setenv bootargs console=${console} earlycon=ns16550a,mmio32,0x02800000
+ root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw
+loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} Image
+loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdtaddr} ${fdtfile}
+mmcboot=run mmcargs;
+ mmc dev ${mmcdev};
+ mmc rescan;
+ run loadimage;
+ run loadfdt;
+ booti ${loadaddr} - ${fdtaddr}
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for AM62
+#
+
+---
+
+pm-cfg:
+ rev:
+ boardcfg_abi_maj : 0x0
+ boardcfg_abi_min : 0x1
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM62
+#
+
+---
+
+rm-cfg:
+ rm_boardcfg:
+ rev:
+ boardcfg_abi_maj : 0x0
+ boardcfg_abi_min : 0x1
+ host_cfg:
+ subhdr:
+ magic: 0x4C41
+ size : 356
+ host_cfg_entries:
+ - #1
+ host_id: 12
+ allowed_atype : 0x2A
+ allowed_qos : 0xAAAA
+ allowed_orderid : 0xAAAAAAAA
+ allowed_priority : 0xAAAA
+ allowed_sched_priority : 0xAA
+ - #2
+ host_id: 30
+ allowed_atype : 0x2A
+ allowed_qos : 0xAAAA
+ allowed_orderid : 0xAAAAAAAA
+ allowed_priority : 0xAAAA
+ allowed_sched_priority : 0xAA
+ - #3
+ host_id: 36
+ allowed_atype : 0x2A
+ allowed_qos : 0xAAAA
+ allowed_orderid : 0xAAAAAAAA
+ allowed_priority : 0xAAAA
+ allowed_sched_priority : 0xAA
+ - #4
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #5
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #6
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #7
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #8
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #9
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #10
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #11
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #12
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #13
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #14
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #15
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #16
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #17
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #18
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #19
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #20
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #21
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #22
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #23
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #24
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #25
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #26
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #27
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #28
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #29
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #30
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #31
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #32
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ resasg:
+ subhdr:
+ magic: 0x7B25
+ size : 8
+ resasg_entries_size: 960
+ reserved : 0
+ resasg_entries:
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 64
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 4
+ type: 64
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 4
+ type: 64
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 20
+ num_resource: 22
+ type: 64
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 192
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 34
+ num_resource: 2
+ type: 192
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 4
+ type: 320
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 4
+ num_resource: 4
+ type: 320
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 0
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+ type: 384
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 50176
+ num_resource: 164
+ type: 1666
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 1667
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 18
+ type: 1677
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 18
+ num_resource: 6
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+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 18
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+ reserved: 0
+
+ -
+ start_resource: 24
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+
+ -
+ start_resource: 26
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+
+ -
+ start_resource: 54
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+ reserved: 0
+
+ -
+ start_resource: 72
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+
+ -
+ start_resource: 72
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+ reserved: 0
+
+ -
+ start_resource: 78
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+
+ -
+ start_resource: 80
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+
+ -
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+
+ -
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+
+ -
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+
+ -
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+
+ -
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+
+ -
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+
+ -
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+
+ -
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+
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+
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+
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+
+ -
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+
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+
+ -
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+
+ -
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+
+ -
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+
+ -
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+
+ -
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+
+ -
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+
+ -
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+ num_resource: 256
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+ reserved: 0
+
+ -
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+
+ -
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+ num_resource: 627
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+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
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+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 4096
+ num_resource: 29
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+ reserved: 0
+
+ -
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+ num_resource: 99
+ type: 1809
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+ reserved: 0
+
+ -
+ start_resource: 5120
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+ reserved: 0
+
+ -
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+ reserved: 0
+
+ -
+ start_resource: 6144
+ num_resource: 51
+ type: 1812
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 6656
+ num_resource: 51
+ type: 1813
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 8192
+ num_resource: 32
+ type: 1814
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 8704
+ num_resource: 32
+ type: 1815
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 9216
+ num_resource: 32
+ type: 1816
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 9728
+ num_resource: 22
+ type: 1817
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 10240
+ num_resource: 22
+ type: 1818
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 10752
+ num_resource: 22
+ type: 1819
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 11264
+ num_resource: 28
+ type: 1820
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 11776
+ num_resource: 28
+ type: 1821
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 12288
+ num_resource: 28
+ type: 1822
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 1923
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1936
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1936
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1936
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1936
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1936
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 64
+ type: 1937
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 64
+ type: 1937
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 83
+ num_resource: 8
+ type: 1938
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 91
+ num_resource: 8
+ type: 1939
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 99
+ num_resource: 10
+ type: 1942
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 109
+ num_resource: 3
+ type: 1942
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 109
+ num_resource: 3
+ type: 1942
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 112
+ num_resource: 3
+ type: 1942
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 115
+ num_resource: 3
+ type: 1942
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 118
+ num_resource: 16
+ type: 1943
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 118
+ num_resource: 16
+ type: 1943
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 134
+ num_resource: 8
+ type: 1944
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 134
+ num_resource: 8
+ type: 1945
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 142
+ num_resource: 8
+ type: 1946
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 142
+ num_resource: 8
+ type: 1947
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1955
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1955
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1955
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1955
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1955
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 8
+ type: 1956
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 8
+ type: 1956
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 27
+ num_resource: 1
+ type: 1957
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 28
+ num_resource: 1
+ type: 1958
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1961
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1961
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1961
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1961
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1961
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1962
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1962
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1962
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1962
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1962
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 1963
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 1963
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 16
+ type: 1964
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 16
+ type: 1964
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 20
+ num_resource: 1
+ type: 1965
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 35
+ num_resource: 8
+ type: 1966
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 21
+ num_resource: 1
+ type: 1967
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 35
+ num_resource: 8
+ type: 1968
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 22
+ num_resource: 1
+ type: 1969
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 43
+ num_resource: 8
+ type: 1970
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 23
+ num_resource: 1
+ type: 1971
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 43
+ num_resource: 8
+ type: 1972
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 2112
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 2122
+ host_id: 12
+ reserved: 0
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security management configuration for AM62
+#
+
+---
+
+sec-cfg:
+ rev:
+ boardcfg_abi_maj : 0x0
+ boardcfg_abi_min : 0x1
+ processor_acl_list:
+ subhdr:
+ magic: 0xF1EA
+ size: 164
+ proc_acl_entries:
+ - #1
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #2
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #3
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #4
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #5
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #6
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #7
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #8
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #9
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #10
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #11
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #12
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #13
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #14
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #15
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #16
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #17
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #18
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #19
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #20
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #21
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #22
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #23
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #24
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #25
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #26
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #27
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #28
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #29
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #30
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #31
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #32
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ host_hierarchy:
+ subhdr:
+ magic: 0x8D27
+ size: 68
+ host_hierarchy_entries:
+ - #1
+ host_id: 0
+ supervisor_host_id: 0
+ - #2
+ host_id: 0
+ supervisor_host_id: 0
+ - #3
+ host_id: 0
+ supervisor_host_id: 0
+ - #4
+ host_id: 0
+ supervisor_host_id: 0
+ - #5
+ host_id: 0
+ supervisor_host_id: 0
+ - #6
+ host_id: 0
+ supervisor_host_id: 0
+ - #7
+ host_id: 0
+ supervisor_host_id: 0
+ - #8
+ host_id: 0
+ supervisor_host_id: 0
+ - #9
+ host_id: 0
+ supervisor_host_id: 0
+ - #10
+ host_id: 0
+ supervisor_host_id: 0
+ - #11
+ host_id: 0
+ supervisor_host_id: 0
+ - #12
+ host_id: 0
+ supervisor_host_id: 0
+ - #13
+ host_id: 0
+ supervisor_host_id: 0
+ - #14
+ host_id: 0
+ supervisor_host_id: 0
+ - #15
+ host_id: 0
+ supervisor_host_id: 0
+ - #16
+ host_id: 0
+ supervisor_host_id: 0
+ - #17
+ host_id: 0
+ supervisor_host_id: 0
+ - #18
+ host_id: 0
+ supervisor_host_id: 0
+ - #19
+ host_id: 0
+ supervisor_host_id: 0
+ - #20
+ host_id: 0
+ supervisor_host_id: 0
+ - #21
+ host_id: 0
+ supervisor_host_id: 0
+ - #22
+ host_id: 0
+ supervisor_host_id: 0
+ - #23
+ host_id: 0
+ supervisor_host_id: 0
+ - #24
+ host_id: 0
+ supervisor_host_id: 0
+ - #25
+ host_id: 0
+ supervisor_host_id: 0
+ - #26
+ host_id: 0
+ supervisor_host_id: 0
+ - #27
+ host_id: 0
+ supervisor_host_id: 0
+ - #28
+ host_id: 0
+ supervisor_host_id: 0
+ - #29
+ host_id: 0
+ supervisor_host_id: 0
+ - #30
+ host_id: 0
+ supervisor_host_id: 0
+ - #31
+ host_id: 0
+ supervisor_host_id: 0
+ - #32
+ host_id: 0
+ supervisor_host_id: 0
+ otp_config:
+ subhdr:
+ magic: 0x4081
+ size: 69
+ write_host_id : 0
+ otp_entry:
+ - #1
+ host_id: 0
+ host_perms: 0
+ - #2
+ host_id: 0
+ host_perms: 0
+ - #3
+ host_id: 0
+ host_perms: 0
+ - #4
+ host_id: 0
+ host_perms: 0
+ - #5
+ host_id: 0
+ host_perms: 0
+ - #6
+ host_id: 0
+ host_perms: 0
+ - #7
+ host_id: 0
+ host_perms: 0
+ - #8
+ host_id: 0
+ host_perms: 0
+ - #9
+ host_id: 0
+ host_perms: 0
+ - #10
+ host_id: 0
+ host_perms: 0
+ - #11
+ host_id: 0
+ host_perms: 0
+ - #12
+ host_id: 0
+ host_perms: 0
+ - #13
+ host_id: 0
+ host_perms: 0
+ - #14
+ host_id: 0
+ host_perms: 0
+ - #15
+ host_id: 0
+ host_perms: 0
+ - #16
+ host_id: 0
+ host_perms: 0
+ - #17
+ host_id: 0
+ host_perms: 0
+ - #18
+ host_id: 0
+ host_perms: 0
+ - #19
+ host_id: 0
+ host_perms: 0
+ - #20
+ host_id: 0
+ host_perms: 0
+ - #21
+ host_id: 0
+ host_perms: 0
+ - #22
+ host_id: 0
+ host_perms: 0
+ - #23
+ host_id: 0
+ host_perms: 0
+ - #24
+ host_id: 0
+ host_perms: 0
+ - #25
+ host_id: 0
+ host_perms: 0
+ - #26
+ host_id: 0
+ host_perms: 0
+ - #27
+ host_id: 0
+ host_perms: 0
+ - #28
+ host_id: 0
+ host_perms: 0
+ - #29
+ host_id: 0
+ host_perms: 0
+ - #30
+ host_id: 0
+ host_perms: 0
+ - #31
+ host_id: 0
+ host_perms: 0
+ - #32
+ host_id: 0
+ host_perms: 0
+ dkek_config:
+ subhdr:
+ magic: 0x5170
+ size: 12
+ allowed_hosts: [128, 0, 0, 0]
+ allow_dkek_export_tisci : 0x5A
+ rsvd: [0, 0, 0]
+ sa2ul_cfg:
+ subhdr:
+ magic: 0x23BE
+ size : 0
+ auth_resource_owner: 0
+ enable_saul_psil_global_config_writes: 0x5A
+ rsvd: [0, 0]
+ sec_dbg_config:
+ subhdr:
+ magic: 0x42AF
+ size: 16
+ allow_jtag_unlock : 0x5A
+ allow_wildcard_unlock : 0x5A
+ allowed_debug_level_rsvd: 0
+ rsvd: 0
+ min_cert_rev : 0x0
+ jtag_unlock_hosts: [0, 0, 0, 0]
+ sec_handover_cfg:
+ subhdr:
+ magic: 0x608F
+ size: 10
+ handover_msg_sender : 0
+ handover_to_host_id : 0
+ rsvd: [0, 0, 0, 0]
F: arch/arm/dts/imx8mm-phyboard-polis-rdk.dts
F: arch/arm/dts/imx8mm-phycore-som.dtsi
F: arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
+F: arch/arm/dts/imx8mm-phygate-tauri-l.dts
+F: arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi
F: board/phytec/phycore_imx8mm/
+F: configs/imx8mm-phygate-tauri-l_defconfig
F: configs/phycore-imx8mm_defconfig
+F: doc/board/phytec/imx8mm-phygate-tauri-l.rst
+F: doc/board/phytec/index.rst
+F: doc/board/phytec/phycore_imx8mm.rst
F: include/configs/phycore_imx8mm.h
F: arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
F: board/phytec/phycore_imx8mp/
F: configs/phycore-imx8mp_defconfig
+F: doc/board/phytec/phycore-imx8mp.rst
F: include/configs/phycore_imx8mp.h
--- /dev/null
+if TARGET_PE2201
+
+config SYS_BOARD
+ default "pe2201"
+
+config SYS_VENDOR
+ default "phytium"
+
+config SYS_CONFIG_NAME
+ default "pe2201"
+
+endif
--- /dev/null
+PE2201 BOARD
+M: lixinde <lixinde@phytium.com.cn>
+M: weichangzheng <weichangzheng@phytium.com.cn>
+S: Maintained
+F: board/phytium/pe2201/*
+F: include/configs/pe2201.h
+F: configs/pe2201_defconfig
+F: arch/arm/dts/phytium-pe2201.dts
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023, Phytium Technology Co., Ltd.
+# lixinde <lixinde@phytium.com.cn>
+# weichangzheng <weichangzheng@phytium.com.cn>
+#
+
+obj-y += pe2201.o
+obj-y += pll.o
+obj-y += pcie.o
+obj-y += ddr.o
+obj-y += sec.o
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023, Phytium Technology Co., Ltd.
+ * lixinde <lixinde@phytium.com.cn>
+ * weichangzheng <weichangzheng@phytium.com.cn>
+ */
+
+#ifndef _FT_PE2201_H
+#define _FT_PE2201_H
+
+/* SMCCC ID */
+#define CPU_SVC_VERSION 0xC2000F00
+#define CPU_GET_RST_SOURCE 0xC2000F01
+#define CPU_INIT_PLL 0xC2000F02
+#define CPU_INIT_PCIE 0xC2000F03
+#define CPU_INIT_MEM 0xC2000F04
+#define CPU_INIT_SEC_SVC 0xC2000F05
+
+/* CPU RESET */
+#define CPU_RESET_POWER_ON 0x1
+#define CPU_RESET_PLL 0x4
+#define CPU_RESET_WATCH_DOG 0x8
+
+/* PLL */
+#define PARAMETER_PLL_MAGIC 0x54460020
+
+/* PCIE */
+#define PARAMETER_PCIE_MAGIC 0x54460021
+#define CFG_INDEPENDENT_TREE 0x0
+#define PCI_PEU0 0x1
+#define PCI_PEU1 0x1
+#define PEU1_OFFSET 16
+#define PEU_C_OFFSET_MODE 16
+#define PEU_C_OFFSET_SPEED 0
+#define X1X1X1X1 0x2
+#define X1X1 0x0
+#define EP_MODE 0x0
+#define RC_MODE 0x1
+#define GEN3 3
+
+/* DDR */
+#define PARAMETER_MCU_MAGIC 0x54460024
+#define PARAM_MCU_VERSION 0x3
+#define PARAM_MCU_SIZE 0x100
+#define PARAM_CH_ENABLE 0x1
+
+#define RDIMM_TYPE 0x1
+#define UDIMM_TYPE 0x2
+#define LPDDR4_TYPE 0x10
+#define DIMM_X8 0x1
+#define DIMM_X16 0x2
+#define NO_MIRROR 0x0
+#define NO_ECC_TYPE 0
+#define DDR4_TYPE 0xC
+
+/* SEC */
+#define PARAMETER_COMMON_MAGIC 0x54460013
+
+void ddr_init(void);
+void sec_init(void);
+void check_reset(void);
+void pcie_init(void);
+
+#endif /* _FT_PE2201_H */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023, Phytium Technology Co., Ltd.
+ * lixinde <lixinde@phytium.com.cn>
+ * weichangzheng <weichangzheng@phytium.com.cn>
+ */
+
+#include <stdio.h>
+#include <linux/arm-smccc.h>
+#include <init.h>
+#include "cpu.h"
+
+struct ddr_spd {
+ /***************** read from spd ******************/
+ u8 dimm_type; /* 1: RDIMM; 2: UDIMM; 3: SODIMM; 4: LRDIMM */
+ u8 data_width; /* 0: x4; 1: x8; 2: x16; 3: x32 */
+ u8 mirror_type; /* 0: standard; 1: mirror */
+ u8 ecc_type; /* 0: no-ecc; 1: ecc */
+ u8 dram_type; /* 0xB: DDR3; 0xC: DDR4 */
+ u8 rank_num;
+ u8 row_num;
+ u8 col_num;
+
+ u8 bg_num; /* DDR4/DDR5 */
+ u8 bank_num;
+ u16 module_manufacturer_id;
+ u16 taamin;
+ u16 trcdmin;
+
+ u16 trpmin;
+ u16 trasmin;
+ u16 trcmin;
+ u16 tfawmin; /* only DDR3/DDR4 */
+
+ u16 trrd_smin; /* only DDR4 */
+ u16 trrd_lmin; /* only DDR4 */
+ u16 tccd_lmin; /* only DDR4 */
+ u16 twrmin;
+
+ u16 twtr_smin; /* only DDR4 */
+ u16 twtr_lmin; /* only DDR4 */
+ u32 trfc1min;
+
+ u32 trfc2min;
+ u32 trfc4_rfcsbmin; /* DDR4: tRFC4min; DDR5: tRFCsbmin */
+ u8 resv[8];
+
+ /***************** RCD control words ******************/
+ u8 f0rc03; /* bit[3:2]:CS bit[1:0]:CA */
+ u8 f0rc04; /* bit[3:2]:ODT bit[1:0]:CKE */
+ u8 f0rc05; /* bit[3:2]:CLK-A side bit[1:0]:CLK-B side */
+ u8 rcd_num; /* Registers used on RDIMM */
+
+ u8 lrdimm_resv[4];
+ u8 lrdimm_resv1[8];
+ u8 lrdimm_resv2[8];
+} __attribute((aligned(4)));
+
+struct mcu_config {
+ u32 magic;
+ u32 version;
+ u32 size;
+ u8 rev1[4];
+
+ u8 ch_enable;
+ u8 resv1[7];
+
+ u64 misc_enable;
+
+ u8 train_debug;
+ u8 train_recover;
+ u8 train_param_type;
+ u8 train_param_1; /* DDR4: cpu_odt */
+ u8 train_param_2; /* DDR4: cpu_drv */
+ u8 train_param_3; /* DDR4: mr_drv */
+ u8 train_param_4; /* DDR4: rtt_nom */
+ u8 train_param_5; /* DDR4: rtt_park */
+
+ u8 train_param_6; /* DDR4: rtt_wr */
+ u8 resv2[7];
+
+ /***************** for LPDDR4 dq swap ******************/
+ u32 data_byte_swap;
+ u32 slice0_dq_swizzle;
+
+ u32 slice1_dq_swizzle;
+ u32 slice2_dq_swizzle;
+
+ u32 slice3_dq_swizzle;
+ u32 slice4_dq_swizzle;
+
+ u32 slice5_dq_swizzle;
+ u32 slice6_dq_swizzle;
+
+ u32 slice7_dq_swizzle;
+ u8 resv3[4];
+ u8 resv4[8];
+
+ struct ddr_spd ddr_spd_info;
+} __attribute((aligned(4)));
+
+static void get_mcu_up_info_default(struct mcu_config *pm)
+{
+ pm->magic = PARAMETER_MCU_MAGIC;
+ pm->version = PARAM_MCU_VERSION;
+ pm->size = PARAM_MCU_SIZE;
+ pm->ch_enable = PARAM_CH_ENABLE;
+}
+
+static u8 init_dimm_param(struct mcu_config *pm)
+{
+ debug("manual config dimm info...\n");
+ pm->misc_enable = 0x2001;
+ pm->train_debug = 0x0;
+ pm->train_recover = 0x0;
+ pm->train_param_type = 0x0;
+ pm->train_param_1 = 0x0;
+ pm->train_param_2 = 0x0;
+ pm->train_param_3 = 0x0;
+ pm->train_param_4 = 0x0;
+ pm->train_param_5 = 0x0;
+ pm->train_param_6 = 0x0;
+
+ pm->data_byte_swap = 0x76543210;
+ pm->slice0_dq_swizzle = 0x3145726;
+
+ pm->slice1_dq_swizzle = 0x54176230;
+ pm->slice2_dq_swizzle = 0x57604132;
+
+ pm->slice3_dq_swizzle = 0x20631547;
+ pm->slice4_dq_swizzle = 0x16057423;
+
+ pm->slice5_dq_swizzle = 0x16057423;
+ pm->slice6_dq_swizzle = 0x16057423;
+
+ pm->slice7_dq_swizzle = 0x16057423;
+
+ pm->ddr_spd_info.dimm_type = RDIMM_TYPE;
+ pm->ddr_spd_info.data_width = DIMM_X16;
+ pm->ddr_spd_info.mirror_type = NO_MIRROR;
+ pm->ddr_spd_info.ecc_type = NO_ECC_TYPE;
+ pm->ddr_spd_info.dram_type = LPDDR4_TYPE;
+ pm->ddr_spd_info.rank_num = 0x1;
+ pm->ddr_spd_info.row_num = 0x10;
+ pm->ddr_spd_info.col_num = 0xa;
+ pm->ddr_spd_info.bg_num = 0x0;
+ pm->ddr_spd_info.bank_num = 0x8;
+ pm->ddr_spd_info.taamin = 0x0;
+ pm->ddr_spd_info.trcdmin = 0x0;
+
+ pm->ddr_spd_info.trpmin = 0x0;
+ pm->ddr_spd_info.trasmin = 0x0;
+ pm->ddr_spd_info.trcmin = 0x0;
+ pm->ddr_spd_info.tfawmin = 0x0;
+
+ pm->ddr_spd_info.trrd_smin = 0x0;
+ pm->ddr_spd_info.trrd_lmin = 0x0;
+ pm->ddr_spd_info.tccd_lmin = 0x0;
+ pm->ddr_spd_info.twrmin = 0x0;
+
+ pm->ddr_spd_info.twtr_smin = 0x0;
+ pm->ddr_spd_info.twtr_lmin = 0x0;
+
+ return 0;
+}
+
+void get_default_mcu_info(u8 *data)
+{
+ get_mcu_up_info_default((struct mcu_config *)data);
+}
+
+void fix_mcu_info(u8 *data)
+{
+ struct mcu_config *mcu_info = (struct mcu_config *)data;
+
+ init_dimm_param(mcu_info);
+}
+
+void ddr_init(void)
+{
+ u8 buffer[0x100];
+ struct arm_smccc_res res;
+
+ get_default_mcu_info(buffer);
+ fix_mcu_info(buffer);
+
+ arm_smccc_smc(CPU_INIT_MEM, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
+ if (res.a0 != 0)
+ panic("DRAM init failed :0x%lx\n", res.a0);
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023, Phytium Technology Co., Ltd.
+ * lixinde <lixinde@phytium.com.cn>
+ * weichangzheng <weichangzheng@phytium.com.cn>
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <linux/arm-smccc.h>
+#include <init.h>
+#include "cpu.h"
+
+struct pcu_ctr {
+ u32 base_config[4];
+ u32 equalization[4];
+ u8 rev[72];
+} __attribute((aligned(4)));
+
+struct pcu_config {
+ u32 magic;
+ u32 version;
+ u32 size;
+ u8 rev1[4];
+ u32 independent_tree;
+ u32 base_cfg;
+ u8 rev2[16];
+ struct pcu_ctr ctr_cfg[2];
+} __attribute((aligned(4)));
+
+struct pcu_config const peu_base_info = {
+ .magic = PARAMETER_PCIE_MAGIC,
+ .version = 0x4,
+ .size = 0x100,
+ .independent_tree = CFG_INDEPENDENT_TREE,
+ .base_cfg = ((PCI_PEU1 | (X1X1X1X1 << 1)) << PEU1_OFFSET | (PCI_PEU0 | (X1X1 << 1))),
+ .ctr_cfg[0].base_config[0] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
+ .ctr_cfg[0].base_config[1] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
+ .ctr_cfg[0].base_config[2] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
+ .ctr_cfg[1].base_config[0] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
+ .ctr_cfg[1].base_config[1] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
+ .ctr_cfg[1].base_config[2] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
+ .ctr_cfg[0].equalization[0] = 0x7,
+ .ctr_cfg[0].equalization[1] = 0x7,
+ .ctr_cfg[0].equalization[2] = 0x7,
+ .ctr_cfg[1].equalization[0] = 0x7,
+ .ctr_cfg[1].equalization[1] = 0x7,
+ .ctr_cfg[1].equalization[2] = 0x7,
+};
+
+void pcie_init(void)
+{
+ u8 buffer[0x100];
+ struct arm_smccc_res res;
+
+ memcpy(buffer, &peu_base_info, sizeof(peu_base_info));
+ arm_smccc_smc(CPU_INIT_PCIE, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
+ if (res.a0 != 0)
+ panic("PCIE init failed :0x%lx\n", res.a0);
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023, Phytium Technology Co., Ltd.
+ * lixinde <lixinde@phytium.com.cn>
+ * weichangzheng <weichangzheng@phytium.com.cn>
+ */
+
+#include <stdio.h>
+#include <command.h>
+#include <init.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <linux/arm-smccc.h>
+#include <scsi.h>
+#include <asm/u-boot.h>
+#include "cpu.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mach_cpu_init(void)
+{
+ check_reset();
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ pcie_init();
+ return 0;
+}
+
+int dram_init(void)
+{
+ debug("Phytium ddr init\n");
+ ddr_init();
+
+ gd->mem_clk = 0;
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+
+ sec_init();
+ debug("PBF relocate done\n");
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(void)
+{
+ struct arm_smccc_res res;
+
+ debug("run in reset cpu\n");
+ arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
+ if (res.a0 != 0)
+ panic("reset cpu error, %lx\n", res.a0);
+}
+
+static struct mm_region pe2201_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN
+ },
+ {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x7b000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NS | PTE_BLOCK_INNER_SHARE
+ },
+ {
+ 0,
+ }
+};
+
+struct mm_region *mem_map = pe2201_mem_map;
+
+int last_stage_init(void)
+{
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023, Phytium Technology Co., Ltd.
+ */
+
+/* Initial environment variables */
+
+image=Image
+scriptaddr=0x90100000
+script_offset_f=0xc00000
+script_size_f=0x2000
+kernel_addr_r=0x90200000
+fdt_addr_r=0x90000000
+boot_fit=no
+fdtfile=phytium-pe2201.dtb
+ft_fdt_name=boot/dtb/pe2201.dtb
+fdtoverlay_addr_r=0x95100000
+kernel_comp_addr_r=0x96000000
+kernel_comp_size=0x2000000
+pxefile_addr_r=0x9A000000
+ramdisk_addr_r=0x95000000
+load_kernel=ext4load scsi 0:2 $kernel_addr_r boot/uImage-2004
+load_initrd=ext4load scsi 0:2 $ramdisk_addr_r initrd.img-4.19.0.pe2201
+load_fdt=ext4load scsi 0:2 $fdt_addr_r $ft_fdt_name
+distro_bootcmd=run load_kernel; run load_initrd; run load_fdt; run boot_os
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023, Phytium Technology Co., Ltd.
+ * lixinde <lixinde@phytium.com.cn>
+ * weichangzheng <weichangzheng@phytium.com.cn>
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <asm/io.h>
+#include <linux/arm-smccc.h>
+#include <init.h>
+#include "cpu.h"
+
+struct pll_config {
+ u32 magic;
+ u32 version;
+ u32 size;
+ u8 rev1[4];
+ u32 clust0_pll;
+ u32 clust1_pll;
+ u32 clust2_pll;
+ u32 noc_pll;
+ u32 dmu_pll;
+} __attribute((aligned(4)));
+
+struct pll_config const pll_base_info = {
+ .magic = PARAMETER_PLL_MAGIC,
+ .version = 0x2,
+ .size = 0x100,
+ .clust0_pll = 2000,
+ .clust1_pll = 2000,
+ .clust2_pll = 2000,
+ .noc_pll = 1800,
+ .dmu_pll = 600,
+};
+
+u32 get_reset_source(void)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(CPU_GET_RST_SOURCE, 0, 0, 0, 0, 0, 0, 0, &res);
+
+ return res.a0;
+}
+
+void pll_init(void)
+{
+ u8 buffer[0x100];
+ struct arm_smccc_res res;
+
+ memcpy(buffer, &pll_base_info, sizeof(pll_base_info));
+ arm_smccc_smc(CPU_INIT_PLL, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
+ if (res.a0 != 0)
+ panic("PLL init failed :0x%lx\n", res.a0);
+}
+
+void check_reset(void)
+{
+ u32 rst;
+
+ rst = get_reset_source();
+
+ switch (rst) {
+ case CPU_RESET_POWER_ON:
+ pll_init();
+ break;
+ case CPU_RESET_PLL:
+ break;
+ case CPU_RESET_WATCH_DOG:
+ break;
+ default:
+ panic("other reset source\n");
+ }
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023, Phytium Technology Co., Ltd.
+ * lixinde <lixinde@phytium.com.cn>
+ * weichangzheng <weichangzheng@phytium.com.cn>
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <linux/arm-smccc.h>
+#include <init.h>
+#include "cpu.h"
+
+struct common_config {
+ u32 magic;
+ u32 version;
+ u32 size;
+ u8 rev1[4];
+ u64 core_bit_map;
+} __attribute((aligned(4)));
+
+struct common_config const common_base_info = {
+ .magic = PARAMETER_COMMON_MAGIC,
+ .version = 0x1,
+ .core_bit_map = 0x3333,
+};
+
+void sec_init(void)
+{
+ u8 buffer[0x100];
+ struct arm_smccc_res res;
+
+ memcpy(buffer, &common_base_info, sizeof(common_base_info));
+ arm_smccc_smc(CPU_INIT_SEC_SVC, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
+ if (res.a0 != 0)
+ panic("SEC init failed :0x%lx\n", res.a0);
+}
* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
*/
+#include <button.h>
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
/* Check for vol- button - if pressed - stop autoboot */
int misc_init_r(void)
{
- struct udevice *pon;
- struct gpio_desc resin;
- int node, ret;
+ struct udevice *btn;
+ int ret;
+ enum button_state_t state;
- ret = uclass_get_device_by_name(UCLASS_GPIO, "pm8916_pon@800", &pon);
+ ret = button_get_by_label("vol_down", &btn);
if (ret < 0) {
- printf("Failed to find PMIC pon node. Check device tree\n");
- return 0;
+ printf("Couldn't find power button!\n");
+ return ret;
}
- node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
- "key_vol_down");
- if (node < 0) {
- printf("Failed to find key_vol_down node. Check device tree\n");
- return 0;
- }
-
- if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
- &resin, 0)) {
- printf("Failed to request key_vol_down button.\n");
- return 0;
- }
-
- if (dm_gpio_get_value(&resin)) {
+ state = button_get_state(btn);
+ if (state == BUTTON_ON) {
env_set("preboot", "setenv preboot; fastboot 0");
- printf("key_vol_down pressed - Starting fastboot.\n");
+ printf("vol_down pressed - Starting fastboot.\n");
}
return 0;
* (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
*/
+#include <button.h>
#include <cpu_func.h>
#include <init.h>
-#include <asm/arch/sysmap-apq8096.h>
#include <env.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/psci.h>
#include <asm/gpio.h>
+#define TLMM_BASE_ADDR (0x1010000)
+
+/* Strength (sdc1) */
+#define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000)
+
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
/* Check for vol- button - if pressed - stop autoboot */
int misc_init_r(void)
{
- struct udevice *pon;
- struct gpio_desc resin;
- int node, ret;
+ struct udevice *btn;
+ int ret;
+ enum button_state_t state;
- ret = uclass_get_device_by_name(UCLASS_GPIO, "pm8994_pon@800", &pon);
+ ret = button_get_by_label("pwrkey", &btn);
if (ret < 0) {
- printf("Failed to find PMIC pon node. Check device tree\n");
- return 0;
- }
-
- node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
- "key_vol_down");
- if (node < 0) {
- printf("Failed to find key_vol_down node. Check device tree\n");
- return 0;
- }
-
- if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
- &resin, 0)) {
- printf("Failed to request key_vol_down button.\n");
- return 0;
+ printf("Couldn't find power button!\n");
+ return ret;
}
- if (dm_gpio_get_value(&resin)) {
+ state = button_get_state(btn);
+ if (state == BUTTON_ON) {
env_set("bootdelay", "-1");
printf("Power button pressed - dropping to console.\n");
}
+++ /dev/null
-/*
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.__image_copy_start)
- *(.vectors)
- CPUDIR/start.o (.text*)
- board/ti/am335x/built-in.o (.text*)
- }
-
- /* This needs to come before *(.text*) */
- .__efi_runtime_start : {
- *(.__efi_runtime_start)
- }
-
- .efi_runtime : {
- *(.text.efi_runtime*)
- *(.rodata.efi_runtime*)
- *(.data.efi_runtime*)
- }
-
- .__efi_runtime_stop : {
- *(.__efi_runtime_stop)
- }
-
- .text_rest :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- . = .;
-
- . = ALIGN(4);
- __u_boot_list : {
- KEEP(*(SORT(__u_boot_list*)));
- }
-
- . = ALIGN(4);
-
- .efi_runtime_rel_start :
- {
- *(.__efi_runtime_rel_start)
- }
-
- .efi_runtime_rel : {
- *(.rel*.efi_runtime)
- *(.rel*.efi_runtime.*)
- }
-
- .efi_runtime_rel_stop :
- {
- *(.__efi_runtime_rel_stop)
- }
-
- . = ALIGN(4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- .hash : { *(.hash*) }
-
- .end :
- {
- *(.__end)
- }
-
- _image_binary_end = .;
-
- /*
- * Deprecated: this MMU section is used by pxa at present but
- * should not be used by new boards/CPUs.
- */
- . = ALIGN(4096);
- .mmutable : {
- *(.mmutable)
- }
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
-
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _image_binary_end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .gnu.hash : { *(.gnu.hash) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
config BOOTMETH_EFILOADER
bool "Bootdev support for EFI boot"
- depends on BOOTEFI_BOOTMGR
+ depends on EFI_BINARY_EXEC
default y
help
Enables support for EFI boot using bootdevs. This makes the
select BOOTMETH_SCRIPT if CMDLINE # E.g. Armbian uses scripts
select BOOTMETH_EXTLINUX # E.g. Debian uses these
select BOOTMETH_EXTLINUX_PXE if CMD_PXE && CMD_NET && DM_ETH
- select BOOTMETH_EFILOADER if BOOTEFI_BOOTMGR # E.g. Ubuntu uses this
+ select BOOTMETH_EFILOADER if EFI_BINARY_EXEC # E.g. Ubuntu uses this
config SPL_BOOTMETH_VBE
bool "Bootdev support for Verified Boot for Embedded (SPL)"
config CEDIT
bool "Configuration editor"
- depends on BOOTSTD
+ depends on EXPO
help
Provides a way to deal with board configuration and present it to
the user for adjustment.
obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_CROS) += bootm.o bootm_os.o bootmeth_cros.o
obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SANDBOX) += bootmeth_sandbox.o
obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SCRIPT) += bootmeth_script.o
+obj-$(CONFIG_$(SPL_TPL_)CEDIT) += cedit.o
ifdef CONFIG_$(SPL_TPL_)BOOTSTD_FULL
-obj-$(CONFIG_BOOTEFI_BOOTMGR) += bootmeth_efi_mgr.o
+obj-$(CONFIG_EFI_BOOTMGR) += bootmeth_efi_mgr.o
obj-$(CONFIG_$(SPL_TPL_)EXPO) += bootflow_menu.o
obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootflow_menu.o
-obj-$(CONFIG_$(SPL_TPL_)CEDIT) += cedit.o
endif
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o
if (store_needed) {
abc->crc32_le = ab_control_compute_crc(abc);
- ab_control_store(dev_desc, part_info, abc, 0);
+ ret = ab_control_store(dev_desc, part_info, abc, 0);
+ if (ret < 0) {
+#if ANDROID_AB_BACKUP_OFFSET
+ free(backup_abc);
+#endif
+ free(abc);
+ return ret;
+ }
}
#if ANDROID_AB_BACKUP_OFFSET
* to the backup offset
*/
if (memcmp(backup_abc, abc, sizeof(*abc)) != 0) {
- ab_control_store(dev_desc, part_info, abc,
- ANDROID_AB_BACKUP_OFFSET);
+ ret = ab_control_store(dev_desc, part_info, abc,
+ ANDROID_AB_BACKUP_OFFSET);
+ if (ret < 0) {
+ free(backup_abc);
+ free(abc);
+ return ret;
+ }
}
free(backup_abc);
#endif
if (!load)
return 1;
os.load = load;
+ images->ep = load;
debug("Allocated %lx bytes at %lx for kernel (size %lx) decompression\n",
req_size, load, image_len);
}
log_debug("parsing bflow file size %x\n", bflow->size);
membuff_init(&mb, bflow->buf, bflow->size);
membuff_putraw(&mb, bflow->size, true, &data);
- while (len = membuff_readline(&mb, line, sizeof(line) - 1, ' '), len) {
+ while (len = membuff_readline(&mb, line, sizeof(line) - 1, ' ', true), len) {
char *tok, *p = line;
tok = strsep(&p, " ");
config BOOTM_EFI
bool "Support booting UEFI FIT images"
- depends on BOOTEFI_BOOTMGR && CMD_BOOTM && FIT
+ depends on EFI_BINARY_EXEC && CMD_BOOTM && FIT
default y
help
Support booting UEFI FIT images via the bootm command.
if CMD_BOOTEFI
config CMD_BOOTEFI_BINARY
bool "Allow booting an EFI binary directly"
- depends on BOOTEFI_BOOTMGR
+ depends on EFI_BINARY_EXEC
default y
help
Select this option to enable direct execution of binary at 'bootefi'.
config CMD_BOOTEFI_BOOTMGR
bool "UEFI Boot Manager command"
- depends on BOOTEFI_BOOTMGR
+ depends on EFI_BOOTMGR
default y
help
Select this option to enable the 'bootmgr' subcommand of 'bootefi'.
config CMD_BOOTEFI_HELLO
bool "Allow booting a standard EFI hello world for testing"
- depends on CMD_BOOTEFI_HELLO_COMPILE
+ depends on CMD_BOOTEFI_BINARY && CMD_BOOTEFI_HELLO_COMPILE
default y if CMD_BOOTEFI_SELFTEST
help
This adds a standard EFI hello world application to U-Boot so that
config CMD_EFICONFIG
bool "eficonfig - provide menu-driven uefi variables maintenance interface"
default y if !HAS_BOARD_SIZE_LIMIT
- depends on BOOTEFI_BOOTMGR
+ depends on EFI_BOOTMGR
select MENU
help
Enable the 'eficonfig' command which provides the menu-driven UEFI
dp = efi_dp_shorten(dp_volume);
if (!dp)
dp = dp_volume;
- dp = efi_dp_append(dp, &fp->dp);
+ dp = efi_dp_concat(dp, &fp->dp, false);
free(buf);
return dp;
ret = EFI_OUT_OF_RESOURCES;
goto out;
}
- initrd_dp = efi_dp_append((const struct efi_device_path *)&id_dp, dp);
+ initrd_dp = efi_dp_concat((const struct efi_device_path *)&id_dp,
+ dp, false);
efi_free_pool(dp);
}
}
final_dp_size = efi_dp_size(dp) + sizeof(END);
if (initrd_dp) {
- final_dp = efi_dp_concat(dp, initrd_dp);
+ final_dp = efi_dp_concat(dp, initrd_dp, true);
final_dp_size += efi_dp_size(initrd_dp) + sizeof(END);
} else {
final_dp = efi_dp_dup(dp);
if (!short_fp)
short_fp = tmp_fp;
- initrd_dp = efi_dp_append((const struct efi_device_path *)&id_dp,
- short_fp);
+ initrd_dp = efi_dp_concat((const struct efi_device_path *)&id_dp,
+ short_fp, false);
out:
efi_free_pool(tmp_dp);
uridp_len = sizeof(struct efi_device_path) + strlen(argv[3]) + 1;
uridp = efi_alloc(uridp_len + sizeof(END));
+ if (!uridp) {
+ log_err("Out of memory\n");
+ return CMD_RET_FAILURE;
+ }
uridp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
uridp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_URI;
uridp->dp.length = uridp_len;
goto out;
}
- final_fp = efi_dp_concat(file_path, initrd_dp);
+ final_fp = efi_dp_concat(file_path, initrd_dp, true);
if (!final_fp) {
printf("Cannot create final device path\n");
r = CMD_RET_FAILURE;
}
static struct cmd_tbl cmd_efidebug_test_sub[] = {
-#ifdef CONFIG_BOOTEFI_BOOTMGR
+#ifdef CONFIG_EFI_BOOTMGR
U_BOOT_CMD_MKENT(bootmgr, CONFIG_SYS_MAXARGS, 1, do_efi_test_bootmgr,
"", ""),
#endif
" - show UEFI memory map\n"
"efidebug tables\n"
" - show UEFI configuration tables\n"
-#ifdef CONFIG_BOOTEFI_BOOTMGR
+#ifdef CONFIG_EFI_BOOTMGR
"efidebug test bootmgr\n"
" - run simple bootmgr for test\n"
#endif
DECLARE_GLOBAL_DATA_PTR;
/* Create a compile-time value */
-#ifdef MEM_SUPPORT_64BIT_DATA
-#define SUPPORT_64BIT_DATA 1
+#if MEM_SUPPORT_64BIT_DATA
#define HELP_Q ", .q"
#else
-#define SUPPORT_64BIT_DATA 0
#define HELP_Q ""
#endif
static int do_mem_mw(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- ulong writeval; /* 64-bit if SUPPORT_64BIT_DATA */
+ ulong writeval; /* 64-bit if MEM_SUPPORT_64BIT_DATA */
ulong addr, count;
int size;
void *buf, *start;
/* Get the value to write.
*/
- if (SUPPORT_64BIT_DATA)
+ if (MEM_SUPPORT_64BIT_DATA)
writeval = simple_strtoull(argv[2], NULL, 16);
else
writeval = hextoul(argv[2], NULL);
while (count-- > 0) {
if (size == 4)
*((u32 *)buf) = (u32)writeval;
- else if (SUPPORT_64BIT_DATA && size == 8)
+ else if (MEM_SUPPORT_64BIT_DATA && size == 8)
*((ulong *)buf) = writeval;
else if (size == 2)
*((u16 *)buf) = (u16)writeval;
int rcode = 0;
const char *type;
const void *buf1, *buf2, *base;
- ulong word1, word2; /* 64-bit if SUPPORT_64BIT_DATA */
+ ulong word1, word2; /* 64-bit if MEM_SUPPORT_64BIT_DATA */
if (argc != 4)
return CMD_RET_USAGE;
if (size == 4) {
word1 = *(u32 *)buf1;
word2 = *(u32 *)buf2;
- } else if (SUPPORT_64BIT_DATA && size == 8) {
+ } else if (MEM_SUPPORT_64BIT_DATA && size == 8) {
word1 = *(ulong *)buf1;
word2 = *(ulong *)buf2;
} else if (size == 2) {
}
#endif
- memcpy(dst, src, count * size);
+ memmove(dst, src, count * size);
unmap_sysmem(src);
unmap_sysmem(dst);
{
ulong addr, length, i, bytes;
int size;
- volatile ulong *llp; /* 64-bit if SUPPORT_64BIT_DATA */
+ volatile ulong *llp; /* 64-bit if MEM_SUPPORT_64BIT_DATA */
volatile u32 *longp;
volatile u16 *shortp;
volatile u8 *cp;
* If we have only one object, just run infinite loops.
*/
if (length == 1) {
- if (SUPPORT_64BIT_DATA && size == 8) {
+ if (MEM_SUPPORT_64BIT_DATA && size == 8) {
llp = (ulong *)buf;
for (;;)
i = *llp;
i = *cp;
}
- if (SUPPORT_64BIT_DATA && size == 8) {
+ if (MEM_SUPPORT_64BIT_DATA && size == 8) {
for (;;) {
llp = (ulong *)buf;
i = length;
{
ulong addr, length, i, bytes;
int size;
- volatile ulong *llp; /* 64-bit if SUPPORT_64BIT_DATA */
- ulong data; /* 64-bit if SUPPORT_64BIT_DATA */
+ volatile ulong *llp; /* 64-bit if MEM_SUPPORT_64BIT_DATA */
+ ulong data; /* 64-bit if MEM_SUPPORT_64BIT_DATA */
volatile u32 *longp;
volatile u16 *shortp;
volatile u8 *cp;
length = hextoul(argv[2], NULL);
/* data to write */
- if (SUPPORT_64BIT_DATA)
+ if (MEM_SUPPORT_64BIT_DATA)
data = simple_strtoull(argv[3], NULL, 16);
else
data = hextoul(argv[3], NULL);
* If we have only one object, just run infinite loops.
*/
if (length == 1) {
- if (SUPPORT_64BIT_DATA && size == 8) {
+ if (MEM_SUPPORT_64BIT_DATA && size == 8) {
llp = (ulong *)buf;
for (;;)
*llp = data;
*cp = data;
}
- if (SUPPORT_64BIT_DATA && size == 8) {
+ if (MEM_SUPPORT_64BIT_DATA && size == 8) {
for (;;) {
llp = (ulong *)buf;
i = length;
char *const argv[])
{
ulong addr;
- ulong i; /* 64-bit if SUPPORT_64BIT_DATA */
+ ulong i; /* 64-bit if MEM_SUPPORT_64BIT_DATA */
int nbytes, size;
void *ptr = NULL;
printf("%08lx:", addr);
if (size == 4)
printf(" %08x", *((u32 *)ptr));
- else if (SUPPORT_64BIT_DATA && size == 8)
+ else if (MEM_SUPPORT_64BIT_DATA && size == 8)
printf(" %0lx", *((ulong *)ptr));
else if (size == 2)
printf(" %04x", *((u16 *)ptr));
#endif
else {
char *endp;
- if (SUPPORT_64BIT_DATA)
+ if (MEM_SUPPORT_64BIT_DATA)
i = simple_strtoull(console_buffer, &endp, 16);
else
i = hextoul(console_buffer, &endp);
bootretry_reset_cmd_timeout();
if (size == 4)
*((u32 *)ptr) = i;
- else if (SUPPORT_64BIT_DATA && size == 8)
+ else if (MEM_SUPPORT_64BIT_DATA && size == 8)
*((ulong *)ptr) = i;
else if (size == 2)
*((u16 *)ptr) = i;
if (has_pages) {
for (page = 0; page < npages; page++) {
- u64 data_off = page * mtd->writesize;
+ u64 data_off = (u64)page * mtd->writesize;
printf("\nDump %d data bytes from 0x%08llx:\n",
mtd->writesize, start_off + data_off);
mtd->writesize, start_off + data_off);
if (woob) {
- u64 oob_off = page * mtd->oobsize;
+ u64 oob_off = (u64)page * mtd->oobsize;
printf("Dump %d OOB bytes from page at 0x%08llx:\n",
mtd->oobsize, start_off + data_off);
#endif
#ifdef CMD_DATA_SIZE
-int cmd_get_data_size(char* arg, int default_size)
+int cmd_get_data_size(const char *arg, int default_size)
{
/* Check for a size specification .b, .w or .l.
*/
int len = strlen(arg);
- if (len > 2 && arg[len-2] == '.') {
+ if (len >= 2 && arg[len-2] == '.') {
switch (arg[len-1]) {
case 'b':
return 1;
ret = membuff_new((struct membuff *)&gd->console_in,
CONFIG_CONSOLE_RECORD_IN_SIZE);
+ /* Start recording from the beginning */
+ gd->flags |= GD_FLG_RECORD;
+
return ret;
}
return -ENOSPC;
return membuff_readline((struct membuff *)&gd->console_out, str,
- maxlen, '\0');
+ maxlen, '\0', false);
}
int console_record_avail(void)
return membuff_avail((struct membuff *)&gd->console_out);
}
+bool console_record_isempty(void)
+{
+ return membuff_isempty((struct membuff *)&gd->console_out);
+}
+
int console_in_puts(const char *str)
{
return membuff_put((struct membuff *)&gd->console_in, str, strlen(str));
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_SYS_PBSIZE=1048
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PBSIZE=532
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_PART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXS_SPI=y
+CONFIG_SPL_CRC8=y
# CONFIG_SPL_OF_LIBFDT is not set
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_BUS=3
+CONFIG_SF_DEFAULT_BUS=2
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_SPANSION=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x3C0000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phygate-tauri-l"
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_PHYCORE_IMX8MM=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0x920000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x3E0000
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_LTO=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
+CONFIG_DEFAULT_FDT_FILE="oftree"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x910000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_SYS_MAXARGS=64
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_SIZE=4096
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x51
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_WATCHDOG=y
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x700000
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
-CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk"
CONFIG_SPL_TEXT_BASE=0x2049A000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x400000
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
-CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk"
CONFIG_SPL_TEXT_BASE=0x2049A000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x700000
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
-CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx93-var-som-symphony"
CONFIG_SPL_TEXT_BASE=0x2049A000
CONFIG_TARGET_IMX93_VAR_SOM=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x20519dd0
CONFIG_SPL=y
CONFIG_CMD_DEKBLOB=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
-CONFIG_SPL_LOAD_IMX_CONTAINER=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x90000000
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="run bsp_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx93-var-som-symphony.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
-CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x83200000
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
CONFIG_SPL_I2C=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_NVEDIT_EFI=y
-CONFIG_CMD_NET=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_I2C_EEPROM_BUS=3
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_WDT=y
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
-CONFIG_SYSCON=y
CONFIG_SPL_CLK_IMX93=y
CONFIG_CLK_IMX93=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82800000
-CONFIG_FASTBOOT_BUF_SIZE=0x20000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_UUU_SUPPORT=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_GPIO_HOG=y
CONFIG_IMX_RGPIO2P=y
CONFIG_DM_PCA953X=y
CONFIG_PHY_ADIN=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_REALTEK=y
-CONFIG_DM_ETH=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_DWC_ETH_QOS=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_MIPI_DPHY_HELPERS=y
-CONFIG_PHY_IMX93_MIPI_DPHY=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX93=y
CONFIG_POWER_DOMAIN=y
-CONFIG_IMX93_BLK_CTRL=y
CONFIG_DM_PMIC=y
CONFIG_SPL_DM_PMIC_PCA9450=y
CONFIG_DM_REGULATOR=y
CONFIG_FSL_LPUART=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_TMU=y
-CONFIG_CI_UDC=y
CONFIG_ULP_WATCHDOG=y
+CONFIG_WDT=y
CONFIG_LZO=y
CONFIG_BZIP2=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_WATCHDOG=y
-CONFIG_WDT=y
-CONFIG_CMD_WDT=y
-CONFIG_ETHPRIME="eth0"
-CONFIG_SYS_I2C_SPEED=100000
-CONFIG_IMX_BOOTAUX=y
-CONFIG_CMD_READ=y
-CONFIG_SERIAL_TAG=y
\ No newline at end of file
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_TARGET_PE2201=y
+CONFIG_TEXT_BASE=0x38180000
+CONFIG_SYS_MALLOC_LEN=0x101000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x30c1a000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_DEFAULT_DEVICE_TREE="phytium-pe2201"
+CONFIG_BOARD_EARLY_INIT_F=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x90000000
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="earlycon=pl011,0x2800c000 root=/dev/sda2 rw"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_SYS_PROMPT="pe2201#"
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_PCI=y
+CONFIG_CMD_DM=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_NET is not set
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_BLK=y
+# CONFIG_MMC is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_PHYTIUM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_CMD_BOOTMETH=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_AM625=y
+CONFIG_K3_ATF_LOAD_ADDR=0x9e780000
+CONFIG_TARGET_PHYCORE_AM62X_A53=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000
+CONFIG_SF_DEFAULT_SPEED=25000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am625-phyboard-lyra-rdk"
+CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SIZE_LIMIT=0x40000
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+# CONFIG_PSCI_RESET is not set
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_SYS_BOOTM_LEN=0x800000
+CONFIG_BOOTCOMMAND="run mmcboot; bootflow scan -lb"
+CONFIG_DEFAULT_FDT_FILE="oftree"
+CONFIG_SPL_MAX_SIZE=0x58000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x80c80000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_POWER_DOMAIN=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_PHY_FIXED=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x08000000
+CONFIG_SYS_MALLOC_F_LEN=0x9000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_AM625=y
+CONFIG_TARGET_PHYCORE_AM62X_R5=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c3a7f0
+CONFIG_SF_DEFAULT_SPEED=25000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-phycore-som-2gb"
+CONFIG_SPL_TEXT_BASE=0x43c00000
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000
+CONFIG_SPL_SIZE_LIMIT=0x3A7F0
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_MAX_SIZE=0x3B000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x43c3b000
+CONFIG_SPL_BSS_MAX_SIZE=0x3000
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_REMOTEPROC=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_SPL_MISC=y
+CONFIG_ESM_K3=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
CONFIG_SYS_ATA_REG_OFFSET=1
CONFIG_SYS_ATA_ALT_OFFSET=2
CONFIG_SYS_ATA_IDE0_OFFSET=0
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_BUTTON_GPIO=y
CONFIG_CLK=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_CLK_K210=y
bootloader requiring a signature before
it will install or boot images.
+ all Provides all info from commands above as
+ they were called one by one
+
Names starting with a lowercase character are reserved by this
specification. OEM-specific names should not start with lowercase
characters.
with <arg> = boot_ack boot_partition
- ``oem bootbus`` - this executes ``mmc bootbus %x %s`` to configure eMMC
- ``oem run`` - this executes an arbitrary U-Boot command
+- ``oem console`` - this dumps U-Boot console record buffer
Support for both eMMC and NAND devices is included.
If you want to use ELF as the coreboot payload, change U-Boot configuration to
use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
-To enable video you must enable these options in coreboot:
+To enable video you must enable CONFIG_GENERIC_LINEAR_FRAMEBUFFER in coreboot:
- - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
- - Keep VESA framebuffer
+ - Devices->Display->Framebuffer mode->Linear "high resolution" framebuffer
At present it seems that for Minnowboard Max, coreboot does not pass through
the video information correctly (it always says the resolution is 0x0). This
To update the `coreboot.rom` file which is used:
-#. Build coreboot with `CONFIG_LINEAR_FRAMEBUFFER=y`. If using `make menuconfig`
- this is under
- `Devices ->Display->Framebuffer mode->Linear "high resolution" framebuffer`.
+#. Build coreboot with `CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y`. If using
+ `make menuconfig`, this is under
+ `Devices->Display->Framebuffer mode->Linear "high resolution" framebuffer`.
#. Compress the resulting `coreboot.rom`::
- xz -c /path/to/coreboot/build/coreboot.rom >coreboot.rom.xz
+ xz -c /path/to/coreboot/build/coreboot.rom > coreboot.rom.xz
#. Upload the file to Google drive
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+phyGATE-Tauri-L-i.MX 8M Mini
+============================
+
+The phyGATE-Tauri-L-i.MX 8M Mini with 2GB of main memory is supported.
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get ddr firmware
+- Build U-Boot
+- Boot
+
+Build the ARM Trusted firmware binary
+-------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+ $ cd trusted-firmware-a
+ $ export CROSS_COMPILE=aarch64-linux-gnu
+ $ export IMX_BOOT_UART_BASE=0x30880000
+ $ make PLAT=imx8mm bl31
+
+Get the ddr firmware
+--------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.23.bin
+ $ chmod +x firmware-imx-8.23.bin
+ $ ./firmware-imx-8.23.bin
+
+Build U-Boot for SD card
+------------------------
+
+Copy binaries
+^^^^^^^^^^^^^
+
+.. code-block:: bash
+
+ $ cp <TF-A dir>/build/imx8mm/release/bl31.bin .
+ $ cp firmware-imx-8.23/firmware/ddr/synopsys/lpddr4*.bin .
+
+Build U-Boot
+^^^^^^^^^^^^
+
+.. code-block:: bash
+
+ $ make imx8mm-phygate-tauri-l_defconfig
+ $ make flash.bin
+
+Flash SD card
+^^^^^^^^^^^^^
+
+.. code-block:: bash
+
+ $ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 conv=sync
.. toctree::
:maxdepth: 2
+ imx8mm-phygate-tauri-l
+ phycore-am62x
phycore-imx8mm
phycore-imx8mp
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Wadim Egorov <w.egorov@phytec.de>
+
+phyCORE-AM62x
+=============
+
+The `phyCORE-AM62x <https://www.phytec.com/product/phycore-am62x>`_ is a
+SoM (System on Module) featuring TI's AM62x SoC. It can be used in combination
+with different carrier boards. This module can come with different sizes and
+models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM62x family.
+
+A development Kit, called `phyBOARD-Lyra <https://www.phytec.com/product/phyboard-am62x>`_
+is used as a carrier board reference design around the AM62x SoM.
+
+Quickstart
+----------
+
+* Download sources and TI firmware blobs
+* Build Trusted Firmware-A
+* Build OP-TEE
+* Build U-Boot for the R5
+* Build U-Boot for the A53
+* Create bootable uSD Card
+* Boot
+
+Sources
+-------
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_boot_sources
+ :end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure
+---------------
+
+Setup the environment variables:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_desc
+ :end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_board_env_vars_desc
+ :end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_defn
+ :end-before: .. k3_rst_include_end_common_env_vars_defn
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=phycore_am62x_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=phycore_am62x_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ # we don't use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-am62x
+ $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
+
+.. include:: ../ti/am62x_sk.rst
+ :start-after: .. am62x_evm_rst_include_start_build_steps
+ :end-before: .. am62x_evm_rst_include_end_build_steps
+
+uSD Card creation
+-----------------
+
+Use fdisk to partition the uSD card. The layout should look similar to:
+
+.. code-block:: bash
+
+ $ sudo fdisk -l /dev/mmcblk0
+ Disk /dev/mmcblk0: 7.56 GiB, 8120172544 bytes, 15859712 sectors
+ Units: sectors of 1 * 512 = 512 bytes
+ Sector size (logical/physical): 512 bytes / 512 bytes
+ I/O size (minimum/optimal): 512 bytes / 512 bytes
+ Disklabel type: dos
+ Disk identifier: 0x6583d9a3
+
+ Device Boot Start End Sectors Size Id Type
+ /dev/mmcblk0p1 * 2048 264191 262144 128M c W95 FAT32 (LBA)
+ /dev/mmcblk0p2 264192 1934953 1670762 815.8M 83 Linux
+
+
+Once partitioned, the boot partition has to be formatted with a FAT filesystem.
+Assuming the uSD card is `/dev/mmcblk0`:
+
+.. code-block:: bash
+
+ $ mkfs.vfat /dev/mmcblk0p1
+
+To boot from a micro SD card on a HSFS device simply copy the following
+artifacts to the FAT partition:
+
+* tiboot3.bin from R5 build as tiboot3.bin
+* tispl.bin_unsigned from Cortex-A build as tispl.bin
+* u-boot.img_unsigned from Cortex-A build as u-boot.img
+
+Boot
+----
+
+Put the uSD card in the slot on the board and apply power. Check the serial
+console for output.
+
+Flash to SPI NOR
+----------------
+
+Below commands can be used to flash the SPI NOR flash; assuming
+tiboot3.bin, tispl.bin and u-boot.img are stored on the uSD card.
+
+.. code-block:: bash
+
+ sf probe
+ fatload mmc 1 ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ fatload mmc 1 ${loadaddr} tispl.bin
+ sf update $loadaddr 0x80000 $filesize
+ fatload mmc 1 ${loadaddr} u-boot.img
+ sf update $loadaddr 0x280000 $filesize
+
+
+Boot Modes
+----------
+
+The phyCORE-AM62x development kit supports booting from many different
+interfaces. By default, the development kit is set to boot from the micro-SD
+card. To change the boot device, DIP switches S5 and S6 can be used.
+Boot switches should be changed with power off.
+
+.. list-table:: Boot Modes
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Switch Label
+ - SW5: 12345678
+ - SW6: 12345678
+
+ * - uSD
+ - 11000010
+ - 01000000
+
+ * - eMMC
+ - 11010010
+ - 00000000
+
+ * - OSPI
+ - 11010000
+ - 10000000
+
+ * - UART
+ - 11011100
+ - 00000000
+
+Further Information
+-------------------
+
+Please see :doc:`../ti/am62x_sk` chapter for further AM62 SoC related documentation
+and https://docs.phytec.com/phycore-am62x for vendor documentation.
am62ax_sk
am62x_sk
../beagle/am62x_beagleplay
+ ../phytec/phycore-am62x
../toradex/verdin-am62
am64x_evm
am65x_evm
.. SPDX-License-Identifier: GPL-2.0+
imx93_var_som
-=======================
+=============
U-Boot for the Variscite VAR-SOM-MX93 Symphony evaluation board
$ cp firmware-imx-8.21/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
Get ahab-container.img
----------------------------------------
+----------------------
.. code-block:: bash
try:
import sphinx_rtd_theme
html_theme = 'sphinx_rtd_theme'
- html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
+ extensions.append('sphinx_rtd_theme')
except ImportError:
sys.stderr.write('Warning: The Sphinx \'sphinx_rtd_theme\' HTML theme was not found. Make sure you have the theme installed to produce pretty HTML output. Falling back to the default theme.\n')
* For new features: a description of the feature and your implementation.
* Additional comments which you don't want included in U-Boot's history can be
- included below the first "---" in the message body.
+ included below the first "``---``" in the message body.
* If your description gets too long, that's a strong indication that you should
split up your patch.
* Please make sure to keep a "change log", i.e. a description of what you have
changed compared to previous versions of this patch. This change log should
- be added below the "---" line in the patch, which starts the "comment
+ be added below the "``---``" line in the patch, which starts the "comment
section", i.e. which contains text that does not get included into the
actual commit message.
Note: it is *not* sufficient to provide a change log in some cover letter
+++ /dev/null
-Driver for part of pm8916 PMIC - gpio and power/reset keys
-
-This device should be child of SPMI pmic.
-
-1) GPIO driver
-
-Required properties:
-- compatible: "qcom,pm8916-gpio"
-- reg: peripheral ID, size of register block
-- gpio-controller
-- gpio-count: number of GPIOs
-- #gpio-cells: 2
-
-Optional properties:
-- gpio-bank-name: name of bank (as default "pm8916" is used)
-
-Example:
-
-pmic_gpios: gpios@c000 {
- compatible = "qcom,pm8916-gpio";
- reg = <0xc000 0x400>;
- gpio-controller;
- gpio-count = <4>;
- #gpio-cells = <2>;
- gpio-bank-name="pmic";
-};
-
-
-2) Power/Reset key driver
-
-Required properties:
-- compatible: "qcom,pm8916-pwrkey"
-- reg: peripheral ID, size of register block
-- gpio-controller
-- #gpio-cells: 2
-
-Optional properties:
-- gpio-bank-name: name of bank (as default "pm8916_key" is used)
-
-
-Example:
-
-pmic_pon: pon@800 {
- compatible = "qcom,pm8916-pwrkey";
- reg = <0x800 0x96>;
- #gpio-cells = <2>;
- gpio-controller;
-};
"da_ref": the reference clock of analog phy, used if the clocks
of analog and digital phys are separated, otherwise uses
"ref" clock only if needed.
+- mediatek,eye-vrt : The selection of VRT reference voltage (U2 phy),
+ the value is [1, 7]
+- mediatek,eye-term : The selection of HS_TX TERM reference voltage (U2 phy),
+ the value is [1, 7]
+- mediatek,discth : The selection of disconnect threshold (U2 phy),
+ the value is [1, 15]
+- mediatek,pre-emphasis : The level of pre-emphasis which used to widen
+ the eye opening and boost eye swing,
+ the value is [1, 3]
Example:
+++ /dev/null
- Qualcomm SPMI PMICs multi-function device bindings
-
-The Qualcomm SPMI series presently includes PM8941, PM8841 and PMA8084
-PMICs. These PMICs use a QPNP scheme through SPMI interface.
-QPNP is effectively a partitioning scheme for dividing the SPMI extended
-register space up into logical pieces, and set of fixed register
-locations/definitions within these regions, with some of these regions
-specifically used for interrupt handling.
-
-The QPNP PMICs are used with the Qualcomm Snapdragon series SoCs, and are
-interfaced to the chip via the SPMI (System Power Management Interface) bus.
-Support for multiple independent functions are implemented by splitting the
-16-bit SPMI slave address space into 256 smaller fixed-size regions, 256 bytes
-each. A function can consume one or more of these fixed-size register regions.
-
-Required properties:
-- compatible: Should contain one of:
- "qcom,pm660",
- "qcom,pm660l",
- "qcom,pm7325",
- "qcom,pm8004",
- "qcom,pm8005",
- "qcom,pm8019",
- "qcom,pm8028",
- "qcom,pm8110",
- "qcom,pm8150",
- "qcom,pm8150b",
- "qcom,pm8150c",
- "qcom,pm8150l",
- "qcom,pm8226",
- "qcom,pm8350c",
- "qcom,pm8841",
- "qcom,pm8901",
- "qcom,pm8909",
- "qcom,pm8916",
- "qcom,pm8941",
- "qcom,pm8950",
- "qcom,pm8953",
- "qcom,pm8994",
- "qcom,pm8998",
- "qcom,pma8084",
- "qcom,pmd9635",
- "qcom,pmi8950",
- "qcom,pmi8962",
- "qcom,pmi8994",
- "qcom,pmi8998",
- "qcom,pmk8002",
- "qcom,pmk8350",
- "qcom,pmr735a",
- "qcom,smb2351",
- or generalized "qcom,spmi-pmic".
-- reg: Specifies the SPMI USID slave address for this device.
- For more information see:
- Documentation/devicetree/bindings/spmi/spmi.yaml
-
-Required properties for peripheral child nodes:
-- compatible: Should contain "qcom,xxx", where "xxx" is a peripheral name.
-
-Optional properties for peripheral child nodes:
-- interrupts: Interrupts are specified as a 4-tuple. For more information
- see:
- Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml
-- interrupt-names: Corresponding interrupt name to the interrupts property
-
-Each child node of SPMI slave id represents a function of the PMIC. In the
-example below the rtc device node represents a peripheral of pm8941
-SID = 0. The regulator device node represents a peripheral of pm8941 SID = 1.
-
-Example:
-
- spmi {
- compatible = "qcom,spmi-pmic-arb";
-
- pm8941@0 {
- compatible = "qcom,pm8941", "qcom,spmi-pmic";
- reg = <0x0 SPMI_USID>;
-
- rtc {
- compatible = "qcom,rtc";
- interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "alarm";
- };
- };
-
- pm8941@1 {
- compatible = "qcom,pm8941", "qcom,spmi-pmic";
- reg = <0x1 SPMI_USID>;
-
- regulator {
- compatible = "qcom,regulator";
- regulator-name = "8941_boost";
- };
- };
- };
+++ /dev/null
-Qualcomm SPMI arbiter/bus driver
-
-This is bus driver for Qualcomm chips that use SPMI to communicate with PMICs.
-
-Required properties:
-- compatible: "qcom,spmi-pmic-arb"
-- reg: Register block adresses and sizes for various parts of device:
- 1) PMIC arbiter channel mapping base (PMIC_ARB_REG_CHNLn)
- 2) SPMI write command (master) registers (PMIC_ARB_CORE_SW_DEC_CHANNELS)
- 3) SPMI read command (observer) registers (PMIC_ARB_CORE_REGISTERS_OBS)
-
-Optional properties (if not set by parent):
-- #address-cells: 0x1 - childs slave ID address
-- #size-cells: 0x1
-
-All PMICs should be placed as a child nodes of bus arbiter.
-Automatic detection of childs is currently not supported.
-
-Example:
-
-spmi@200f000 {
- compatible = "qcom,spmi-pmic-arb";
- reg = <0x200f800 0x200 0x2400000 0x400000 0x2c00000 0x400000>;
- #address-cells = <0x1>;
- #size-cells = <0x1>;
-};
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+Index
+=====
Indices and tables
==================
-* :ref:`genindex`
+.. toctree::
+ :maxdepth: 1
+
+ genindex
/* -*- coding: utf-8; mode: css -*-
*
* Sphinx HTML theme customization: read the doc
- *
+ * Please don't add any color definition here, as the theme should
+ * work for both normal and dark modes.
*/
+@import 'css/theme.css';
+@import 'pygments.css';
+
+/* Improve contrast and increase size for easier reading. */
+
+body {
+ font-family: sans-serif;
+ font-size: 100%;
+}
+
+h1, h2, .rst-content .toctree-wrapper p.caption, h3, h4, h5, h6, legend {
+ font-family: sans-serif;
+}
+
+div[class^="highlight"] pre {
+ font-family: monospace;
+ font-size: 100%;
+}
+
+.wy-menu-vertical {
+ font-family: sans-serif;
+}
+
+.c {
+ font-style: normal;
+}
+
+p {
+ font-size: 100%;
+}
+
/* Interim: Code-blocks with line nos - lines and line numbers don't line up.
* see: https://github.com/rtfd/sphinx_rtd_theme/issues/419
*/
line-height: normal;
}
+/* Keep fields from being strangely far apart due to inheirited table CSS. */
+.rst-content table.field-list th.field-name {
+ padding-top: 1px;
+ padding-bottom: 1px;
+}
+.rst-content table.field-list td.field-body {
+ padding-top: 1px;
+ padding-bottom: 1px;
+}
+
@media screen {
/* content column
/* Menu selection and keystrokes */
span.menuselection {
- color: blue;
font-family: "Courier New", Courier, monospace
}
code.kbd, code.kbd span {
- color: white;
- background-color: darkblue;
font-weight: bold;
font-family: "Courier New", Courier, monospace
}
lineoffset = int(match.group(1)) - 1
# we must eat our comments since the upset the markup
else:
- doc = env.srcdir + "/" + env.docname + ":" + str(self.lineno)
+ doc = str(env.srcdir) + "/" + env.docname + ":" + str(self.lineno)
result.append(line, doc + ": " + filename, lineoffset)
lineoffset += 1
if dst_fname:
# the builder needs not to copy one more time, so pop it if exists.
translator.builder.images.pop(img_node['uri'], None)
- _name = dst_fname[len(translator.builder.outdir) + 1:]
+ _name = dst_fname[len(str(translator.builder.outdir)) + 1:]
if isNewer(dst_fname, src_fname):
kernellog.verbose(app,
-alabaster==0.7.12
-Babel==2.9.1
-certifi==2023.07.22
-charset-normalizer==2.0.12
-docutils==0.16
-idna==3.3
-imagesize==1.3.0
-Jinja2==3.0.3
-MarkupSafe==2.1.1
-packaging==21.3
-Pygments==2.15.1
-pyparsing==3.0.7
-pytz==2023.3
+alabaster==0.7.16
+Babel==2.14.0
+certifi==2023.11.17
+charset-normalizer==3.3.2
+docutils==0.20.1
+idna==3.6
+imagesize==1.4.1
+Jinja2==3.1.3
+MarkupSafe==2.1.3
+packaging==23.2
+Pygments==2.17.2
requests==2.31.0
six==1.16.0
snowballstemmer==2.2.0
-Sphinx==3.4.3
-sphinx-prompt==1.5.0
-sphinx-rtd-theme==1.0.0
-sphinxcontrib-applehelp==1.0.2
-sphinxcontrib-devhelp==1.0.2
-sphinxcontrib-htmlhelp==2.0.0
+Sphinx==7.2.6
+sphinx-prompt==1.8.0
+sphinx-rtd-theme==2.0.0
+sphinxcontrib-applehelp==1.0.8
+sphinxcontrib-devhelp==1.0.6
+sphinxcontrib-htmlhelp==2.0.5
+sphinxcontrib-jquery==4.1
sphinxcontrib-jsmath==1.0.1
-sphinxcontrib-qthelp==1.0.3
-sphinxcontrib-serializinghtml==1.1.5
-urllib3==2.0.7
+sphinxcontrib-qthelp==1.0.7
+sphinxcontrib-serializinghtml==1.1.10
+urllib3==2.1.0
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: acpi (command)
+
acpi command
============
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: addrmap (command)
+
addrmap command
===============
.. SPDX-License-Identifier: GPL-2.0+
.. Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+.. index::
+ single: armffa (command)
+
armffa command
==============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: askenv (command)
+
askenv command
==============
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: base (command)
+
base command
============
.. SPDX-License-Identifier: GPL-2.0+
.. Copyright 2023, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+.. index::
+ single: bdinfo (command)
+
bdinfo command
==============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: bind (command)
+
bind command
============
.. SPDX-License-Identifier: GPL-2.0+
.. Copyright 2023, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+.. index::
+ single: blkcache (command)
+
blkcache command
================
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: bootd (command)
+
bootd command
=============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: bootdev (command)
+
bootdev command
===============
.. SPDX-License-Identifier: GPL-2.0+
.. Copyright 2020, Heinrich Schuchardt <xypron.glpk@gmx.de>
+.. index::
+ single: bootefi (command)
+
bootefi command
===============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: bootflow (command)
+
bootflow command
================
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: booti (command)
+
booti command
=============
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: bootm (command)
+
bootm command
=============
.. SPDX-License-Identifier: GPL-2.0+
.. (C) Copyright 2011-2012 Pali Rohár <pali@kernel.org>
+.. index::
+ single: bootmenu (command)
+
bootmenu command
================
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: bootmeth (command)
+
bootmeth command
================
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: bootz (command)
+
bootz command
=============
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: button (command)
+
button command
==============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: cat (command)
+
cat command
===========
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: cedit (command)
+
cedit command
=============
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: cli (command)
+
cli command
===========
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: cls (command)
+
cls command
===========
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: cmp (command)
+
cmp command
===========
-------------
The cmp command is only available if CONFIG_CMD_MEMORY=y. The cmp.q command is
-only available if additionally CONFIG_MEM_SUPPORT_64BIT_DATA=y.
+only available on 64-bit targets.
Return value
------------
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: coninfo (command)
+
coninfo command
===============
+.. index::
+ single: conitrace (command)
+
conitrace command
=================
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: cp (command)
+
cp command
==========
The cp command is used to copy *count* chunks of memory from the *source*
address to the *target* address. If the *target* address points to NOR flash,
-the flash is programmed.
+the flash is programmed. When the *target* address points at ordinary memory,
+memmove() is used, so the two regions may overlap.
The number bytes in one chunk is defined by the suffix defaulting to 4 bytes:
-------------
The cp command is available if CONFIG_CMD_MEMORY=y. Support for 64 bit words
-(cp.q) depends on CONFIG_MEM_SUPPORT_64BIT_DATA=y. Copying to flash depends on
+(cp.q) is only available on 64-bit targets. Copying to flash depends on
CONFIG_MTD_NOR_FLASH=y.
Return value
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: cyclic (command)
+
cyclic command
==============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: dm (command)
+
dm command
==========
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: ebtupdate (command)
+
ebtupdate command
=================
+.. index::
+ single: echo (command)
+
echo command
============
.. SPDX-License-Identifier: GPL-2.0+
.. Copyright 2020, Heinrich Schuchardt <xypron.glpk@gmx.de>
+.. index::
+ single: efi (command)
+
efi command
===========
.. SPDX-License-Identifier: GPL-2.0+
.. (C) Copyright 2022, Masahisa Kojima <masahisa.kojima@linaro.org>
+.. index::
+ single: eficonfig (command)
+
eficonfig command
=================
.. SPDX-License-Identifier: GPL-2.0-or-later:
+.. index::
+ single: env (command)
+
env command
===========
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: event (command)
+
event command
=============
+.. index::
+ single: exception (command)
+
exception command
=================
+.. index::
+ single: exit (command)
+
exit command
============
.. SPDX-License-Identifier: GPL-2.0+
.. Copyright 2021, Kory Maincent <kory.maincent@bootlin.com>
+.. index::
+ single: extension (command)
+
extension command
=================
+.. index::
+ single: false (command)
+
false command
=============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: fatinfo (command)
+
fatinfo command
===============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: fatload (command)
+
fatload command
===============
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: fdt (command)
+
fdt command
===========
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: font (command)
+
font command
============
+.. index::
+ single: for (command)
+
for command
===========
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: fwu_mdata_read (command)
+
fwu_mdata_read command
======================
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: gpio (command)
+
gpio command
============
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: gpt (command)
+
gpt command
===========
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: history (command)
+
history command
===============
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: host (command)
+
host command
============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: imxtract (command)
+
imxtract command
================
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: load (command)
+
load command
============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: loadb (command)
+
loadb command
=============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: loadm (command)
+
loadm command
=============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: loads (command)
+
loads command
=============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: loadx (command)
+
loadx command
=============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: loady (command)
+
loady command
=============
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: mbr (command)
+
mbr command
===========
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: md (command)
+
md command
==========
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: mmc (command)
+
mmc command
===========
.. SPDX-License-Identifier: GPL-2.0+
.. Copyright 2022, Heinrich Schuchardt <xypron.glpk@gmx.de>
+.. index::
+ single: mtest (command)
+
mtest command
=============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: mtrr (command)
+
mtrr command
============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: panic (command)
+
panic command
=============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: part (command)
+
part command
============
.. SPDX-License-Identifier: GPL-2.0-or-later:
+.. index::
+ single: pause (command)
+
pause command
=============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: pinmux (command)
+
pinmux command
==============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: printenv (command)
+
printenv command
================
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: pstore (command)
+
pstore command
==============
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: qfw (command)
+
qfw command
===========
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: reset (command)
+
reset command
=============
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: rng (command)
+
rng command
===========
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: saves (command)
+
saves command
=============
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: sbi (command)
+
sbi command
===========
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: scmi (command)
+
scmi command
============
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: scp03 (command)
+
scp03 command
=============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: seama (command)
+
seama command
=============
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: setexpr (command)
+
setexpr command
===============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: sf (command)
+
sf command
==========
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: size (command)
+
size command
============
.. SPDX-License-Identifier: GPL-2.0+
.. Copyright 2023, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+.. index::
+ single: sleep (command)
+
sleep command
=============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: sm (command)
+
sm command
==========
.. SPDX-License-Identifier: GPL-2.0+
.. Copyright 2022, Heinrich Schuchardt <xypron.glpk@gmx.de>
+.. index::
+ single: sound (command)
+
sound command
=============
.. SPDX-License-Identifier: GPL-2.0+
.. Copyright 2022, Heinrich Schuchardt <xypron.glpk@gmx.de>
+.. index::
+ single: source (command)
+
source command
==============
.. SPDX-License-Identifier: GPL-2.0-or-later
+.. index::
+ single: temperature (command)
+
temperature command
===================
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: tftpput (command)
+
tftpput command
===============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: trace (command)
+
trace command
=============
+.. index::
+ single: true (command)
+
true command
============
.. SPDX-License-Identifier: GPL-2.0+
+.. index::
+ single: ums (command)
+
ums command
===========
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: unbind (command)
+
unbind command
==============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: ut (command)
+
ut command
==========
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: wdt (command)
+
wdt command
===========
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: wget (command)
+
wget command
============
.. SPDX-License-Identifier: GPL-2.0-or-later:
+.. index::
+ single: write (command)
+
write command
=============
.. SPDX-License-Identifier: GPL-2.0+:
+.. index::
+ single: xxd (command)
+
xxd command
===========
Overview
--------
-The Device Firmware Upgrade (DFU) allows to download and upload firmware
-to/from U-Boot connected over USB.
+Device Firmware Upgrade (DFU) enables the download and upload of firmware
+to/from U-Boot while connected over USB.
U-Boot follows the Universal Serial Bus Device Class Specification for
-Device Firmware Upgrade Version 1.1 the USB forum (DFU v1.1 in www.usb.org).
+Device Firmware Upgrade Version 1.1 from the USB forum (DFU v1.1 in www.usb.org).
U-Boot implements this DFU capability (CONFIG_DFU) with the command dfu
(cmd/dfu.c / CONFIG_CMD_DFU) based on:
Configuration Options
---------------------
-The following configuration option are relevant for device firmware upgrade:
+The following configuration options are relevant to device firmware upgrade:
* CONFIG_DFU
* CONFIG_DFU_OVER_USB
Environment variables
---------------------
-The dfu command uses 3 environments variables:
+The dfu command uses 3 environment variables:
dfu_alt_info
The DFU setting for the USB download gadget with a semicolon separated
--------
dfu <USB_controller> [<interface> <dev>] list
- list the alternate device defined in *dfu_alt_info*
+ List the alternate device defined in *dfu_alt_info*.
dfu <USB_controller> [<interface> <dev>] [<timeout>]
- start the dfu stack on the USB instance with the selected medium
+ Start the dfu stack on the USB instance with the selected medium
backend and use the *dfu_alt_info* variable to configure the
- alternate setting and link each one with the medium
- The dfu command continue until receive a ^C in console or
- a DFU detach transaction from HOST. If CONFIG_DFU_TIMEOUT option
- is enabled and <timeout> parameter is present in the command line,
+ alternate setting and link each one with the medium.
+ The dfu command continues until it receives a ^C in the console or
+ a DFU detach transaction from the HOST. If the CONFIG_DFU_TIMEOUT option
+ is enabled and a <timeout> parameter is present in the command line,
the DFU operation will be aborted automatically after <timeout>
- seconds of waiting remote to initiate DFU session.
+ seconds of waiting for the remote to initiate a DFU session.
The possible values of <interface> are (with <USB controller> = 0 in the dfu
command example)
u-boot raw 0x80 0x800;uImage ext4 0 2
- If don't want to flash given image file to storage, use "skip" type
- entity.
+ If you don't want to flash the given image file to storage, use the "skip"
+ type entity.
- - It can be used to protect flashing wrong image for the specific board.
- - Especailly, this layout will be useful when thor protocol is used,
+ - It can be used to protect from flashing the wrong image for the specific board.
+ - Especially, this layout will be useful when the thor protocol is used,
which performs flashing in batch mode, where more than one file is
processed.
u-boot-<board1>.bin raw 0x80 0x800; u-boot-<board2>.bin skip 0 0
- When flashing new system image requires do some more complex things
- than just writing data to the storage medium, one can use 'script'
- type. Data written to such entity will be executed as a command list
- in the u-boot's shell. This for example allows to re-create partition
- layout and even set new *dfu_alt_info* for the newly created paritions.
- Such script would look like::
+ When flashing a new system image requires you to do some more complex
+ things than just writing data to the storage medium, one can use 'script'
+ type. Data written to such an entity will be executed as a command list
+ in the u-boot's shell. This for example allows you to re-create a partition
+ layout and even set a new *dfu_alt_info* for the newly created partitions.
+ Such a script would look like::
setenv dfu_alt_info ...
setenv mbr_parts ...
mbr write ...
- Please note that this means that user will be able to execute any
+ Please note that this means the user will be able to execute any
arbitrary commands just like in the u-boot's shell.
nand
each element in *dfu_alt_info* being either of:
* <name> raw <offset> <size> raw access to sf device
- * <name> part <dev_id> <part_id> raw acces to partition
- * <name> partubi <dev_id> <part_id> raw acces to ubi partition
+ * <name> part <dev_id> <part_id> raw access to partition
+ * <name> partubi <dev_id> <part_id> raw access to ubi partition
with
The weak callback functions can be implemented to manage specific behavior
dfu_initiated_callback
- called when the DFU transaction is started, used to initiase the device
+ called when the DFU transaction is started, used to initialize the device
dfu_flush_callback
called at the end of the DFU write after DFU manifestation, used to manage
- the device when DFU transaction is closed
+ the device when the DFU transaction is closed
Host tools
----------
When U-Boot runs the dfu stack, the DFU host tools can be used
-to send/receive firmwares on each configurated alternate.
+to send/receive firmware images on each configured alternate.
For example dfu-util is a host side implementation of the DFU 1.1
specifications(http://dfu-util.sourceforge.net/) which works with U-Boot.
Example 3
-firmware located in SD Card (mmc) and virtual partition on OTP and PMIC not
-volatile memory
+firmware located in SD Card (mmc) and virtual partition on OTP and PMIC
+non-volatile memory
- alternate 1 (alt=1) for scard
- alternate 2 (alt=2) for OTP (virtual)
The GPIO driver must used driver model. Buttons are configured using
the device tree.
+config BUTTON_QCOM_PMIC
+ bool "Qualcomm power button"
+ depends on BUTTON
+ depends on PMIC_QCOM
+ help
+ Enable support for the power and "resin" (usually volume down) buttons
+ on Qualcomm SoCs. These will be configured as the Enter and Down keys
+ respectively, allowing navigation of bootmenu with buttons on device.
+
endmenu
obj-$(CONFIG_BUTTON) += button-uclass.o
obj-$(CONFIG_BUTTON_ADC) += button-adc.o
obj-$(CONFIG_BUTTON_GPIO) += button-gpio.o
+obj-$(CONFIG_BUTTON_QCOM_PMIC) += button-qcom-pmic.o
\ No newline at end of file
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm generic pmic gpio driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ * (C) Copyright 2023 Linaro Ltd.
+ */
+
+#include <button.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <log.h>
+#include <power/pmic.h>
+#include <spmi/spmi.h>
+#include <linux/bitops.h>
+
+#define REG_TYPE 0x4
+#define REG_SUBTYPE 0x5
+
+struct qcom_pmic_btn_priv {
+ u32 base;
+ u32 status_bit;
+ int code;
+ struct udevice *pmic;
+};
+
+#define PON_INT_RT_STS 0x10
+#define KPDPWR_ON_INT_BIT 0
+#define RESIN_ON_INT_BIT 1
+
+#define NODE_IS_PWRKEY(node) (!strncmp(ofnode_get_name(node), "pwrkey", strlen("pwrkey")))
+#define NODE_IS_RESIN(node) (!strncmp(ofnode_get_name(node), "resin", strlen("resin")))
+
+static enum button_state_t qcom_pwrkey_get_state(struct udevice *dev)
+{
+ struct qcom_pmic_btn_priv *priv = dev_get_priv(dev);
+
+ int reg = pmic_reg_read(priv->pmic, priv->base + PON_INT_RT_STS);
+
+ if (reg < 0)
+ return 0;
+
+ return (reg & BIT(priv->status_bit)) != 0;
+}
+
+static int qcom_pwrkey_get_code(struct udevice *dev)
+{
+ struct qcom_pmic_btn_priv *priv = dev_get_priv(dev);
+
+ return priv->code;
+}
+
+static int qcom_pwrkey_probe(struct udevice *dev)
+{
+ struct button_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+ struct qcom_pmic_btn_priv *priv = dev_get_priv(dev);
+ ofnode node = dev_ofnode(dev);
+ int ret;
+ u64 base;
+
+ /* Ignore the top-level pon node */
+ if (!uc_plat->label)
+ return 0;
+
+ /* the pwrkey and resin nodes are children of the "pon" node, get the
+ * PMIC device to use in pmic_reg_* calls.
+ */
+ priv->pmic = dev->parent->parent;
+
+ /* Get the address of the parent pon node */
+ base = dev_read_addr(dev->parent);
+ if (base == FDT_ADDR_T_NONE) {
+ printf("%s: Can't find address\n", dev->name);
+ return -EINVAL;
+ }
+
+ priv->base = base;
+
+ /* Do a sanity check */
+ ret = pmic_reg_read(priv->pmic, priv->base + REG_TYPE);
+ if (ret != 0x1 && ret != 0xb) {
+ printf("%s: unexpected PMIC function type %d\n", dev->name, ret);
+ return -ENXIO;
+ }
+
+ ret = pmic_reg_read(priv->pmic, priv->base + REG_SUBTYPE);
+ if ((ret & 0x7) == 0) {
+ printf("%s: unexpected PMCI function subtype %d\n", dev->name, ret);
+ return -ENXIO;
+ }
+
+ if (NODE_IS_PWRKEY(node)) {
+ priv->status_bit = 0;
+ priv->code = KEY_ENTER;
+ } else if (NODE_IS_RESIN(node)) {
+ priv->status_bit = 1;
+ priv->code = KEY_DOWN;
+ } else {
+ /* Should not get here! */
+ printf("Invalid pon node '%s' should be 'pwrkey' or 'resin'\n",
+ ofnode_get_name(node));
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int button_qcom_pmic_bind(struct udevice *parent)
+{
+ struct udevice *dev;
+ ofnode node;
+ int ret;
+
+ dev_for_each_subnode(node, parent) {
+ struct button_uc_plat *uc_plat;
+ const char *label;
+
+ if (!ofnode_is_enabled(node))
+ continue;
+
+ ret = device_bind_driver_to_node(parent, "qcom_pwrkey",
+ ofnode_get_name(node),
+ node, &dev);
+ if (ret) {
+ printf("Failed to bind %s! %d\n", label, ret);
+ return ret;
+ }
+ uc_plat = dev_get_uclass_plat(dev);
+ if (NODE_IS_PWRKEY(node)) {
+ uc_plat->label = "pwrkey";
+ } else if (NODE_IS_RESIN(node)) {
+ uc_plat->label = "vol_down";
+ } else {
+ printf("Unknown button node '%s' should be 'pwrkey' or 'resin'\n",
+ ofnode_get_name(node));
+ device_unbind(dev);
+ }
+ }
+
+ return 0;
+}
+
+static const struct button_ops button_qcom_pmic_ops = {
+ .get_state = qcom_pwrkey_get_state,
+ .get_code = qcom_pwrkey_get_code,
+};
+
+static const struct udevice_id qcom_pwrkey_ids[] = {
+ { .compatible = "qcom,pm8916-pon" },
+ { .compatible = "qcom,pm8941-pon" },
+ { .compatible = "qcom,pm8998-pon" },
+ { }
+};
+
+U_BOOT_DRIVER(qcom_pwrkey) = {
+ .name = "qcom_pwrkey",
+ .id = UCLASS_BUTTON,
+ .of_match = qcom_pwrkey_ids,
+ .bind = button_qcom_pmic_bind,
+ .probe = qcom_pwrkey_probe,
+ .ops = &button_qcom_pmic_ops,
+ .priv_auto = sizeof(struct qcom_pmic_btn_priv),
+};
source "drivers/clk/microchip/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/owl/Kconfig"
+source "drivers/clk/qcom/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/sunxi/Kconfig"
source "drivers/clk/sifive/Kconfig"
obj-$(CONFIG_CLK_MVEBU) += mvebu/
obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
obj-$(CONFIG_CLK_OWL) += owl/
+obj-$(CONFIG_CLK_QCOM) += qcom/
obj-$(CONFIG_CLK_RENESAS) += renesas/
obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o
obj-$(CONFIG_CLK_SIFIVE) += sifive/
--- /dev/null
+if ARCH_SNAPDRAGON || ARCH_IPQ40XX
+
+config CLK_QCOM
+ bool
+ depends on CLK && DM_RESET
+ def_bool n
+
+menu "Qualcomm clock drivers"
+
+config CLK_QCOM_APQ8016
+ bool "Qualcomm APQ8016 GCC"
+ select CLK_QCOM
+ help
+ Say Y here to enable support for the Global Clock Controller
+ on the Snapdragon APQ8016 SoC. This driver supports the clocks
+ and resets exposed by the GCC hardware block.
+
+config CLK_QCOM_APQ8096
+ bool "Qualcomm APQ8096 GCC"
+ select CLK_QCOM
+ help
+ Say Y here to enable support for the Global Clock Controller
+ on the Snapdragon APQ8096 SoC. This driver supports the clocks
+ and resets exposed by the GCC hardware block.
+
+config CLK_QCOM_IPQ4019
+ bool "Qualcomm IPQ4019 GCC"
+ select CLK_QCOM
+ help
+ Say Y here to enable support for the Global Clock Controller
+ on the Snapdragon IPQ4019 SoC. This driver supports the clocks
+ and resets exposed by the GCC hardware block.
+
+config CLK_QCOM_QCS404
+ bool "Qualcomm QCS404 GCC"
+ select CLK_QCOM
+ help
+ Say Y here to enable support for the Global Clock Controller
+ on the Snapdragon QCS404 SoC. This driver supports the clocks
+ and resets exposed by the GCC hardware block.
+
+config CLK_QCOM_SDM845
+ bool "Qualcomm SDM845 GCC"
+ select CLK_QCOM
+ help
+ Say Y here to enable support for the Global Clock Controller
+ on the Snapdragon 845 SoC. This driver supports the clocks
+ and resets exposed by the GCC hardware block.
+
+endmenu
+
+endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2023 Linaro
+
+obj-y += clock-qcom.o
+obj-$(CONFIG_CLK_QCOM_SDM845) += clock-sdm845.o
+obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
+obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
+obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
+obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
#include <errno.h>
#include <asm/io.h>
#include <linux/bitops.h>
-#include "clock-snapdragon.h"
+
+#include "clock-qcom.h"
+
+/* Clocks: (from CLK_CTL_BASE) */
+#define GPLL0_STATUS (0x2101C)
+#define APCS_GPLL_ENA_VOTE (0x45000)
+#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
+
+#define SDCC_BCR(n) ((n * 0x1000) + 0x41000)
+#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004)
+#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008)
+#define SDCC_M(n) ((n * 0x1000) + 0x4100C)
+#define SDCC_N(n) ((n * 0x1000) + 0x41010)
+#define SDCC_D(n) ((n * 0x1000) + 0x41014)
+#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018)
+#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C)
+
+/* BLSP1 AHB clock (root clock for BLSP) */
+#define BLSP1_AHB_CBCR 0x1008
+
+/* Uart clock control registers */
+#define BLSP1_UART2_BCR (0x3028)
+#define BLSP1_UART2_APPS_CBCR (0x302C)
+#define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
+#define BLSP1_UART2_APPS_CFG_RCGR (0x3038)
+#define BLSP1_UART2_APPS_M (0x303C)
+#define BLSP1_UART2_APPS_N (0x3040)
+#define BLSP1_UART2_APPS_D (0x3044)
/* GPLL0 clock control registers */
#define GPLL0_STATUS_ACTIVE BIT(17)
/* SDHCI */
static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
{
- int div = 8; /* 100MHz default */
+ int div = 15; /* 100MHz default */
if (rate == 200000000)
div = 4;
clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot));
/* 800Mhz/div, gpll0 */
clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0,
- CFG_CLK_SRC_GPLL0);
+ CFG_CLK_SRC_GPLL0, 8);
clk_enable_gpll0(priv->base, &gpll0_vote_clk);
clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
/* 7372800 uart block clock @ GPLL0 */
clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
- CFG_CLK_SRC_GPLL0);
+ CFG_CLK_SRC_GPLL0, 16);
/* Vote for gpll0 clock */
clk_enable_gpll0(priv->base, &gpll0_vote_clk);
return 0;
}
-ulong msm_set_rate(struct clk *clk, ulong rate)
+static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
}
}
-int msm_enable(struct clk *clk)
-{
- return 0;
-}
+static struct msm_clk_data apq8016_clk_data = {
+ .set_rate = apq8016_clk_set_rate,
+};
+
+static const struct udevice_id gcc_apq8016_of_match[] = {
+ {
+ .compatible = "qcom,gcc-apq8016",
+ .data = (ulong)&apq8016_clk_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(gcc_apq8016) = {
+ .name = "gcc_apq8016",
+ .id = UCLASS_NOP,
+ .of_match = gcc_apq8016_of_match,
+ .bind = qcom_cc_bind,
+ .flags = DM_FLAG_PRE_RELOC,
+};
#include <errno.h>
#include <asm/io.h>
#include <linux/bitops.h>
-#include "clock-snapdragon.h"
+
+#include "clock-qcom.h"
+
+/* Clocks: (from CLK_CTL_BASE) */
+#define GPLL0_STATUS (0x0000)
+#define APCS_GPLL_ENA_VOTE (0x52000)
+#define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004)
+
+#define SDCC2_BCR (0x14000) /* block reset */
+#define SDCC2_APPS_CBCR (0x14004) /* branch control */
+#define SDCC2_AHB_CBCR (0x14008)
+#define SDCC2_CMD_RCGR (0x14010)
+#define SDCC2_CFG_RCGR (0x14014)
+#define SDCC2_M (0x14018)
+#define SDCC2_N (0x1401C)
+#define SDCC2_D (0x14020)
+
+#define BLSP2_AHB_CBCR (0x25004)
+#define BLSP2_UART2_APPS_CBCR (0x29004)
+#define BLSP2_UART2_APPS_CMD_RCGR (0x2900C)
+#define BLSP2_UART2_APPS_CFG_RCGR (0x29010)
+#define BLSP2_UART2_APPS_M (0x29014)
+#define BLSP2_UART2_APPS_N (0x29018)
+#define BLSP2_UART2_APPS_D (0x2901C)
/* GPLL0 clock control registers */
#define GPLL0_STATUS_ACTIVE BIT(30)
static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
{
- int div = 3;
+ int div = 5;
clk_enable_cbc(priv->base + SDCC2_AHB_CBCR);
clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0,
- CFG_CLK_SRC_GPLL0);
+ CFG_CLK_SRC_GPLL0, 8);
clk_enable_gpll0(priv->base, &gpll0_vote_clk);
clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);
/* 7372800 uart block clock @ GPLL0 */
clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625,
- CFG_CLK_SRC_GPLL0);
+ CFG_CLK_SRC_GPLL0, 16);
/* Vote for gpll0 clock */
clk_enable_gpll0(priv->base, &gpll0_vote_clk);
return 0;
}
-ulong msm_set_rate(struct clk *clk, ulong rate)
+static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
}
}
-int msm_enable(struct clk *clk)
-{
- return 0;
-}
+static struct msm_clk_data apq8096_clk_data = {
+ .set_rate = apq8096_clk_set_rate,
+};
+
+static const struct udevice_id gcc_apq8096_of_match[] = {
+ {
+ .compatible = "qcom,gcc-apq8096",
+ .data = (ulong)&apq8096_clk_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(gcc_apq8096) = {
+ .name = "gcc_apq8096",
+ .id = UCLASS_NOP,
+ .of_match = gcc_apq8096_of_match,
+ .bind = qcom_cc_bind,
+ .flags = DM_FLAG_PRE_RELOC,
+};
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
/*
+ * Clock drivers for Qualcomm IPQ40xx
+ *
* Copyright (c) 2020 Sartura Ltd.
- * Copyright (c) 2022 Linaro Ltd.
*
* Author: Robert Marko <robert.marko@sartura.hr>
- * Sumit Garg <sumit.garg@linaro.org>
*
- * Based on Linux driver
*/
-#include <asm/io.h>
+#include <clk-uclass.h>
#include <common.h>
#include <dm.h>
-#include <reset-uclass.h>
-#include <linux/bitops.h>
-#include <malloc.h>
+#include <errno.h>
+#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
-struct qcom_reset_priv {
- phys_addr_t base;
-};
+#include "clock-qcom.h"
-struct qcom_reset_map {
- unsigned int reg;
- u8 bit;
-};
+static ulong ipq4019_clk_set_rate(struct clk *clk, ulong rate)
+{
+ switch (clk->id) {
+ case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
+ /* This clock is already initialized by SBL1 */
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
-#ifdef CONFIG_ARCH_IPQ40XX
-#include <dt-bindings/reset/qcom,ipq4019-reset.h>
-static const struct qcom_reset_map gcc_qcom_resets[] = {
+static int ipq4019_clk_enable(struct clk *clk)
+{
+ switch (clk->id) {
+ case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/
+ /* This clock is already initialized by SBL1 */
+ return 0;
+ case GCC_PRNG_AHB_CLK: /*PRNG*/
+ /* This clock is already initialized by SBL1 */
+ return 0;
+ case GCC_USB3_MASTER_CLK:
+ case GCC_USB3_SLEEP_CLK:
+ case GCC_USB3_MOCK_UTMI_CLK:
+ case GCC_USB2_MASTER_CLK:
+ case GCC_USB2_SLEEP_CLK:
+ case GCC_USB2_MOCK_UTMI_CLK:
+ /* These clocks is already initialized by SBL1 */
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct qcom_reset_map gcc_ipq4019_resets[] = {
[WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
[WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
[WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
[GCC_MPM_BCR] = {0x24000, 0},
[GCC_SPDM_BCR] = {0x25000, 0},
};
-#endif
-
-#ifdef CONFIG_TARGET_QCS404EVB
-#include <dt-bindings/clock/qcom,gcc-qcs404.h>
-static const struct qcom_reset_map gcc_qcom_resets[] = {
- [GCC_GENI_IR_BCR] = { 0x0F000 },
- [GCC_CDSP_RESTART] = { 0x18000 },
- [GCC_USB_HS_BCR] = { 0x41000 },
- [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
- [GCC_QUSB2_PHY_BCR] = { 0x4103c },
- [GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },
- [GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },
- [GCC_USB3_PHY_BCR] = { 0x39004 },
- [GCC_USB_30_BCR] = { 0x39000 },
- [GCC_USB3PHY_PHY_BCR] = { 0x39008 },
- [GCC_PCIE_0_BCR] = { 0x3e000 },
- [GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
- [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
- [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
- [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
- [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
- [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
- [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
- [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
- [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
- [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
- [GCC_EMAC_BCR] = { 0x4e000 },
- [GCC_WDSP_RESTART] = {0x19000},
-};
-#endif
-
-static int qcom_reset_assert(struct reset_ctl *rst)
-{
- struct qcom_reset_priv *priv = dev_get_priv(rst->dev);
- const struct qcom_reset_map *reset_map = gcc_qcom_resets;
- const struct qcom_reset_map *map;
- u32 value;
-
- map = &reset_map[rst->id];
- value = readl(priv->base + map->reg);
- value |= BIT(map->bit);
- writel(value, priv->base + map->reg);
-
- return 0;
-}
-
-static int qcom_reset_deassert(struct reset_ctl *rst)
-{
- struct qcom_reset_priv *priv = dev_get_priv(rst->dev);
- const struct qcom_reset_map *reset_map = gcc_qcom_resets;
- const struct qcom_reset_map *map;
- u32 value;
-
- map = &reset_map[rst->id];
-
- value = readl(priv->base + map->reg);
- value &= ~BIT(map->bit);
- writel(value, priv->base + map->reg);
-
- return 0;
-}
-
-static const struct reset_ops qcom_reset_ops = {
- .rst_assert = qcom_reset_assert,
- .rst_deassert = qcom_reset_deassert,
+static struct msm_clk_data ipq4019_clk_data = {
+ .enable = ipq4019_clk_enable,
+ .set_rate = ipq4019_clk_set_rate,
+ .resets = gcc_ipq4019_resets,
+ .num_resets = ARRAY_SIZE(gcc_ipq4019_resets),
};
-static const struct udevice_id qcom_reset_ids[] = {
- { .compatible = "qcom,gcc-reset-ipq4019" },
- { .compatible = "qcom,gcc-reset-qcs404" },
+static const struct udevice_id gcc_ipq4019_of_match[] = {
+ {
+ .compatible = "qcom,gcc-ipq4019",
+ .data = (ulong)&ipq4019_clk_data,
+ },
{ }
};
-static int qcom_reset_probe(struct udevice *dev)
-{
- struct qcom_reset_priv *priv = dev_get_priv(dev);
-
- priv->base = dev_read_addr(dev);
- if (priv->base == FDT_ADDR_T_NONE)
- return -EINVAL;
-
- return 0;
-}
-
-U_BOOT_DRIVER(qcom_reset) = {
- .name = "qcom_reset",
- .id = UCLASS_RESET,
- .of_match = qcom_reset_ids,
- .ops = &qcom_reset_ops,
- .probe = qcom_reset_probe,
- .priv_auto = sizeof(struct qcom_reset_priv),
+U_BOOT_DRIVER(gcc_ipq4019) = {
+ .name = "gcc_ipq4019",
+ .id = UCLASS_NOP,
+ .of_match = gcc_ipq4019_of_match,
+ .bind = qcom_cc_bind,
+ .flags = DM_FLAG_PRE_RELOC,
};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause AND GPL-2.0
+/*
+ * Clock and reset drivers for Qualcomm platforms Global Clock
+ * Controller (GCC).
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ * (C) Copyright 2020 Sartura Ltd. (reset driver)
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ * (C) Copyright 2022 Linaro Ltd. (reset driver)
+ * Author: Sumit Garg <sumit.garg@linaro.org>
+ *
+ * Based on Little Kernel driver, simplified
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/delay.h>
+#include <linux/bitops.h>
+#include <reset-uclass.h>
+
+#include "clock-qcom.h"
+
+/* CBCR register fields */
+#define CBCR_BRANCH_ENABLE_BIT BIT(0)
+#define CBCR_BRANCH_OFF_BIT BIT(31)
+
+/* Enable clock controlled by CBC soft macro */
+void clk_enable_cbc(phys_addr_t cbcr)
+{
+ setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT);
+
+ while (readl(cbcr) & CBCR_BRANCH_OFF_BIT)
+ ;
+}
+
+void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0)
+{
+ if (readl(base + gpll0->status) & gpll0->status_bit)
+ return; /* clock already enabled */
+
+ setbits_le32(base + gpll0->ena_vote, gpll0->vote_bit);
+
+ while ((readl(base + gpll0->status) & gpll0->status_bit) == 0)
+ ;
+}
+
+#define BRANCH_ON_VAL (0)
+#define BRANCH_NOC_FSM_ON_VAL BIT(29)
+#define BRANCH_CHECK_MASK GENMASK(31, 28)
+
+void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk)
+{
+ u32 val;
+
+ setbits_le32(base + vclk->ena_vote, vclk->vote_bit);
+ do {
+ val = readl(base + vclk->cbcr_reg);
+ val &= BRANCH_CHECK_MASK;
+ } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL));
+}
+
+#define APPS_CMD_RCGR_UPDATE BIT(0)
+
+/* Update clock command via CMD_RCGR */
+void clk_bcr_update(phys_addr_t apps_cmd_rcgr)
+{
+ u32 count;
+ setbits_le32(apps_cmd_rcgr, APPS_CMD_RCGR_UPDATE);
+
+ /* Wait for frequency to be updated. */
+ for (count = 0; count < 50000; count++) {
+ if (!(readl(apps_cmd_rcgr) & APPS_CMD_RCGR_UPDATE))
+ break;
+ udelay(1);
+ }
+ WARN(count == 50000, "WARNING: RCG @ %#llx [%#010x] stuck at off\n",
+ apps_cmd_rcgr, readl(apps_cmd_rcgr));
+}
+
+#define CFG_SRC_DIV_MASK 0b11111
+#define CFG_SRC_SEL_SHIFT 8
+#define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT)
+#define CFG_MODE_SHIFT 12
+#define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT)
+#define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT)
+#define CFG_HW_CLK_CTRL_MASK BIT(20)
+
+/*
+ * root set rate for clocks with half integer and MND divider
+ * div should be pre-calculated ((div * 2) - 1)
+ */
+void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
+ int div, int m, int n, int source, u8 mnd_width)
+{
+ u32 cfg;
+ /* M value for MND divider. */
+ u32 m_val = m;
+ u32 n_minus_m = n - m;
+ /* NOT(N-M) value for MND divider. */
+ u32 n_val = ~n_minus_m * !!(n);
+ /* NOT 2D value for MND divider. */
+ u32 d_val = ~(clamp_t(u32, n, m, n_minus_m));
+ u32 mask = BIT(mnd_width) - 1;
+
+ debug("m %#x n %#x d %#x div %#x mask %#x\n", m_val, n_val, d_val, div, mask);
+
+ /* Program MND values */
+ writel(m_val & mask, base + regs->M);
+ writel(n_val & mask, base + regs->N);
+ writel(d_val & mask, base + regs->D);
+
+ /* setup src select and divider */
+ cfg = readl(base + regs->cfg_rcgr);
+ cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK);
+ cfg |= source & CFG_SRC_SEL_MASK; /* Select clock source */
+
+ if (div)
+ cfg |= div & CFG_SRC_DIV_MASK;
+
+ if (n && n != m)
+ cfg |= CFG_MODE_DUAL_EDGE;
+
+ writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
+
+ /* Inform h/w to start using the new config. */
+ clk_bcr_update(base + regs->cmd_rcgr);
+}
+
+/* root set rate for clocks with half integer and mnd_width=0 */
+void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
+ int source)
+{
+ u32 cfg;
+
+ /* setup src select and divider */
+ cfg = readl(base + regs->cfg_rcgr);
+ cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK);
+ cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
+
+ /*
+ * Set the divider; HW permits fraction dividers (+0.5), but
+ * for simplicity, we will support integers only
+ */
+ if (div)
+ cfg |= (2 * div - 1) & CFG_SRC_DIV_MASK;
+
+ writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
+
+ /* Inform h/w to start using the new config. */
+ clk_bcr_update(base + regs->cmd_rcgr);
+}
+
+const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate)
+{
+ if (!f)
+ return NULL;
+
+ if (!f->freq)
+ return f;
+
+ for (; f->freq; f++)
+ if (rate <= f->freq)
+ return f;
+
+ /* Default to our fastest rate */
+ return f - 1;
+}
+
+static int msm_clk_probe(struct udevice *dev)
+{
+ struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev);
+ struct msm_clk_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr(dev);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->data = data;
+
+ return 0;
+}
+
+static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(clk->dev);
+
+ if (data->set_rate)
+ return data->set_rate(clk, rate);
+
+ return 0;
+}
+
+static int msm_clk_enable(struct clk *clk)
+{
+ struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(clk->dev);
+
+ if (data->enable)
+ return data->enable(clk);
+
+ return 0;
+}
+
+static struct clk_ops msm_clk_ops = {
+ .set_rate = msm_clk_set_rate,
+ .enable = msm_clk_enable,
+};
+
+U_BOOT_DRIVER(qcom_clk) = {
+ .name = "qcom_clk",
+ .id = UCLASS_CLK,
+ .ops = &msm_clk_ops,
+ .priv_auto = sizeof(struct msm_clk_priv),
+ .probe = msm_clk_probe,
+};
+
+int qcom_cc_bind(struct udevice *parent)
+{
+ struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(parent);
+ struct udevice *clkdev, *rstdev;
+ struct driver *drv;
+ int ret;
+
+ /* Get a handle to the common clk handler */
+ drv = lists_driver_lookup_name("qcom_clk");
+ if (!drv)
+ return -ENOENT;
+
+ /* Register the clock controller */
+ ret = device_bind_with_driver_data(parent, drv, "qcom_clk", (ulong)data,
+ dev_ofnode(parent), &clkdev);
+ if (ret)
+ return ret;
+
+ /* Bail out early if resets are not specified for this platform */
+ if (!data->resets)
+ return ret;
+
+ /* Get a handle to the common reset handler */
+ drv = lists_driver_lookup_name("qcom_reset");
+ if (!drv)
+ return -ENOENT;
+
+ /* Register the reset controller */
+ ret = device_bind_with_driver_data(parent, drv, "qcom_reset", (ulong)data,
+ dev_ofnode(parent), &rstdev);
+ if (ret)
+ device_unbind(clkdev);
+
+ return ret;
+}
+
+static int qcom_reset_set(struct reset_ctl *rst, bool assert)
+{
+ struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(rst->dev);
+ void __iomem *base = dev_get_priv(rst->dev);
+ const struct qcom_reset_map *map;
+ u32 value;
+
+ map = &data->resets[rst->id];
+
+ value = readl(base + map->reg);
+
+ if (assert)
+ value |= BIT(map->bit);
+ else
+ value &= ~BIT(map->bit);
+
+ writel(value, base + map->reg);
+
+ return 0;
+}
+
+static int qcom_reset_assert(struct reset_ctl *rst)
+{
+ return qcom_reset_set(rst, true);
+}
+
+static int qcom_reset_deassert(struct reset_ctl *rst)
+{
+ return qcom_reset_set(rst, false);
+}
+
+static const struct reset_ops qcom_reset_ops = {
+ .rst_assert = qcom_reset_assert,
+ .rst_deassert = qcom_reset_deassert,
+};
+
+static int qcom_reset_probe(struct udevice *dev)
+{
+ /* Set our priv pointer to the base address */
+ dev_set_priv(dev, (void *)dev_read_addr(dev));
+
+ return 0;
+}
+
+U_BOOT_DRIVER(qcom_reset) = {
+ .name = "qcom_reset",
+ .id = UCLASS_RESET,
+ .ops = &qcom_reset_ops,
+ .probe = qcom_reset_probe,
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ */
+#ifndef _CLOCK_QCOM_H
+#define _CLOCK_QCOM_H
+
+#include <asm/io.h>
+
+#define CFG_CLK_SRC_CXO (0 << 8)
+#define CFG_CLK_SRC_GPLL0 (1 << 8)
+#define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
+#define CFG_CLK_SRC_MASK (7 << 8)
+
+struct pll_vote_clk {
+ uintptr_t status;
+ int status_bit;
+ uintptr_t ena_vote;
+ int vote_bit;
+};
+
+struct vote_clk {
+ uintptr_t cbcr_reg;
+ uintptr_t ena_vote;
+ int vote_bit;
+};
+struct bcr_regs {
+ uintptr_t cfg_rcgr;
+ uintptr_t cmd_rcgr;
+ uintptr_t M;
+ uintptr_t N;
+ uintptr_t D;
+};
+
+struct freq_tbl {
+ uint freq;
+ uint src;
+ u8 pre_div;
+ u16 m;
+ u16 n;
+};
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+struct gate_clk {
+ uintptr_t reg;
+ u32 en_val;
+ const char *name;
+};
+
+#ifdef DEBUG
+#define GATE_CLK(clk, reg, val) [clk] = { reg, val, #clk }
+#else
+#define GATE_CLK(clk, reg, val) [clk] = { reg, val, NULL }
+#endif
+
+struct qcom_reset_map {
+ unsigned int reg;
+ u8 bit;
+};
+
+struct clk;
+
+struct msm_clk_data {
+ const struct qcom_reset_map *resets;
+ unsigned long num_resets;
+ const struct gate_clk *clks;
+ unsigned long num_clks;
+
+ int (*enable)(struct clk *clk);
+ unsigned long (*set_rate)(struct clk *clk, unsigned long rate);
+};
+
+struct msm_clk_priv {
+ phys_addr_t base;
+ struct msm_clk_data *data;
+};
+
+int qcom_cc_bind(struct udevice *parent);
+void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0);
+void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
+void clk_enable_cbc(phys_addr_t cbcr);
+void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk);
+const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate);
+void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
+ int div, int m, int n, int source, u8 mnd_width);
+void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
+ int source);
+
+static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
+{
+ u32 val;
+ if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0)
+ return;
+
+ val = readl(priv->base + priv->data->clks[id].reg);
+ writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg);
+}
+
+#endif
#include <errno.h>
#include <asm/io.h>
#include <linux/bitops.h>
-#include "clock-snapdragon.h"
-
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
+#include "clock-qcom.h"
+
+/* Clocks: (from CLK_CTL_BASE) */
+#define GPLL0_STATUS (0x21000)
+#define GPLL1_STATUS (0x20000)
+#define APCS_GPLL_ENA_VOTE (0x45000)
+#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
+
+/* BLSP1 AHB clock (root clock for BLSP) */
+#define BLSP1_AHB_CBCR 0x1008
+
+/* Uart clock control registers */
+#define BLSP1_UART2_BCR (0x3028)
+#define BLSP1_UART2_APPS_CBCR (0x302C)
+#define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
+#define BLSP1_UART2_APPS_CFG_RCGR (0x3038)
+#define BLSP1_UART2_APPS_M (0x303C)
+#define BLSP1_UART2_APPS_N (0x3040)
+#define BLSP1_UART2_APPS_D (0x3044)
+
+/* I2C controller clock control registerss */
+#define BLSP1_QUP0_I2C_APPS_CBCR (0x6028)
+#define BLSP1_QUP0_I2C_APPS_CMD_RCGR (0x602C)
+#define BLSP1_QUP0_I2C_APPS_CFG_RCGR (0x6030)
+#define BLSP1_QUP1_I2C_APPS_CBCR (0x2008)
+#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x200C)
+#define BLSP1_QUP1_I2C_APPS_CFG_RCGR (0x2010)
+#define BLSP1_QUP2_I2C_APPS_CBCR (0x3010)
+#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x3000)
+#define BLSP1_QUP2_I2C_APPS_CFG_RCGR (0x3004)
+#define BLSP1_QUP3_I2C_APPS_CBCR (0x4020)
+#define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x4000)
+#define BLSP1_QUP3_I2C_APPS_CFG_RCGR (0x4004)
+#define BLSP1_QUP4_I2C_APPS_CBCR (0x5020)
+#define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x5000)
+#define BLSP1_QUP4_I2C_APPS_CFG_RCGR (0x5004)
+
+/* SD controller clock control registers */
+#define SDCC_BCR(n) (((n) * 0x1000) + 0x41000)
+#define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x41004)
+#define SDCC_CFG_RCGR(n) (((n) * 0x1000) + 0x41008)
+#define SDCC_M(n) (((n) * 0x1000) + 0x4100C)
+#define SDCC_N(n) (((n) * 0x1000) + 0x41010)
+#define SDCC_D(n) (((n) * 0x1000) + 0x41014)
+#define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018)
+#define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C)
+
+/* USB-3.0 controller clock control registers */
+#define SYS_NOC_USB3_CBCR (0x26014)
+#define USB30_BCR (0x39000)
+#define USB3PHY_BCR (0x39008)
+#define USB30_MASTER_CBCR (0x3900C)
+#define USB30_SLEEP_CBCR (0x39010)
+#define USB30_MOCK_UTMI_CBCR (0x39014)
+#define USB30_MOCK_UTMI_CMD_RCGR (0x3901C)
+#define USB30_MOCK_UTMI_CFG_RCGR (0x39020)
+#define USB30_MASTER_CMD_RCGR (0x39028)
+#define USB30_MASTER_CFG_RCGR (0x3902C)
+#define USB30_MASTER_M (0x39030)
+#define USB30_MASTER_N (0x39034)
+#define USB30_MASTER_D (0x39038)
+#define USB2A_PHY_SLEEP_CBCR (0x4102C)
+#define USB_HS_PHY_CFG_AHB_CBCR (0x41030)
+
+/* ETH controller clock control registers */
+#define ETH_PTP_CBCR (0x4e004)
+#define ETH_RGMII_CBCR (0x4e008)
+#define ETH_SLAVE_AHB_CBCR (0x4e00c)
+#define ETH_AXI_CBCR (0x4e010)
+#define EMAC_PTP_CMD_RCGR (0x4e014)
+#define EMAC_PTP_CFG_RCGR (0x4e018)
+#define EMAC_CMD_RCGR (0x4e01c)
+#define EMAC_CFG_RCGR (0x4e020)
+#define EMAC_M (0x4e024)
+#define EMAC_N (0x4e028)
+#define EMAC_D (0x4e02c)
+
+
/* GPLL0 clock control registers */
#define GPLL0_STATUS_ACTIVE BIT(31)
/* mnd_width = 0 */
};
-ulong msm_set_rate(struct clk *clk, ulong rate)
+static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
case GCC_BLSP1_UART2_APPS_CLK:
/* UART: 115200 */
clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
- CFG_CLK_SRC_CXO);
+ CFG_CLK_SRC_CXO, 16);
clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
break;
case GCC_BLSP1_AHB_CLK:
break;
case GCC_SDCC1_APPS_CLK:
/* SDCC1: 200MHz */
- clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 4, 0, 0,
- CFG_CLK_SRC_GPLL0);
+ clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 7, 0, 0,
+ CFG_CLK_SRC_GPLL0, 8);
clk_enable_gpll0(priv->base, &gpll0_vote_clk);
clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
break;
break;
case GCC_ETH_RGMII_CLK:
if (rate == 250000000)
- clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0,
- CFG_CLK_SRC_GPLL1);
+ clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0,
+ CFG_CLK_SRC_GPLL1, 8);
else if (rate == 125000000)
- clk_rcg_set_rate_mnd(priv->base, &emac_regs, 4, 0, 0,
- CFG_CLK_SRC_GPLL1);
+ clk_rcg_set_rate_mnd(priv->base, &emac_regs, 7, 0, 0,
+ CFG_CLK_SRC_GPLL1, 8);
else if (rate == 50000000)
- clk_rcg_set_rate_mnd(priv->base, &emac_regs, 10, 0, 0,
- CFG_CLK_SRC_GPLL1);
+ clk_rcg_set_rate_mnd(priv->base, &emac_regs, 19, 0, 0,
+ CFG_CLK_SRC_GPLL1, 8);
else if (rate == 5000000)
- clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 1, 50,
- CFG_CLK_SRC_GPLL1);
+ clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50,
+ CFG_CLK_SRC_GPLL1, 8);
break;
default:
return 0;
return 0;
}
-int msm_enable(struct clk *clk)
+static int qcs404_clk_enable(struct clk *clk)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) {
case GCC_USB30_MASTER_CLK:
clk_enable_cbc(priv->base + USB30_MASTER_CBCR);
- clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 4, 0, 0,
- CFG_CLK_SRC_GPLL0);
+ clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 7, 0, 0,
+ CFG_CLK_SRC_GPLL0, 8);
break;
case GCC_SYS_NOC_USB3_CLK:
clk_enable_cbc(priv->base + SYS_NOC_USB3_CBCR);
/* SPEED_1000: freq -> 250MHz */
clk_enable_cbc(priv->base + ETH_PTP_CBCR);
clk_enable_gpll0(priv->base, &gpll1_vote_clk);
- clk_rcg_set_rate_mnd(priv->base, &emac_ptp_regs, 2, 0, 0,
- CFG_CLK_SRC_GPLL1);
+ clk_rcg_set_rate_mnd(priv->base, &emac_ptp_regs, 3, 0, 0,
+ CFG_CLK_SRC_GPLL1, 8);
break;
case GCC_ETH_RGMII_CLK:
/* SPEED_1000: freq -> 250MHz */
clk_enable_cbc(priv->base + ETH_RGMII_CBCR);
clk_enable_gpll0(priv->base, &gpll1_vote_clk);
- clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0,
- CFG_CLK_SRC_GPLL1);
+ clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0,
+ CFG_CLK_SRC_GPLL1, 8);
break;
case GCC_ETH_SLAVE_AHB_CLK:
clk_enable_cbc(priv->base + ETH_SLAVE_AHB_CBCR);
return 0;
}
+
+static const struct qcom_reset_map qcs404_gcc_resets[] = {
+ [GCC_GENI_IR_BCR] = { 0x0F000 },
+ [GCC_CDSP_RESTART] = { 0x18000 },
+ [GCC_USB_HS_BCR] = { 0x41000 },
+ [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
+ [GCC_QUSB2_PHY_BCR] = { 0x4103c },
+ [GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },
+ [GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },
+ [GCC_USB3_PHY_BCR] = { 0x39004 },
+ [GCC_USB_30_BCR] = { 0x39000 },
+ [GCC_USB3PHY_PHY_BCR] = { 0x39008 },
+ [GCC_PCIE_0_BCR] = { 0x3e000 },
+ [GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
+ [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
+ [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
+ [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
+ [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
+ [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
+ [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
+ [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
+ [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
+ [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
+ [GCC_EMAC_BCR] = { 0x4e000 },
+ [GCC_WDSP_RESTART] = {0x19000},
+};
+
+static const struct msm_clk_data qcs404_clk_gcc_data = {
+ .resets = qcs404_gcc_resets,
+ .num_resets = ARRAY_SIZE(qcs404_gcc_resets),
+ .enable = qcs404_clk_enable,
+ .set_rate = qcs404_clk_set_rate,
+};
+
+static const struct udevice_id gcc_qcs404_of_match[] = {
+ {
+ .compatible = "qcom,gcc-qcs404",
+ .data = (ulong)&qcs404_clk_gcc_data
+ },
+ { }
+};
+
+U_BOOT_DRIVER(gcc_qcs404) = {
+ .name = "gcc_qcs404",
+ .id = UCLASS_NOP,
+ .of_match = gcc_qcs404_of_match,
+ .bind = qcom_cc_bind,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Clock drivers for Qualcomm SDM845
+ *
+ * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+ *
+ * Based on Little Kernel driver, simplified
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+
+#include "clock-qcom.h"
+
+#define SE9_AHB_CBCR 0x25004
+#define SE9_UART_APPS_CBCR 0x29004
+#define SE9_UART_APPS_CMD_RCGR 0x18148
+#define SE9_UART_APPS_CFG_RCGR 0x1814C
+#define SE9_UART_APPS_M 0x18150
+#define SE9_UART_APPS_N 0x18154
+#define SE9_UART_APPS_D 0x18158
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
+ F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
+ F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
+ F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+ F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
+ F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
+ F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
+ F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
+ F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
+ F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
+ F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
+ F(102400000, CFG_CLK_SRC_GPLL0_EVEN, 1, 128, 375),
+ F(112000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75),
+ F(117964800, CFG_CLK_SRC_GPLL0_EVEN, 1, 6144, 15625),
+ F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
+ F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75),
+ { }
+};
+
+static const struct bcr_regs uart2_regs = {
+ .cfg_rcgr = SE9_UART_APPS_CFG_RCGR,
+ .cmd_rcgr = SE9_UART_APPS_CMD_RCGR,
+ .M = SE9_UART_APPS_M,
+ .N = SE9_UART_APPS_N,
+ .D = SE9_UART_APPS_D,
+};
+
+static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+ const struct freq_tbl *freq;
+
+ switch (clk->id) {
+ case GCC_QUPV3_WRAP1_S1_CLK: /* UART9 */
+ freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, &uart2_regs,
+ freq->pre_div, freq->m, freq->n, freq->src, 16);
+ return freq->freq;
+ default:
+ return 0;
+ }
+}
+
+static const struct gate_clk sdm845_clks[] = {
+ GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, 0x00000400),
+ GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, 0x00000800),
+ GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, 0x00001000),
+ GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x5200c, 0x00002000),
+ GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x5200c, 0x00004000),
+ GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x5200c, 0x00008000),
+ GATE_CLK(GCC_QUPV3_WRAP0_S6_CLK, 0x5200c, 0x00010000),
+ GATE_CLK(GCC_QUPV3_WRAP0_S7_CLK, 0x5200c, 0x00020000),
+ GATE_CLK(GCC_QUPV3_WRAP1_S0_CLK, 0x5200c, 0x00400000),
+ GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK, 0x5200c, 0x00800000),
+ GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK, 0x5200c, 0x02000000),
+ GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, 0x04000000),
+ GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, 0x08000000),
+ GATE_CLK(GCC_QUPV3_WRAP1_S6_CLK, 0x5200c, 0x10000000),
+ GATE_CLK(GCC_QUPV3_WRAP1_S7_CLK, 0x5200c, 0x20000000),
+ GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x5200c, 0x00000040),
+ GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x5200c, 0x00000080),
+ GATE_CLK(GCC_QUPV3_WRAP_1_M_AHB_CLK, 0x5200c, 0x00100000),
+ GATE_CLK(GCC_QUPV3_WRAP_1_S_AHB_CLK, 0x5200c, 0x00200000),
+ GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, 0x00000001),
+ GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, 0x00000001),
+ GATE_CLK(GCC_SDCC4_AHB_CLK, 0x16008, 0x00000001),
+ GATE_CLK(GCC_SDCC4_APPS_CLK, 0x16004, 0x00000001),
+ GATE_CLK(GCC_UFS_CARD_AHB_CLK, 0x75010, 0x00000001),
+ GATE_CLK(GCC_UFS_CARD_AXI_CLK, 0x7500c, 0x00000001),
+ GATE_CLK(GCC_UFS_CARD_CLKREF_CLK, 0x8c004, 0x00000001),
+ GATE_CLK(GCC_UFS_CARD_ICE_CORE_CLK, 0x75058, 0x00000001),
+ GATE_CLK(GCC_UFS_CARD_PHY_AUX_CLK, 0x7508c, 0x00000001),
+ GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_0_CLK, 0x75018, 0x00000001),
+ GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_1_CLK, 0x750a8, 0x00000001),
+ GATE_CLK(GCC_UFS_CARD_TX_SYMBOL_0_CLK, 0x75014, 0x00000001),
+ GATE_CLK(GCC_UFS_CARD_UNIPRO_CORE_CLK, 0x75054, 0x00000001),
+ GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, 0x00000001),
+ GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77010, 0x00000001),
+ GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x7700c, 0x00000001),
+ GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77058, 0x00000001),
+ GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7708c, 0x00000001),
+ GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x77018, 0x00000001),
+ GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x770a8, 0x00000001),
+ GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77014, 0x00000001),
+ GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77054, 0x00000001),
+ GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x0f00c, 0x00000001),
+ GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x0f014, 0x00000001),
+ GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x0f010, 0x00000001),
+ GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x1000c, 0x00000001),
+ GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x10014, 0x00000001),
+ GATE_CLK(GCC_USB30_SEC_SLEEP_CLK, 0x10010, 0x00000001),
+ GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x8c008, 0x00000001),
+ GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x0f04c, 0x00000001),
+ GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x0f050, 0x00000001),
+ GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x0f054, 0x00000001),
+ GATE_CLK(GCC_USB3_SEC_CLKREF_CLK, 0x8c028, 0x00000001),
+ GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK, 0x1004c, 0x00000001),
+ GATE_CLK(GCC_USB3_SEC_PHY_PIPE_CLK, 0x10054, 0x00000001),
+ GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x10050, 0x00000001),
+ GATE_CLK(GCC_USB_PHY_CFG_AHB2PHY_CLK, 0x6a004, 0x00000001),
+};
+
+static int sdm845_clk_enable(struct clk *clk)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+ debug("%s: clk %s\n", __func__, sdm845_clks[clk->id].name);
+
+ qcom_gate_clk_en(priv, clk->id);
+
+ return 0;
+}
+
+static const struct qcom_reset_map sdm845_gcc_resets[] = {
+ [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
+ [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
+ [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
+ [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
+ [GCC_SDCC2_BCR] = { 0x14000 },
+ [GCC_SDCC4_BCR] = { 0x16000 },
+ [GCC_UFS_CARD_BCR] = { 0x75000 },
+ [GCC_UFS_PHY_BCR] = { 0x77000 },
+ [GCC_USB30_PRIM_BCR] = { 0xf000 },
+ [GCC_USB30_SEC_BCR] = { 0x10000 },
+ [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
+ [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
+ [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
+ [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
+ [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
+ [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
+ [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
+};
+
+static struct msm_clk_data sdm845_clk_data = {
+ .resets = sdm845_gcc_resets,
+ .num_resets = ARRAY_SIZE(sdm845_gcc_resets),
+ .clks = sdm845_clks,
+ .num_clks = ARRAY_SIZE(sdm845_clks),
+
+ .enable = sdm845_clk_enable,
+ .set_rate = sdm845_clk_set_rate,
+};
+
+static const struct udevice_id gcc_sdm845_of_match[] = {
+ {
+ .compatible = "qcom,gcc-sdm845",
+ .data = (ulong)&sdm845_clk_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(gcc_sdm845) = {
+ .name = "gcc_sdm845",
+ .id = UCLASS_NOP,
+ .of_match = gcc_sdm845_of_match,
+ .bind = qcom_cc_bind,
+ .flags = DM_FLAG_PRE_RELOC,
+};
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
+ DEF_GEN3_Z("zg", R8A774A1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
};
static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
+ DEF_MOD("3dge", 112, R8A774A1_CLK_ZG),
DEF_MOD("tmu4", 121, R8A774A1_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A774A1_CLK_S3D2),
DEF_MOD("tmu2", 123, R8A774A1_CLK_S3D2),
DEF_MOD("rpc-if", 917, R8A774A1_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6),
+ DEF_MOD("adg", 922, R8A774A1_CLK_S0D4),
DEF_MOD("iic-pmic", 926, R8A774A1_CLK_CP),
DEF_MOD("i2c4", 927, R8A774A1_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A774A1_CLK_S0D6),
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A774B1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
+ DEF_GEN3_Z("zg", R8A774B1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
DEF_FIXED("ztr", R8A774B1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A774B1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A774B1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
};
static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
+ DEF_MOD("3dge", 112, R8A774B1_CLK_ZG),
DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2),
DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2),
DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6),
+ DEF_MOD("adg", 922, R8A774B1_CLK_S0D4),
DEF_MOD("iic-pmic", 926, R8A774B1_CLK_CP),
DEF_MOD("i2c4", 927, R8A774B1_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A774B1_CLK_S0D6),
DEF_MOD("rpc-if", 917, R8A774C0_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2),
DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2),
+ DEF_MOD("adg", 922, R8A774C0_CLK_ZA2),
DEF_MOD("iic-pmic", 926, R8A774C0_CLK_CP),
DEF_MOD("i2c4", 927, R8A774C0_CLK_S3D2),
DEF_MOD("i2c3", 928, R8A774C0_CLK_S3D2),
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A774E1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
+ DEF_GEN3_Z("zg", R8A774E1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
DEF_FIXED("ztr", R8A774E1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A774E1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A774E1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
};
static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = {
+ DEF_MOD("3dge", 112, R8A774E1_CLK_ZG),
DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1),
DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A774E1_CLK_S0D6),
DEF_MOD("rpc-if", 917, R8A774E1_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774E1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774E1_CLK_S0D6),
- DEF_MOD("adg", 922, R8A774E1_CLK_S0D1),
+ DEF_MOD("adg", 922, R8A774E1_CLK_S0D4),
DEF_MOD("iic-pmic", 926, R8A774E1_CLK_CP),
DEF_MOD("i2c4", 927, R8A774E1_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A774E1_CLK_S0D6),
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
+ DEF_GEN3_Z("zg", R8A7796_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
};
static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
+ DEF_MOD("3dge", 112, R8A7796_CLK_ZG),
DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A7796_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A7796_CLK_S3D2),
DEF_MOD("rpc-if", 917, R8A7796_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
+ DEF_MOD("adg", 922, R8A7796_CLK_S0D4),
DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A7796_CLK_S0D6),
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
+ DEF_GEN3_Z("zg", R8A77965_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
};
static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
+ DEF_MOD("3dge", 112, R8A77965_CLK_ZG),
DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A77965_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A77965_CLK_S3D2),
DEF_MOD("rpc-if", 917, R8A77965_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A77965_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A77965_CLK_S0D6),
+ DEF_MOD("adg", 922, R8A77965_CLK_S0D4),
DEF_MOD("i2c-dvfs", 926, R8A77965_CLK_CP),
DEF_MOD("i2c4", 927, R8A77965_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A77965_CLK_S0D6),
DEF_MOD("rpc-if", 917, R8A77990_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2),
DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2),
+ DEF_MOD("adg", 922, R8A77990_CLK_ZA2),
DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP),
DEF_MOD("i2c4", 927, R8A77990_CLK_S3D2),
DEF_MOD("i2c3", 928, R8A77990_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
DEF_MOD("rpc-if", 917, R8A77995_CLK_RPCD2),
+ DEF_MOD("adg", 922, R8A77995_CLK_ZA2),
DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
CLK_TYPE_GEN3_R,
CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
CLK_TYPE_GEN3_Z,
+ CLK_TYPE_GEN3_ZG,
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
CLK_TYPE_GEN3_RPCSRC,
/* save the hart id */
plat->cpu_id = dev_read_addr(dev);
+ if (IS_ENABLED(CONFIG_64BIT))
+ plat->family = 0x201;
+ else
+ plat->family = 0x200;
/* first examine the property in current cpu node */
ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
/* if not found, then look at the parent /cpus node */
this feature if you are using verified boot, as it will allow an
attacker to bypass any restrictions you have in place.
+config FASTBOOT_CMD_OEM_CONSOLE
+ bool "Enable the 'oem console' command"
+ depends on CONSOLE_RECORD
+ help
+ Add support for the "oem console" command to input and read console
+ record buffer.
+
endif # FASTBOOT
endmenu
#include <common.h>
#include <command.h>
+#include <console.h>
#include <env.h>
#include <fastboot.h>
#include <fastboot-internal.h>
static void oem_format(char *, char *);
static void oem_partconf(char *, char *);
static void oem_bootbus(char *, char *);
+static void oem_console(char *, char *);
static void run_ucmd(char *, char *);
static void run_acmd(char *, char *);
.command = "oem run",
.dispatch = CONFIG_IS_ENABLED(FASTBOOT_OEM_RUN, (run_ucmd), (NULL))
},
+ [FASTBOOT_COMMAND_OEM_CONSOLE] = {
+ .command = "oem console",
+ .dispatch = CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_CONSOLE, (oem_console), (NULL))
+ },
[FASTBOOT_COMMAND_UCMD] = {
.command = "UCmd",
.dispatch = CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT, (run_ucmd), (NULL))
return -1;
}
+void fastboot_multiresponse(int cmd, char *response)
+{
+ switch (cmd) {
+ case FASTBOOT_COMMAND_GETVAR:
+ fastboot_getvar_all(response);
+ break;
+ case FASTBOOT_COMMAND_OEM_CONSOLE:
+ if (CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_CONSOLE)) {
+ char buf[FASTBOOT_RESPONSE_LEN] = { 0 };
+
+ if (console_record_isempty()) {
+ console_record_reset();
+ fastboot_okay(NULL, response);
+ } else {
+ int ret = console_record_readline(buf, sizeof(buf) - 5);
+
+ if (ret < 0)
+ fastboot_fail("Error reading console", response);
+ else
+ fastboot_response("INFO", response, "%s", buf);
+ }
+ break;
+ }
+ default:
+ fastboot_fail("Unknown multiresponse command", response);
+ break;
+ }
+}
+
/**
* okay() - Send bare OKAY response
*
else
fastboot_okay(NULL, response);
}
+
+/**
+ * oem_console() - Execute the OEM console command
+ *
+ * @cmd_parameter: Pointer to command parameter
+ * @response: Pointer to fastboot response buffer
+ */
+static void __maybe_unused oem_console(char *cmd_parameter, char *response)
+{
+ if (cmd_parameter)
+ console_in_puts(cmd_parameter);
+
+ if (console_record_isempty())
+ fastboot_fail("Empty console", response);
+ else
+ fastboot_response(FASTBOOT_MULTIRESPONSE_START, response, NULL);
+}
static const struct {
const char *variable;
+ bool list;
void (*dispatch)(char *var_parameter, char *response);
} getvar_dispatch[] = {
{
.variable = "version",
- .dispatch = getvar_version
+ .dispatch = getvar_version,
+ .list = true,
}, {
.variable = "version-bootloader",
- .dispatch = getvar_version_bootloader
+ .dispatch = getvar_version_bootloader,
+ .list = true
}, {
.variable = "downloadsize",
- .dispatch = getvar_downloadsize
+ .dispatch = getvar_downloadsize,
+ .list = true
}, {
.variable = "max-download-size",
- .dispatch = getvar_downloadsize
+ .dispatch = getvar_downloadsize,
+ .list = true
}, {
.variable = "serialno",
- .dispatch = getvar_serialno
+ .dispatch = getvar_serialno,
+ .list = true
}, {
.variable = "version-baseband",
- .dispatch = getvar_version_baseband
+ .dispatch = getvar_version_baseband,
+ .list = true
}, {
.variable = "product",
- .dispatch = getvar_product
+ .dispatch = getvar_product,
+ .list = true
}, {
.variable = "platform",
- .dispatch = getvar_platform
+ .dispatch = getvar_platform,
+ .list = true
}, {
.variable = "current-slot",
- .dispatch = getvar_current_slot
+ .dispatch = getvar_current_slot,
+ .list = true
#if IS_ENABLED(CONFIG_FASTBOOT_FLASH)
}, {
.variable = "has-slot",
- .dispatch = getvar_has_slot
+ .dispatch = getvar_has_slot,
+ .list = false
#endif
#if IS_ENABLED(CONFIG_FASTBOOT_FLASH_MMC)
}, {
.variable = "partition-type",
- .dispatch = getvar_partition_type
+ .dispatch = getvar_partition_type,
+ .list = false
#endif
#if IS_ENABLED(CONFIG_FASTBOOT_FLASH)
}, {
.variable = "partition-size",
- .dispatch = getvar_partition_size
+ .dispatch = getvar_partition_size,
+ .list = false
#endif
}, {
.variable = "is-userspace",
- .dispatch = getvar_is_userspace
+ .dispatch = getvar_is_userspace,
+ .list = true
}
};
fastboot_okay("no", response);
}
+static int current_all_dispatch;
+void fastboot_getvar_all(char *response)
+{
+ /*
+ * Find a dispatch getvar that can be listed and send
+ * it as INFO until we reach the end.
+ */
+ while (current_all_dispatch < ARRAY_SIZE(getvar_dispatch)) {
+ if (!getvar_dispatch[current_all_dispatch].list) {
+ current_all_dispatch++;
+ continue;
+ }
+
+ char envstr[FASTBOOT_RESPONSE_LEN] = { 0 };
+
+ getvar_dispatch[current_all_dispatch].dispatch(NULL, envstr);
+
+ char *envstr_start = envstr;
+
+ if (!strncmp("OKAY", envstr, 4) || !strncmp("FAIL", envstr, 4))
+ envstr_start += 4;
+
+ fastboot_response("INFO", response, "%s: %s",
+ getvar_dispatch[current_all_dispatch].variable,
+ envstr_start);
+
+ current_all_dispatch++;
+ return;
+ }
+
+ fastboot_response("OKAY", response, NULL);
+ current_all_dispatch = 0;
+}
+
/**
* fastboot_getvar() - Writes variable indicated by cmd_parameter to response.
*
{
if (!cmd_parameter) {
fastboot_fail("missing var", response);
+ } else if (!strncmp("all", cmd_parameter, 3) && strlen(cmd_parameter) == 3) {
+ current_all_dispatch = 0;
+ fastboot_response(FASTBOOT_MULTIRESPONSE_START, response, NULL);
} else {
#define FASTBOOT_ENV_PREFIX "fastboot."
int i;
config QCOM_PMIC_GPIO
bool "Qualcomm generic PMIC GPIO/keypad driver"
depends on DM_GPIO && PMIC_QCOM
+ select BUTTON
help
Support for GPIO pins and power/reset buttons found on
Qualcomm SoCs PMIC.
- Default name for GPIO bank is "pm8916".
- Power and reset buttons are placed in "pwkey_qcom" bank and
- have gpio numbers 0 and 1 respectively.
+ The GPIO bank is called "pmic"
config PCF8575_GPIO
bool "PCF8575 I2C GPIO Expander driver"
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
+#include <mach/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
-/* Register offsets */
-#define GPIO_CONFIG_OFF(no) ((no) * 0x1000)
-#define GPIO_IN_OUT_OFF(no) ((no) * 0x1000 + 0x4)
-
/* OE */
#define GPIO_OE_DISABLE (0x0 << 9)
#define GPIO_OE_ENABLE (0x1 << 9)
struct msm_gpio_bank {
phys_addr_t base;
+ const struct msm_pin_data *pin_data;
};
+#define GPIO_CONFIG_REG(dev, x) \
+ (qcom_pin_offset(((struct msm_gpio_bank *)dev_get_priv(dev))->pin_data->pin_offsets, x))
+
+#define GPIO_IN_OUT_REG(dev, x) \
+ (GPIO_CONFIG_REG(dev, x) + 0x4)
+
static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
- phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
/* Disable OE bit */
- clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_DISABLE);
+ clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio),
+ GPIO_OE_MASK, GPIO_OE_DISABLE);
return 0;
}
-static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
+static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
value = !!value;
/* set value */
- writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
+ writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
return 0;
}
-static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio,
+static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio,
int value)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
- phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
value = !!value;
/* set value */
- writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
+ writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
/* switch direction */
- clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_ENABLE);
+ clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio),
+ GPIO_OE_MASK, GPIO_OE_ENABLE);
return 0;
}
-static int msm_gpio_get_value(struct udevice *dev, unsigned gpio)
+static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
- return !!(readl(priv->base + GPIO_IN_OUT_OFF(gpio)) >> GPIO_IN);
+ return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN);
}
-static int msm_gpio_get_function(struct udevice *dev, unsigned offset)
+static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
- if (readl(priv->base + GPIO_CONFIG_OFF(offset)) & GPIO_OE_ENABLE)
+ if (readl(priv->base + GPIO_CONFIG_REG(dev, gpio)) & GPIO_OE_ENABLE)
return GPIOF_OUTPUT;
return GPIOF_INPUT;
struct msm_gpio_bank *priv = dev_get_priv(dev);
priv->base = dev_read_addr(dev);
+ priv->pin_data = (struct msm_pin_data *)dev_get_driver_data(dev);
return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
}
static int msm_gpio_of_to_plat(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ const struct msm_pin_data *pin_data = (struct msm_pin_data *)dev_get_driver_data(dev);
- uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "gpio-count", 0);
+ /* Get the pin count from the pinctrl driver */
+ uc_priv->gpio_count = pin_data->pin_count;
uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"gpio-bank-name", NULL);
if (uc_priv->bank_name == NULL)
{
struct qcom_gpio_bank *priv = dev_get_priv(dev);
int reg;
+ u64 pid;
- priv->pid = dev_read_addr(dev);
- if (priv->pid == FDT_ADDR_T_NONE)
+ pid = dev_read_addr(dev);
+ if (pid == FDT_ADDR_T_NONE)
return log_msg_ret("bad address", -EINVAL);
+ priv->pid = pid;
+
/* Do a sanity check */
reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE);
if (reg != REG_TYPE_VAL)
return 0;
}
+/*
+ * Parse basic GPIO count specified via the gpio-ranges property
+ * as specified in Linux devicetrees
+ * Returns < 0 on error, otherwise gpio count
+ */
+static int qcom_gpio_of_parse_ranges(struct udevice *dev)
+{
+ int ret;
+ struct ofnode_phandle_args args;
+
+ ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "gpio-ranges",
+ NULL, 3, 0, &args);
+ if (ret)
+ return log_msg_ret("gpio-ranges", ret);
+
+ return args.args[2];
+}
+
static int qcom_gpio_of_to_plat(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ int ret;
+
+ ret = qcom_gpio_of_parse_ranges(dev);
+ if (ret > 0)
+ uc_priv->gpio_count = ret;
+ else
+ return ret;
- uc_priv->gpio_count = dev_read_u32_default(dev, "gpio-count", 0);
- uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
- if (uc_priv->bank_name == NULL)
- uc_priv->bank_name = "qcom_pmic";
+ uc_priv->bank_name = "pmic";
return 0;
}
.priv_auto = sizeof(struct qcom_gpio_bank),
};
-
-/* Add pmic buttons as GPIO as well - there is no generic way for now */
-#define PON_INT_RT_STS 0x10
-#define KPDPWR_ON_INT_BIT 0
-#define RESIN_ON_INT_BIT 1
-
-static int qcom_pwrkey_get_function(struct udevice *dev, unsigned offset)
-{
- return GPIOF_INPUT;
-}
-
-static int qcom_pwrkey_get_value(struct udevice *dev, unsigned offset)
-{
- struct qcom_gpio_bank *priv = dev_get_priv(dev);
-
- int reg = pmic_reg_read(dev->parent, priv->pid + PON_INT_RT_STS);
-
- if (reg < 0)
- return 0;
-
- switch (offset) {
- case 0: /* Power button */
- return (reg & BIT(KPDPWR_ON_INT_BIT)) != 0;
- break;
- case 1: /* Reset button */
- default:
- return (reg & BIT(RESIN_ON_INT_BIT)) != 0;
- break;
- }
-}
-
-/*
- * Since pmic buttons modelled as GPIO, we need empty direction functions
- * to trick u-boot button driver
- */
-static int qcom_pwrkey_direction_input(struct udevice *dev, unsigned int offset)
-{
- return 0;
-}
-
-static int qcom_pwrkey_direction_output(struct udevice *dev, unsigned int offset, int value)
-{
- return -EOPNOTSUPP;
-}
-
-static const struct dm_gpio_ops qcom_pwrkey_ops = {
- .get_value = qcom_pwrkey_get_value,
- .get_function = qcom_pwrkey_get_function,
- .direction_input = qcom_pwrkey_direction_input,
- .direction_output = qcom_pwrkey_direction_output,
-};
-
-static int qcom_pwrkey_probe(struct udevice *dev)
-{
- struct qcom_gpio_bank *priv = dev_get_priv(dev);
- int reg;
-
- priv->pid = dev_read_addr(dev);
- if (priv->pid == FDT_ADDR_T_NONE)
- return log_msg_ret("bad address", -EINVAL);
-
- /* Do a sanity check */
- reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE);
- if (reg != 0x1)
- return log_msg_ret("bad type", -ENXIO);
-
- reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
- if ((reg & 0x5) == 0)
- return log_msg_ret("bad subtype", -ENXIO);
-
- return 0;
-}
-
-static int qcom_pwrkey_of_to_plat(struct udevice *dev)
-{
- struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-
- uc_priv->gpio_count = 2;
- uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
- if (uc_priv->bank_name == NULL)
- uc_priv->bank_name = "pwkey_qcom";
-
- return 0;
-}
-
-static const struct udevice_id qcom_pwrkey_ids[] = {
- { .compatible = "qcom,pm8916-pwrkey" },
- { .compatible = "qcom,pm8994-pwrkey" },
- { .compatible = "qcom,pm8998-pwrkey" },
- { }
-};
-
-U_BOOT_DRIVER(pwrkey_qcom) = {
- .name = "pwrkey_qcom",
- .id = UCLASS_GPIO,
- .of_match = qcom_pwrkey_ids,
- .of_to_plat = qcom_pwrkey_of_to_plat,
- .probe = qcom_pwrkey_probe,
- .ops = &qcom_pwrkey_ops,
- .priv_auto = sizeof(struct qcom_gpio_bank),
-};
*/
#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
#include <clk.h>
#include <common.h>
#include <dm.h>
#include <linux/mtd/omap_gpmc.h>
#include <linux/ioport.h>
#include <linux/io.h>
+#include <linux/sizes.h>
#include "ti-gpmc.h"
enum gpmc_clk_domain {
legacy UART or other devices in the Winbond Super IO chips
on X86 platforms.
-config QCOM_GENI_SE
- bool "Qualcomm GENI Serial Engine Driver"
- depends on ARCH_SNAPDRAGON
- help
- The driver manages Generic Interface (GENI) firmware based
- Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper.
-
config QFW
bool
help
Hidden option to enable MMIO QEMU fw_cfg interface. This will be
selected by the appropriate QEMU board.
+config QFW_SMBIOS
+ bool
+ default y
+ depends on QFW && SMBIOS && !SANDBOX
+ help
+ Hidden option to read SMBIOS tables from QEMU.
+
config I2C_EEPROM
bool "Enable driver for generic I2C-attached EEPROMs"
depends on MISC
obj-$(CONFIG_P2SB) += p2sb-uclass.o
obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
-obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
ifdef CONFIG_QFW
obj-y += qfw.o
obj-$(CONFIG_QFW_ACPI) += qfw_acpi.o
obj-$(CONFIG_QFW_PIO) += qfw_pio.o
obj-$(CONFIG_QFW_MMIO) += qfw_mmio.o
+obj-$(CONFIG_QFW_SMBIOS) += qfw_smbios.o
obj-$(CONFIG_SANDBOX) += qfw_sandbox.o
endif
obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm Generic Interface (GENI) Serial Engine (SE) Wrapper
- *
- * Copyright (C) 2023 Linaro Ltd. <vladimir.zapolskiy@linaro.org>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <misc.h>
-#include <asm/io.h>
-
-static int geni_se_qup_read(struct udevice *dev, int offset,
- void *buf, int size)
-{
- fdt_addr_t base = dev_read_addr(dev);
-
- if (size != sizeof(u32))
- return -EINVAL;
-
- *(u32 *)buf = readl(base + offset);
-
- return size;
-}
-
-static struct misc_ops geni_se_qup_ops = {
- .read = geni_se_qup_read,
-};
-
-static const struct udevice_id geni_se_qup_ids[] = {
- { .compatible = "qcom,geni-se-qup" },
- {}
-};
-
-U_BOOT_DRIVER(geni_se_qup) = {
- .name = "geni_se_qup",
- .id = UCLASS_MISC,
- .of_match = geni_se_qup_ids,
- .ops = &geni_se_qup_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2023 Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+ */
+
+#define LOG_CATEGORY UCLASS_QFW
+
+#include <efi_loader.h>
+#include <errno.h>
+#include <log.h>
+#include <malloc.h>
+#include <mapmem.h>
+#include <qfw.h>
+#include <smbios.h>
+#include <tables_csum.h>
+#include <linux/sizes.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * qfw_load_smbios_table() - load a QEMU firmware file
+ *
+ * @dev: QEMU firmware device
+ * @size: parameter to return the size of the loaded table
+ * @name: name of the table to load
+ * Return: address of the loaded table, NULL on error
+ */
+static void *qfw_load_smbios_table(struct udevice *dev, uint32_t *size,
+ char *name)
+{
+ struct fw_file *file;
+ struct bios_linker_entry *table;
+
+ file = qfw_find_file(dev, name);
+ if (!file) {
+ log_debug("Can't find %s\n", name);
+ return NULL;
+ }
+
+ *size = be32_to_cpu(file->cfg.size);
+
+ table = malloc(*size);
+ if (!table) {
+ log_err("Out of memory\n");
+ return NULL;
+ }
+
+ qfw_read_entry(dev, be16_to_cpu(file->cfg.select), *size, table);
+
+ return table;
+}
+
+/**
+ * qfw_parse_smbios_anchor() - parse QEMU's SMBIOS anchor
+ *
+ * @dev: QEMU firmware device
+ * @entry: SMBIOS 3 structure to be filled from QEMU's anchor
+ * Return: 0 for success, -ve on error
+ */
+static int qfw_parse_smbios_anchor(struct udevice *dev,
+ struct smbios3_entry *entry)
+{
+ void *table;
+ uint32_t size;
+ struct smbios_entry *entry2;
+ struct smbios3_entry *entry3;
+ const char smbios_sig[] = "_SM_";
+ const char smbios3_sig[] = "_SM3_";
+ int ret = 0;
+
+ table = qfw_load_smbios_table(dev, &size, "etc/smbios/smbios-anchor");
+ if (!table)
+ return -ENOMEM;
+ if (!memcmp(table, smbios3_sig, sizeof(smbios3_sig) - 1)) {
+ entry3 = table;
+ if (entry3->length != sizeof(struct smbios3_entry)) {
+ ret = -ENOENT;
+ goto out;
+ }
+ memcpy(entry, entry3, sizeof(struct smbios3_entry));
+ } else if (!memcmp(table, smbios_sig, sizeof(smbios_sig) - 1)) {
+ entry2 = table;
+ if (entry2->length != sizeof(struct smbios_entry)) {
+ ret = -ENOENT;
+ goto out;
+ }
+ memset(entry, 0, sizeof(struct smbios3_entry));
+ memcpy(entry, smbios3_sig, sizeof(smbios3_sig));
+ entry->length = sizeof(struct smbios3_entry);
+ entry->major_ver = entry2->major_ver;
+ entry->minor_ver = entry2->minor_ver;
+ entry->max_struct_size = entry2->max_struct_size;
+ } else {
+ ret = -ENOENT;
+ goto out;
+ }
+ ret = 0;
+out:
+ free(table);
+
+ return ret;
+}
+
+/**
+ * qfw_write_smbios_tables() - copy SMBIOS tables from QEMU
+ *
+ * @addr: target buffer
+ * @size: size of target buffer
+ * Return: 0 for success, -ve on error
+ */
+static int qfw_write_smbios_tables(u8 *addr, uint32_t size)
+{
+ int ret;
+ struct udevice *dev;
+ struct smbios3_entry *entry = (void *)addr;
+ void *table;
+ uint32_t table_size;
+
+ ret = qfw_get_dev(&dev);
+ if (ret) {
+ log_err("No QEMU firmware device\n");
+ return ret;
+ }
+
+ ret = qfw_read_firmware_list(dev);
+ if (ret) {
+ log_err("Can't read firmware file list\n");
+ return ret;
+ }
+
+ ret = qfw_parse_smbios_anchor(dev, entry);
+ if (ret) {
+ log_debug("Can't parse anchor\n");
+ return ret;
+ }
+
+ addr += entry->length;
+ entry->struct_table_address = (uintptr_t)addr;
+ entry->checksum = 0;
+ entry->checksum = table_compute_checksum(entry,
+ sizeof(struct smbios3_entry));
+
+ table = qfw_load_smbios_table(dev, &table_size,
+ "etc/smbios/smbios-tables");
+ if (table_size + sizeof(struct smbios3_entry) > size) {
+ free(table);
+ return -ENOMEM;
+ }
+ memcpy(addr, table, table_size);
+ free(table);
+
+ return 0;
+}
+
+/**
+ * qfw_evt_write_smbios_tables() - event handler for copying QEMU SMBIOS tables
+ *
+ * Return: 0 on success, -ve on error (only out of memory)
+ */
+static int qfw_evt_write_smbios_tables(void)
+{
+ phys_addr_t addr;
+ void *ptr;
+ int ret;
+ /*
+ * TODO:
+ * This size is currently hard coded in lib/efi_loader/efi_smbios.c.
+ * We need a field in global data for the size.
+ */
+ uint32_t size = SZ_4K;
+
+ /* Reserve 64K for SMBIOS tables, aligned to a 4K boundary */
+ ptr = memalign(SZ_4K, size);
+ if (!ptr) {
+ log_err("Out of memory\n");
+ return -ENOMEM;
+ }
+ addr = map_to_sysmem(ptr);
+
+ /* Generate SMBIOS tables */
+ ret = qfw_write_smbios_tables(ptr, size);
+ if (ret) {
+ if (CONFIG_IS_ENABLED(GENERATE_SMBIOS_TABLE)) {
+ log_info("Falling back to U-Boot generated SMBIOS tables\n");
+ write_smbios_table(addr);
+ }
+ } else {
+ log_debug("SMBIOS tables copied from QEMU\n");
+ }
+
+ gd_set_smbios_start(addr);
+
+ return 0;
+}
+
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, qfw_evt_write_smbios_tables);
{
int i;
+ if (!mtd)
+ return -ENODEV;
+
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) {
- if (mtd && get_nand_dev_by_index(i) == mtd)
+ if (get_nand_dev_by_index(i) == mtd)
return i;
}
/* Register an initialized NAND mtd device with the U-Boot NAND command. */
int nand_register(int devnum, struct mtd_info *mtd)
{
- if (devnum >= CONFIG_SYS_MAX_NAND_DEVICE)
+ if (!mtd || devnum >= CONFIG_SYS_MAX_NAND_DEVICE)
return -EINVAL;
nand_info[devnum] = mtd;
;
}
-#ifdef ELM_BASE
/**
* elm_init - Initialize ELM module
*
*/
void elm_init(void)
{
+#ifdef ELM_BASE
elm_cfg = (struct elm *)ELM_BASE;
elm_reset();
-}
#endif
+}
#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
u32 *error_locations);
int elm_config(enum bch_level level);
void elm_reset(void);
-#ifdef ELM_BASE
void elm_init(void);
-#else
-static inline void elm_init(void)
-{
-}
-#endif
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_ELM_H */
#include <log.h>
#include <system-constants.h>
#include <asm/io.h>
-#include <dm/uclass.h>
+#include <dm.h>
#include <linux/errno.h>
#ifdef CONFIG_ARCH_OMAP2PLUS
#include <asm/arch/mem.h>
#endif
+#include <linux/io.h>
+#include <linux/ioport.h>
#include <linux/mtd/omap_gpmc.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/rawnand.h>
break;
case OMAP_ECC_BCH8_CODE_HW:
bch_type = 1;
- nsectors = chip->ecc.steps;
+ nsectors = 1;
if (mode == NAND_ECC_READ) {
wr_mode = BCH_WRAPMODE_1;
ecc_size0 = BCH8R_ECC_SIZE0;
break;
case OMAP_ECC_BCH16_CODE_HW:
bch_type = 0x2;
- nsectors = chip->ecc.steps;
+ nsectors = 1;
if (mode == NAND_ECC_READ) {
wr_mode = 0x01;
ecc_size0 = 52; /* ECC bits in nibbles per sector */
}
/**
- * _omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
+ * omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
* @mtd: MTD device structure
* @dat: The pointer to data on which ecc is computed
* @ecc_code: The ecc_code buffer
- * @sector: The sector number (for a multi sector page)
*
* Support calculating of BCH4/8/16 ECC vectors for one sector
* within a page. Sector number is in @sector.
*/
-static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
- u8 *ecc_code, int sector)
+static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
+ u8 *ecc_code)
{
struct nand_chip *chip = mtd_to_nand(mtd);
struct omap_nand_info *info = nand_get_controller_data(chip);
case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
#endif
case OMAP_ECC_BCH8_CODE_HW:
- ptr = &gpmc_cfg->bch_result_0_3[sector].bch_result_x[3];
+ ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
val = readl(ptr);
ecc_code[i++] = (val >> 0) & 0xFF;
ptr--;
break;
case OMAP_ECC_BCH16_CODE_HW:
- val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[2]);
+ val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]);
ecc_code[i++] = (val >> 8) & 0xFF;
ecc_code[i++] = (val >> 0) & 0xFF;
- val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[1]);
+ val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]);
ecc_code[i++] = (val >> 24) & 0xFF;
ecc_code[i++] = (val >> 16) & 0xFF;
ecc_code[i++] = (val >> 8) & 0xFF;
ecc_code[i++] = (val >> 0) & 0xFF;
- val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[0]);
+ val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]);
ecc_code[i++] = (val >> 24) & 0xFF;
ecc_code[i++] = (val >> 16) & 0xFF;
ecc_code[i++] = (val >> 8) & 0xFF;
ecc_code[i++] = (val >> 0) & 0xFF;
for (j = 3; j >= 0; j--) {
- val = readl(&gpmc_cfg->bch_result_0_3[sector].bch_result_x[j]
+ val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j]
);
ecc_code[i++] = (val >> 24) & 0xFF;
ecc_code[i++] = (val >> 16) & 0xFF;
return 0;
}
-/**
- * omap_calculate_ecc_bch - ECC generator for 1 sector
- * @mtd: MTD device structure
- * @dat: The pointer to data on which ecc is computed
- * @ecc_code: The ecc_code buffer
- *
- * Support calculating of BCH4/8/16 ECC vectors for one sector. This is used
- * when SW based correction is required as ECC is required for one sector
- * at a time.
- */
-static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd,
- const u_char *dat, u_char *ecc_calc)
-{
- return _omap_calculate_ecc_bch(mtd, dat, ecc_calc, 0);
-}
-
static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
struct nand_chip *chip = mtd_to_nand(mtd);
#ifdef CONFIG_NAND_OMAP_ELM
-/**
- * omap_calculate_ecc_bch_multi - Generate ECC for multiple sectors
- * @mtd: MTD device structure
- * @dat: The pointer to data on which ecc is computed
- * @ecc_code: The ecc_code buffer
- *
- * Support calculating of BCH4/8/16 ecc vectors for the entire page in one go.
- */
-static int omap_calculate_ecc_bch_multi(struct mtd_info *mtd,
- const u_char *dat, u_char *ecc_calc)
-{
- struct nand_chip *chip = mtd_to_nand(mtd);
- int eccbytes = chip->ecc.bytes;
- unsigned long nsectors;
- int i, ret;
-
- nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1;
- for (i = 0; i < nsectors; i++) {
- ret = _omap_calculate_ecc_bch(mtd, dat, ecc_calc, i);
- if (ret)
- return ret;
-
- ecc_calc += eccbytes;
- }
-
- return 0;
-}
-
/*
* omap_reverse_list - re-orders list elements in reverse order [internal]
* @list: pointer to start of list
{
int i, eccsize = chip->ecc.size;
int eccbytes = chip->ecc.bytes;
- int ecctotal = chip->ecc.total;
int eccsteps = chip->ecc.steps;
uint8_t *p = buf;
uint8_t *ecc_calc = chip->buffers->ecccalc;
uint32_t *eccpos = chip->ecc.layout->eccpos;
uint8_t *oob = chip->oob_poi;
uint32_t oob_pos;
+ u32 data_pos = 0;
/* oob area start */
oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
oob += chip->ecc.layout->eccpos[0];
- /* Enable ECC engine */
- chip->ecc.hwctl(mtd, NAND_ECC_READ);
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
+ oob += eccbytes) {
+ /* Enable ECC engine */
+ chip->ecc.hwctl(mtd, NAND_ECC_READ);
- /* read entire page */
- chip->cmdfunc(mtd, NAND_CMD_RNDOUT, 0, -1);
- chip->read_buf(mtd, buf, mtd->writesize);
+ /* read data */
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1);
+ chip->read_buf(mtd, p, eccsize);
- /* read all ecc bytes from oob area */
- chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
- chip->read_buf(mtd, oob, ecctotal);
+ /* read respective ecc from oob area */
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
+ chip->read_buf(mtd, oob, eccbytes);
+ /* read syndrome */
+ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
- /* Calculate ecc bytes */
- omap_calculate_ecc_bch_multi(mtd, buf, ecc_calc);
+ data_pos += eccsize;
+ oob_pos += eccbytes;
+ }
for (i = 0; i < chip->ecc.total; i++)
ecc_code[i] = chip->oob_poi[eccpos[i]];
nand->ecc.hwctl = omap_enable_hwecc_bch;
nand->ecc.correct = omap_correct_data_bch_sw;
nand->ecc.calculate = omap_calculate_ecc_bch;
+ nand->ecc.steps = eccsteps;
/* define ecc-layout */
ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH;
nand->ecc.correct = omap_correct_data_bch;
nand->ecc.calculate = omap_calculate_ecc_bch;
nand->ecc.read_page = omap_read_page_bch;
+ nand->ecc.steps = eccsteps;
/* define ecc-layout */
ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
for (i = 0; i < ecclayout->eccbytes; i++)
nand->ecc.correct = omap_correct_data_bch;
nand->ecc.calculate = omap_calculate_ecc_bch;
nand->ecc.read_page = omap_read_page_bch;
+ nand->ecc.steps = eccsteps;
/* define ecc-layout */
ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
for (i = 0; i < ecclayout->eccbytes; i++)
* nand_scan about special functionality. See the defines for further
* explanation
*/
-int gpmc_nand_init(struct nand_chip *nand)
+int gpmc_nand_init(struct nand_chip *nand, void __iomem *nand_base)
{
int32_t gpmc_config = 0;
int cs = cs_next++;
info->control = NULL;
info->cs = cs;
info->ws = wscfg[cs];
- info->fifo = (void __iomem *)CFG_SYS_NAND_BASE;
+ info->fifo = nand_base;
nand_set_controller_data(nand, &omap_nand_info[cs]);
nand->cmd_ctrl = omap_nand_hwcontrol;
nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
{
struct nand_chip *nand = dev_get_priv(dev);
struct mtd_info *mtd = nand_to_mtd(nand);
+ struct resource res;
+ void __iomem *base;
int ret;
- gpmc_nand_init(nand);
+ ret = dev_read_resource(dev, 0, &res);
+ if (ret)
+ return ret;
+
+ base = devm_ioremap(dev, res.start, resource_size(&res));
+ gpmc_nand_init(nand, base);
+ mtd->dev = dev;
+ nand_set_flash_node(nand, dev_ofnode(dev));
ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);
if (ret)
int board_nand_init(struct nand_chip *nand)
{
- return gpmc_nand_init(nand);
+ return gpmc_nand_init(nand, (void __iomem *)CFG_SYS_NAND_BASE);
}
#endif /* CONFIG_SYS_NAND_SELF_INIT */
RTL_STS_RXBADALIGN)) ||
(rx_size < ETH_ZLEN) ||
(rx_size > ETH_FRAME_LEN + 4)) {
- printf("rx error %hX\n", rx_status);
+ debug("rx error %hX\n", rx_status);
/* this clears all interrupts still pending */
rtl8139_reset(priv);
return 0;
ret = smc911x_send_common(priv, packet, length);
- return ret ? 0 : -ETIMEDOUT;
+ return ret ? -ETIMEDOUT : 0;
}
static int smc911x_recv(struct udevice *dev, int flags, uchar **packetp)
#define PA0_USB20_PLL_PREDIV GENMASK(7, 6)
#define PA0_RG_USB20_INTR_EN BIT(5)
+#define U3P_USBPHYACR1 0x004
+#define PA1_RG_INTR_CAL GENMASK(23, 19)
+#define PA1_RG_VRT_SEL GENMASK(14, 12)
+#define PA1_RG_TERM_SEL GENMASK(10, 8)
+
#define U3P_USBPHYACR2 0x008
#define PA2_RG_U2PLL_BW GENMASK(21, 19)
#define PA5_RG_U2_HS_100U_U3_EN BIT(11)
#define U3P_USBPHYACR6 0x018
+#define PA6_RG_U2_PRE_EMP GENMASK(31, 30)
#define PA6_RG_U2_BC11_SW_EN BIT(23)
#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
+#define PA6_RG_U2_DISCTH GENMASK(7, 4)
#define PA6_RG_U2_SQTH GENMASK(3, 0)
#define U3P_U2PHYACR4 0x020
struct mtk_phy_instance {
void __iomem *port_base;
- const struct device_node *np;
+ struct device_node *np;
union {
struct u2phy_banks u2_banks;
struct u3phy_banks u3_banks;
struct clk da_ref_clk; /* reference clock of analog phy */
u32 index;
u32 type;
+
+ u32 eye_vrt;
+ u32 eye_term;
+ u32 discth;
+ u32 pre_emphasis;
};
struct mtk_tphy {
}
}
+static void phy_parse_property(struct mtk_tphy *tphy,
+ struct mtk_phy_instance *instance)
+{
+ ofnode node = np_to_ofnode(instance->np);
+
+ if (instance->type != PHY_TYPE_USB2)
+ return;
+
+ ofnode_read_u32(node, "mediatek,eye-vrt", &instance->eye_vrt);
+ ofnode_read_u32(node, "mediatek,eye-term", &instance->eye_term);
+ ofnode_read_u32(node, "mediatek,discth", &instance->discth);
+ ofnode_read_u32(node, "mediatek,pre-emphasis", &instance->pre_emphasis);
+
+ dev_dbg(tphy->dev, "vrt:%d, term:%d, disc:%d, emp:%d\n",
+ instance->eye_vrt, instance->eye_term,
+ instance->discth, instance->pre_emphasis);
+}
+
+static void u2_phy_props_set(struct mtk_tphy *tphy,
+ struct mtk_phy_instance *instance)
+{
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ void __iomem *com = u2_banks->com;
+
+ if (instance->eye_vrt)
+ clrsetbits_le32(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL,
+ FIELD_PREP(PA1_RG_VRT_SEL, instance->eye_vrt));
+
+ if (instance->eye_term)
+ clrsetbits_le32(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL,
+ FIELD_PREP(PA1_RG_TERM_SEL, instance->eye_term));
+
+ if (instance->discth)
+ clrsetbits_le32(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH,
+ FIELD_PREP(PA6_RG_U2_DISCTH, instance->discth));
+
+ if (instance->pre_emphasis)
+ clrsetbits_le32(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP,
+ FIELD_PREP(PA6_RG_U2_PRE_EMP, instance->pre_emphasis));
+}
+
static int mtk_phy_init(struct phy *phy)
{
struct mtk_tphy *tphy = dev_get_priv(phy->dev);
switch (instance->type) {
case PHY_TYPE_USB2:
u2_phy_instance_init(tphy, instance);
+ u2_phy_props_set(tphy, instance);
break;
case PHY_TYPE_USB3:
u3_phy_instance_init(tphy, instance);
return -EINVAL;
}
+ phy_parse_property(tphy, instance);
+
return 0;
}
source "drivers/pinctrl/nexell/Kconfig"
source "drivers/pinctrl/nuvoton/Kconfig"
source "drivers/pinctrl/nxp/Kconfig"
+source "drivers/pinctrl/qcom/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/rockchip/Kconfig"
source "drivers/pinctrl/sunxi/Kconfig"
obj-$(CONFIG_PINCTRL_INTEL) += intel/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
obj-$(CONFIG_ARCH_NPCM) += nuvoton/
+obj-$(CONFIG_PINCTRL_QCOM) += qcom/
obj-$(CONFIG_ARCH_RMOBILE) += renesas/
obj-$(CONFIG_ARCH_RZN1) += renesas/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <asm/global_data.h>
#include <asm/io.h>
#include "pinctrl-exynos.h"
-DECLARE_GLOBAL_DATA_PTR;
+/* CON, DAT, PUD, DRV */
+const struct samsung_pin_bank_type bank_type_alive = {
+ .fld_width = { 4, 1, 2, 2, },
+ .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
+};
+
+static const char * const exynos_pinctrl_props[PINCFG_TYPE_NUM] = {
+ [PINCFG_TYPE_FUNC] = "samsung,pin-function",
+ [PINCFG_TYPE_DAT] = "samsung,pin-val",
+ [PINCFG_TYPE_PUD] = "samsung,pin-pud",
+ [PINCFG_TYPE_DRV] = "samsung,pin-drv",
+};
/**
* exynos_pinctrl_setup_peri: setup pinctrl for a peripheral.
}
}
-/* given a pin-name, return the address of pin config registers */
-static unsigned long pin_to_bank_base(struct udevice *dev, const char *pin_name,
- u32 *pin)
+static void parse_pin(const char *pin_name, u32 *pin, char *bank_name)
{
- struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
- const struct samsung_pin_ctrl *pin_ctrl_array = priv->pin_ctrl;
- const struct samsung_pin_bank_data *bank_data;
- u32 nr_banks, pin_ctrl_idx = 0, idx = 0, bank_base;
- char bank[10];
+ u32 idx = 0;
/*
- * The format of the pin name is <bank name>-<pin_number>.
- * Example: gpa0-4 (gpa0 is the bank name and 4 is the pin number.
+ * The format of the pin name is <bank
_name name>-<pin_number>.
+ * Example: gpa0-4 (gpa0 is the bank_name name and 4 is the pin number.
*/
while (pin_name[idx] != '-') {
- bank[idx] = pin_name[idx];
+ bank_name[idx] = pin_name[idx];
idx++;
}
- bank[idx] = '\0';
+ bank_name[idx] = '\0';
*pin = pin_name[++idx] - '0';
+}
+
+/* given a bank name, find out the pin bank structure */
+static const struct samsung_pin_bank_data *get_bank(struct udevice *dev,
+ const char *bank_name)
+{
+ struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
+ const struct samsung_pin_ctrl *pin_ctrl_array = priv->pin_ctrl;
+ const struct samsung_pin_bank_data *bank_data;
+ u32 nr_banks, pin_ctrl_idx = 0, idx = 0;
/* lookup the pin bank data using the pin bank name */
while (true) {
- const struct samsung_pin_ctrl *pin_ctrl = &pin_ctrl_array[pin_ctrl_idx];
+ const struct samsung_pin_ctrl *pin_ctrl =
+ &pin_ctrl_array[pin_ctrl_idx];
nr_banks = pin_ctrl->nr_banks;
if (!nr_banks)
for (idx = 0; idx < nr_banks; idx++) {
debug("pinctrl[%d] bank_data[%d] name is: %s\n",
pin_ctrl_idx, idx, bank_data[idx].name);
- if (!strcmp(bank, bank_data[idx].name)) {
- bank_base = priv->base + bank_data[idx].offset;
- break;
- }
+ if (!strcmp(bank_name, bank_data[idx].name))
+ return &bank_data[idx];
}
pin_ctrl_idx++;
}
- return bank_base;
+ return NULL;
+}
+
+static void exynos_pinctrl_set_pincfg(unsigned long reg_base, u32 pin_num,
+ u32 val, enum pincfg_type pincfg,
+ const struct samsung_pin_bank_type *type)
+{
+ u32 width = type->fld_width[pincfg];
+ u32 reg_offset = type->reg_offset[pincfg];
+ u32 mask = (1 << width) - 1;
+ u32 shift = pin_num * width;
+ u32 data;
+
+ data = readl(reg_base + reg_offset);
+ data &= ~(mask << shift);
+ data |= val << shift;
+ writel(data, reg_base + reg_offset);
}
/**
*/
int exynos_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
- const void *fdt = gd->fdt_blob;
- int node = dev_of_offset(config);
- unsigned int count, idx, pin_num;
- unsigned int pinfunc, pinpud, pindrv;
- unsigned long reg, value;
- const char *name;
+ struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
+ unsigned int count, idx;
+ unsigned int pinvals[PINCFG_TYPE_NUM];
/*
* refer to the following document for the pinctrl bindings
* linux/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
*/
- count = fdt_stringlist_count(fdt, node, "samsung,pins");
+ count = dev_read_string_count(config, "samsung,pins");
if (count <= 0)
return -EINVAL;
- pinfunc = fdtdec_get_int(fdt, node, "samsung,pin-function", -1);
- pinpud = fdtdec_get_int(fdt, node, "samsung,pin-pud", -1);
- pindrv = fdtdec_get_int(fdt, node, "samsung,pin-drv", -1);
+ for (idx = 0; idx < PINCFG_TYPE_NUM; ++idx) {
+ pinvals[idx] = dev_read_u32_default(config,
+ exynos_pinctrl_props[idx], -1);
+ }
+ pinvals[PINCFG_TYPE_DAT] = -1; /* ignore GPIO data register */
for (idx = 0; idx < count; idx++) {
- name = fdt_stringlist_get(fdt, node, "samsung,pins", idx, NULL);
- if (!name)
+ const struct samsung_pin_bank_data *bank;
+ unsigned int pin_num;
+ char bank_name[10];
+ unsigned long reg;
+ const char *name = NULL;
+ int pincfg, err;
+
+ err = dev_read_string_index(config, "samsung,pins", idx, &name);
+ if (err || !name)
continue;
- reg = pin_to_bank_base(dev, name, &pin_num);
- if (pinfunc != -1) {
- value = readl(reg + PIN_CON);
- value &= ~(0xf << (pin_num << 2));
- value |= (pinfunc << (pin_num << 2));
- writel(value, reg + PIN_CON);
- }
+ parse_pin(name, &pin_num, bank_name);
+ bank = get_bank(dev, bank_name);
+ reg = priv->base + bank->offset;
- if (pinpud != -1) {
- value = readl(reg + PIN_PUD);
- value &= ~(0x3 << (pin_num << 1));
- value |= (pinpud << (pin_num << 1));
- writel(value, reg + PIN_PUD);
- }
+ for (pincfg = 0; pincfg < PINCFG_TYPE_NUM; ++pincfg) {
+ unsigned int val = pinvals[pincfg];
- if (pindrv != -1) {
- value = readl(reg + PIN_DRV);
- value &= ~(0x3 << (pin_num << 1));
- value |= (pindrv << (pin_num << 1));
- writel(value, reg + PIN_DRV);
+ if (val != -1)
+ exynos_pinctrl_set_pincfg(reg, pin_num, val,
+ pincfg, bank->type);
}
}
#ifndef __PINCTRL_EXYNOS_H_
#define __PINCTRL_EXYNOS_H_
-#define PIN_CON 0x00 /* Offset of pin function register */
-#define PIN_DAT 0x04 /* Offset of pin data register */
-#define PIN_PUD 0x08 /* Offset of pin pull up/down config register */
-#define PIN_DRV 0x0C /* Offset of pin drive strength register */
+/**
+ * enum pincfg_type - possible pin configuration types supported.
+ * @PINCFG_TYPE_FUNC: Function configuration.
+ * @PINCFG_TYPE_DAT: Pin value configuration.
+ * @PINCFG_TYPE_PUD: Pull up/down configuration.
+ * @PINCFG_TYPE_DRV: Drive strength configuration.
+ */
+enum pincfg_type {
+ PINCFG_TYPE_FUNC,
+ PINCFG_TYPE_DAT,
+ PINCFG_TYPE_PUD,
+ PINCFG_TYPE_DRV,
+
+ PINCFG_TYPE_NUM
+};
+
+/**
+ * struct samsung_pin_bank_type: pin bank type description
+ * @fld_width: widths of configuration bitfields (0 if unavailable)
+ * @reg_offset: offsets of configuration registers (don't care of width is 0)
+ */
+struct samsung_pin_bank_type {
+ u8 fld_width[PINCFG_TYPE_NUM];
+ u8 reg_offset[PINCFG_TYPE_NUM];
+};
/**
* struct samsung_pin_bank_data: represent a controller pin-bank data.
+ * @type: type of the bank (register offsets and bitfield widths)
* @offset: starting offset of the pin-bank registers.
* @nr_pins: number of pins included in this bank.
* @name: name to be prefixed for each pin in this pin bank.
*/
struct samsung_pin_bank_data {
+ const struct samsung_pin_bank_type *type;
u32 offset;
u8 nr_pins;
const char *name;
};
+extern const struct samsung_pin_bank_type bank_type_alive;
+
#define EXYNOS_PIN_BANK(pins, reg, id) \
{ \
- .offset = reg, \
+ .type = &bank_type_alive, \
+ .offset = reg, \
.nr_pins = pins, \
.name = id \
}
#include "pinctrl-exynos.h"
#define GPD1_OFFSET 0xc0
+#define PIN_CON 0x00 /* Offset of pin function register */
+#define PIN_PUD 0x08 /* Offset of pin pull up/down config register */
static struct exynos_pinctrl_config_data serial2_conf[] = {
{
--- /dev/null
+if ARCH_SNAPDRAGON
+
+config PINCTRL_QCOM
+ depends on PINCTRL_GENERIC
+ def_bool n
+
+menu "Qualcomm pinctrl drivers"
+
+config PINCTRL_QCOM_APQ8016
+ bool "Qualcomm APQ8016 GCC"
+ select PINCTRL_QCOM
+ help
+ Say Y here to enable support for pinctrl on the MSM8916 / APQ8016
+ Snapdragon 410 SoC, as well as the associated GPIO driver.
+
+config PINCTRL_QCOM_APQ8096
+ bool "Qualcomm APQ8096 GCC"
+ select PINCTRL_QCOM
+ help
+ Say Y here to enable support for pinctrl on the MSM8996 / APQ8096
+ Snapdragon 820 SoC, as well as the associated GPIO driver.
+
+config PINCTRL_QCOM_IPQ4019
+ bool "Qualcomm IPQ4019 GCC"
+ select PINCTRL_QCOM
+ help
+ Say Y here to enable support for pinctrl on the IPQ4019 SoC,
+ as well as the associated GPIO driver.
+
+config PINCTRL_QCOM_QCS404
+ bool "Qualcomm QCS404 GCC"
+ select PINCTRL_QCOM
+ help
+ Say Y here to enable support for pinctrl on the Snapdragon QCS404 SoC,
+ as well as the associated GPIO driver.
+
+config PINCTRL_QCOM_SDM845
+ bool "Qualcomm SDM845 GCC"
+ select PINCTRL_QCOM
+ help
+ Say Y here to enable support for pinctrl on the Snapdragon 845 SoC,
+ as well as the associated GPIO driver.
+
+endmenu
+
+endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2023 Linaro Ltd.
+
+obj-$(CONFIG_PINCTRL_QCOM) += pinctrl-qcom.o
+obj-$(CONFIG_PINCTRL_QCOM_APQ8016) += pinctrl-apq8016.o
+obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o
+obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
+obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
+obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
*
*/
-#include "pinctrl-snapdragon.h"
#include <common.h>
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
#define MAX_PIN_NAME_LEN 32
static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
return msm_pinctrl_functions[selector].val;
}
-struct msm_pinctrl_data apq8016_data = {
- .pin_count = 133,
+static const struct msm_pinctrl_data apq8016_data = {
+ .pin_data = { .pin_count = 133, },
.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
.get_function_name = apq8016_get_function_name,
.get_function_mux = apq8016_get_function_mux,
.get_pin_name = apq8016_get_pin_name,
};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+ { .compatible = "qcom,msm8916-pinctrl", .data = (ulong)&apq8016_data },
+ { /* Sentinal */ }
+};
+
+U_BOOT_DRIVER(pinctrl_apq8016) = {
+ .name = "pinctrl_apq8016",
+ .id = UCLASS_NOP,
+ .of_match = msm_pinctrl_ids,
+ .ops = &msm_pinctrl_ops,
+ .bind = msm_pinctrl_bind,
+};
*
*/
-#include "pinctrl-snapdragon.h"
#include <common.h>
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
#define MAX_PIN_NAME_LEN 32
static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
return msm_pinctrl_functions[selector].val;
}
-struct msm_pinctrl_data apq8096_data = {
- .pin_count = 157,
+static const struct msm_pinctrl_data apq8096_data = {
+ .pin_data = { .pin_count = 157, },
.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
.get_function_name = apq8096_get_function_name,
.get_function_mux = apq8096_get_function_mux,
.get_pin_name = apq8096_get_pin_name,
};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+ { .compatible = "qcom,msm8996-pinctrl", .data = (ulong)&apq8096_data },
+ { /* Sentinal */ }
+};
+
+U_BOOT_DRIVER(pinctrl_apq8096) = {
+ .name = "pinctrl_apq8096",
+ .id = UCLASS_NOP,
+ .of_match = msm_pinctrl_ids,
+ .ops = &msm_pinctrl_ops,
+ .bind = msm_pinctrl_bind,
+};
* Author: Robert Marko <robert.marko@sartura.hr>
*/
-#include "pinctrl-snapdragon.h"
#include <common.h>
+#include <dm.h>
-#define MAX_PIN_NAME_LEN 32
-static char pin_name[MAX_PIN_NAME_LEN];
+#include "pinctrl-qcom.h"
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
static const struct pinctrl_function msm_pinctrl_functions[] = {
{"gpio", 0},
{"blsp_uart0_0", 1}, /* Only for GPIO:16,17 */
{"mdc_0", 1}, /* Only for GPIO7 */
{"mdc_1", 2}, /* Only for GPIO52 */
};
-
static const char *ipq4019_get_function_name(struct udevice *dev,
unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
-struct msm_pinctrl_data ipq4019_data = {
- .pin_count = 100,
+static const struct msm_pinctrl_data ipq4019_data = {
+ .pin_data = { .pin_count = 100, },
.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
.get_function_name = ipq4019_get_function_name,
.get_function_mux = ipq4019_get_function_mux,
.get_pin_name = ipq4019_get_pin_name,
};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+ { .compatible = "qcom,ipq4019-pinctrl", .data = (ulong)&ipq4019_data },
+ { /* Sentinal */ }
+};
+
+U_BOOT_DRIVER(pinctrl_ipq4019) = {
+ .name = "pinctrl_ipq4019",
+ .id = UCLASS_NOP,
+ .of_match = msm_pinctrl_ids,
+ .ops = &msm_pinctrl_ops,
+ .bind = msm_pinctrl_bind,
+};
#include <errno.h>
#include <asm/io.h>
#include <dm/device_compat.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
+#include <asm/gpio.h>
#include <dm/pinctrl.h>
#include <linux/bitops.h>
-#include "pinctrl-snapdragon.h"
+#include <mach/gpio.h>
+
+#include "pinctrl-qcom.h"
struct msm_pinctrl_priv {
phys_addr_t base;
struct msm_pinctrl_data *data;
};
-#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000)
+#define GPIO_CONFIG_REG(priv, x) \
+ (qcom_pin_offset((priv)->data->pin_data.pin_offsets, x))
+
#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
- return priv->data->pin_count;
+ return priv->data->pin_data.pin_count;
}
static const char *msm_get_function_name(struct udevice *dev,
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
priv->base = dev_read_addr(dev);
- priv->data = (struct msm_pinctrl_data *)dev->driver_data;
+ priv->data = (struct msm_pinctrl_data *)dev_get_driver_data(dev);
return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
}
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
- clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
+ clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
priv->data->get_function_mux(func_selector) << 2);
return 0;
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH:
argument = (argument / 2) - 1;
- clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
+ clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
TLMM_DRV_STRENGTH_MASK, argument << 6);
break;
case PIN_CONFIG_BIAS_DISABLE:
- clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
+ clrbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
TLMM_GPIO_PULL_MASK);
break;
case PIN_CONFIG_BIAS_PULL_UP:
- clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
+ clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
TLMM_GPIO_PULL_MASK, argument);
break;
default:
return 0;
}
-static struct pinctrl_ops msm_pinctrl_ops = {
+struct pinctrl_ops msm_pinctrl_ops = {
.get_pins_count = msm_get_pins_count,
.get_pin_name = msm_get_pin_name,
.set_state = pinctrl_generic_set_state,
.get_function_name = msm_get_function_name,
};
-static int msm_pinctrl_bind(struct udevice *dev)
+int msm_pinctrl_bind(struct udevice *dev)
{
ofnode node = dev_ofnode(dev);
+ struct msm_pinctrl_data *data = (struct msm_pinctrl_data *)dev_get_driver_data(dev);
+ struct driver *drv;
+ struct udevice *pinctrl_dev;
const char *name;
int ret;
+ drv = lists_driver_lookup_name("pinctrl_qcom");
+ if (!drv)
+ return -ENOENT;
+
+ ret = device_bind_with_driver_data(dev_get_parent(dev), drv, ofnode_get_name(node), (ulong)data,
+ dev_ofnode(dev), &pinctrl_dev);
+ if (ret)
+ return ret;
+
ofnode_get_property(node, "gpio-controller", &ret);
if (ret < 0)
return 0;
if (!name)
return -EINVAL;
- /* Bind gpio node */
- ret = device_bind_driver_to_node(dev, "gpio_msm",
- name, node, NULL);
- if (ret)
- return ret;
+ drv = lists_driver_lookup_name("gpio_msm");
+ if (!drv) {
+ printf("Can't find gpio_msm driver\n");
+ return -ENODEV;
+ }
- dev_dbg(dev, "bind %s\n", name);
+ /* Bind gpio device as a child of the pinctrl device */
+ ret = device_bind_with_driver_data(pinctrl_dev, drv,
+ name, (ulong)&data->pin_data, node, NULL);
+ if (ret) {
+ device_unbind(pinctrl_dev);
+ return ret;
+ }
return 0;
}
-static const struct udevice_id msm_pinctrl_ids[] = {
- { .compatible = "qcom,msm8916-pinctrl", .data = (ulong)&apq8016_data },
- { .compatible = "qcom,msm8996-pinctrl", .data = (ulong)&apq8096_data },
- { .compatible = "qcom,sdm845-pinctrl", .data = (ulong)&sdm845_data },
- { .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_snapdraon) = {
- .name = "pinctrl_msm",
+U_BOOT_DRIVER(pinctrl_qcom) = {
+ .name = "pinctrl_qcom",
.id = UCLASS_PINCTRL,
- .of_match = msm_pinctrl_ids,
.priv_auto = sizeof(struct msm_pinctrl_priv),
.ops = &msm_pinctrl_ops,
.probe = msm_pinctrl_probe,
- .bind = msm_pinctrl_bind,
};
* (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
*
*/
-#ifndef _PINCTRL_SNAPDRAGON_H
-#define _PINCTRL_SNAPDRAGON_H
+#ifndef _PINCTRL_QCOM_H
+#define _PINCTRL_QCOM_H
+
+#include <asm/types.h>
+#include <mach/gpio.h>
+
+struct udevice;
struct msm_pinctrl_data {
- int pin_count;
+ struct msm_pin_data pin_data;
int functions_count;
const char *(*get_function_name)(struct udevice *dev,
unsigned int selector);
int val;
};
-extern struct msm_pinctrl_data ipq4019_data;
+extern struct pinctrl_ops msm_pinctrl_ops;
+
+int msm_pinctrl_bind(struct udevice *dev);
#endif
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
-#include "pinctrl-snapdragon.h"
#include <common.h>
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
#define MAX_PIN_NAME_LEN 32
static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
return msm_pinctrl_functions[selector].val;
}
-struct msm_pinctrl_data qcs404_data = {
- .pin_count = 126,
+static struct msm_pinctrl_data qcs404_data = {
+ .pin_data = { .pin_count = 126, },
.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
.get_function_name = qcs404_get_function_name,
.get_function_mux = qcs404_get_function_mux,
.get_pin_name = qcs404_get_pin_name,
};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+ { .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data },
+ { /* Sentinal */ }
+};
+
+U_BOOT_DRIVER(pinctrl_qcs404) = {
+ .name = "pinctrl_qcs404",
+ .id = UCLASS_NOP,
+ .of_match = msm_pinctrl_ids,
+ .ops = &msm_pinctrl_ops,
+ .bind = msm_pinctrl_bind,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm SDM845 pinctrl
+ *
+ * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
+ * (C) Copyright 2023 Linaro Ltd.
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
+
+#define NORTH 0x00500000
+#define SOUTH 0x00900000
+#define EAST 0x00100000
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+ {"qup9", 1},
+ {"gpio", 0},
+};
+
+static const unsigned int sdm845_pin_offsets[] = {
+ [0] = EAST, [1] = EAST, [2] = EAST, [3] = EAST, [4] = NORTH,
+ [5] = NORTH, [6] = NORTH, [7] = NORTH, [8] = EAST, [9] = EAST,
+ [10] = EAST, [11] = EAST, [12] = SOUTH, [13] = SOUTH, [14] = SOUTH,
+ [15] = SOUTH, [16] = SOUTH, [17] = SOUTH, [18] = SOUTH, [19] = SOUTH,
+ [20] = SOUTH, [21] = SOUTH, [22] = SOUTH, [23] = SOUTH, [24] = SOUTH,
+ [25] = SOUTH, [26] = SOUTH, [27] = EAST, [28] = EAST, [29] = EAST,
+ [30] = EAST, [31] = NORTH, [32] = NORTH, [33] = NORTH, [34] = NORTH,
+ [35] = SOUTH, [36] = SOUTH, [37] = SOUTH, [38] = NORTH, [39] = EAST,
+ [40] = SOUTH, [41] = EAST, [42] = EAST, [43] = EAST, [44] = EAST,
+ [45] = EAST, [46] = EAST, [47] = EAST, [48] = EAST, [49] = NORTH,
+ [50] = NORTH, [51] = NORTH, [52] = NORTH, [53] = NORTH, [54] = NORTH,
+ [55] = NORTH, [56] = NORTH, [57] = NORTH, [58] = NORTH, [59] = NORTH,
+ [60] = NORTH, [61] = NORTH, [62] = NORTH, [63] = NORTH, [64] = NORTH,
+ [65] = NORTH, [66] = NORTH, [67] = NORTH, [68] = NORTH, [69] = EAST,
+ [70] = EAST, [71] = EAST, [72] = EAST, [73] = EAST, [74] = EAST,
+ [75] = EAST, [76] = EAST, [77] = EAST, [78] = EAST, [79] = NORTH,
+ [80] = NORTH, [81] = NORTH, [82] = NORTH, [83] = NORTH, [84] = NORTH,
+ [85] = EAST, [86] = EAST, [87] = EAST, [88] = EAST, [89] = SOUTH,
+ [90] = SOUTH, [91] = SOUTH, [92] = SOUTH, [93] = SOUTH, [94] = SOUTH,
+ [95] = SOUTH, [96] = SOUTH, [97] = NORTH, [98] = NORTH, [99] = NORTH,
+ [100] = NORTH, [101] = NORTH, [102] = NORTH, [103] = NORTH, [104] = NORTH,
+ [105] = NORTH, [106] = NORTH, [107] = NORTH, [108] = NORTH, [109] = NORTH,
+ [110] = NORTH, [111] = NORTH, [112] = NORTH, [113] = NORTH, [114] = NORTH,
+ [115] = NORTH, [116] = NORTH, [117] = NORTH, [118] = NORTH, [119] = NORTH,
+ [120] = NORTH, [121] = NORTH, [122] = EAST, [123] = EAST, [124] = EAST,
+ [125] = EAST, [126] = EAST, [127] = NORTH, [128] = NORTH, [129] = NORTH,
+ [130] = NORTH, [131] = NORTH, [132] = NORTH, [133] = NORTH, [134] = NORTH,
+ [135] = NORTH, [136] = NORTH, [137] = NORTH, [138] = NORTH, [139] = NORTH,
+ [140] = NORTH, [141] = NORTH, [142] = NORTH, [143] = NORTH, [144] = NORTH,
+ [145] = NORTH, [146] = NORTH, [147] = NORTH, [148] = NORTH, [149] = NORTH,
+};
+
+static const char *sdm845_get_function_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].name;
+}
+
+static const char *sdm845_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+ return pin_name;
+}
+
+static unsigned int sdm845_get_function_mux(unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].val;
+}
+
+static struct msm_pinctrl_data sdm845_data = {
+ .pin_data = {
+ .pin_offsets = sdm845_pin_offsets,
+ .pin_count = ARRAY_SIZE(sdm845_pin_offsets),
+ },
+ .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+ .get_function_name = sdm845_get_function_name,
+ .get_function_mux = sdm845_get_function_mux,
+ .get_pin_name = sdm845_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+ { .compatible = "qcom,sdm845-pinctrl", .data = (ulong)&sdm845_data },
+ { /* Sentinal */ }
+};
+
+U_BOOT_DRIVER(pinctrl_sdm845) = {
+ .name = "pinctrl_sdm845",
+ .id = UCLASS_NOP,
+ .of_match = msm_pinctrl_ids,
+ .ops = &msm_pinctrl_ops,
+ .bind = msm_pinctrl_bind,
+};
static int pmic_qcom_probe(struct udevice *dev)
{
struct pmic_qcom_priv *priv = dev_get_priv(dev);
-
- priv->usid = dev_read_addr(dev);
-
- if (priv->usid == FDT_ADDR_T_NONE)
+ int ret;
+
+ /*
+ * dev_read_addr() can't be used here because the reg property actually
+ * contains two discrete values, not a single 64-bit address.
+ * The address is the first value.
+ */
+ ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 0, &priv->usid);
+ if (ret < 0)
return -EINVAL;
+ debug("usid: %d\n", priv->usid);
+
return 0;
}
help
Support for reset controller on MediaTek MIPS platform.
+config RESET_NPCM
+ bool "Reset controller driver for Nuvoton BMCs"
+ depends on DM_RESET && ARCH_NPCM
+ default y
+ help
+ Support for reset controller on Nuvotom BMCs.
+
config RESET_SUNXI
bool "RESET support for Allwinner SoCs"
depends on DM_RESET && ARCH_SUNXI
help
Support for reset controller on i.MX7/8 SoCs.
-config RESET_QCOM
- bool "Reset driver for Qualcomm SoCs"
- depends on DM_RESET && (ARCH_SNAPDRAGON || ARCH_IPQ40XX)
- default y
- help
- Support for reset controller on Qualcomm SoCs.
-
config RESET_SIFIVE
bool "Reset Driver for SiFive SoC's"
depends on DM_RESET && CLK_SIFIVE_PRCI && (TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED)
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
+obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
-obj-$(CONFIG_RESET_QCOM) += reset-qcom.o
obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o
obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2023 Nuvoton Technology Corp.
+ */
+
+#include <dm.h>
+#include <reset-uclass.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+
+struct npcm_reset_priv {
+ void __iomem *base;
+};
+
+static int npcm_reset_request(struct reset_ctl *rst)
+{
+ return 0;
+}
+
+static int npcm_reset_free(struct reset_ctl *rst)
+{
+ return 0;
+}
+
+static int npcm_reset_assert(struct reset_ctl *rst)
+{
+ struct npcm_reset_priv *priv = dev_get_priv(rst->dev);
+ u32 val;
+
+ debug("%s: id 0x%lx, data %ld\n", __func__, rst->id, rst->data);
+ val = readl(priv->base + rst->id);
+ val |= BIT(rst->data);
+ writel(val, priv->base + rst->id);
+
+ return 0;
+}
+
+static int npcm_reset_deassert(struct reset_ctl *rst)
+{
+ struct npcm_reset_priv *priv = dev_get_priv(rst->dev);
+ u32 val;
+
+ debug("%s: id 0x%lx, data %ld\n", __func__, rst->id, rst->data);
+ val = readl(priv->base + rst->id);
+ val &= ~BIT(rst->data);
+ writel(val, priv->base + rst->id);
+
+ return 0;
+}
+
+static int npcm_reset_xlate(struct reset_ctl *rst,
+ struct ofnode_phandle_args *args)
+{
+ if (args->args_count != 2) {
+ dev_err(rst->dev, "Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ /* Use id field as register offset and data field as reset bit positiion */
+ rst->id = args->args[0];
+ rst->data = args->args[1];
+
+ return 0;
+}
+
+static int npcm_reset_probe(struct udevice *dev)
+{
+ struct npcm_reset_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_remap_addr(dev);
+ if (!priv->base)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int npcm_reset_bind(struct udevice *dev)
+{
+ void __iomem *reg_base;
+ u32 *rcr_values;
+ int num_fields;
+ u32 reg, val;
+ int ret, i;
+
+ reg_base = dev_remap_addr(dev);
+ if (!reg_base)
+ return -EINVAL;
+
+ /*
+ * Set RCR initial value
+ * The rcr-initial-values cell is <reg_offset val>
+ */
+ num_fields = dev_read_size(dev, "rcr-initial-values");
+ if (num_fields < 2)
+ return 0;
+
+ num_fields /= sizeof(u32);
+ if (num_fields % 2)
+ return -EINVAL;
+
+ num_fields = num_fields / 2;
+ rcr_values = malloc(num_fields * 2 * sizeof(u32));
+ if (!rcr_values)
+ return -ENOMEM;
+
+ ret = dev_read_u32_array(dev, "rcr-initial-values", rcr_values,
+ num_fields * 2);
+ if (ret < 0) {
+ free(rcr_values);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < num_fields; i++) {
+ reg = rcr_values[2 * i];
+ val = rcr_values[2 * i + 1];
+ writel(val, reg_base + reg);
+ }
+ free(rcr_values);
+
+ return 0;
+}
+
+static const struct udevice_id npcm_reset_ids[] = {
+ { .compatible = "nuvoton,npcm845-reset" },
+ { .compatible = "nuvoton,npcm750-reset" },
+ { }
+};
+
+struct reset_ops npcm_reset_ops = {
+ .request = npcm_reset_request,
+ .rfree = npcm_reset_free,
+ .rst_assert = npcm_reset_assert,
+ .rst_deassert = npcm_reset_deassert,
+ .of_xlate = npcm_reset_xlate,
+};
+
+U_BOOT_DRIVER(npcm_reset) = {
+ .name = "npcm_reset",
+ .id = UCLASS_RESET,
+ .of_match = npcm_reset_ids,
+ .bind = npcm_reset_bind,
+ .probe = npcm_reset_probe,
+ .ops = &npcm_reset_ops,
+ .priv_auto = sizeof(struct npcm_reset_priv),
+};
.read = arm_rndr_read,
};
-static int arm_rndr_probe(struct udevice *dev)
+static int arm_rndr_bind(struct udevice *dev)
{
if (!cpu_has_rndr())
- return -ENODEV;
+ return -ENOENT;
return 0;
}
.name = DRIVER_NAME,
.id = UCLASS_RNG,
.ops = &arm_rndr_ops,
- .probe = arm_rndr_probe,
+ .bind = arm_rndr_bind,
};
U_BOOT_DRVINFO(cpu_arm_rndr) = {
}
break;
case DEAD:
- return -ENODEV;
+ return -ENOENT;
}
}
}
/**
- * riscv_zkr_probe() - check if the seed register is available
+ * riscv_zkr_bind() - check if the seed register is available
*
- * If the SBI software has not set mseccfg.sseed=1 or the Zkr
- * extension is not available this probe function will result
- * in an exception. Currently we cannot recover from this.
+ * If the SBI software has not set mseccfg.sseed=1 or the Zkr extension is not
+ * available, reading the seed register will result in an exception from which
+ * this function safely resumes.
*
* @dev: RNG device
* Return: 0 if successfully probed
*/
-static int riscv_zkr_probe(struct udevice *dev)
+static int riscv_zkr_bind(struct udevice *dev)
{
struct resume_data resume;
int ret;
val = read_seed();
set_resume(NULL);
if (ret)
- return -ENODEV;
+ return -ENOENT;
+
+ return 0;
+}
+
+/**
+ * riscv_zkr_probe() - check if entropy is available
+ *
+ * The bind method already checked that the seed register can be read without
+ * excpetiong. Here we wait for the self test to finish and entropy becoming
+ * available.
+ *
+ * @dev: RNG device
+ * Return: 0 if successfully probed
+ */
+static int riscv_zkr_probe(struct udevice *dev)
+{
+ u32 val;
do {
val = read_seed();
} while (val == BIST || val == WAIT);
if (val == DEAD)
- return -ENODEV;
+ return -ENOENT;
return 0;
}
.name = DRIVER_NAME,
.id = UCLASS_RNG,
.ops = &riscv_zkr_ops,
+ .bind = riscv_zkr_bind,
.probe = riscv_zkr_probe,
};
CONFIG_BOOTP_NTPSERVER. The RTC time is advanced according to CPU
ticks.
+config RTC_GOLDFISH
+ bool "Enable Goldfish driver"
+ depends on DM_RTC
+ help
+ The Goldfish RTC is a virtual device which may be supplied by QEMU.
+ It is enabled by default on QEMU's RISC-V virt machine.
+
config RTC_ISL1208
bool "Enable ISL1208 driver"
depends on DM_RTC
obj-$(CONFIG_RTC_DS3231) += ds3231.o
obj-$(CONFIG_RTC_DS3232) += ds3232.o
obj-$(CONFIG_RTC_EMULATION) += emul_rtc.o
+obj-$(CONFIG_RTC_GOLDFISH) += goldfish_rtc.o
obj-$(CONFIG_RTC_HT1380) += ht1380.o
obj-$(CONFIG_$(SPL_TPL_)RTC_SANDBOX) += i2c_rtc_emul.o
obj-$(CONFIG_RTC_ISL1208) += isl1208.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2023, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+ *
+ * This driver emulates a real time clock based on timer ticks.
+ */
+
+#include <div64.h>
+#include <dm.h>
+#include <mapmem.h>
+#include <rtc.h>
+#include <linux/io.h>
+
+/**
+ * struct goldfish_rtc - private data for RTC driver
+ */
+struct goldfish_rtc {
+ /**
+ * @base: base address for register file
+ */
+ void __iomem *base;
+ /**
+ * @isdst: daylight saving time
+ */
+ int isdst;
+};
+
+/* Register offsets */
+#define GOLDFISH_TIME_LOW 0x00
+#define GOLDFISH_TIME_HIGH 0x04
+
+static int goldfish_rtc_get(struct udevice *dev, struct rtc_time *time)
+{
+ struct goldfish_rtc *priv = dev_get_priv(dev);
+ void __iomem *base = priv->base;
+ u64 time_high;
+ u64 time_low;
+ u64 now;
+
+ time_low = ioread32(base + GOLDFISH_TIME_LOW);
+ time_high = ioread32(base + GOLDFISH_TIME_HIGH);
+ now = (time_high << 32) | time_low;
+
+ do_div(now, 1000000000U);
+
+ rtc_to_tm(now, time);
+ time->tm_isdst = priv->isdst;
+
+ return 0;
+}
+
+static int goldfish_rtc_set(struct udevice *dev, const struct rtc_time *time)
+{
+ struct goldfish_rtc *priv = dev_get_priv(dev);
+ void __iomem *base = priv->base;
+ u64 now;
+
+ if (time->tm_year < 1970)
+ return -EINVAL;
+
+ now = rtc_mktime(time) * 1000000000ULL;
+ iowrite32(now >> 32, base + GOLDFISH_TIME_HIGH);
+ iowrite32(now, base + GOLDFISH_TIME_LOW);
+
+ if (time->tm_isdst > 0)
+ priv->isdst = 1;
+ else if (time->tm_isdst < 0)
+ priv->isdst = -1;
+ else
+ priv->isdst = 0;
+
+ return 0;
+}
+
+int goldfish_rtc_probe(struct udevice *dev)
+{
+ struct goldfish_rtc *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ priv->base = map_sysmem(addr, 0x20);
+
+ return 0;
+}
+
+static const struct rtc_ops goldfish_rtc_ops = {
+ .get = goldfish_rtc_get,
+ .set = goldfish_rtc_set,
+};
+
+static const struct udevice_id goldfish_rtc_of_match[] = {
+ { .compatible = "google,goldfish-rtc", },
+ {},
+};
+
+U_BOOT_DRIVER(rtc_goldfish) = {
+ .name = "rtc_goldfish",
+ .id = UCLASS_RTC,
+ .ops = &goldfish_rtc_ops,
+ .probe = goldfish_rtc_probe,
+ .of_match = goldfish_rtc_of_match,
+ .priv_auto = sizeof(struct goldfish_rtc),
+};
config MSM_GENI_SERIAL
bool "Qualcomm on-chip GENI UART"
- select MISC
- imply QCOM_GENI_SE
help
Support UART based on Generic Interface (GENI) Serial Engine (SE),
used on Qualcomm Snapdragon SoCs. Should support all qualcomm SOCs
int ret;
clk = devm_clk_get(dev, NULL);
- if (!clk)
- return -EINVAL;
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
ret = clk_set_rate(clk, rate);
return ret;
struct msm_serial_data *priv = dev_get_priv(dev);
u64 clk_rate;
u32 clk_div;
+ int ret;
priv->baud = baud;
clk_rate = get_clk_div_rate(baud, priv->oversampling, &clk_div);
- geni_serial_set_clock_rate(dev, clk_rate);
+ ret = geni_serial_set_clock_rate(dev, clk_rate);
+ if (ret < 0) {
+ pr_err("%s: Couldn't set clock rate: %d\n", __func__, ret);
+ return ret;
+ }
geni_serial_baud(priv->base, clk_div, baud);
return 0;
.setbrg = msm_serial_setbrg,
};
-static void geni_set_oversampling(struct udevice *dev)
+static int geni_set_oversampling(struct udevice *dev)
{
struct msm_serial_data *priv = dev_get_priv(dev);
- struct udevice *parent_dev = dev_get_parent(dev);
+ ofnode parent_node = ofnode_get_parent(dev_ofnode(dev));
u32 geni_se_version;
- int ret;
+ fdt_addr_t addr;
priv->oversampling = UART_OVERSAMPLING;
* It could happen that GENI SE IP is missing in the board's device
* tree or GENI UART node is a direct child of SoC device tree node.
*/
- if (device_get_uclass_id(parent_dev) != UCLASS_MISC)
- return;
+ if (!ofnode_device_is_compatible(parent_node, "qcom,geni-se-qup")) {
+ pr_err("%s: UART node must be a child of geniqup node\n",
+ __func__);
+ return -ENODEV;
+ }
- ret = misc_read(parent_dev, QUP_HW_VER_REG,
- &geni_se_version, sizeof(geni_se_version));
- if (ret != sizeof(geni_se_version))
- return;
+ /* Read the HW_VER register relative to the parents address space */
+ addr = ofnode_get_addr(parent_node);
+ geni_se_version = readl(addr + QUP_HW_VER_REG);
if (geni_se_version >= QUP_SE_VERSION_2_5)
priv->oversampling /= 2;
+
+ return 0;
}
static inline void geni_serial_init(struct udevice *dev)
static int msm_serial_probe(struct udevice *dev)
{
struct msm_serial_data *priv = dev_get_priv(dev);
+ int ret;
- geni_set_oversampling(dev);
+ ret = geni_set_oversampling(dev);
+ if (ret < 0)
+ return ret;
/* No need to reinitialize the UART after relocation */
if (gd->flags & GD_FLG_RELOC)
struct msm_spmi_priv {
phys_addr_t arb_chnl; /* ARB channel mapping base */
- phys_addr_t spmi_core; /* SPMI core */
+ phys_addr_t spmi_chnls; /* SPMI channels */
phys_addr_t spmi_obs; /* SPMI observer */
/* SPMI channel map */
uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
/* Disable IRQ mode for the current channel*/
writel(0x0,
- priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
+ priv->spmi_chnls + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
/* Write single byte */
- writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
+ writel(val, priv->spmi_chnls + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
/* Prepare write command */
reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
ch_offset = SPMI_CH_OFFSET(channel);
/* Send write command */
- writel(reg, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
+ writel(reg, priv->spmi_chnls + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
/* Wait till CMD DONE status */
reg = 0;
while (!reg) {
- reg = readl(priv->spmi_core + SPMI_CH_OFFSET(channel) +
+ reg = readl(priv->spmi_chnls + SPMI_CH_OFFSET(channel) +
SPMI_REG_STATUS);
}
static int msm_spmi_probe(struct udevice *dev)
{
struct msm_spmi_priv *priv = dev_get_priv(dev);
- phys_addr_t config_addr;
+ phys_addr_t core_addr;
u32 hw_ver;
- u32 version;
int i;
- int err;
- config_addr = dev_read_addr_index(dev, 0);
- priv->spmi_core = dev_read_addr_index(dev, 1);
- priv->spmi_obs = dev_read_addr_index(dev, 2);
+ core_addr = dev_read_addr_name(dev, "core");
+ priv->spmi_chnls = dev_read_addr_name(dev, "chnls");
+ priv->spmi_obs = dev_read_addr_name(dev, "obsrvr");
- hw_ver = readl(config_addr + PMIC_ARB_VERSION);
+ hw_ver = readl(core_addr + PMIC_ARB_VERSION);
if (hw_ver < PMIC_ARB_VERSION_V3_MIN) {
priv->arb_ver = V2;
- version = 2;
- priv->arb_chnl = config_addr + APID_MAP_OFFSET_V1_V2_V3;
+ priv->arb_chnl = core_addr + APID_MAP_OFFSET_V1_V2_V3;
} else if (hw_ver < PMIC_ARB_VERSION_V5_MIN) {
priv->arb_ver = V3;
- version = 3;
- priv->arb_chnl = config_addr + APID_MAP_OFFSET_V1_V2_V3;
+ priv->arb_chnl = core_addr + APID_MAP_OFFSET_V1_V2_V3;
} else {
priv->arb_ver = V5;
- version = 5;
- priv->arb_chnl = config_addr + APID_MAP_OFFSET_V5;
-
- if (err) {
- dev_err(dev, "could not read APID->PPID mapping table, rc= %d\n", err);
- return -1;
- }
+ priv->arb_chnl = core_addr + APID_MAP_OFFSET_V5;
}
- dev_dbg(dev, "PMIC Arb Version-%d (0x%x)\n", version, hw_ver);
+ dev_dbg(dev, "PMIC Arb Version-%d (%#x)\n", hw_ver >> 28, hw_ver);
if (priv->arb_chnl == FDT_ADDR_T_NONE ||
- priv->spmi_core == FDT_ADDR_T_NONE ||
+ priv->spmi_chnls == FDT_ADDR_T_NONE ||
priv->spmi_obs == FDT_ADDR_T_NONE)
return -EINVAL;
- dev_dbg(dev, "priv->arb_chnl address (%llu)\n", priv->arb_chnl);
- dev_dbg(dev, "priv->spmi_core address (%llu)\n", priv->spmi_core);
- dev_dbg(dev, "priv->spmi_obs address (%llu)\n", priv->spmi_obs);
+ dev_dbg(dev, "priv->arb_chnl address (%#08llx)\n", priv->arb_chnl);
+ dev_dbg(dev, "priv->spmi_chnls address (%#08llx)\n", priv->spmi_chnls);
+ dev_dbg(dev, "priv->spmi_obs address (%#08llx)\n", priv->spmi_obs);
/* Scan peripherals connected to each SPMI channel */
for (i = 0; i < SPMI_MAX_PERIPH; i++) {
uint32_t periph = readl(priv->arb_chnl + ARB_CHANNEL_OFFSET(i));
do_exit_on_complete(ep, req);
}
+static int multiresponse_cmd = -1;
+static void multiresponse_on_complete(struct usb_ep *ep, struct usb_request *req)
+{
+ char response[FASTBOOT_RESPONSE_LEN] = {0};
+
+ if (multiresponse_cmd == -1)
+ return;
+
+ /* Call handler to obtain next response */
+ fastboot_multiresponse(multiresponse_cmd, response);
+ fastboot_tx_write_str(response);
+
+ /* If response is final OKAY/FAIL response disconnect this handler and unset cmd */
+ if (!strncmp("OKAY", response, 4) || !strncmp("FAIL", response, 4)) {
+ multiresponse_cmd = -1;
+ fastboot_func->in_req->complete = fastboot_complete;
+ }
+}
+
static void do_acmd_complete(struct usb_ep *ep, struct usb_request *req)
{
/* When usb dequeue complete will be called
fastboot_fail("buffer overflow", response);
}
+ if (!strncmp(FASTBOOT_MULTIRESPONSE_START, response, 4)) {
+ multiresponse_cmd = cmd;
+ fastboot_multiresponse(multiresponse_cmd, response);
+
+ /* Only add complete callback if first is not a final OKAY/FAIL response */
+ if (strncmp("OKAY", response, 4) && strncmp("FAIL", response, 4)) {
+ fastboot_func->in_req->complete = multiresponse_on_complete;
+ }
+ }
+
if (!strncmp("DATA", response, 4)) {
req->complete = rx_handler_dl_image;
req->length = rx_bytes_expected(ep);
return 1;
}
- if (IS_ENABLED(CONFIG_CMD_BOOTEFI))
- efi_set_bootdev(argv[1], (argc > 2) ? argv[2] : "",
- (argc > 4) ? argv[4] : "", map_sysmem(addr, 0),
- len_read);
+ efi_set_bootdev(argv[1], (argc > 2) ? argv[2] : "",
+ (argc > 4) ? argv[4] : "", map_sysmem(addr, 0),
+ len_read);
printf("%llu bytes read in %lu ms", len_read, time);
if (time > 0) {
* Return: data size in bytes (1, 2, 4, 8) or CMD_DATA_SIZE_ERR for an invalid
* character, or CMD_DATA_SIZE_STR for a string
*/
-int cmd_get_data_size(char *arg, int default_size);
+int cmd_get_data_size(const char *arg, int default_size);
#endif
#ifdef CONFIG_CMD_BOOTD
#define PCIE_ARGS "pcie_args=pci=pcie_bus_safe pcie_ports=native vfio_pci.disable_idle_d3=1\0"
#ifdef CONFIG_BCM_SF2_ETH
-#define ETH_ADDR "ethaddr=00:0A:F7:95:65:A4\0"
+#define BCM_ETH_ADDR "ethaddr=00:0A:F7:95:65:A4\0"
#define NET_ARGS "bgmac_platform.ethaddr=${ethaddr} " \
"ip=${ipaddr}::${gatewayip}:${netmask}::${ethif}:off"
#else
-#define ETH_ADDR
+#define BMC_ETH_ADDR
#define NET_ARGS
#endif
OS_LOG_LEVEL \
EXTRA_ARGS \
PCIE_ARGS \
- ETH_ADDR \
+ BMC_ETH_ADDR \
RESERVED_MEM \
SETBOOTARGS \
UPDATEME_FLASH_PARAMS \
#define __CONFIGS_DRAGONBOARD410C_H
#include <linux/sizes.h>
-#include <asm/arch/sysmap-apq8016.h>
/* Build new ELF image from u-boot.bin (U-Boot + appended DTB) */
#define __CONFIGS_DRAGONBOARD820C_H
#include <linux/sizes.h>
-#include <asm/arch/sysmap-apq8096.h>
/* Physical Memory Map */
#define __CONFIGS_SDM845_H
#include <linux/sizes.h>
-#include <asm/arch/sysmap-sdm845.h>
#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
#define CFG_SYS_FSL_USDHC_NUM 2
#define CFG_SYS_FSL_ESDHC_ADDR 0
-#define CFG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
"altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \
"bootlimit=3\0" \
"devtype=mmc\0" \
"devpart=1\0" \
- /* Give slow devices beyond USB HUB chance to come up. */ \
- "usb_pgood_delay=2000\0" \
"dfu_alt_info=" \
/* RAM block at DRAM offset 256..768 MiB */ \
"ram ram0=ram ram 0x50000000 0x20000000&" \
"setenv stderr ${stderr},nc && " \
"setenv stdout ${stdout},nc && " \
"setenv stdin ${stdin},nc ; " \
- "fi"
+ "fi\0" \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0" \
+ /* Give slow devices beyond USB HUB chance to come up. */ \
+ "usb_pgood_delay=2000\0"
#endif
"bootlimit=3\0" \
"devtype=mmc\0" \
"devpart=1\0" \
- /* Give slow devices beyond USB HUB chance to come up. */ \
- "usb_pgood_delay=2000\0" \
"dmo_update_env=" \
"setenv dmo_update_env true ; saveenv ; saveenv\0" \
"dmo_update_sf_write_data=" \
"run dmo_update_sf_write_data\0" \
"dmo_update_sd_to_sf=" \
"load mmc 1:1 ${loadaddr} boot/flash.bin && " \
- "run dmo_update_sf_write_data\0"
+ "run dmo_update_sf_write_data\0" \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0" \
+ /* Give slow devices beyond USB HUB chance to come up. */ \
+ "usb_pgood_delay=2000\0"
#endif
#define CFG_SYS_FSL_USDHC_NUM 2
#define CFG_SYS_FSL_ESDHC_ADDR 0
-#define CFG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
"altbootcmd=run bootcmd ; reset\0" \
"bootlimit=3\0" \
- "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
- "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
- "ramdisk_addr_r=0x58000000\0" \
- "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
- /* Give slow devices beyond USB HUB chance to come up. */ \
- "usb_pgood_delay=2000\0" \
"dfu_alt_info=" \
/* RAM block at DRAM offset 256..768 MiB */ \
"ram ram0=ram ram 0x50000000 0x20000000&" \
"dh_update_emmc_to_sf=" \
"load mmc 1:1 ${loadaddr} boot/flash.bin && " \
"run dh_update_sf_gen_fcfb dh_update_sf_write_data\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "ramdisk_addr_r=0x58000000\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0" \
+ /* Give slow devices beyond USB HUB chance to come up. */ \
+ "usb_pgood_delay=2000\0" \
BOOTENV
#define BOOT_TARGET_DEVICES(func) \
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023, Phytium Technology Co., Ltd.
+ * lixinde <lixinde@phytium.com.cn>
+ * weichangzheng <weichangzheng@phytium.com.cn>
+ */
+
+#ifndef __PE2201_CONFIG_H
+#define __PE2201_CONFIG_H
+
+/* SDRAM Bank #1 start address */
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_1_SIZE 0x74000000
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration header file for PHYTEC phyCORE-AM62x
+ *
+ * Copyright (C) 2023 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ */
+
+#ifndef __PHYCORE_AM62X_H
+#define __PHYCORE_AM62X_H
+
+/* DDR Configuration */
+#define CFG_SYS_SDRAM_BASE 0x80000000
+
+#endif /* __PHYCORE_AM62X_H */
#define __CONFIGS_QCS404EVB_H
#include <linux/sizes.h>
-#include <asm/arch/sysmap-qcs404.h>
#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
#define __CONFIGS_SDM845_H
#include <linux/sizes.h>
-#include <asm/arch/sysmap-sdm845.h>
#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-/* Extra Environment */
-
-#define CFG_EXTRA_ENV_SETTINGS \
- "bootmode=update\0" \
- "bootpri=mmc_mmc\0" \
- "bootsec=sf_swu\0" \
- "consdev=ttyAMA0\0" \
- "baudrate=115200\0" \
- "dtbaddr=0x44000000\0" \
- "dtbfile=imx28-xea.dtb\0" \
- "rootdev=/dev/mmcblk0p2\0" \
- "netdev=eth0\0" \
- "rdaddr=0x43000000\0" \
- "swufile=swupdate.img\0" \
- "sf_kernel_offset=0x100000\0" \
- "sf_kernel_size=0x400000\0" \
- "sf_swu_offset=0x500000\0" \
- "sf_swu_size=0x800000\0" \
- "rootpath=/opt/eldk-5.5/armv5te/rootfs-qte-sdk\0" \
- "do_update_mmc=" \
- "if mmc rescan ; then " \
- "mmc dev 0 ${update_mmc_part} ; " \
- "if dhcp ${hostname}/${update_filename} ; then " \
- "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \
- "setexpr fw_sz ${fw_sz} + 1 ; " \
- "mmc write ${loadaddr} ${update_offset} ${fw_sz} ; " \
- "fi ; " \
- "fi\0" \
- "do_update_sf=" \
- "if sf probe ; then " \
- "if dhcp ${hostname}/${update_filename} ; then " \
- "sf erase ${update_offset} +${filesize} ; " \
- "sf write ${loadaddr} ${update_offset} ${filesize} ; " \
- "fi ; " \
- "fi\0" \
- "update_spl_filename=u-boot.sb\0" \
- "update_spl=" \
- "setenv update_filename ${update_spl_filename} ; " \
- "setenv update_offset 0 ; " \
- "run do_update_sf\0" \
- "update_uboot_filename=u-boot.img\0" \
- "update_uboot=" \
- "setenv update_filename ${update_uboot_filename} ; " \
- "setenv update_offset 0x10000 ; " \
- "run do_update_sf ; " \
- "setenv update_mmc_part 1 ; " \
- "setenv update_offset 0 ; " \
- "run do_update_mmc\0" \
- "update_kernel_filename=uImage\0" \
- "update_kernel=" \
- "setenv update_mmc_part 1 ; " \
- "setenv update_filename ${update_kernel_filename} ; " \
- "setenv update_offset 0x800 ; " \
- "run do_update_mmc ; " \
- "setenv update_filename ${dtbfile} ; " \
- "setenv update_offset 0x400 ; " \
- "run do_update_mmc\0" \
- "update_sfkernel=" \
- "setenv update_filename fitImage ; " \
- "setenv update_offset ${sf_kernel_offset} ; " \
- "run do_update_sf\0" \
- "update_swu=" \
- "setenv update_filename ${swufile} ; " \
- "setenv update_offset ${sf_swu_offset} ; " \
- "run do_update_sf\0" \
- "addcons=" \
- "setenv bootargs ${bootargs} " \
- "console=${consdev},${baudrate}\0" \
- "addip=" \
- "setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}:${netdev}:off\0" \
- "addmisc=" \
- "setenv bootargs ${bootargs} ${miscargs}\0" \
- "addargs=run addcons addmisc\0" \
- "mmcload=" \
- "mmc rescan ; " \
- "mmc dev 0 1 ; " \
- "mmc read ${loadaddr} 0x800 0x2000 ; " \
- "mmc read ${dtbaddr} 0x400 0x80\0" \
- "netload=" \
- "dhcp ${loadaddr} ${hostname}/${bootfile} ; " \
- "tftp ${dtbaddr} ${hostname}/${dtbfile}\0" \
- "sfload=" \
- "sf probe ; " \
- "sf read ${loadaddr} ${sf_kernel_offset} ${sf_kernel_size}\0" \
- "usbload=" \
- "usb start ; " \
- "load usb 0:1 ${loadaddr} ${bootfile}\0" \
- "miscargs=panic=1\0" \
- "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \
- "nfsargs=" \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath},v3,tcp\0" \
- "mmc_mmc=" \
- "if run mmcload mmcargs addargs ; then " \
- "bootm ${loadaddr} - ${dtbaddr} ; " \
- "fi\0" \
- "mmc_nfs=" \
- "if run mmcload nfsargs addip addargs ; then " \
- "bootm ${loadaddr} - ${dtbaddr} ; " \
- "fi\0" \
- "sf_mmc=" \
- "if run sfload mmcargs addargs ; then " \
- "bootm ${loadaddr} - ${dtbaddr} ; " \
- "fi\0" \
- "sf_swu=" \
- "if run sfload ; then " \
- "sf read ${rdaddr} ${sf_swu_offset} ${sf_swu_size} ; " \
- "setenv bootargs root=/dev/ram0 rw ; " \
- "run addargs ; " \
- "bootm ${loadaddr} ${rdaddr} ; " \
- "fi\0" \
- "net_mmc=" \
- "if run netload mmcargs addargs ; then " \
- "bootm ${loadaddr} - ${dtbaddr} ; " \
- "fi\0" \
- "net_nfs=" \
- "if run netload nfsargs addip addargs ; then " \
- "bootm ${loadaddr} - ${dtbaddr} ; " \
- "fi\0" \
- "prebootcmd=" \
- "if test \"${envsaved}\" != y ; then ; " \
- "setenv envsaved y ; " \
- "saveenv ; " \
- "fi ; " \
- "if test \"${bootmode}\" = normal ; then " \
- "setenv bootdelay 0 ; " \
- "setenv bootpri mmc_mmc ; " \
- "elif test \"${bootmode}\" = devel ; then " \
- "setenv bootdelay 3 ; " \
- "setenv bootpri net_mmc ; " \
- "else " \
- "if test \"${bootmode}\" != update ; then " \
- "echo Warning: unknown bootmode \"${bootmode}\" ; " \
- "fi ; " \
- "setenv bootdelay 1 ; " \
- "setenv bootpri sf_swu ; " \
- "fi\0"
-
/* The rest of the configuration is shared */
#include <configs/mxs.h>
*/
int console_record_avail(void);
+/**
+ * console_record_isempty() - Returns if console output is empty
+ *
+ * Return: true if empty
+ */
+bool console_record_isempty(void);
+
/**
* console_in_puts() - Write a string to the console input buffer
*
return 0;
}
+static inline bool console_record_isempty(void)
+{
+ /* Always empty */
+ return true;
+}
+
#endif /* !CONFIG_CONSOLE_RECORD */
/**
#define GCC_APSS_CPU_PLLDIV_CLK 74
#define GCC_PCNOC_AHB_CLK_SRC 75
+#define WIFI0_CPU_INIT_RESET 0
+#define WIFI0_RADIO_SRIF_RESET 1
+#define WIFI0_RADIO_WARM_RESET 2
+#define WIFI0_RADIO_COLD_RESET 3
+#define WIFI0_CORE_WARM_RESET 4
+#define WIFI0_CORE_COLD_RESET 5
+#define WIFI1_CPU_INIT_RESET 6
+#define WIFI1_RADIO_SRIF_RESET 7
+#define WIFI1_RADIO_WARM_RESET 8
+#define WIFI1_RADIO_COLD_RESET 9
+#define WIFI1_CORE_WARM_RESET 10
+#define WIFI1_CORE_COLD_RESET 11
+#define USB3_UNIPHY_PHY_ARES 12
+#define USB3_HSPHY_POR_ARES 13
+#define USB3_HSPHY_S_ARES 14
+#define USB2_HSPHY_POR_ARES 15
+#define USB2_HSPHY_S_ARES 16
+#define PCIE_PHY_AHB_ARES 17
+#define PCIE_AHB_ARES 18
+#define PCIE_PWR_ARES 19
+#define PCIE_PIPE_STICKY_ARES 20
+#define PCIE_AXI_M_STICKY_ARES 21
+#define PCIE_PHY_ARES 22
+#define PCIE_PARF_XPU_ARES 23
+#define PCIE_AXI_S_XPU_ARES 24
+#define PCIE_AXI_M_VMIDMT_ARES 25
+#define PCIE_PIPE_ARES 26
+#define PCIE_AXI_S_ARES 27
+#define PCIE_AXI_M_ARES 28
+#define ESS_RESET 29
+#define GCC_BLSP1_BCR 30
+#define GCC_BLSP1_QUP1_BCR 31
+#define GCC_BLSP1_UART1_BCR 32
+#define GCC_BLSP1_QUP2_BCR 33
+#define GCC_BLSP1_UART2_BCR 34
+#define GCC_BIMC_BCR 35
+#define GCC_TLMM_BCR 36
+#define GCC_IMEM_BCR 37
+#define GCC_ESS_BCR 38
+#define GCC_PRNG_BCR 39
+#define GCC_BOOT_ROM_BCR 40
+#define GCC_CRYPTO_BCR 41
+#define GCC_SDCC1_BCR 42
+#define GCC_SEC_CTRL_BCR 43
+#define GCC_AUDIO_BCR 44
+#define GCC_QPIC_BCR 45
+#define GCC_PCIE_BCR 46
+#define GCC_USB2_BCR 47
+#define GCC_USB2_PHY_BCR 48
+#define GCC_USB3_BCR 49
+#define GCC_USB3_PHY_BCR 50
+#define GCC_SYSTEM_NOC_BCR 51
+#define GCC_PCNOC_BCR 52
+#define GCC_DCD_BCR 53
+#define GCC_SNOC_BUS_TIMEOUT0_BCR 54
+#define GCC_SNOC_BUS_TIMEOUT1_BCR 55
+#define GCC_SNOC_BUS_TIMEOUT2_BCR 56
+#define GCC_SNOC_BUS_TIMEOUT3_BCR 57
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67
+#define GCC_TCSR_BCR 68
+#define GCC_QDSS_BCR 69
+#define GCC_MPM_BCR 70
+#define GCC_SPDM_BCR 71
+
#endif
+++ /dev/null
-/* Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-#ifndef __QCOM_RESET_IPQ4019_H__
-#define __QCOM_RESET_IPQ4019_H__
-
-#define WIFI0_CPU_INIT_RESET 0
-#define WIFI0_RADIO_SRIF_RESET 1
-#define WIFI0_RADIO_WARM_RESET 2
-#define WIFI0_RADIO_COLD_RESET 3
-#define WIFI0_CORE_WARM_RESET 4
-#define WIFI0_CORE_COLD_RESET 5
-#define WIFI1_CPU_INIT_RESET 6
-#define WIFI1_RADIO_SRIF_RESET 7
-#define WIFI1_RADIO_WARM_RESET 8
-#define WIFI1_RADIO_COLD_RESET 9
-#define WIFI1_CORE_WARM_RESET 10
-#define WIFI1_CORE_COLD_RESET 11
-#define USB3_UNIPHY_PHY_ARES 12
-#define USB3_HSPHY_POR_ARES 13
-#define USB3_HSPHY_S_ARES 14
-#define USB2_HSPHY_POR_ARES 15
-#define USB2_HSPHY_S_ARES 16
-#define PCIE_PHY_AHB_ARES 17
-#define PCIE_AHB_ARES 18
-#define PCIE_PWR_ARES 19
-#define PCIE_PIPE_STICKY_ARES 20
-#define PCIE_AXI_M_STICKY_ARES 21
-#define PCIE_PHY_ARES 22
-#define PCIE_PARF_XPU_ARES 23
-#define PCIE_AXI_S_XPU_ARES 24
-#define PCIE_AXI_M_VMIDMT_ARES 25
-#define PCIE_PIPE_ARES 26
-#define PCIE_AXI_S_ARES 27
-#define PCIE_AXI_M_ARES 28
-#define ESS_RESET 29
-#define GCC_BLSP1_BCR 30
-#define GCC_BLSP1_QUP1_BCR 31
-#define GCC_BLSP1_UART1_BCR 32
-#define GCC_BLSP1_QUP2_BCR 33
-#define GCC_BLSP1_UART2_BCR 34
-#define GCC_BIMC_BCR 35
-#define GCC_TLMM_BCR 36
-#define GCC_IMEM_BCR 37
-#define GCC_ESS_BCR 38
-#define GCC_PRNG_BCR 39
-#define GCC_BOOT_ROM_BCR 40
-#define GCC_CRYPTO_BCR 41
-#define GCC_SDCC1_BCR 42
-#define GCC_SEC_CTRL_BCR 43
-#define GCC_AUDIO_BCR 44
-#define GCC_QPIC_BCR 45
-#define GCC_PCIE_BCR 46
-#define GCC_USB2_BCR 47
-#define GCC_USB2_PHY_BCR 48
-#define GCC_USB3_BCR 49
-#define GCC_USB3_PHY_BCR 50
-#define GCC_SYSTEM_NOC_BCR 51
-#define GCC_PCNOC_BCR 52
-#define GCC_DCD_BCR 53
-#define GCC_SNOC_BUS_TIMEOUT0_BCR 54
-#define GCC_SNOC_BUS_TIMEOUT1_BCR 55
-#define GCC_SNOC_BUS_TIMEOUT2_BCR 56
-#define GCC_SNOC_BUS_TIMEOUT3_BCR 57
-#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58
-#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59
-#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60
-#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61
-#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62
-#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63
-#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64
-#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65
-#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66
-#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67
-#define GCC_TCSR_BCR 68
-#define GCC_QDSS_BCR 69
-#define GCC_MPM_BCR 70
-#define GCC_SPDM_BCR 71
-
-#endif
* back to u-boot world
*/
void efi_restore_gd(void);
-/* Call this to unset the current device name */
-void efi_clear_bootdev(void);
-/* Call this to set the current device name */
-void efi_set_bootdev(const char *dev, const char *devnr, const char *path,
- void *buffer, size_t buffer_size);
+
/* Called by networking code to memorize the dhcp ack package */
void efi_net_set_dhcp_ack(void *pkt, int len);
/* Print information about all loaded images */
/* No loader configured, stub out EFI_ENTRY */
static inline void efi_restore_gd(void) { }
-static inline void efi_clear_bootdev(void) { }
-static inline void efi_set_bootdev(const char *dev, const char *devnr,
- const char *path, void *buffer,
- size_t buffer_size) { }
static inline void efi_net_set_dhcp_ack(void *pkt, int len) { }
static inline void efi_print_image_infos(void *pc) { }
static inline efi_status_t efi_launch_capsules(void)
#endif /* CONFIG_IS_ENABLED(EFI_LOADER) */
+#if CONFIG_IS_ENABLED(EFI_BINARY_EXEC)
+/* Call this to unset the current device name */
+void efi_clear_bootdev(void);
+/* Call this to set the current device name */
+void efi_set_bootdev(const char *dev, const char *devnr, const char *path,
+ void *buffer, size_t buffer_size);
+#else
+static inline void efi_clear_bootdev(void) { }
+
+static inline void efi_set_bootdev(const char *dev, const char *devnr,
+ const char *path, void *buffer,
+ size_t buffer_size) { }
+#endif
+
/* Maximum number of configuration tables */
#define EFI_MAX_CONFIGURATION_TABLES 16
u16 **load_options);
/* Install device tree */
efi_status_t efi_install_fdt(void *fdt);
-/* Run loaded UEFI image */
-efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size);
+/* Execute loaded UEFI image */
+efi_status_t do_bootefi_exec(efi_handle_t handle, void *load_options);
/* Run loaded UEFI image with given fdt */
efi_status_t efi_binary_run(void *image, size_t size, void *fdt);
/* Initialize variable services */
/* size of multi-instance device path excluding end node */
efi_uintn_t efi_dp_size(const struct efi_device_path *dp);
struct efi_device_path *efi_dp_dup(const struct efi_device_path *dp);
-struct efi_device_path *efi_dp_append(const struct efi_device_path *dp1,
- const struct efi_device_path *dp2);
struct efi_device_path *efi_dp_append_node(const struct efi_device_path *dp,
const struct efi_device_path *node);
/* Create a device path node of given type, sub-type, length */
struct efi_device_path *efi_dp_from_lo(struct efi_load_option *lo,
const efi_guid_t *guid);
struct efi_device_path *efi_dp_concat(const struct efi_device_path *dp1,
- const struct efi_device_path *dp2);
+ const struct efi_device_path *dp2,
+ bool split_end_node);
struct efi_device_path *search_gpt_dp_node(struct efi_device_path *device_path);
efi_status_t efi_deserialize_load_option(struct efi_load_option *lo, u8 *data,
efi_uintn_t *size);
*/
extern void (*fastboot_progress_callback)(const char *msg);
+/**
+ * fastboot_getvar_all() - Writes current variable being listed from "all" to response.
+ *
+ * @response: Pointer to fastboot response buffer
+ */
+void fastboot_getvar_all(char *response);
+
/**
* fastboot_getvar() - Writes variable indicated by cmd_parameter to response.
*
#define FASTBOOT_VERSION "0.4"
+/*
+ * Signals u-boot fastboot code to send multiple responses by
+ * calling response generating function repeatedly until a OKAY/FAIL
+ * is generated as final response.
+ *
+ * This status code is only used internally to signal, must NOT
+ * be sent to host.
+ */
+#define FASTBOOT_MULTIRESPONSE_START ("MORE")
+
/* The 64 defined bytes plus \0 */
#define FASTBOOT_COMMAND_LEN (64 + 1)
#define FASTBOOT_RESPONSE_LEN (64 + 1)
FASTBOOT_COMMAND_OEM_PARTCONF,
FASTBOOT_COMMAND_OEM_BOOTBUS,
FASTBOOT_COMMAND_OEM_RUN,
+ FASTBOOT_COMMAND_OEM_CONSOLE,
FASTBOOT_COMMAND_ACMD,
FASTBOOT_COMMAND_UCMD,
FASTBOOT_COMMAND_COUNT
*/
void fastboot_data_complete(char *response);
+/**
+ * fastboot_handle_multiresponse() - Called for each response to send
+ *
+ * @cmd: Command id that requested multiresponse
+ * @response: Pointer to fastboot response buffer
+ */
+void fastboot_multiresponse(int cmd, char *response);
+
void fastboot_acmd_complete(void);
#endif /* _FASTBOOT_H_ */
int fwu_set_active_index(uint active_idx);
/**
- * fwu_get_image_index() - Get the Image Index to be used for capsule update
- * @image_index: The Image Index for the image
- *
- * The FWU multi bank update feature computes the value of image_index at
- * runtime, based on the bank to which the image needs to be written to.
- * Derive the image_index value for the image.
+ * fwu_get_dfu_alt_num() - Get the dfu_alt_num to be used for capsule update
+ * @image_index: The Image Index for the image
+ * @alt_num: pointer to store dfu_alt_num
*
* Currently, the capsule update driver uses the DFU framework for
* the updates. This function gets the DFU alt number which is to
- * be used as the Image Index
+ * be used for capsule update.
*
* Return: 0 if OK, -ve on error
*
*/
-int fwu_get_image_index(u8 *image_index);
+int fwu_get_dfu_alt_num(u8 image_index, u8 *alt_num);
/**
* fwu_revert_boot_index() - Revert the active index in the FWU metadata
* device
*/
#if defined(USE_HOSTCC)
-# if defined(CONFIG_FIT_SIGNATURE)
+# if CONFIG_IS_ENABLED(FIT_SIGNATURE)
# define IMAGE_ENABLE_SIGN 1
# define FIT_IMAGE_ENABLE_VERIFY 1
# include <openssl/evp.h>
* @mb: membuff to adjust
* @str: Place to put the line
* @maxlen: Maximum line length (excluding terminator)
+ * @must_fit: If true then str is empty if line doesn't fit
* Return: number of bytes read (including terminator) if a line has been
- * read, 0 if nothing was there
+ * read, 0 if nothing was there or line didn't fit when must_fit is set
*/
-int membuff_readline(struct membuff *mb, char *str, int maxlen, int minch);
+int membuff_readline(struct membuff *mb, char *str, int maxlen, int minch, bool must_fit);
/**
* membuff_extend_by() - expand a membuff
#ifndef _SMBIOS_H_
#define _SMBIOS_H_
-#include <dm/ofnode.h>
+#include <linux/types.h>
/* SMBIOS spec version implemented */
#define SMBIOS_MAJOR_VER 3
u64 struct_table_address;
};
-/* These two structures should use the same amount of 16-byte-aligned space */
-static_assert(ALIGN(16, sizeof(struct smbios_entry)) ==
- ALIGN(16, sizeof(struct smbios3_entry)));
-
/* BIOS characteristics */
#define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7)
#define BIOS_CHARACTERISTICS_UPGRADEABLE (1 << 11)
* @len: configuration table size
* @return: the 8-bit checksum
*/
-u8 table_compute_checksum(void *v, int len);
+u8 table_compute_checksum(const void *v, const int len);
#endif
#
# (C) Copyright 2015 Google, Inc
-obj-$(CONFIG_EFI_APP) += efi_app.o efi.o
+obj-$(CONFIG_EFI_APP) += efi_app.o efi.o efi_app_init.o
obj-$(CONFIG_EFI_STUB) += efi_info.o
CFLAGS_REMOVE_efi_stub.o := -mregparm=3 \
return 0;
}
-/**
- * efi_bind_block() - bind a new block device to an EFI device
- *
- * Binds a new top-level EFI_MEDIA device as well as a child block device so
- * that the block device can be accessed in U-Boot.
- *
- * The device can then be accessed using 'part list efi 0', 'fat ls efi 0:1',
- * for example, just like any other interface type.
- *
- * @handle: handle of the controller on which this driver is installed
- * @blkio: block io protocol proxied by this driver
- * @device_path: EFI device path structure for this
- * @len: Length of @device_path in bytes
- * @devp: Returns the bound device
- * Return: 0 if OK, -ve on error
- */
-int efi_bind_block(efi_handle_t handle, struct efi_block_io *blkio,
- struct efi_device_path *device_path, int len,
- struct udevice **devp)
-{
- struct efi_media_plat plat;
- struct udevice *dev;
- char name[18];
- int ret;
-
- plat.handle = handle;
- plat.blkio = blkio;
- plat.device_path = malloc(device_path->length);
- if (!plat.device_path)
- return log_msg_ret("path", -ENOMEM);
- memcpy(plat.device_path, device_path, device_path->length);
- ret = device_bind(dm_root(), DM_DRIVER_GET(efi_media), "efi_media",
- &plat, ofnode_null(), &dev);
- if (ret)
- return log_msg_ret("bind", ret);
-
- snprintf(name, sizeof(name), "efi_media_%x", dev_seq(dev));
- device_set_name(dev, name);
- *devp = dev;
-
- return 0;
-}
-
static efi_status_t setup_memory(struct efi_priv *priv)
{
struct efi_boot_services *boot = priv->boot;
global_data_ptr = NULL;
}
-/**
- * devpath_is_partition() - Figure out if a device path is a partition
- *
- * Checks if a device path refers to a partition on some media device. This
- * works by checking for a valid partition number in a hard-driver media device
- * as the final component of the device path.
- *
- * @path: device path
- * Return: true if a partition, false if not
- * (e.g. it might be media which contains partitions)
- */
-static bool devpath_is_partition(const struct efi_device_path *path)
-{
- const struct efi_device_path *p;
- bool was_part = false;
-
- for (p = path; p->type != DEVICE_PATH_TYPE_END;
- p = (void *)p + p->length) {
- was_part = false;
- if (p->type == DEVICE_PATH_TYPE_MEDIA_DEVICE &&
- p->sub_type == DEVICE_PATH_SUB_TYPE_HARD_DRIVE_PATH) {
- struct efi_device_path_hard_drive_path *hd =
- (void *)path;
-
- if (hd->partition_number)
- was_part = true;
- }
- }
-
- return was_part;
-}
-
-/**
- * setup_block() - Find all block devices and setup EFI devices for them
- *
- * Partitions are ignored, since U-Boot has partition handling. Errors with
- * particular devices produce a warning but execution continues to try to
- * find others.
- *
- * Return: 0 if found, -ENOSYS if there is no boot-services table, -ENOTSUPP
- * if a required protocol is not supported
- */
-static int setup_block(void)
-{
- efi_guid_t efi_blkio_guid = EFI_BLOCK_IO_PROTOCOL_GUID;
- efi_guid_t efi_devpath_guid = EFI_DEVICE_PATH_PROTOCOL_GUID;
- efi_guid_t efi_pathutil_guid = EFI_DEVICE_PATH_UTILITIES_PROTOCOL_GUID;
- efi_guid_t efi_pathtext_guid = EFI_DEVICE_PATH_TO_TEXT_PROTOCOL_GUID;
- struct efi_boot_services *boot = efi_get_boot();
- struct efi_device_path_utilities_protocol *util;
- struct efi_device_path_to_text_protocol *text;
- struct efi_device_path *path;
- struct efi_block_io *blkio;
- efi_uintn_t num_handles;
- efi_handle_t *handle;
- int ret, i;
-
- if (!boot)
- return log_msg_ret("sys", -ENOSYS);
-
- /* Find all devices which support the block I/O protocol */
- ret = boot->locate_handle_buffer(BY_PROTOCOL, &efi_blkio_guid, NULL,
- &num_handles, &handle);
- if (ret)
- return log_msg_ret("loc", -ENOTSUPP);
- log_debug("Found %d handles:\n", (int)num_handles);
-
- /* We need to look up the path size and convert it to text */
- ret = boot->locate_protocol(&efi_pathutil_guid, NULL, (void **)&util);
- if (ret)
- return log_msg_ret("util", -ENOTSUPP);
- ret = boot->locate_protocol(&efi_pathtext_guid, NULL, (void **)&text);
- if (ret)
- return log_msg_ret("text", -ENOTSUPP);
-
- for (i = 0; i < num_handles; i++) {
- struct udevice *dev;
- const u16 *name;
- bool is_part;
- int len;
-
- ret = boot->handle_protocol(handle[i], &efi_devpath_guid,
- (void **)&path);
- if (ret) {
- log_warning("- devpath %d failed (ret=%d)\n", i, ret);
- continue;
- }
-
- ret = boot->handle_protocol(handle[i], &efi_blkio_guid,
- (void **)&blkio);
- if (ret) {
- log_warning("- blkio %d failed (ret=%d)\n", i, ret);
- continue;
- }
-
- name = text->convert_device_path_to_text(path, true, false);
- is_part = devpath_is_partition(path);
-
- if (!is_part) {
- len = util->get_device_path_size(path);
- ret = efi_bind_block(handle[i], blkio, path, len, &dev);
- if (ret) {
- log_warning("- blkio bind %d failed (ret=%d)\n",
- i, ret);
- continue;
- }
- } else {
- dev = NULL;
- }
-
- /*
- * Show the device name if we created one. Otherwise indicate
- * that it is a partition.
- */
- printf("%2d: %-12s %ls\n", i, dev ? dev->name : "<partition>",
- name);
- }
- boot->free_pool(handle);
-
- return 0;
-}
-
-/**
- * dm_scan_other() - Scan for UEFI devices that should be available to U-Boot
- *
- * This sets up block devices within U-Boot for those found in UEFI. With this,
- * U-Boot can access those devices
- *
- * @pre_reloc_only: true to only bind pre-relocation devices (ignored)
- * Returns: 0 on success, -ve on error
- */
-int dm_scan_other(bool pre_reloc_only)
-{
- if (gd->flags & GD_FLG_RELOC) {
- int ret;
-
- ret = setup_block();
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
static void scan_tables(struct efi_system_table *sys_table)
{
efi_guid_t acpi = EFI_ACPI_TABLE_GUID;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * EFI-app board implementation
+ *
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <dm.h>
+#include <efi.h>
+#include <efi_api.h>
+#include <errno.h>
+#include <malloc.h>
+#include <asm/global_data.h>
+#include <dm/device-internal.h>
+#include <dm/root.h>
+#include <linux/types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * efi_bind_block() - bind a new block device to an EFI device
+ *
+ * Binds a new top-level EFI_MEDIA device as well as a child block device so
+ * that the block device can be accessed in U-Boot.
+ *
+ * The device can then be accessed using 'part list efi 0', 'fat ls efi 0:1',
+ * for example, just like any other interface type.
+ *
+ * @handle: handle of the controller on which this driver is installed
+ * @blkio: block io protocol proxied by this driver
+ * @device_path: EFI device path structure for this
+ * @len: Length of @device_path in bytes
+ * @devp: Returns the bound device
+ * Return: 0 if OK, -ve on error
+ */
+int efi_bind_block(efi_handle_t handle, struct efi_block_io *blkio,
+ struct efi_device_path *device_path, int len,
+ struct udevice **devp)
+{
+ struct efi_media_plat plat;
+ struct udevice *dev;
+ char name[18];
+ int ret;
+
+ plat.handle = handle;
+ plat.blkio = blkio;
+ plat.device_path = malloc(device_path->length);
+ if (!plat.device_path)
+ return log_msg_ret("path", -ENOMEM);
+ memcpy(plat.device_path, device_path, device_path->length);
+ ret = device_bind(dm_root(), DM_DRIVER_GET(efi_media), "efi_media",
+ &plat, ofnode_null(), &dev);
+ if (ret)
+ return log_msg_ret("bind", ret);
+
+ snprintf(name, sizeof(name), "efi_media_%x", dev_seq(dev));
+ device_set_name(dev, name);
+ *devp = dev;
+
+ return 0;
+}
+
+/**
+ * devpath_is_partition() - Figure out if a device path is a partition
+ *
+ * Checks if a device path refers to a partition on some media device. This
+ * works by checking for a valid partition number in a hard-driver media device
+ * as the final component of the device path.
+ *
+ * @path: device path
+ * Return: true if a partition, false if not
+ * (e.g. it might be media which contains partitions)
+ */
+static bool devpath_is_partition(const struct efi_device_path *path)
+{
+ const struct efi_device_path *p;
+ bool was_part = false;
+
+ for (p = path; p->type != DEVICE_PATH_TYPE_END;
+ p = (void *)p + p->length) {
+ was_part = false;
+ if (p->type == DEVICE_PATH_TYPE_MEDIA_DEVICE &&
+ p->sub_type == DEVICE_PATH_SUB_TYPE_HARD_DRIVE_PATH) {
+ struct efi_device_path_hard_drive_path *hd =
+ (void *)path;
+
+ if (hd->partition_number)
+ was_part = true;
+ }
+ }
+
+ return was_part;
+}
+
+/**
+ * setup_block() - Find all block devices and setup EFI devices for them
+ *
+ * Partitions are ignored, since U-Boot has partition handling. Errors with
+ * particular devices produce a warning but execution continues to try to
+ * find others.
+ *
+ * Return: 0 if found, -ENOSYS if there is no boot-services table, -ENOTSUPP
+ * if a required protocol is not supported
+ */
+static int setup_block(void)
+{
+ efi_guid_t efi_blkio_guid = EFI_BLOCK_IO_PROTOCOL_GUID;
+ efi_guid_t efi_devpath_guid = EFI_DEVICE_PATH_PROTOCOL_GUID;
+ efi_guid_t efi_pathutil_guid = EFI_DEVICE_PATH_UTILITIES_PROTOCOL_GUID;
+ efi_guid_t efi_pathtext_guid = EFI_DEVICE_PATH_TO_TEXT_PROTOCOL_GUID;
+ struct efi_boot_services *boot = efi_get_boot();
+ struct efi_device_path_utilities_protocol *util;
+ struct efi_device_path_to_text_protocol *text;
+ struct efi_device_path *path;
+ struct efi_block_io *blkio;
+ efi_uintn_t num_handles;
+ efi_handle_t *handle;
+ int ret, i;
+
+ if (!boot)
+ return log_msg_ret("sys", -ENOSYS);
+
+ /* Find all devices which support the block I/O protocol */
+ ret = boot->locate_handle_buffer(BY_PROTOCOL, &efi_blkio_guid, NULL,
+ &num_handles, &handle);
+ if (ret)
+ return log_msg_ret("loc", -ENOTSUPP);
+ log_debug("Found %d handles:\n", (int)num_handles);
+
+ /* We need to look up the path size and convert it to text */
+ ret = boot->locate_protocol(&efi_pathutil_guid, NULL, (void **)&util);
+ if (ret)
+ return log_msg_ret("util", -ENOTSUPP);
+ ret = boot->locate_protocol(&efi_pathtext_guid, NULL, (void **)&text);
+ if (ret)
+ return log_msg_ret("text", -ENOTSUPP);
+
+ for (i = 0; i < num_handles; i++) {
+ struct udevice *dev;
+ const u16 *name;
+ bool is_part;
+ int len;
+
+ ret = boot->handle_protocol(handle[i], &efi_devpath_guid,
+ (void **)&path);
+ if (ret) {
+ log_warning("- devpath %d failed (ret=%d)\n", i, ret);
+ continue;
+ }
+
+ ret = boot->handle_protocol(handle[i], &efi_blkio_guid,
+ (void **)&blkio);
+ if (ret) {
+ log_warning("- blkio %d failed (ret=%d)\n", i, ret);
+ continue;
+ }
+
+ name = text->convert_device_path_to_text(path, true, false);
+ is_part = devpath_is_partition(path);
+
+ if (!is_part) {
+ len = util->get_device_path_size(path);
+ ret = efi_bind_block(handle[i], blkio, path, len, &dev);
+ if (ret) {
+ log_warning("- blkio bind %d failed (ret=%d)\n",
+ i, ret);
+ continue;
+ }
+ } else {
+ dev = NULL;
+ }
+
+ /*
+ * Show the device name if we created one. Otherwise indicate
+ * that it is a partition.
+ */
+ printf("%2d: %-12s %ls\n", i, dev ? dev->name : "<partition>",
+ name);
+ }
+ boot->free_pool(handle);
+
+ return 0;
+}
+
+/**
+ * board_early_init_r() - Scan for UEFI devices that should be available
+ *
+ * This sets up block devices within U-Boot for those found in UEFI. With this,
+ * U-Boot can access those devices
+ *
+ * Returns: 0 on success, -ve on error
+ */
+int board_early_init_r(void)
+{
+ if (gd->flags & GD_FLG_RELOC) {
+ int ret;
+
+ ret = setup_block();
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
if EFI_LOADER
-config BOOTEFI_BOOTMGR
+config EFI_BINARY_EXEC
+ bool "Execute UEFI binary"
+ default y
+ help
+ Select this option if you want to execute the UEFI binary after
+ loading it with U-Boot load commands or other methods.
+ You may enable CMD_BOOTEFI_BINARY so that you can use bootefi
+ command to do that.
+
+config EFI_BOOTMGR
bool "UEFI Boot Manager"
default y
select BOOTMETH_GLOBAL if BOOTSTD
CFLAGS_REMOVE_boothart.o := $(CFLAGS_NON_EFI)
CFLAGS_helloworld.o := $(CFLAGS_EFI) -Os -ffreestanding
CFLAGS_REMOVE_helloworld.o := $(CFLAGS_NON_EFI)
+CFLAGS_smbiosdump.o := $(CFLAGS_EFI) -Os -ffreestanding
+CFLAGS_REMOVE_smbiosdump.o := $(CFLAGS_NON_EFI)
CFLAGS_dtbdump.o := $(CFLAGS_EFI) -Os -ffreestanding
CFLAGS_REMOVE_dtbdump.o := $(CFLAGS_NON_EFI)
CFLAGS_initrddump.o := $(CFLAGS_EFI) -Os -ffreestanding
targets += helloworld.o
endif
+ifneq ($(CONFIG_GENERATE_SMBIOS_TABLE),)
+always += smbiosdump.efi
+targets += smbiosdump.o
+endif
+
ifeq ($(CONFIG_GENERATE_ACPI_TABLE),)
always += dtbdump.efi
targets += dtbdump.o
endif
obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o
-obj-$(CONFIG_BOOTEFI_BOOTMGR) += efi_bootmgr.o
+obj-$(CONFIG_EFI_BOOTMGR) += efi_bootmgr.o
+obj-$(CONFIG_EFI_BINARY_EXEC) += efi_bootbin.o
obj-y += efi_boottime.o
obj-y += efi_helper.o
obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += efi_capsule.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * For the code moved from cmd/bootefi.c
+ * Copyright (c) 2016 Alexander Graf
+ */
+
+#define LOG_CATEGORY LOGC_EFI
+
+#include <charset.h>
+#include <efi.h>
+#include <efi_loader.h>
+#include <env.h>
+#include <image.h>
+#include <log.h>
+#include <malloc.h>
+
+static struct efi_device_path *bootefi_image_path;
+static struct efi_device_path *bootefi_device_path;
+static void *image_addr;
+static size_t image_size;
+
+/**
+ * efi_get_image_parameters() - return image parameters
+ *
+ * @img_addr: address of loaded image in memory
+ * @img_size: size of loaded image
+ */
+void efi_get_image_parameters(void **img_addr, size_t *img_size)
+{
+ *img_addr = image_addr;
+ *img_size = image_size;
+}
+
+/**
+ * efi_clear_bootdev() - clear boot device
+ */
+void efi_clear_bootdev(void)
+{
+ efi_free_pool(bootefi_device_path);
+ efi_free_pool(bootefi_image_path);
+ bootefi_device_path = NULL;
+ bootefi_image_path = NULL;
+ image_addr = NULL;
+ image_size = 0;
+}
+
+/**
+ * efi_set_bootdev() - set boot device
+ *
+ * This function is called when a file is loaded, e.g. via the 'load' command.
+ * We use the path to this file to inform the UEFI binary about the boot device.
+ *
+ * @dev: device, e.g. "MMC"
+ * @devnr: number of the device, e.g. "1:2"
+ * @path: path to file loaded
+ * @buffer: buffer with file loaded
+ * @buffer_size: size of file loaded
+ */
+void efi_set_bootdev(const char *dev, const char *devnr, const char *path,
+ void *buffer, size_t buffer_size)
+{
+ struct efi_device_path *device, *image;
+ efi_status_t ret;
+
+ log_debug("dev=%s, devnr=%s, path=%s, buffer=%p, size=%zx\n", dev,
+ devnr, path, buffer, buffer_size);
+
+ /* Forget overwritten image */
+ if (buffer + buffer_size >= image_addr &&
+ image_addr + image_size >= buffer)
+ efi_clear_bootdev();
+
+ /* Remember only PE-COFF and FIT images */
+ if (efi_check_pe(buffer, buffer_size, NULL) != EFI_SUCCESS) {
+ if (IS_ENABLED(CONFIG_FIT) &&
+ !fit_check_format(buffer, IMAGE_SIZE_INVAL)) {
+ /*
+ * FIT images of type EFI_OS are started via command
+ * bootm. We should not use their boot device with the
+ * bootefi command.
+ */
+ buffer = 0;
+ buffer_size = 0;
+ } else {
+ log_debug("- not remembering image\n");
+ return;
+ }
+ }
+
+ /* efi_set_bootdev() is typically called repeatedly, recover memory */
+ efi_clear_bootdev();
+
+ image_addr = buffer;
+ image_size = buffer_size;
+
+ ret = efi_dp_from_name(dev, devnr, path, &device, &image);
+ if (ret == EFI_SUCCESS) {
+ bootefi_device_path = device;
+ if (image) {
+ /* FIXME: image should not contain device */
+ struct efi_device_path *image_tmp = image;
+
+ efi_dp_split_file_path(image, &device, &image);
+ efi_free_pool(image_tmp);
+ }
+ bootefi_image_path = image;
+ log_debug("- boot device %pD\n", device);
+ if (image)
+ log_debug("- image %pD\n", image);
+ } else {
+ log_debug("- efi_dp_from_name() failed, err=%lx\n", ret);
+ efi_clear_bootdev();
+ }
+}
+
+/**
+ * efi_run_image() - run loaded UEFI image
+ *
+ * @source_buffer: memory address of the UEFI image
+ * @source_size: size of the UEFI image
+ * Return: status code
+ */
+efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size)
+{
+ efi_handle_t mem_handle = NULL, handle;
+ struct efi_device_path *file_path = NULL;
+ struct efi_device_path *msg_path;
+ efi_status_t ret, ret2;
+ u16 *load_options;
+
+ if (!bootefi_device_path || !bootefi_image_path) {
+ log_debug("Not loaded from disk\n");
+ /*
+ * Special case for efi payload not loaded from disk,
+ * such as 'bootefi hello' or for example payload
+ * loaded directly into memory via JTAG, etc:
+ */
+ file_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE,
+ (uintptr_t)source_buffer,
+ source_size);
+ /*
+ * Make sure that device for device_path exist
+ * in load_image(). Otherwise, shell and grub will fail.
+ */
+ ret = efi_install_multiple_protocol_interfaces(&mem_handle,
+ &efi_guid_device_path,
+ file_path, NULL);
+ if (ret != EFI_SUCCESS)
+ goto out;
+ msg_path = file_path;
+ } else {
+ file_path = efi_dp_concat(bootefi_device_path,
+ bootefi_image_path, false);
+ msg_path = bootefi_image_path;
+ log_debug("Loaded from disk\n");
+ }
+
+ log_info("Booting %pD\n", msg_path);
+
+ ret = EFI_CALL(efi_load_image(false, efi_root, file_path, source_buffer,
+ source_size, &handle));
+ if (ret != EFI_SUCCESS) {
+ log_err("Loading image failed\n");
+ goto out;
+ }
+
+ /* Transfer environment variable as load options */
+ ret = efi_env_set_load_options(handle, "bootargs", &load_options);
+ if (ret != EFI_SUCCESS)
+ goto out;
+
+ ret = do_bootefi_exec(handle, load_options);
+
+out:
+ ret2 = efi_uninstall_multiple_protocol_interfaces(mem_handle,
+ &efi_guid_device_path,
+ file_path, NULL);
+ efi_free_pool(file_path);
+ return (ret != EFI_SUCCESS) ? ret : ret2;
+}
+
+/**
+ * efi_binary_run() - run loaded UEFI image
+ *
+ * @image: memory address of the UEFI image
+ * @size: size of the UEFI image
+ * @fdt: device-tree
+ *
+ * Execute an EFI binary image loaded at @image.
+ * @size may be zero if the binary is loaded with U-Boot load command.
+ *
+ * Return: status code
+ */
+efi_status_t efi_binary_run(void *image, size_t size, void *fdt)
+{
+ efi_status_t ret;
+
+ /* Initialize EFI drivers */
+ ret = efi_init_obj_list();
+ if (ret != EFI_SUCCESS) {
+ log_err("Error: Cannot initialize UEFI sub-system, r = %lu\n",
+ ret & ~EFI_ERROR_MASK);
+ return -1;
+ }
+
+ ret = efi_install_fdt(fdt);
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ return efi_run_image(image, size);
+}
* EFI boot manager
*
* Copyright (c) 2017 Rob Clark
- * For the code moved from cmd/bootefi.c
- * Copyright (c) 2016 Alexander Graf
*/
#define LOG_CATEGORY LOGC_EFI
#include <efi_variable.h>
#include <asm/unaligned.h>
-/* TODO: temporarily added here; clean up later */
-#include <bootm.h>
-#include <efi_selftest.h>
-#include <env.h>
-#include <mapmem.h>
-#include <asm/global_data.h>
-#include <linux/libfdt.h>
-#include <linux/libfdt_env.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct efi_boot_services *bs;
static const struct efi_runtime_services *rs;
if (!dp)
continue;
- dp = efi_dp_append(dp, fp);
+ dp = efi_dp_concat(dp, fp, false);
if (!dp)
continue;
return ret;
}
-static struct efi_device_path *bootefi_image_path;
-static struct efi_device_path *bootefi_device_path;
-static void *image_addr;
-static size_t image_size;
-
-/**
- * efi_get_image_parameters() - return image parameters
- *
- * @img_addr: address of loaded image in memory
- * @img_size: size of loaded image
- */
-void efi_get_image_parameters(void **img_addr, size_t *img_size)
-{
- *img_addr = image_addr;
- *img_size = image_size;
-}
-
-/**
- * efi_clear_bootdev() - clear boot device
- */
-void efi_clear_bootdev(void)
-{
- efi_free_pool(bootefi_device_path);
- efi_free_pool(bootefi_image_path);
- bootefi_device_path = NULL;
- bootefi_image_path = NULL;
- image_addr = NULL;
- image_size = 0;
-}
-
-/**
- * efi_set_bootdev() - set boot device
- *
- * This function is called when a file is loaded, e.g. via the 'load' command.
- * We use the path to this file to inform the UEFI binary about the boot device.
- *
- * @dev: device, e.g. "MMC"
- * @devnr: number of the device, e.g. "1:2"
- * @path: path to file loaded
- * @buffer: buffer with file loaded
- * @buffer_size: size of file loaded
- */
-void efi_set_bootdev(const char *dev, const char *devnr, const char *path,
- void *buffer, size_t buffer_size)
-{
- struct efi_device_path *device, *image;
- efi_status_t ret;
-
- log_debug("dev=%s, devnr=%s, path=%s, buffer=%p, size=%zx\n", dev,
- devnr, path, buffer, buffer_size);
-
- /* Forget overwritten image */
- if (buffer + buffer_size >= image_addr &&
- image_addr + image_size >= buffer)
- efi_clear_bootdev();
-
- /* Remember only PE-COFF and FIT images */
- if (efi_check_pe(buffer, buffer_size, NULL) != EFI_SUCCESS) {
- if (IS_ENABLED(CONFIG_FIT) &&
- !fit_check_format(buffer, IMAGE_SIZE_INVAL)) {
- /*
- * FIT images of type EFI_OS are started via command
- * bootm. We should not use their boot device with the
- * bootefi command.
- */
- buffer = 0;
- buffer_size = 0;
- } else {
- log_debug("- not remembering image\n");
- return;
- }
- }
-
- /* efi_set_bootdev() is typically called repeatedly, recover memory */
- efi_clear_bootdev();
-
- image_addr = buffer;
- image_size = buffer_size;
-
- ret = efi_dp_from_name(dev, devnr, path, &device, &image);
- if (ret == EFI_SUCCESS) {
- bootefi_device_path = device;
- if (image) {
- /* FIXME: image should not contain device */
- struct efi_device_path *image_tmp = image;
-
- efi_dp_split_file_path(image, &device, &image);
- efi_free_pool(image_tmp);
- }
- bootefi_image_path = image;
- log_debug("- boot device %pD\n", device);
- if (image)
- log_debug("- image %pD\n", image);
- } else {
- log_debug("- efi_dp_from_name() failed, err=%lx\n", ret);
- efi_clear_bootdev();
- }
-}
-
-/**
- * efi_env_set_load_options() - set load options from environment variable
- *
- * @handle: the image handle
- * @env_var: name of the environment variable
- * @load_options: pointer to load options (output)
- * Return: status code
- */
-efi_status_t efi_env_set_load_options(efi_handle_t handle,
- const char *env_var,
- u16 **load_options)
-{
- const char *env = env_get(env_var);
- size_t size;
- u16 *pos;
- efi_status_t ret;
-
- *load_options = NULL;
- if (!env)
- return EFI_SUCCESS;
- size = sizeof(u16) * (utf8_utf16_strlen(env) + 1);
- pos = calloc(size, 1);
- if (!pos)
- return EFI_OUT_OF_RESOURCES;
- *load_options = pos;
- utf8_utf16_strcpy(&pos, env);
- ret = efi_set_load_options(handle, size, *load_options);
- if (ret != EFI_SUCCESS) {
- free(*load_options);
- *load_options = NULL;
- }
- return ret;
-}
-
-/**
- * copy_fdt() - Copy the device tree to a new location available to EFI
- *
- * The FDT is copied to a suitable location within the EFI memory map.
- * Additional 12 KiB are added to the space in case the device tree needs to be
- * expanded later with fdt_open_into().
- *
- * @fdtp: On entry a pointer to the flattened device tree.
- * On exit a pointer to the copy of the flattened device tree.
- * FDT start
- * Return: status code
- */
-static efi_status_t copy_fdt(void **fdtp)
-{
- unsigned long fdt_ram_start = -1L, fdt_pages;
- efi_status_t ret = 0;
- void *fdt, *new_fdt;
- u64 new_fdt_addr;
- uint fdt_size;
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- u64 ram_start = gd->bd->bi_dram[i].start;
- u64 ram_size = gd->bd->bi_dram[i].size;
-
- if (!ram_size)
- continue;
-
- if (ram_start < fdt_ram_start)
- fdt_ram_start = ram_start;
- }
-
- /*
- * Give us at least 12 KiB of breathing room in case the device tree
- * needs to be expanded later.
- */
- fdt = *fdtp;
- fdt_pages = efi_size_in_pages(fdt_totalsize(fdt) + 0x3000);
- fdt_size = fdt_pages << EFI_PAGE_SHIFT;
-
- ret = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES,
- EFI_ACPI_RECLAIM_MEMORY, fdt_pages,
- &new_fdt_addr);
- if (ret != EFI_SUCCESS) {
- log_err("ERROR: Failed to reserve space for FDT\n");
- goto done;
- }
- new_fdt = (void *)(uintptr_t)new_fdt_addr;
- memcpy(new_fdt, fdt, fdt_totalsize(fdt));
- fdt_set_totalsize(new_fdt, fdt_size);
-
- *fdtp = (void *)(uintptr_t)new_fdt_addr;
-done:
- return ret;
-}
-
-/**
- * get_config_table() - get configuration table
- *
- * @guid: GUID of the configuration table
- * Return: pointer to configuration table or NULL
- */
-static void *get_config_table(const efi_guid_t *guid)
-{
- size_t i;
-
- for (i = 0; i < systab.nr_tables; i++) {
- if (!guidcmp(guid, &systab.tables[i].guid))
- return systab.tables[i].table;
- }
- return NULL;
-}
-
-/**
- * efi_install_fdt() - install device tree
- *
- * If fdt is not EFI_FDT_USE_INTERNAL, the device tree located at that memory
- * address will be installed as configuration table, otherwise the device
- * tree located at the address indicated by environment variable fdt_addr or as
- * fallback fdtcontroladdr will be used.
- *
- * On architectures using ACPI tables device trees shall not be installed as
- * configuration table.
- *
- * @fdt: address of device tree or EFI_FDT_USE_INTERNAL to use
- * the hardware device tree as indicated by environment variable
- * fdt_addr or as fallback the internal device tree as indicated by
- * the environment variable fdtcontroladdr
- * Return: status code
- */
-efi_status_t efi_install_fdt(void *fdt)
-{
- struct bootm_headers img = { 0 };
- efi_status_t ret;
-
- /*
- * The EBBR spec requires that we have either an FDT or an ACPI table
- * but not both.
- */
- if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) && fdt)
- log_warning("WARNING: Can't have ACPI table and device tree - ignoring DT.\n");
-
- if (fdt == EFI_FDT_USE_INTERNAL) {
- const char *fdt_opt;
- uintptr_t fdt_addr;
-
- /* Look for device tree that is already installed */
- if (get_config_table(&efi_guid_fdt))
- return EFI_SUCCESS;
- /* Check if there is a hardware device tree */
- fdt_opt = env_get("fdt_addr");
- /* Use our own device tree as fallback */
- if (!fdt_opt) {
- fdt_opt = env_get("fdtcontroladdr");
- if (!fdt_opt) {
- log_err("ERROR: need device tree\n");
- return EFI_NOT_FOUND;
- }
- }
- fdt_addr = hextoul(fdt_opt, NULL);
- if (!fdt_addr) {
- log_err("ERROR: invalid $fdt_addr or $fdtcontroladdr\n");
- return EFI_LOAD_ERROR;
- }
- fdt = map_sysmem(fdt_addr, 0);
- }
-
- /* Install device tree */
- if (fdt_check_header(fdt)) {
- log_err("ERROR: invalid device tree\n");
- return EFI_LOAD_ERROR;
- }
-
- /* Create memory reservations as indicated by the device tree */
- efi_carve_out_dt_rsv(fdt);
-
- if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE))
- return EFI_SUCCESS;
-
- /* Prepare device tree for payload */
- ret = copy_fdt(&fdt);
- if (ret) {
- log_err("ERROR: out of memory\n");
- return EFI_OUT_OF_RESOURCES;
- }
-
- if (image_setup_libfdt(&img, fdt, NULL)) {
- log_err("ERROR: failed to process device tree\n");
- return EFI_LOAD_ERROR;
- }
-
- efi_try_purge_kaslr_seed(fdt);
-
- if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) {
- ret = efi_tcg2_measure_dtb(fdt);
- if (ret == EFI_SECURITY_VIOLATION) {
- log_err("ERROR: failed to measure DTB\n");
- return ret;
- }
- }
-
- /* Install device tree as UEFI table */
- ret = efi_install_configuration_table(&efi_guid_fdt, fdt);
- if (ret != EFI_SUCCESS) {
- log_err("ERROR: failed to install device tree\n");
- return ret;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- * do_bootefi_exec() - execute EFI binary
- *
- * The image indicated by @handle is started. When it returns the allocated
- * memory for the @load_options is freed.
- *
- * @handle: handle of loaded image
- * @load_options: load options
- * Return: status code
- *
- * Load the EFI binary into a newly assigned memory unwinding the relocation
- * information, install the loaded image protocol, and call the binary.
- */
-static efi_status_t do_bootefi_exec(efi_handle_t handle, void *load_options)
-{
- efi_status_t ret;
- efi_uintn_t exit_data_size = 0;
- u16 *exit_data = NULL;
- struct efi_event *evt;
-
- /* On ARM switch from EL3 or secure mode to EL2 or non-secure mode */
- switch_to_non_secure_mode();
-
- /*
- * The UEFI standard requires that the watchdog timer is set to five
- * minutes when invoking an EFI boot option.
- *
- * Unified Extensible Firmware Interface (UEFI), version 2.7 Errata A
- * 7.5. Miscellaneous Boot Services - EFI_BOOT_SERVICES.SetWatchdogTimer
- */
- ret = efi_set_watchdog(300);
- if (ret != EFI_SUCCESS) {
- log_err("ERROR: Failed to set watchdog timer\n");
- goto out;
- }
-
- /* Call our payload! */
- ret = EFI_CALL(efi_start_image(handle, &exit_data_size, &exit_data));
- if (ret != EFI_SUCCESS) {
- log_err("## Application failed, r = %lu\n",
- ret & ~EFI_ERROR_MASK);
- if (exit_data) {
- log_err("## %ls\n", exit_data);
- efi_free_pool(exit_data);
- }
- }
-
- efi_restore_gd();
-
-out:
- free(load_options);
-
- if (IS_ENABLED(CONFIG_EFI_LOAD_FILE2_INITRD)) {
- if (efi_initrd_deregister() != EFI_SUCCESS)
- log_err("Failed to remove loadfile2 for initrd\n");
- }
-
- /* Notify EFI_EVENT_GROUP_RETURN_TO_EFIBOOTMGR event group. */
- list_for_each_entry(evt, &efi_events, link) {
- if (evt->group &&
- !guidcmp(evt->group,
- &efi_guid_event_group_return_to_efibootmgr)) {
- efi_signal_event(evt);
- EFI_CALL(systab.boottime->close_event(evt));
- break;
- }
- }
-
- /* Control is returned to U-Boot, disable EFI watchdog */
- efi_set_watchdog(0);
-
- return ret;
-}
-
/**
* efi_bootmgr_run() - execute EFI boot manager
* @fdt: Flat device tree
return do_bootefi_exec(handle, load_options);
}
-
-/**
- * efi_run_image() - run loaded UEFI image
- *
- * @source_buffer: memory address of the UEFI image
- * @source_size: size of the UEFI image
- * Return: status code
- */
-efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size)
-{
- efi_handle_t mem_handle = NULL, handle;
- struct efi_device_path *file_path = NULL;
- struct efi_device_path *msg_path;
- efi_status_t ret, ret2;
- u16 *load_options;
-
- if (!bootefi_device_path || !bootefi_image_path) {
- log_debug("Not loaded from disk\n");
- /*
- * Special case for efi payload not loaded from disk,
- * such as 'bootefi hello' or for example payload
- * loaded directly into memory via JTAG, etc:
- */
- file_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE,
- (uintptr_t)source_buffer,
- source_size);
- /*
- * Make sure that device for device_path exist
- * in load_image(). Otherwise, shell and grub will fail.
- */
- ret = efi_install_multiple_protocol_interfaces(&mem_handle,
- &efi_guid_device_path,
- file_path, NULL);
- if (ret != EFI_SUCCESS)
- goto out;
- msg_path = file_path;
- } else {
- file_path = efi_dp_append(bootefi_device_path,
- bootefi_image_path);
- msg_path = bootefi_image_path;
- log_debug("Loaded from disk\n");
- }
-
- log_info("Booting %pD\n", msg_path);
-
- ret = EFI_CALL(efi_load_image(false, efi_root, file_path, source_buffer,
- source_size, &handle));
- if (ret != EFI_SUCCESS) {
- log_err("Loading image failed\n");
- goto out;
- }
-
- /* Transfer environment variable as load options */
- ret = efi_env_set_load_options(handle, "bootargs", &load_options);
- if (ret != EFI_SUCCESS)
- goto out;
-
- ret = do_bootefi_exec(handle, load_options);
-
-out:
- ret2 = efi_uninstall_multiple_protocol_interfaces(mem_handle,
- &efi_guid_device_path,
- file_path, NULL);
- efi_free_pool(file_path);
- return (ret != EFI_SUCCESS) ? ret : ret2;
-}
-
-/**
- * efi_binary_run() - run loaded UEFI image
- *
- * @image: memory address of the UEFI image
- * @size: size of the UEFI image
- * @fdt: device-tree
- *
- * Execute an EFI binary image loaded at @image.
- * @size may be zero if the binary is loaded with U-Boot load command.
- *
- * Return: status code
- */
-efi_status_t efi_binary_run(void *image, size_t size, void *fdt)
-{
- efi_status_t ret;
-
- /* Initialize EFI drivers */
- ret = efi_init_obj_list();
- if (ret != EFI_SUCCESS) {
- log_err("Error: Cannot initialize UEFI sub-system, r = %lu\n",
- ret & ~EFI_ERROR_MASK);
- return -1;
- }
-
- ret = efi_install_fdt(fdt);
- if (ret != EFI_SUCCESS)
- return ret;
-
- return efi_run_image(image, size);
-}
if (device_path) {
info->device_handle = efi_dp_find_obj(device_path, NULL, NULL);
- dp = efi_dp_append(device_path, file_path);
+ dp = efi_dp_concat(device_path, file_path, false);
if (!dp) {
ret = EFI_OUT_OF_RESOURCES;
goto failure;
}
/**
- * efi_dp_append_or_concatenate() - Append or concatenate two device paths.
- * Concatenated device path will be separated
- * by a sub-type 0xff end node
+ * efi_dp_concat() - Concatenate two device paths and add and terminate them
+ * with an end node.
*
- * @dp1: First device path
- * @dp2: Second device path
- * @concat: If true the two device paths will be concatenated and separated
- * by an end of entrire device path sub-type 0xff end node.
- * If true the second device path will be appended to the first and
- * terminated by an end node
+ * @dp1: First device path
+ * @dp2: Second device path
+ * @split_end_node: If true the two device paths will be concatenated and
+ * separated by an end node (DEVICE_PATH_SUB_TYPE_END).
+ * If false the second device path will be concatenated to the
+ * first one as-is.
*
* Return:
* concatenated device path or NULL. Caller must free the returned value
*/
-static struct
-efi_device_path *efi_dp_append_or_concatenate(const struct efi_device_path *dp1,
- const struct efi_device_path *dp2,
- bool concat)
+struct
+efi_device_path *efi_dp_concat(const struct efi_device_path *dp1,
+ const struct efi_device_path *dp2,
+ bool split_end_node)
{
struct efi_device_path *ret;
- size_t end_size = sizeof(END);
+ size_t end_size;
- if (concat)
- end_size = 2 * sizeof(END);
if (!dp1 && !dp2) {
/* return an end node */
ret = efi_dp_dup(&END);
/* both dp1 and dp2 are non-null */
unsigned sz1 = efi_dp_size(dp1);
unsigned sz2 = efi_dp_size(dp2);
- void *p = efi_alloc(sz1 + sz2 + end_size);
+ void *p;
+
+ if (split_end_node)
+ end_size = 2 * sizeof(END);
+ else
+ end_size = sizeof(END);
+ p = efi_alloc(sz1 + sz2 + end_size);
if (!p)
return NULL;
ret = p;
memcpy(p, dp1, sz1);
p += sz1;
- if (concat) {
+ if (split_end_node) {
memcpy(p, &END, sizeof(END));
p += sizeof(END);
}
return ret;
}
-/**
- * efi_dp_append() - Append a device to an existing device path.
- *
- * @dp1: First device path
- * @dp2: Second device path
- *
- * Return:
- * concatenated device path or NULL. Caller must free the returned value
- */
-struct efi_device_path *efi_dp_append(const struct efi_device_path *dp1,
- const struct efi_device_path *dp2)
-{
- return efi_dp_append_or_concatenate(dp1, dp2, false);
-}
-
-/**
- * efi_dp_concat() - Concatenate 2 device paths. The final device path will
- * contain two device paths separated by and end node (0xff).
- *
- * @dp1: First device path
- * @dp2: Second device path
- *
- * Return:
- * concatenated device path or NULL. Caller must free the returned value
- */
-struct efi_device_path *efi_dp_concat(const struct efi_device_path *dp1,
- const struct efi_device_path *dp2)
-{
- return efi_dp_append_or_concatenate(dp1, dp2, true);
-}
-
struct efi_device_path *efi_dp_append_node(const struct efi_device_path *dp,
const struct efi_device_path *node)
{
if (path && !file)
return EFI_INVALID_PARAMETER;
- if (!strcmp(dev, "Mem") || !strcmp(dev, "hostfs")) {
+ if (IS_ENABLED(CONFIG_EFI_BINARY_EXEC) &&
+ (!strcmp(dev, "Mem") || !strcmp(dev, "hostfs"))) {
/* loadm command and semihosting */
efi_get_image_parameters(&image_addr, &image_size);
const struct efi_device_path *src2)
{
EFI_ENTRY("%pD, %pD", src1, src2);
- return EFI_EXIT(efi_dp_append(src1, src2));
+ return EFI_EXIT(efi_dp_concat(src1, src2, false));
}
/*
*
* @header: EFI object header
* @ops: EFI disk I/O protocol interface
- * @dev_index: device index of block device
* @media: block I/O media information
* @dp: device path to the block device
- * @part: partition
* @volume: simple file system protocol of the partition
- * @dev: associated DM device
*/
struct efi_disk_obj {
struct efi_object header;
struct efi_block_io ops;
- int dev_index;
struct efi_block_io_media media;
struct efi_device_path *dp;
- unsigned int part;
struct efi_simple_file_system_protocol *volume;
};
* @parent: parent handle
* @dp_parent: parent device path
* @desc: internal block device
- * @dev_index: device index for block device
* @part_info: partition info
* @part: partition
* @disk: pointer to receive the created handle
efi_handle_t parent,
struct efi_device_path *dp_parent,
struct blk_desc *desc,
- int dev_index,
struct disk_partition *part_info,
unsigned int part,
struct efi_disk_obj **disk,
diskobj->dp = efi_dp_from_part(desc, part);
diskobj->media.last_block = desc->lba - 1;
}
- diskobj->part = part;
/*
* Install the device path and the block IO protocol.
goto error;
}
diskobj->ops = block_io_disk_template;
- diskobj->dev_index = dev_index;
/* Fill in EFI IO Media info (for read/write callbacks) */
diskobj->media.removable_media = desc->removable;
EFI_PRINT("BlockIO: part %u, present %d, logical %d, removable %d"
", last_block %llu\n",
- diskobj->part,
+ part,
diskobj->media.media_present,
diskobj->media.logical_partition,
diskobj->media.removable_media,
diskid = desc->devnum;
ret = efi_disk_add_dev(NULL, NULL, desc,
- diskid, NULL, 0, &disk, agent_handle);
+ NULL, 0, &disk, agent_handle);
if (ret != EFI_SUCCESS) {
if (ret == EFI_NOT_READY) {
log_notice("Disk %s not ready\n", dev->name);
return -1;
dp_parent = (struct efi_device_path *)handler->protocol_interface;
- ret = efi_disk_add_dev(parent, dp_parent, desc, diskid,
+ ret = efi_disk_add_dev(parent, dp_parent, desc,
info, part, &disk, agent_handle);
if (ret != EFI_SUCCESS) {
log_err("Adding partition for %s failed\n", dev->name);
if (ret != EFI_SUCCESS) {
EFI_PRINT("ESRT Unable to find FMP handle (%u)\n",
idx);
- goto out;
+ continue;
}
fmp = handler->protocol_interface;
* fmp->get_image_info to return BUFFER_TO_SMALL.
*/
EFI_PRINT("ESRT erroneous FMP implementation\n");
- ret = EFI_INVALID_PARAMETER;
- goto out;
+ continue;
}
ret = efi_allocate_pool(EFI_BOOT_SERVICES_DATA, info_size,
(void **)&img_info);
if (ret != EFI_SUCCESS) {
EFI_PRINT("ESRT failed to allocate memory for image info\n");
- goto out;
+ continue;
}
/*
if (ret != EFI_SUCCESS) {
EFI_PRINT("ESRT failed to obtain image info from FMP\n");
efi_free_pool(img_info);
- goto out;
+ continue;
}
num_entries += desc_count;
efi_free_pool(img_info);
}
+ /* error occurs in fmp->get_image_info() if num_entries is 0 here */
+ if (!num_entries) {
+ EFI_PRINT("Error occurs, num_entries should not be 0\n");
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
EFI_PRINT("ESRT create table with %u entries\n", num_entries);
/*
* Allocate an ESRT with the sufficient number of entries to accommodate
if (ret != EFI_SUCCESS) {
EFI_PRINT("ESRT unable to find FMP handle (%u)\n",
idx);
- break;
+ continue;
}
fmp = handler->protocol_interface;
{
u16 varname[13]; /* u"FmpStateXXXX" */
efi_status_t ret;
- efi_uintn_t size;
- struct fmp_state var_state = { 0 };
-
- efi_create_indexed_name(varname, sizeof(varname), "FmpState",
- fw_array->image_index);
- size = sizeof(var_state);
- ret = efi_get_variable_int(varname, &fw_array->image_type_id,
- NULL, &size, &var_state, NULL);
- if (ret == EFI_SUCCESS)
- image_info->version = var_state.fw_version;
- else
- image_info->version = 0;
+ efi_uintn_t size, expected_size;
+ uint num_banks = 1;
+ uint active_index = 0;
+ struct fmp_state *var_state;
efi_firmware_get_lsv_from_dtb(fw_array->image_index,
&fw_array->image_type_id,
image_info->version_name = NULL; /* not supported */
image_info->last_attempt_version = 0;
image_info->last_attempt_status = LAST_ATTEMPT_STATUS_SUCCESS;
+ image_info->version = 0;
+
+ /* get the fw_version */
+ efi_create_indexed_name(varname, sizeof(varname), "FmpState",
+ fw_array->image_index);
+ if (IS_ENABLED(CONFIG_FWU_MULTI_BANK_UPDATE)) {
+ ret = fwu_get_active_index(&active_index);
+ if (ret)
+ return;
+
+ num_banks = CONFIG_FWU_NUM_BANKS;
+ }
+
+ size = num_banks * sizeof(*var_state);
+ expected_size = size;
+ var_state = calloc(1, size);
+ if (!var_state)
+ return;
+
+ ret = efi_get_variable_int(varname, &fw_array->image_type_id,
+ NULL, &size, var_state, NULL);
+ if (ret == EFI_SUCCESS && expected_size == size)
+ image_info->version = var_state[active_index].fw_version;
+
+ free(var_state);
}
/**
{
u16 varname[13]; /* u"FmpStateXXXX" */
efi_status_t ret;
+ uint num_banks = 1;
+ uint update_bank = 0;
+ efi_uintn_t size;
efi_guid_t *image_type_id;
- struct fmp_state var_state = { 0 };
+ struct fmp_state *var_state;
image_type_id = efi_firmware_get_image_type_id(image_index);
if (!image_type_id)
efi_create_indexed_name(varname, sizeof(varname), "FmpState",
image_index);
+ if (IS_ENABLED(CONFIG_FWU_MULTI_BANK_UPDATE)) {
+ ret = fwu_plat_get_update_index(&update_bank);
+ if (ret)
+ return EFI_INVALID_PARAMETER;
+
+ num_banks = CONFIG_FWU_NUM_BANKS;
+ }
+
+ size = num_banks * sizeof(*var_state);
+ var_state = calloc(1, size);
+ if (!var_state)
+ return EFI_OUT_OF_RESOURCES;
+
+ /*
+ * GetVariable may fail, EFI_NOT_FOUND is returned if FmpState
+ * variable has not been set yet.
+ * Ignore the error here since the correct FmpState variable
+ * is set later.
+ */
+ efi_get_variable_int(varname, image_type_id, NULL, &size, var_state,
+ NULL);
+
/*
* Only the fw_version is set here.
* lowest_supported_version in FmpState variable is ignored since
* it can be tampered if the file based EFI variable storage is used.
*/
- var_state.fw_version = state->fw_version;
+ var_state[update_bank].fw_version = state->fw_version;
+ size = num_banks * sizeof(*var_state);
ret = efi_set_variable_int(varname, image_type_id,
EFI_VARIABLE_READ_ONLY |
EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
- sizeof(var_state), &var_state, false);
+ size, var_state, false);
+
+ free(var_state);
return ret;
}
u16 **abort_reason)
{
int ret;
+ u8 dfu_alt_num;
efi_status_t status;
struct fmp_state state = { 0 };
if (status != EFI_SUCCESS)
return EFI_EXIT(status);
+ /*
+ * dfu_alt_num is assigned from 0 while image_index starts from 1.
+ * dfu_alt_num is calculated by (image_index - 1) when multi bank update
+ * is not used.
+ */
+ dfu_alt_num = image_index - 1;
if (IS_ENABLED(CONFIG_FWU_MULTI_BANK_UPDATE)) {
/*
* Based on the value of update bank, derive the
* image index value.
*/
- ret = fwu_get_image_index(&image_index);
+ ret = fwu_get_dfu_alt_num(image_index, &dfu_alt_num);
if (ret) {
log_debug("Unable to get FWU image_index\n");
return EFI_EXIT(EFI_DEVICE_ERROR);
}
}
- if (dfu_write_by_alt(image_index - 1, (void *)image, image_size,
+ if (dfu_write_by_alt(dfu_alt_num, (void *)image, image_size,
NULL, NULL))
return EFI_EXIT(EFI_DEVICE_ERROR);
*/
#define LOG_CATEGORY LOGC_EFI
+#include <bootm.h>
#include <env.h>
+#include <image.h>
+#include <log.h>
#include <malloc.h>
+#include <mapmem.h>
#include <dm.h>
#include <fs.h>
+#include <efi_api.h>
#include <efi_load_initrd.h>
#include <efi_loader.h>
#include <efi_variable.h>
+#include <linux/libfdt.h>
+#include <linux/list.h>
#if defined(CONFIG_CMD_EFIDEBUG) || defined(CONFIG_EFI_LOAD_FILE2_INITRD)
/* GUID used by Linux to identify the LoadFile2 protocol with the initrd */
return false;
}
+
+/**
+ * efi_env_set_load_options() - set load options from environment variable
+ *
+ * @handle: the image handle
+ * @env_var: name of the environment variable
+ * @load_options: pointer to load options (output)
+ * Return: status code
+ */
+efi_status_t efi_env_set_load_options(efi_handle_t handle,
+ const char *env_var,
+ u16 **load_options)
+{
+ const char *env = env_get(env_var);
+ size_t size;
+ u16 *pos;
+ efi_status_t ret;
+
+ *load_options = NULL;
+ if (!env)
+ return EFI_SUCCESS;
+ size = sizeof(u16) * (utf8_utf16_strlen(env) + 1);
+ pos = calloc(size, 1);
+ if (!pos)
+ return EFI_OUT_OF_RESOURCES;
+ *load_options = pos;
+ utf8_utf16_strcpy(&pos, env);
+ ret = efi_set_load_options(handle, size, *load_options);
+ if (ret != EFI_SUCCESS) {
+ free(*load_options);
+ *load_options = NULL;
+ }
+ return ret;
+}
+
+/**
+ * copy_fdt() - Copy the device tree to a new location available to EFI
+ *
+ * The FDT is copied to a suitable location within the EFI memory map.
+ * Additional 12 KiB are added to the space in case the device tree needs to be
+ * expanded later with fdt_open_into().
+ *
+ * @fdtp: On entry a pointer to the flattened device tree.
+ * On exit a pointer to the copy of the flattened device tree.
+ * FDT start
+ * Return: status code
+ */
+static efi_status_t copy_fdt(void **fdtp)
+{
+ unsigned long fdt_ram_start = -1L, fdt_pages;
+ efi_status_t ret = 0;
+ void *fdt, *new_fdt;
+ u64 new_fdt_addr;
+ uint fdt_size;
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ u64 ram_start = gd->bd->bi_dram[i].start;
+ u64 ram_size = gd->bd->bi_dram[i].size;
+
+ if (!ram_size)
+ continue;
+
+ if (ram_start < fdt_ram_start)
+ fdt_ram_start = ram_start;
+ }
+
+ /*
+ * Give us at least 12 KiB of breathing room in case the device tree
+ * needs to be expanded later.
+ */
+ fdt = *fdtp;
+ fdt_pages = efi_size_in_pages(fdt_totalsize(fdt) + 0x3000);
+ fdt_size = fdt_pages << EFI_PAGE_SHIFT;
+
+ ret = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES,
+ EFI_ACPI_RECLAIM_MEMORY, fdt_pages,
+ &new_fdt_addr);
+ if (ret != EFI_SUCCESS) {
+ log_err("ERROR: Failed to reserve space for FDT\n");
+ goto done;
+ }
+ new_fdt = (void *)(uintptr_t)new_fdt_addr;
+ memcpy(new_fdt, fdt, fdt_totalsize(fdt));
+ fdt_set_totalsize(new_fdt, fdt_size);
+
+ *fdtp = (void *)(uintptr_t)new_fdt_addr;
+done:
+ return ret;
+}
+
+/**
+ * get_config_table() - get configuration table
+ *
+ * @guid: GUID of the configuration table
+ * Return: pointer to configuration table or NULL
+ */
+static void *get_config_table(const efi_guid_t *guid)
+{
+ size_t i;
+
+ for (i = 0; i < systab.nr_tables; i++) {
+ if (!guidcmp(guid, &systab.tables[i].guid))
+ return systab.tables[i].table;
+ }
+ return NULL;
+}
+
+/**
+ * efi_install_fdt() - install device tree
+ *
+ * If fdt is not EFI_FDT_USE_INTERNAL, the device tree located at that memory
+ * address will be installed as configuration table, otherwise the device
+ * tree located at the address indicated by environment variable fdt_addr or as
+ * fallback fdtcontroladdr will be used.
+ *
+ * On architectures using ACPI tables device trees shall not be installed as
+ * configuration table.
+ *
+ * @fdt: address of device tree or EFI_FDT_USE_INTERNAL to use
+ * the hardware device tree as indicated by environment variable
+ * fdt_addr or as fallback the internal device tree as indicated by
+ * the environment variable fdtcontroladdr
+ * Return: status code
+ */
+efi_status_t efi_install_fdt(void *fdt)
+{
+ struct bootm_headers img = { 0 };
+ efi_status_t ret;
+
+ /*
+ * The EBBR spec requires that we have either an FDT or an ACPI table
+ * but not both.
+ */
+ if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) && fdt)
+ log_warning("WARNING: Can't have ACPI table and device tree - ignoring DT.\n");
+
+ if (fdt == EFI_FDT_USE_INTERNAL) {
+ const char *fdt_opt;
+ uintptr_t fdt_addr;
+
+ /* Look for device tree that is already installed */
+ if (get_config_table(&efi_guid_fdt))
+ return EFI_SUCCESS;
+ /* Check if there is a hardware device tree */
+ fdt_opt = env_get("fdt_addr");
+ /* Use our own device tree as fallback */
+ if (!fdt_opt) {
+ fdt_opt = env_get("fdtcontroladdr");
+ if (!fdt_opt) {
+ log_err("ERROR: need device tree\n");
+ return EFI_NOT_FOUND;
+ }
+ }
+ fdt_addr = hextoul(fdt_opt, NULL);
+ if (!fdt_addr) {
+ log_err("ERROR: invalid $fdt_addr or $fdtcontroladdr\n");
+ return EFI_LOAD_ERROR;
+ }
+ fdt = map_sysmem(fdt_addr, 0);
+ }
+
+ /* Install device tree */
+ if (fdt_check_header(fdt)) {
+ log_err("ERROR: invalid device tree\n");
+ return EFI_LOAD_ERROR;
+ }
+
+ /* Create memory reservations as indicated by the device tree */
+ efi_carve_out_dt_rsv(fdt);
+
+ if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE))
+ return EFI_SUCCESS;
+
+ /* Prepare device tree for payload */
+ ret = copy_fdt(&fdt);
+ if (ret) {
+ log_err("ERROR: out of memory\n");
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ if (image_setup_libfdt(&img, fdt, NULL)) {
+ log_err("ERROR: failed to process device tree\n");
+ return EFI_LOAD_ERROR;
+ }
+
+ efi_try_purge_kaslr_seed(fdt);
+
+ if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) {
+ ret = efi_tcg2_measure_dtb(fdt);
+ if (ret == EFI_SECURITY_VIOLATION) {
+ log_err("ERROR: failed to measure DTB\n");
+ return ret;
+ }
+ }
+
+ /* Install device tree as UEFI table */
+ ret = efi_install_configuration_table(&efi_guid_fdt, fdt);
+ if (ret != EFI_SUCCESS) {
+ log_err("ERROR: failed to install device tree\n");
+ return ret;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ * do_bootefi_exec() - execute EFI binary
+ *
+ * The image indicated by @handle is started. When it returns the allocated
+ * memory for the @load_options is freed.
+ *
+ * @handle: handle of loaded image
+ * @load_options: load options
+ * Return: status code
+ *
+ * Load the EFI binary into a newly assigned memory unwinding the relocation
+ * information, install the loaded image protocol, and call the binary.
+ */
+efi_status_t do_bootefi_exec(efi_handle_t handle, void *load_options)
+{
+ efi_status_t ret;
+ efi_uintn_t exit_data_size = 0;
+ u16 *exit_data = NULL;
+ struct efi_event *evt;
+
+ /* On ARM switch from EL3 or secure mode to EL2 or non-secure mode */
+ switch_to_non_secure_mode();
+
+ /*
+ * The UEFI standard requires that the watchdog timer is set to five
+ * minutes when invoking an EFI boot option.
+ *
+ * Unified Extensible Firmware Interface (UEFI), version 2.7 Errata A
+ * 7.5. Miscellaneous Boot Services - EFI_BOOT_SERVICES.SetWatchdogTimer
+ */
+ ret = efi_set_watchdog(300);
+ if (ret != EFI_SUCCESS) {
+ log_err("ERROR: Failed to set watchdog timer\n");
+ goto out;
+ }
+
+ /* Call our payload! */
+ ret = EFI_CALL(efi_start_image(handle, &exit_data_size, &exit_data));
+ if (ret != EFI_SUCCESS) {
+ log_err("## Application failed, r = %lu\n",
+ ret & ~EFI_ERROR_MASK);
+ if (exit_data) {
+ log_err("## %ls\n", exit_data);
+ efi_free_pool(exit_data);
+ }
+ }
+
+ efi_restore_gd();
+
+out:
+ free(load_options);
+
+ if (IS_ENABLED(CONFIG_EFI_LOAD_FILE2_INITRD)) {
+ if (efi_initrd_deregister() != EFI_SUCCESS)
+ log_err("Failed to remove loadfile2 for initrd\n");
+ }
+
+ /* Notify EFI_EVENT_GROUP_RETURN_TO_EFIBOOTMGR event group. */
+ list_for_each_entry(evt, &efi_events, link) {
+ if (evt->group &&
+ !guidcmp(evt->group,
+ &efi_guid_event_group_return_to_efibootmgr)) {
+ efi_signal_event(evt);
+ EFI_CALL(systab.boottime->close_event(evt));
+ break;
+ }
+ }
+
+ /* Control is returned to U-Boot, disable EFI watchdog */
+ efi_set_watchdog(0);
+
+ return ret;
+}
#include <mapmem.h>
#include <smbios.h>
#include <linux/sizes.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
const efi_guid_t smbios3_guid = SMBIOS3_TABLE_GUID;
ulong addr;
void *buf;
- if (!IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE) || IS_ENABLED(CONFIG_X86))
+ if (!IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE) ||
+ IS_ENABLED(CONFIG_X86) ||
+ IS_ENABLED(CONFIG_QFW_SMBIOS))
return 0;
/* Align the table to a 4KB boundary to keep EFI happy */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2023, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+ *
+ * smbiosdump.efi saves the SMBIOS table as file.
+ *
+ * Specifying 'nocolor' as load option data suppresses colored output and
+ * clearing of the screen.
+ */
+
+#include <efi_api.h>
+#include <part.h>
+#include <smbios.h>
+#include <string.h>
+
+#define BUFFER_SIZE 64
+
+static struct efi_simple_text_output_protocol *cerr;
+static struct efi_simple_text_output_protocol *cout;
+static struct efi_simple_text_input_protocol *cin;
+static struct efi_boot_services *bs;
+static efi_handle_t handle;
+static struct efi_system_table *systable;
+static const efi_guid_t smbios_guid = SMBIOS_TABLE_GUID;
+static const efi_guid_t smbios3_guid = SMBIOS3_TABLE_GUID;
+static const efi_guid_t loaded_image_guid = EFI_LOADED_IMAGE_PROTOCOL_GUID;
+static const efi_guid_t guid_simple_file_system_protocol =
+ EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID;
+static const efi_guid_t efi_system_partition_guid = PARTITION_SYSTEM_GUID;
+static bool nocolor;
+
+/**
+ * color() - set foreground color
+ *
+ * @color: foreground color
+ */
+static void color(u8 color)
+{
+ if (!nocolor)
+ cout->set_attribute(cout, color | EFI_BACKGROUND_BLACK);
+}
+
+/**
+ * print() - print string
+ *
+ * @string: text
+ */
+static void print(u16 *string)
+{
+ cout->output_string(cout, string);
+}
+
+/**
+ * cls() - clear screen
+ */
+static void cls(void)
+{
+ if (nocolor)
+ print(u"\r\n");
+ else
+ cout->clear_screen(cout);
+}
+
+/**
+ * error() - print error string
+ *
+ * @string: error text
+ */
+static void error(u16 *string)
+{
+ color(EFI_LIGHTRED);
+ print(string);
+ color(EFI_LIGHTBLUE);
+}
+
+/**
+ * efi_input_yn() - get answer to yes/no question
+ *
+ * Return:
+ * y or Y
+ * EFI_SUCCESS
+ * n or N
+ * EFI_ACCESS_DENIED
+ * ESC
+ * EFI_ABORTED
+ */
+static efi_status_t efi_input_yn(void)
+{
+ struct efi_input_key key = {0};
+ efi_uintn_t index;
+ efi_status_t ret;
+
+ /* Drain the console input */
+ ret = cin->reset(cin, true);
+ for (;;) {
+ ret = bs->wait_for_event(1, &cin->wait_for_key, &index);
+ if (ret != EFI_SUCCESS)
+ continue;
+ ret = cin->read_key_stroke(cin, &key);
+ if (ret != EFI_SUCCESS)
+ continue;
+ switch (key.scan_code) {
+ case 0x17: /* Escape */
+ return EFI_ABORTED;
+ default:
+ break;
+ }
+ /* Convert to lower case */
+ switch (key.unicode_char | 0x20) {
+ case 'y':
+ return EFI_SUCCESS;
+ case 'n':
+ return EFI_ACCESS_DENIED;
+ default:
+ break;
+ }
+ }
+}
+
+/**
+ * efi_input() - read string from console
+ *
+ * @buffer: input buffer
+ * @buffer_size: buffer size
+ * Return: status code
+ */
+static efi_status_t efi_input(u16 *buffer, efi_uintn_t buffer_size)
+{
+ struct efi_input_key key = {0};
+ efi_uintn_t index;
+ efi_uintn_t pos = 0;
+ u16 outbuf[2] = u" ";
+ efi_status_t ret;
+
+ /* Drain the console input */
+ ret = cin->reset(cin, true);
+ *buffer = 0;
+ for (;;) {
+ ret = bs->wait_for_event(1, &cin->wait_for_key, &index);
+ if (ret != EFI_SUCCESS)
+ continue;
+ ret = cin->read_key_stroke(cin, &key);
+ if (ret != EFI_SUCCESS)
+ continue;
+ switch (key.scan_code) {
+ case 0x17: /* Escape */
+ print(u"\r\nAborted\r\n");
+ return EFI_ABORTED;
+ default:
+ break;
+ }
+ switch (key.unicode_char) {
+ case 0x08: /* Backspace */
+ if (pos) {
+ buffer[pos--] = 0;
+ print(u"\b \b");
+ }
+ break;
+ case 0x0a: /* Linefeed */
+ case 0x0d: /* Carriage return */
+ print(u"\r\n");
+ return EFI_SUCCESS;
+ default:
+ break;
+ }
+ /* Ignore surrogate codes */
+ if (key.unicode_char >= 0xD800 && key.unicode_char <= 0xDBFF)
+ continue;
+ if (key.unicode_char >= 0x20 &&
+ pos < buffer_size - 1) {
+ *outbuf = key.unicode_char;
+ buffer[pos++] = key.unicode_char;
+ buffer[pos] = 0;
+ print(outbuf);
+ }
+ }
+}
+
+/**
+ * skip_whitespace() - skip over leading whitespace
+ *
+ * @pos: UTF-16 string
+ * Return: pointer to first non-whitespace
+ */
+static u16 *skip_whitespace(u16 *pos)
+{
+ for (; *pos && *pos <= 0x20; ++pos)
+ ;
+ return pos;
+}
+
+/**
+ * starts_with() - check if @string starts with @keyword
+ *
+ * @string: string to search for keyword
+ * @keyword: keyword to be searched
+ * Return: true fi @string starts with the keyword
+ */
+static bool starts_with(u16 *string, u16 *keyword)
+{
+ if (!string || !keyword)
+ return NULL;
+
+ for (; *keyword; ++string, ++keyword) {
+ if (*string != *keyword)
+ return false;
+ }
+ return true;
+}
+
+/**
+ * open_file_system() - open simple file system protocol
+ *
+ * file_system: interface of the simple file system protocol
+ * Return: status code
+ */
+static efi_status_t
+open_file_system(struct efi_simple_file_system_protocol **file_system)
+{
+ struct efi_loaded_image *loaded_image;
+ efi_status_t ret;
+ efi_handle_t *handle_buffer = NULL;
+ efi_uintn_t count;
+
+ ret = bs->open_protocol(handle, &loaded_image_guid,
+ (void **)&loaded_image, NULL, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret != EFI_SUCCESS) {
+ error(u"Loaded image protocol not found\r\n");
+ return ret;
+ }
+
+ /* Open the simple file system protocol on the same partition */
+ ret = bs->open_protocol(loaded_image->device_handle,
+ &guid_simple_file_system_protocol,
+ (void **)file_system, NULL, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret == EFI_SUCCESS)
+ return ret;
+
+ /* Open the simple file system protocol on the UEFI system partition */
+ ret = bs->locate_handle_buffer(BY_PROTOCOL, &efi_system_partition_guid,
+ NULL, &count, &handle_buffer);
+ if (ret == EFI_SUCCESS && handle_buffer)
+ ret = bs->open_protocol(handle_buffer[0],
+ &guid_simple_file_system_protocol,
+ (void **)file_system, NULL, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret != EFI_SUCCESS)
+ error(u"Failed to open simple file system protocol\r\n");
+ if (handle)
+ bs->free_pool(handle_buffer);
+
+ return ret;
+}
+
+/**
+ * do_help() - print help
+ */
+static void do_help(void)
+{
+ error(u"check - check SMBIOS table\r\n");
+ error(u"save <file> - save SMBIOS table to file\r\n");
+ error(u"exit - exit the shell\r\n");
+}
+
+/**
+ * get_config_table() - get configuration table
+ *
+ * @guid: GUID of the configuration table
+ * Return: pointer to configuration table or NULL
+ */
+static void *get_config_table(const efi_guid_t *guid)
+{
+ size_t i;
+
+ for (i = 0; i < systable->nr_tables; ++i) {
+ if (!memcmp(guid, &systable->tables[i].guid, 16))
+ return systable->tables[i].table;
+ }
+
+ return NULL;
+}
+
+/**
+ * checksum() - calculate checksum
+ *
+ * @buf: buffer to checksum
+ * @len: length of buffer
+ * Return: checksum
+ */
+u8 checksum(void *buf, int len)
+{
+ u8 ret = 0;
+
+ for (u8 *ptr = buf; len; --len, ++ptr)
+ ret -= *ptr;
+
+ return ret;
+}
+
+/**
+ * do_check() - check SMBIOS table
+ *
+ * Return: status code
+ */
+efi_status_t do_check(void)
+{
+ struct smbios3_entry *smbios3_anchor;
+ void *table, *table_end;
+ u32 len;
+
+ smbios3_anchor = get_config_table(&smbios3_guid);
+ if (smbios3_anchor) {
+ int r;
+
+ r = memcmp(smbios3_anchor->anchor, "_SM3_", 5);
+ if (r) {
+ error(u"Invalid anchor string\n");
+ return EFI_LOAD_ERROR;
+ }
+ print(u"Found SMBIOS 3 entry point\n");
+ if (smbios3_anchor->length != 0x18) {
+ error(u"Invalid anchor length\n");
+ return EFI_LOAD_ERROR;
+ }
+ if (checksum(smbios3_anchor, smbios3_anchor->length)) {
+ error(u"Invalid anchor checksum\n");
+ return EFI_LOAD_ERROR;
+ }
+ table = (void *)(uintptr_t)smbios3_anchor->struct_table_address;
+ len = smbios3_anchor->max_struct_size;
+ } else {
+ struct smbios_entry *smbios_anchor;
+ int r;
+
+ smbios_anchor = get_config_table(&smbios_guid);
+ if (!smbios_anchor) {
+ error(u"No SMBIOS table\n");
+ return EFI_NOT_FOUND;
+ }
+ r = memcmp(smbios_anchor->anchor, "_SM_", 4);
+ if (r) {
+ error(u"Invalid anchor string\n");
+ return EFI_LOAD_ERROR;
+ }
+ print(u"Found SMBIOS 2.1 entry point\n");
+ if (smbios_anchor->length != 0x1f) {
+ error(u"Invalid anchor length\n");
+ return EFI_LOAD_ERROR;
+ }
+ if (checksum(smbios_anchor, smbios_anchor->length)) {
+ error(u"Invalid anchor checksum\n");
+ return EFI_LOAD_ERROR;
+ }
+ r = memcmp(smbios_anchor->intermediate_anchor, "_DMI_", 5);
+ if (r) {
+ error(u"Invalid intermediate anchor string\n");
+ return EFI_LOAD_ERROR;
+ }
+ if (checksum(&smbios_anchor->intermediate_anchor, 0xf)) {
+ error(u"Invalid intermediate anchor checksum\n");
+ return EFI_LOAD_ERROR;
+ }
+ table = (void *)(uintptr_t)smbios_anchor->struct_table_address;
+ len = smbios_anchor->struct_table_length;
+ }
+
+ table_end = (void *)((u8 *)table + len);
+ for (struct smbios_header *pos = table; ;) {
+ u8 *str = (u8 *)pos + pos->length;
+
+ if (!*str)
+ ++str;
+ while (*str) {
+ for (; *str; ++str) {
+ if ((void *)str >= table_end) {
+ error(u"Structure table length exceeded\n");
+ return EFI_LOAD_ERROR;
+ }
+ }
+ ++str;
+ }
+ ++str;
+ if ((void *)str > table_end) {
+ error(u"Structure table length exceeded\n");
+ return EFI_LOAD_ERROR;
+ }
+ if (pos->type == 0x7f) /* End of table */
+ break;
+ pos = (struct smbios_header *)str;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ * save_file() - save file to EFI system partition
+ *
+ * @filename: file name
+ * @buf: buffer to write
+ * @size: size of the buffer
+ */
+efi_status_t save_file(u16 *filename, void *buf, efi_uintn_t size)
+{
+ efi_uintn_t ret;
+ struct efi_simple_file_system_protocol *file_system;
+ struct efi_file_handle *root, *file;
+
+ ret = open_file_system(&file_system);
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ /* Open volume */
+ ret = file_system->open_volume(file_system, &root);
+ if (ret != EFI_SUCCESS) {
+ error(u"Failed to open volume\r\n");
+ return ret;
+ }
+ /* Check if file already exists */
+ ret = root->open(root, &file, filename, EFI_FILE_MODE_READ, 0);
+ if (ret == EFI_SUCCESS) {
+ file->close(file);
+ print(u"Overwrite existing file (y/n)? ");
+ ret = efi_input_yn();
+ print(u"\r\n");
+ if (ret != EFI_SUCCESS) {
+ root->close(root);
+ error(u"Aborted by user\r\n");
+ bs->free_pool(buf);
+ return ret;
+ }
+ }
+
+ /* Create file */
+ ret = root->open(root, &file, filename,
+ EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE |
+ EFI_FILE_MODE_CREATE, EFI_FILE_ARCHIVE);
+ if (ret == EFI_SUCCESS) {
+ /* Write file */
+ ret = file->write(file, &size, buf);
+ if (ret != EFI_SUCCESS)
+ error(u"Failed to write file\r\n");
+ file->close(file);
+ } else {
+ error(u"Failed to open file\r\n");
+ }
+ root->close(root);
+
+ return ret;
+}
+
+/**
+ * do_save() - save SMBIOS table
+ *
+ * @filename: file name
+ * Return: status code
+ */
+static efi_status_t do_save(u16 *filename)
+{
+ struct smbios3_entry *smbios3_anchor;
+ u8 *buf;
+ efi_uintn_t size;
+ efi_uintn_t ret;
+
+ ret = do_check();
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ smbios3_anchor = get_config_table(&smbios3_guid);
+ if (smbios3_anchor) {
+ size = 0x20 + smbios3_anchor->max_struct_size;
+ ret = bs->allocate_pool(EFI_LOADER_DATA, size, (void **)&buf);
+ if (ret != EFI_SUCCESS) {
+ error(u"Out of memory\n");
+ return ret;
+ }
+
+ memset(buf, 0, size);
+ memcpy(buf, smbios3_anchor, smbios3_anchor->length);
+ memcpy(buf + 0x20,
+ (void *)(uintptr_t)smbios3_anchor->struct_table_address,
+ smbios3_anchor->max_struct_size);
+
+ smbios3_anchor = (struct smbios3_entry *)buf;
+ smbios3_anchor->struct_table_address = 0x20;
+ smbios3_anchor->checksum +=
+ checksum(smbios3_anchor, smbios3_anchor->length);
+ } else {
+ struct smbios_entry *smbios_anchor;
+
+ smbios_anchor = get_config_table(&smbios_guid);
+ if (!smbios_anchor) {
+ /* Should not be reached after successful do_check() */
+ error(u"No SMBIOS table\n");
+ return EFI_NOT_FOUND;
+ }
+
+ size = 0x20 + smbios_anchor->struct_table_length;
+
+ ret = bs->allocate_pool(EFI_LOADER_DATA, size, (void **)&buf);
+ if (ret != EFI_SUCCESS) {
+ error(u"Out of memory\n");
+ return ret;
+ }
+
+ memset(buf, 0, size);
+ memcpy(buf, smbios_anchor, smbios_anchor->length);
+ memcpy(buf + 0x20,
+ (void *)(uintptr_t)smbios_anchor->struct_table_address,
+ smbios_anchor->struct_table_length);
+
+ smbios_anchor = (struct smbios_entry *)buf;
+ smbios_anchor->struct_table_address = 0x20;
+ smbios_anchor->intermediate_checksum +=
+ checksum(&smbios_anchor->intermediate_anchor, 0xf);
+ smbios_anchor->checksum +=
+ checksum(smbios_anchor, smbios_anchor->length);
+ }
+
+ filename = skip_whitespace(filename);
+
+ ret = save_file(filename, buf, size);
+
+ if (ret == EFI_SUCCESS) {
+ print(filename);
+ print(u" written\r\n");
+ }
+
+ bs->free_pool(buf);
+
+ return ret;
+}
+
+/**
+ * get_load_options() - get load options
+ *
+ * Return: load options or NULL
+ */
+static u16 *get_load_options(void)
+{
+ efi_status_t ret;
+ struct efi_loaded_image *loaded_image;
+
+ ret = bs->open_protocol(handle, &loaded_image_guid,
+ (void **)&loaded_image, NULL, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret != EFI_SUCCESS) {
+ error(u"Loaded image protocol not found\r\n");
+ return NULL;
+ }
+
+ if (!loaded_image->load_options_size || !loaded_image->load_options)
+ return NULL;
+
+ return loaded_image->load_options;
+}
+
+/**
+ * command_loop - process user commands
+ */
+static void command_loop(void)
+{
+ for (;;) {
+ u16 command[BUFFER_SIZE];
+ u16 *pos;
+ efi_uintn_t ret;
+
+ print(u"=> ");
+ ret = efi_input(command, sizeof(command));
+ if (ret == EFI_ABORTED)
+ break;
+ pos = skip_whitespace(command);
+ if (starts_with(pos, u"exit")) {
+ break;
+ } else if (starts_with(pos, u"check")) {
+ ret = do_check();
+ if (ret == EFI_SUCCESS)
+ print(u"OK\n");
+ } else if (starts_with(pos, u"save ")) {
+ do_save(pos + 5);
+ } else {
+ do_help();
+ }
+ }
+}
+
+/**
+ * efi_main() - entry point of the EFI application.
+ *
+ * @handle: handle of the loaded image
+ * @systab: system table
+ * Return: status code
+ */
+efi_status_t EFIAPI efi_main(efi_handle_t image_handle,
+ struct efi_system_table *systab)
+{
+ u16 *load_options;
+
+ handle = image_handle;
+ systable = systab;
+ cerr = systable->std_err;
+ cout = systable->con_out;
+ cin = systable->con_in;
+ bs = systable->boottime;
+ load_options = get_load_options();
+
+ if (starts_with(load_options, u"nocolor"))
+ nocolor = true;
+
+ color(EFI_WHITE);
+ cls();
+ print(u"SMBIOS Dump\r\n===========\r\n\r\n");
+ color(EFI_LIGHTBLUE);
+
+ command_loop();
+
+ color(EFI_LIGHTGRAY);
+ cls();
+
+ return EFI_SUCCESS;
+}
return 0;
}
-static int fwu_get_image_type_id(u8 *image_index, efi_guid_t *image_type_id)
+static int fwu_get_image_type_id(u8 image_index, efi_guid_t *image_type_id)
{
- u8 index;
int i;
struct efi_fw_image *image;
- index = *image_index;
image = update_info.images;
for (i = 0; i < update_info.num_images; i++) {
- if (index == image[i].image_index) {
+ if (image_index == image[i].image_index) {
guidcpy(image_type_id, &image[i].image_type_id);
return 0;
}
}
/**
- * fwu_get_image_index() - Get the Image Index to be used for capsule update
- * @image_index: The Image Index for the image
- *
- * The FWU multi bank update feature computes the value of image_index at
- * runtime, based on the bank to which the image needs to be written to.
- * Derive the image_index value for the image.
+ * fwu_get_dfu_alt_num() - Get the dfu_alt_num to be used for capsule update
+ * @image_index: The Image Index for the image
+ * @alt_num: pointer to store dfu_alt_num
*
* Currently, the capsule update driver uses the DFU framework for
* the updates. This function gets the DFU alt number which is to
- * be used as the Image Index
+ * be used for capsule update.
*
* Return: 0 if OK, -ve on error
*
*/
-int fwu_get_image_index(u8 *image_index)
+int fwu_get_dfu_alt_num(u8 image_index, u8 *alt_num)
{
int ret, i;
- u8 alt_num;
uint update_bank;
efi_guid_t *image_guid, image_type_id;
struct fwu_mdata *mdata = &g_mdata;
ret = fwu_get_image_type_id(image_index, &image_type_id);
if (ret) {
log_debug("Unable to get image_type_id for image_index %u\n",
- *image_index);
+ image_index);
goto out;
}
img_entry = &mdata->img_entry[i];
img_bank_info = &img_entry->img_bank_info[update_bank];
image_guid = &img_bank_info->image_uuid;
- ret = fwu_plat_get_alt_num(g_dev, image_guid, &alt_num);
- if (ret) {
+ ret = fwu_plat_get_alt_num(g_dev, image_guid, alt_num);
+ if (ret)
log_debug("alt_num not found for partition with GUID %pUs\n",
image_guid);
- } else {
+ else
log_debug("alt_num %d for partition %pUs\n",
- alt_num, image_guid);
- *image_index = alt_num + 1;
- }
+ *alt_num, image_guid);
goto out;
}
(mb->end - mb->start) - 1 - membuff_avail(mb);
}
-int membuff_readline(struct membuff *mb, char *str, int maxlen, int minch)
+int membuff_readline(struct membuff *mb, char *str, int maxlen, int minch, bool must_fit)
{
int len; /* number of bytes read (!= string length) */
char *s, *end;
}
/* couldn't get the whole string */
- if (!ok) {
+ if (!ok && must_fit) {
if (maxlen)
*orig = '\0';
return 0;
#define LOG_CATEGORY LOGC_BOOT
+#include <errno.h>
#include <smbios.h>
-
-static inline int verify_checksum(const struct smbios_entry *e)
-{
- /*
- * Checksums for SMBIOS tables are calculated to have a value, so that
- * the sum over all bytes yields zero (using unsigned 8 bit arithmetic).
- */
- u8 *byte = (u8 *)e;
- u8 sum = 0;
-
- for (int i = 0; i < e->length; i++)
- sum += byte[i];
-
- return sum;
-}
+#include <string.h>
+#include <tables_csum.h>
+#include <linux/kernel.h>
const struct smbios_entry *smbios_entry(u64 address, u32 size)
{
if (memcmp(entry->anchor, "_SM_", 4))
return NULL;
- if (verify_checksum(entry))
+ if (table_compute_checksum(entry, entry->length))
return NULL;
return entry;
return pos;
}
-static struct smbios_header *get_next_header(struct smbios_header *curr)
-{
- u8 *pos = ((u8 *)curr) + curr->length;
-
- return (struct smbios_header *)find_next_header(pos);
-}
-
-static const struct smbios_header *next_header(const struct smbios_header *curr)
+static struct smbios_header *get_next_header(const struct smbios_header *curr)
{
u8 *pos = ((u8 *)curr) + curr->length;
if (header->type == type)
return header;
- header = next_header(header);
+ header = get_next_header(header);
}
return NULL;
}
#endif
- t->processor_family = processor_family;
+ t->processor_family = 0xfe;
+ t->processor_family2 = processor_family;
t->processor_manufacturer = smbios_add_prop(ctx, NULL, vendor);
t->processor_version = smbios_add_prop(ctx, NULL, name);
}
t->l1_cache_handle = 0xffff;
t->l2_cache_handle = 0xffff;
t->l3_cache_handle = 0xffff;
- t->processor_family2 = t->processor_family;
len = t->length + smbios_string_table_len(ctx);
*current += len;
#include <linux/types.h>
-u8 table_compute_checksum(void *v, int len)
+u8 table_compute_checksum(const void *v, const int len)
{
- u8 *bytes = v;
+ const u8 *bytes = v;
u8 checksum = 0;
int i;
static int fastboot_our_port;
/**
- * fastboot_udp_send_info() - Send an INFO packet during long commands.
+ * fastboot_udp_send_response() - Send an response into UDP
*
- * @msg: String describing the reason for waiting
+ * @response: Response to send
*/
-static void fastboot_udp_send_info(const char *msg)
+static void fastboot_udp_send_response(const char *response)
{
uchar *packet;
uchar *packet_base;
int len = 0;
- char response[FASTBOOT_RESPONSE_LEN] = {0};
struct fastboot_header response_header = {
.id = FASTBOOT_FASTBOOT,
memcpy(packet, &response_header, sizeof(response_header));
packet += sizeof(response_header);
/* Write response */
- fastboot_response("INFO", response, "%s", msg);
memcpy(packet, response, strlen(response));
packet += strlen(response);
static void fastboot_timed_send_info(const char *msg)
{
static ulong start;
+ char response[FASTBOOT_RESPONSE_LEN] = {0};
/* Initialize timer */
if (start == 0)
/* Send INFO packet to host every 30 seconds */
if (time >= 30000) {
start = get_timer(0);
- fastboot_udp_send_info(msg);
+ fastboot_response("INFO", response, "%s", msg);
+ fastboot_udp_send_response(response);
}
}
} else {
cmd = fastboot_handle_command(command, response);
pending_command = false;
+
+ if (!strncmp(FASTBOOT_MULTIRESPONSE_START, response, 4)) {
+ while (1) {
+ /* Call handler to obtain next response */
+ fastboot_multiresponse(cmd, response);
+
+ /*
+ * Send more responses or break to send
+ * final OKAY/FAIL response
+ */
+ if (strncmp("OKAY", response, 4) &&
+ strncmp("FAIL", response, 4))
+ fastboot_udp_send_response(response);
+ else
+ break;
+ }
+ }
}
/*
* Sent some INFO packets, need to update sequence number in
time_start * 1000, "/s");
}
puts("\ndone\n");
- if (IS_ENABLED(CONFIG_CMD_BOOTEFI)) {
- if (!tftp_put_active)
- efi_set_bootdev("Net", "", tftp_filename,
- map_sysmem(tftp_load_addr, 0),
- net_boot_file_size);
- }
+ if (!tftp_put_active)
+ efi_set_bootdev("Net", "", tftp_filename,
+ map_sysmem(tftp_load_addr, 0),
+ net_boot_file_size);
net_set_state(NETLOOP_SUCCESS);
}
endif
%_defconfig: $(obj)/conf
- $(Q)$< $(silent) --defconfig=arch/$(SRCARCH)/configs/$@ $(Kconfig)
+ $(Q)$(CPP) -nostdinc -I $(srctree) -undef -x assembler-with-cpp $(srctree)/arch/$(SRCARCH)/configs/$@ -o generated_defconfig
+ $(Q)$< $(silent) --defconfig=generated_defconfig $(Kconfig)
# Added for U-Boot (backward compatibility)
%_config: %_defconfig
config UT_BOOTSTD
bool "Unit tests for standard boot"
- depends on UNIT_TEST && SANDBOX
+ depends on UNIT_TEST && BOOTSTD && SANDBOX
default y
config UT_COMPRESSION
obj-y += ut.o
ifeq ($(CONFIG_SPL_BUILD),)
-obj-$(CONFIG_$(SPL_)UT_BOOTSTD) += boot/
+obj-y += boot/
obj-$(CONFIG_UNIT_TEST) += common/
obj-y += log/
obj-$(CONFIG_$(SPL_)UT_UNICODE) += unicode_ut.o
{
struct udevice *bootstd, *dev;
- if (!IS_ENABLED(CONFIG_BOOTEFI_BOOTMGR))
+ if (!IS_ENABLED(CONFIG_EFI_BOOTMGR))
return -EAGAIN;
ut_assertok(uclass_first_device_err(UCLASS_BOOTSTD, &bootstd));
ut_assertok(device_bind(bootstd, DM_DRIVER_GET(bootmeth_efi_mgr),
obj-$(CONFIG_CMD_HISTORY) += history.o
obj-$(CONFIG_CMD_LOADM) += loadm.o
obj-$(CONFIG_CMD_MEM_SEARCH) += mem_search.o
+obj-$(CONFIG_CMD_MEMORY) += mem_copy.o
ifdef CONFIG_CMD_PCI
obj-$(CONFIG_CMD_PCI_MPS) += pci_mps.o
endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Tests for memory 'cp' command
+ */
+
+#include <command.h>
+#include <console.h>
+#include <mapmem.h>
+#include <dm/test.h>
+#include <test/ut.h>
+
+#define BUF_SIZE 256
+
+/* Declare a new mem test */
+#define MEM_TEST(_name) UNIT_TEST(_name, 0, mem_test)
+
+struct param {
+ int d, s, count;
+};
+
+static int do_test(struct unit_test_state *uts,
+ const char *suffix, int d, int s, int count)
+{
+ const long addr = 0x1000;
+ u8 shadow[BUF_SIZE];
+ u8 *buf;
+ int i, w, bytes;
+
+ buf = map_sysmem(addr, BUF_SIZE);
+
+ /* Fill with distinct bytes. */
+ for (i = 0; i < BUF_SIZE; ++i)
+ buf[i] = shadow[i] = i;
+
+ /* Parameter sanity checking. */
+ w = cmd_get_data_size(suffix, 4);
+ ut_assert(w == 1 || w == 2 || w == 4 || (MEM_SUPPORT_64BIT_DATA && w == 8));
+
+ bytes = count * w;
+ ut_assert(d < BUF_SIZE);
+ ut_assert(d + bytes <= BUF_SIZE);
+ ut_assert(s < BUF_SIZE);
+ ut_assert(s + bytes <= BUF_SIZE);
+
+ /* This is exactly what we expect to happen to "buf" */
+ memmove(shadow + d, shadow + s, bytes);
+
+ run_commandf("cp%s 0x%lx 0x%lx 0x%x", suffix, addr + s, addr + d, count);
+
+ ut_asserteq(0, memcmp(buf, shadow, BUF_SIZE));
+
+ unmap_sysmem(buf);
+
+ return 0;
+}
+
+static int mem_test_cp_b(struct unit_test_state *uts)
+{
+ static const struct param tests[] = {
+ { 0, 128, 128 },
+ { 128, 0, 128 },
+ { 0, 16, 32 },
+ { 16, 0, 32 },
+ { 60, 100, 100 },
+ { 100, 60, 100 },
+ { 123, 54, 96 },
+ { 54, 123, 96 },
+ };
+ const struct param *p;
+ int ret, i;
+
+ for (i = 0; i < ARRAY_SIZE(tests); ++i) {
+ p = &tests[i];
+ ret = do_test(uts, ".b", p->d, p->s, p->count);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+MEM_TEST(mem_test_cp_b);
+
+static int mem_test_cp_w(struct unit_test_state *uts)
+{
+ static const struct param tests[] = {
+ { 0, 128, 64 },
+ { 128, 0, 64 },
+ { 0, 16, 16 },
+ { 16, 0, 16 },
+ { 60, 100, 50 },
+ { 100, 60, 50 },
+ { 123, 54, 48 },
+ { 54, 123, 48 },
+ };
+ const struct param *p;
+ int ret, i;
+
+ for (i = 0; i < ARRAY_SIZE(tests); ++i) {
+ p = &tests[i];
+ ret = do_test(uts, ".w", p->d, p->s, p->count);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+MEM_TEST(mem_test_cp_w);
+
+static int mem_test_cp_l(struct unit_test_state *uts)
+{
+ static const struct param tests[] = {
+ { 0, 128, 32 },
+ { 128, 0, 32 },
+ { 0, 16, 8 },
+ { 16, 0, 8 },
+ { 60, 100, 25 },
+ { 100, 60, 25 },
+ { 123, 54, 24 },
+ { 54, 123, 24 },
+ };
+ const struct param *p;
+ int ret, i;
+
+ for (i = 0; i < ARRAY_SIZE(tests); ++i) {
+ p = &tests[i];
+ ret = do_test(uts, ".l", p->d, p->s, p->count);
+ if (ret)
+ return ret;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(tests); ++i) {
+ p = &tests[i];
+ ret = do_test(uts, "", p->d, p->s, p->count);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+MEM_TEST(mem_test_cp_l);
+
+#if MEM_SUPPORT_64BIT_DATA
+static int mem_test_cp_q(struct unit_test_state *uts)
+{
+ static const struct param tests[] = {
+ { 0, 128, 16 },
+ { 128, 0, 16 },
+ { 0, 16, 8 },
+ { 16, 0, 8 },
+ { 60, 100, 15 },
+ { 100, 60, 15 },
+ { 123, 54, 12 },
+ { 54, 123, 12 },
+ };
+ const struct param *p;
+ int ret, i;
+
+ for (i = 0; i < ARRAY_SIZE(tests); ++i) {
+ p = &tests[i];
+ ret = do_test(uts, ".q", p->d, p->s, p->count);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+MEM_TEST(mem_test_cp_q);
+#endif
int offset_count;
/* Get second pin of PMIC GPIO */
- ut_assertok(gpio_lookup_name("spmi1", &dev, &offset, &gpio));
+ ut_assertok(gpio_lookup_name("pmic1", &dev, &offset, &gpio));
/* Check if PMIC is parent */
ut_asserteq(device_get_uclass_id(dev->parent), UCLASS_PMIC);
name = gpio_get_bank_info(dev, &offset_count);
/* Check bank name */
- ut_asserteq_str("spmi", name);
+ ut_asserteq_str("pmic", name);
/* Check pin count */
ut_asserteq(4, offset_count);
# --------------------------------------------
# pre-requisite binaries list.
-PREREQ_BINS="md5sum mkfs mount umount dd fallocate mkdir"
+PREREQ_BINS="sha256sum mkfs mount umount dd fallocate mkdir"
# All generated output files from this test will be in $OUT_DIR
# Hence everything is sandboxed.
# $BIG_FILE is the name of the 2.5GB file in the file system image
BIG_FILE="2.5GB.file"
-# $MD5_FILE will have the expected md5s when we do the test
+# $HASH_FILE will have the expected hashes when we do the test
# They shall have a suffix which represents their file system (ext4/fat16/...)
-MD5_FILE="${OUT_DIR}/md5s.list"
+HASH_FILE="${OUT_DIR}/hash.list"
# $OUT shall be the prefix of the test output. Their suffix will be .out
OUT="${OUT_DIR}/fs-test"
# Clean out all generated files other than the file system images
# We save time by not deleting and recreating the file system images
function prepare_env() {
- rm -f ${MD5_FILE}.* ${OUT}.*
+ rm -f ${HASH_FILE}.* ${OUT}.*
mkdir -p ${OUT_DIR}
}
${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_SMALL
printenv filesize
# Test Case 4b - Read full 1MB of small file
-md5sum $addr \$filesize
+hash sha256 $addr \$filesize
setenv filesize
# Test Case 5a - First 1MB of big file
${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_BIG $length 0x0
printenv filesize
# Test Case 5b - First 1MB of big file
-md5sum $addr \$filesize
+hash sha256 $addr \$filesize
setenv filesize
# fails for ext as no offset support
${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_BIG $length 0x9C300000
printenv filesize
# Test Case 6b - Last 1MB of big file
-md5sum $addr \$filesize
+hash sha256 $addr \$filesize
setenv filesize
# fails for ext as no offset support
${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_BIG $length 0x7FF00000
printenv filesize
# Test Case 7b - One from the last 1MB chunk of 2GB
-md5sum $addr \$filesize
+hash sha256 $addr \$filesize
setenv filesize
# fails for ext as no offset support
${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_BIG $length 0x80000000
printenv filesize
# Test Case 8b - One from the start 1MB chunk from 2GB
-md5sum $addr \$filesize
+hash sha256 $addr \$filesize
setenv filesize
# fails for ext as no offset support
${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_BIG $length 0x7FF80000
printenv filesize
# Test Case 9b - One 1MB chunk crossing the 2GB boundary
-md5sum $addr \$filesize
+hash sha256 $addr \$filesize
setenv filesize
# Generic failure case
${PREFIX}${WRITE} host${SUFFIX} $addr ${FPATH}$FILE_WRITE \$filesize
mw.b $addr 00 100
${PREFIX}load host${SUFFIX} $addr ${FPATH}$FILE_WRITE
-# Test Case 11b - Check md5 of written to is same as the one read from
-md5sum $addr \$filesize
+# Test Case 11b - Check hash of written to is same as the one read from
+hash sha256 $addr \$filesize
setenv filesize
#
${PREFIX}${WRITE} host${SUFFIX} $addr ${FPATH}./${FILE_WRITE}2 \$filesize
mw.b $addr 00 100
${PREFIX}load host${SUFFIX} $addr ${FPATH}./${FILE_WRITE}2
-# Test Case 13b - Check md5 of written to is same as the one read from
-md5sum $addr \$filesize
+# Test Case 13b - Check hash of written to is same as the one read from
+hash sha256 $addr \$filesize
setenv filesize
mw.b $addr 00 100
${PREFIX}load host${SUFFIX} $addr ${FPATH}${FILE_WRITE}2
-# Test Case 13c - Check md5 of written to is same as the one read from
-md5sum $addr \$filesize
+# Test Case 13c - Check hash of written to is same as the one read from
+ hasheshash sha256 $addr \$filesize
setenv filesize
#
reset
}
# 1st argument is the name of the image file.
-# 2nd argument is the file where we generate the md5s of the files
+# 2nd argument is the file where we generate the hashes of the files
# generated with the appropriate start and length that we use to test.
# It creates the necessary files in the image to test.
# $GB2p5 is the path of the big file (2.5 GB)
sudo rm -f "${MB1}.w"
sudo rm -f "${MB1}.w2"
- # Generate the md5sums of reads that we will test against small file
- dd if="${MB1}" bs=1M skip=0 count=1 2> /dev/null | md5sum > "$2"
+ # Generate the hashes of reads that we will test against small file
+ dd if="${MB1}" bs=1M skip=0 count=1 2> /dev/null | sha256sum > "$2"
- # Generate the md5sums of reads that we will test against big file
+ # Generate the hashes of reads that we will test against big file
# One from beginning of file.
dd if="${GB2p5}" bs=1M skip=0 count=1 \
- 2> /dev/null | md5sum >> "$2"
+ 2> /dev/null | sha256sum >> "$2"
# One from end of file.
dd if="${GB2p5}" bs=1M skip=2499 count=1 \
- 2> /dev/null | md5sum >> "$2"
+ 2> /dev/null | sha256sum >> "$2"
# One from the last 1MB chunk of 2GB
dd if="${GB2p5}" bs=1M skip=2047 count=1 \
- 2> /dev/null | md5sum >> "$2"
+ 2> /dev/null | sha256sum >> "$2"
# One from the start 1MB chunk from 2GB
dd if="${GB2p5}" bs=1M skip=2048 count=1 \
- 2> /dev/null | md5sum >> "$2"
+ 2> /dev/null | sha256sum >> "$2"
# One 1MB chunk crossing the 2GB boundary
dd if="${GB2p5}" bs=512K skip=4095 count=2 \
- 2> /dev/null | md5sum >> "$2"
+ 2> /dev/null | sha256sum >> "$2"
sync
sudo umount "$MOUNT_DIR"
fi
}
-# 1st parameter is the string which leads to an md5 generation
+# 1st parameter is the string which leads to an hash generation
# 2nd parameter is the file we grep, for that string
-# 3rd parameter is the name of the file which has md5s in it
-# 4th parameter is the line # in the md5 file that we match it against
-# This function checks if the md5 of the file in the sandbox matches
+# 3rd parameter is the name of the file which has hashes in it
+# 4th parameter is the line # in the hash file that we match against
+# This function checks if the hash of the file in the sandbox matches
# that calculated while generating the file
# 5th parameter is the string to print with the result
-check_md5() {
- # md5sum in u-boot has output of form:
- # md5 for 01000008 ... 01100007 ==> <md5>
- # the 7th field is the actual md5
- md5_src=`grep -A2 "$1" "$2" | grep "md5 for" | tr -d '\r'`
- md5_src=($md5_src)
- md5_src=${md5_src[6]}
-
- # The md5 list, each line is of the form:
- # - <md5>
- # the 2nd field is the actual md5
- md5_dst=`sed -n $4p $3`
- md5_dst=($md5_dst)
- md5_dst=${md5_dst[0]}
+check_hash() {
+ # hash cmd output in u-boot has output of form:
+ # sha256 for 01000008 ... 01100007 ==> <hash>
+ # the 7th field is the actual hash
+ hash_src=`grep -A2 "$1" "$2" | grep "sha256 for" | tr -d '\r'`
+ hash_src=($hash_src)
+ hash_src=${hash_src[6]}
+
+ # The hash list, each line is of the form:
+ # - <hash>
+ # the 2nd field is the actual hash
+ hash_dst=`sed -n $4p $3`
+ hash_dst=($hash_dst)
+ hash_dst=${hash_dst[0]}
# For a pass they should match.
- [ "$md5_src" = "$md5_dst" ]
+ [ "$hash_src" = "$hash_dst" ]
pass_fail "$5"
}
# 1st parameter is the name of the output file to check
-# 2nd parameter is the name of the file containing the md5 expected
+# 2nd parameter is the name of the file containing the expected hash
# 3rd parameter is the name of the small file
# 4th parameter is the name of the big file
# 5th paramter is the name of the written file
# Check read full mb of 1MB.file
grep -A4 "Test Case 4a " "$1" | grep -q "filesize=100000"
pass_fail "TC4: load of $3 size"
- check_md5 "Test Case 4b " "$1" "$2" 1 "TC4: load from $3"
+ check_hash "Test Case 4b " "$1" "$2" 1 "TC4: load from $3"
# Check first mb of 2.5GB.file
grep -A4 "Test Case 5a " "$1" | grep -q "filesize=100000"
pass_fail "TC5: load of 1st MB from $4 size"
- check_md5 "Test Case 5b " "$1" "$2" 2 "TC5: load of 1st MB from $4"
+ check_hash "Test Case 5b " "$1" "$2" 2 "TC5: load of 1st MB from $4"
# Check last mb of 2.5GB.file
grep -A4 "Test Case 6a " "$1" | grep -q "filesize=100000"
pass_fail "TC6: load of last MB from $4 size"
- check_md5 "Test Case 6b " "$1" "$2" 3 "TC6: load of last MB from $4"
+ check_hash "Test Case 6b " "$1" "$2" 3 "TC6: load of last MB from $4"
# Check last 1mb chunk of 2gb from 2.5GB file
grep -A4 "Test Case 7a " "$1" | grep -q "filesize=100000"
pass_fail "TC7: load of last 1mb chunk of 2GB from $4 size"
- check_md5 "Test Case 7b " "$1" "$2" 4 \
+ check_hash "Test Case 7b " "$1" "$2" 4 \
"TC7: load of last 1mb chunk of 2GB from $4"
# Check first 1mb chunk after 2gb from 2.5GB file
grep -A4 "Test Case 8a " "$1" | grep -q "filesize=100000"
pass_fail "TC8: load 1st MB chunk after 2GB from $4 size"
- check_md5 "Test Case 8b " "$1" "$2" 5 \
+ check_hash "Test Case 8b " "$1" "$2" 5 \
"TC8: load 1st MB chunk after 2GB from $4"
# Check 1mb chunk crossing the 2gb boundary from 2.5GB file
grep -A4 "Test Case 9a " "$1" | grep -q "filesize=100000"
pass_fail "TC9: load 1MB chunk crossing 2GB boundary from $4 size"
- check_md5 "Test Case 9b " "$1" "$2" 6 \
+ check_hash "Test Case 9b " "$1" "$2" 6 \
"TC9: load 1MB chunk crossing 2GB boundary from $4"
# Check 2mb chunk from the last 1MB of 2.5GB file loads 1MB
# Check 1mb chunk write
grep -A2 "Test Case 11a " "$1" | grep -q '1048576 bytes written'
pass_fail "TC11: 1MB write to $3.w - write succeeded"
- check_md5 "Test Case 11b " "$1" "$2" 1 \
+ check_hash "Test Case 11b " "$1" "$2" 1 \
"TC11: 1MB write to $3.w - content verified"
# Check lookup of 'dot' directory
# Check directory traversal
grep -A2 "Test Case 13a " "$1" | grep -q '1048576 bytes written'
pass_fail "TC13: 1MB write to ./$3.w2 - write succeeded"
- check_md5 "Test Case 13b " "$1" "$2" 1 \
+ check_hash "Test Case 13b " "$1" "$2" 1 \
"TC13: 1MB read from ./$3.w2 - content verified"
- check_md5 "Test Case 13c " "$1" "$2" 1 \
+ check_hash "Test Case 13c " "$1" "$2" 1 \
"TC13: 1MB read from $3.w2 - content verified"
echo "** End $1"
# be performed.
function test_fs_nonfs() {
echo "Creating files in $fs image if not already present."
- create_files $IMAGE $MD5_FILE_FS
+ create_files $IMAGE $HASH_FILE_FS
OUT_FILE="${OUT}.$1.${fs}.out"
test_image $IMAGE $fs $SMALL_FILE $BIG_FILE $1 "" \
grep -v -e "File System is consistent\|update journal finished" \
-e "reading .*\.file\|writing .*\.file.w" \
< ${OUT_FILE} > ${OUT_FILE}_clean
- check_results ${OUT_FILE}_clean $MD5_FILE_FS $SMALL_FILE \
+ check_results ${OUT_FILE}_clean $HASH_FILE_FS $SMALL_FILE \
$BIG_FILE
TOTAL_FAIL=$((TOTAL_FAIL + FAIL))
TOTAL_PASS=$((TOTAL_PASS + PASS))
echo "Creating $fs image if not already present."
IMAGE=${IMG}.${fs}.img
- MD5_FILE_FS="${MD5_FILE}.${fs}"
+ HASH_FILE_FS="${HASH_FILE}.${fs}"
create_image $IMAGE $fs
# host commands test
echo "Creating files in $fs image if not already present."
- create_files $IMAGE $MD5_FILE_FS
+ create_files $IMAGE $HASH_FILE_FS
# Lets mount the image and test host hostfs commands
mkdir -p "$MOUNT_DIR"
sudo umount "$MOUNT_DIR"
rmdir "$MOUNT_DIR"
- check_results $OUT_FILE $MD5_FILE_FS $SMALL_FILE $BIG_FILE
+ check_results $OUT_FILE $HASH_FILE_FS $SMALL_FILE $BIG_FILE
TOTAL_FAIL=$((TOTAL_FAIL + FAIL))
TOTAL_PASS=$((TOTAL_PASS + PASS))
echo "Summary: PASS: $PASS FAIL: $FAIL"
ut_asserteq(1, run_command("dollar_foo='bar quux", 0));
/* Next line contains error message */
ut_assert_skipline();
-
- if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
- /*
- * For some strange reasons, the console is not empty after
- * running above command.
- * So, we reset it to not have side effects for other tests.
- */
- console_record_reset_enable();
- } else if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
- ut_assert_console_end();
- }
+ ut_assert_console_end();
ut_asserteq(1, run_command("dollar_foo=bar quux\"", 0));
- /* Two next lines contain error message */
- ut_assert_skipline();
+ /* Next line contains error message */
ut_assert_skipline();
-
- if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
- /* See above comments. */
- console_record_reset_enable();
- } else if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
- ut_assert_console_end();
- }
+ ut_assert_console_end();
ut_assertok(run_command("dollar_foo='bar \"quux'", 0));
pbr==5.4.3
pluggy==0.13.0
py==1.10.0
-pycryptodomex==3.9.8
+pycryptodomex==3.19.1
pyelftools==0.27
pygit2==1.9.2
pyparsing==3.0.7
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+# (C) Copyright 2023, Advanced Micro Devices, Inc.
+
+import pytest
+import random
+import re
+
+"""
+Note: This test relies on boardenv_* containing configuration values to define
+the i2c device info including the bus list and eeprom address/value. This test
+will be automatically skipped without this.
+
+For example:
+
+# Setup env__i2c_device_test to set the i2c bus list and probe_all boolean
+# parameter. For i2c_probe_all_buses case, if probe_all parameter is set to
+# False then it probes all the buses listed in bus_list instead of probing all
+# the buses available.
+env__i2c_device_test = {
+ 'bus_list': [0, 2, 5, 12, 16, 18],
+ 'probe_all': False,
+}
+
+# Setup env__i2c_eeprom_device_test to set the i2c bus number, eeprom address
+# and configured value for i2c_eeprom test case. Test will be skipped if
+# env__i2c_eeprom_device_test is not set
+env__i2c_eeprom_device_test = {
+ 'bus': 3,
+ 'eeprom_addr': 0x54,
+ 'eeprom_val': '30 31',
+}
+"""
+
+def get_i2c_test_env(u_boot_console):
+ f = u_boot_console.config.env.get("env__i2c_device_test", None)
+ if not f:
+ pytest.skip("No I2C device to test!")
+ else:
+ bus_list = f.get("bus_list", None)
+ if not bus_list:
+ pytest.skip("I2C bus list is not provided!")
+ probe_all = f.get("probe_all", False)
+ return bus_list, probe_all
+
+@pytest.mark.buildconfigspec("cmd_i2c")
+def test_i2c_bus(u_boot_console):
+ bus_list, probe = get_i2c_test_env(u_boot_console)
+ bus = random.choice(bus_list)
+ expected_response = f"Bus {bus}:"
+ response = u_boot_console.run_command("i2c bus")
+ assert expected_response in response
+
+@pytest.mark.buildconfigspec("cmd_i2c")
+def test_i2c_dev(u_boot_console):
+ bus_list, probe = get_i2c_test_env(u_boot_console)
+ expected_response = "Current bus is"
+ response = u_boot_console.run_command("i2c dev")
+ assert expected_response in response
+
+@pytest.mark.buildconfigspec("cmd_i2c")
+def test_i2c_probe(u_boot_console):
+ bus_list, probe = get_i2c_test_env(u_boot_console)
+ bus = random.choice(bus_list)
+ expected_response = f"Setting bus to {bus}"
+ response = u_boot_console.run_command(f"i2c dev {bus}")
+ assert expected_response in response
+ expected_response = "Valid chip addresses:"
+ response = u_boot_console.run_command("i2c probe")
+ assert expected_response in response
+
+@pytest.mark.buildconfigspec("cmd_i2c")
+def test_i2c_eeprom(u_boot_console):
+ f = u_boot_console.config.env.get("env__i2c_eeprom_device_test", None)
+ if not f:
+ pytest.skip("No I2C eeprom to test!")
+
+ bus = f.get("bus", 0)
+ if bus < 0:
+ pytest.fail("No bus specified via env__i2c_eeprom_device_test!")
+
+ addr = f.get("eeprom_addr", -1)
+ if addr < 0:
+ pytest.fail("No eeprom address specified via env__i2c_eeprom_device_test!")
+
+ value = f.get("eeprom_val")
+ if not value:
+ pytest.fail(
+ "No eeprom configured value provided via env__i2c_eeprom_device_test!"
+ )
+
+ # Enable i2c mux bridge
+ u_boot_console.run_command("i2c dev %x" % bus)
+ u_boot_console.run_command("i2c probe")
+ output = u_boot_console.run_command("i2c md %x 0 5" % addr)
+ assert value in output
+
+@pytest.mark.buildconfigspec("cmd_i2c")
+def test_i2c_probe_all_buses(u_boot_console):
+ bus_list, probe = get_i2c_test_env(u_boot_console)
+ bus = random.choice(bus_list)
+ expected_response = f"Bus {bus}:"
+ response = u_boot_console.run_command("i2c bus")
+ assert expected_response in response
+
+ # Get all the bus list
+ if probe:
+ buses = re.findall("Bus (.+?):", response)
+ bus_list = [int(x) for x in buses]
+
+ for dev in bus_list:
+ expected_response = f"Setting bus to {dev}"
+ response = u_boot_console.run_command(f"i2c dev {dev}")
+ assert expected_response in response
+ expected_response = "Valid chip addresses:"
+ response = u_boot_console.run_command("i2c probe")
+ assert expected_response in response
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+# (C) Copyright 2023, Advanced Micro Devices, Inc.
+
+import pytest
+import re
+
+"""
+Note: This test relies on boardenv_* containing configuration values to define
+the PHY device info including the device name, address, register address/value
+and write data value. This test will be automatically skipped without this.
+
+For example:
+
+# Setup env__mdio_util_test to set the PHY address, device names, register
+# address, register address value, and write data value to test mdio commands.
+# Test will be skipped if env_mdio_util_test is not set
+env__mdio_util_test = {
+ "eth0": {"phy_addr": 0xc, "device_name": "TI DP83867", "reg": 0,
+ "reg_val": 0x1000, "write_val": 0x100},
+ "eth1": {"phy_addr": 0xa0, "device_name": "TI DP83867", "reg": 1,
+ "reg_val": 0x2000, "write_val": 0x100},
+}
+"""
+
+def get_mdio_test_env(u_boot_console):
+ f = u_boot_console.config.env.get("env__mdio_util_test", None)
+ if not f or len(f) == 0:
+ pytest.skip("No PHY device to test!")
+ else:
+ return f
+
+@pytest.mark.buildconfigspec("cmd_mii")
+@pytest.mark.buildconfigspec("phylib")
+def test_mdio_list(u_boot_console):
+ f = get_mdio_test_env(u_boot_console)
+ output = u_boot_console.run_command("mdio list")
+ for dev, val in f.items():
+ phy_addr = val.get("phy_addr")
+ dev_name = val.get("device_name")
+
+ assert f"{phy_addr:x} -" in output
+ assert dev_name in output
+
+@pytest.mark.buildconfigspec("cmd_mii")
+@pytest.mark.buildconfigspec("phylib")
+def test_mdio_read(u_boot_console):
+ f = get_mdio_test_env(u_boot_console)
+ output = u_boot_console.run_command("mdio list")
+ for dev, val in f.items():
+ phy_addr = hex(val.get("phy_addr"))
+ dev_name = val.get("device_name")
+ reg = hex(val.get("reg"))
+ reg_val = hex(val.get("reg_val"))
+
+ output = u_boot_console.run_command(f"mdio read {phy_addr} {reg}")
+ assert f"PHY at address {int(phy_addr, 16):x}:" in output
+ assert f"{int(reg, 16):x} - {reg_val}" in output
+
+@pytest.mark.buildconfigspec("cmd_mii")
+@pytest.mark.buildconfigspec("phylib")
+def test_mdio_write(u_boot_console):
+ f = get_mdio_test_env(u_boot_console)
+ output = u_boot_console.run_command("mdio list")
+ for dev, val in f.items():
+ phy_addr = hex(val.get("phy_addr"))
+ dev_name = val.get("device_name")
+ reg = hex(val.get("reg"))
+ reg_val = hex(val.get("reg_val"))
+ wr_val = hex(val.get("write_val"))
+
+ u_boot_console.run_command(f"mdio write {phy_addr} {reg} {wr_val}")
+ output = u_boot_console.run_command(f"mdio read {phy_addr} {reg}")
+ assert f"PHY at address {int(phy_addr, 16):x}:" in output
+ assert f"{int(reg, 16):x} - {wr_val}" in output
+
+ u_boot_console.run_command(f"mdio write {phy_addr} {reg} {reg_val}")
+ output = u_boot_console.run_command(f"mdio read {phy_addr} {reg}")
+ assert f"PHY at address {int(phy_addr, 16):x}:" in output
+ assert f"{int(reg, 16):x} - {reg_val}" in output
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+# (C) Copyright 2023, Advanced Micro Devices, Inc.
+
+import pytest
+
+"""
+Note: This test relies on boardenv_* containing configuration values to define
+the memory test parameters such as start address, memory size, pattern,
+iterations and timeout. This test will be automatically skipped without this.
+
+For example:
+
+# Setup env__memtest to set the start address of the memory range, size of the
+# memory range to test from starting address, pattern to be written to memory,
+# number of test iterations, and expected time to complete the test of mtest
+# command. start address, size, and pattern parameters value should be in hex
+# and rest of the params value should be integer.
+env__memtest = {
+ 'start_addr': 0x0,
+ 'size': 0x1000,
+ 'pattern': 0x0,
+ 'iteration': 16,
+ 'timeout': 50000,
+}
+"""
+
+def get_memtest_env(u_boot_console):
+ f = u_boot_console.config.env.get("env__memtest", None)
+ if not f:
+ pytest.skip("memtest is not enabled!")
+ else:
+ start = f.get("start_addr", 0x0)
+ size = f.get("size", 0x1000)
+ pattern = f.get("pattern", 0x0)
+ iteration = f.get("iteration", 2)
+ timeout = f.get("timeout", 50000)
+ end = hex(int(start) + int(size))
+ return start, end, pattern, iteration, timeout
+
+@pytest.mark.buildconfigspec("cmd_memtest")
+def test_memtest_negative(u_boot_console):
+ """Negative testcase where end address is smaller than starting address and
+ pattern is invalid."""
+ start, end, pattern, iteration, timeout = get_memtest_env(u_boot_console)
+ expected_response = "Refusing to do empty test"
+ response = u_boot_console.run_command(
+ f"mtest 2000 1000 {pattern} {hex(iteration)}"
+ )
+ assert expected_response in response
+ output = u_boot_console.run_command("echo $?")
+ assert not output.endswith("0")
+ u_boot_console.run_command(f"mtest {start} {end} 'xyz' {hex(iteration)}")
+ output = u_boot_console.run_command("echo $?")
+ assert not output.endswith("0")
+
+@pytest.mark.buildconfigspec("cmd_memtest")
+def test_memtest_ddr(u_boot_console):
+ """Test that md reads memory as expected, and that memory can be modified
+ using the mw command."""
+ start, end, pattern, iteration, timeout = get_memtest_env(u_boot_console)
+ expected_response = f"Tested {str(iteration)} iteration(s) with 0 errors."
+ with u_boot_console.temporary_timeout(timeout):
+ response = u_boot_console.run_command(
+ f"mtest {start} {end} {pattern} {hex(iteration)}"
+ )
+ assert expected_response in response
+ output = u_boot_console.run_command("echo $?")
+ assert output.endswith("0")
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+# (C) Copyright 2023, Advanced Micro Devices, Inc.
+
+import pytest
+import re
+
+"""
+Note: This test doesn't rely on boardenv_* configuration value but they can
+change test behavior.
+
+For example:
+
+# Setup env__mii_deive_test_skip to True if tests with ethernet PHY devices
+# should be skipped. For example: Missing PHY device
+env__mii_device_test_skip = True
+
+# Setup env__mii_device_test to set the MII device names. Test will be skipped
+# if env_mii_device_test is not set
+env__mii_device_test = {
+ 'device_list': ['eth0', 'eth1'],
+}
+"""
+
+@pytest.mark.buildconfigspec("cmd_mii")
+def test_mii_info(u_boot_console):
+ if u_boot_console.config.env.get("env__mii_device_test_skip", False):
+ pytest.skip("MII device test is not enabled!")
+ expected_output = "PHY"
+ output = u_boot_console.run_command("mii info")
+ if not re.search(r"PHY (.+?):", output):
+ pytest.skip("PHY device does not exist!")
+ assert expected_output in output
+
+@pytest.mark.buildconfigspec("cmd_mii")
+def test_mii_list(u_boot_console):
+ if u_boot_console.config.env.get("env__mii_device_test_skip", False):
+ pytest.skip("MII device test is not enabled!")
+
+ f = u_boot_console.config.env.get("env__mii_device_test", None)
+ if not f:
+ pytest.skip("No MII device to test!")
+
+ dev_list = f.get("device_list")
+ if not dev_list:
+ pytest.fail("No MII device list provided via env__mii_device_test!")
+
+ expected_output = "Current device"
+ output = u_boot_console.run_command("mii device")
+ mii_devices = (
+ re.search(r"MII devices: '(.+)'", output).groups()[0].replace("'", "").split()
+ )
+
+ assert len([x for x in dev_list if x in mii_devices]) == len(dev_list)
+ assert expected_output in output
+
+@pytest.mark.buildconfigspec("cmd_mii")
+def test_mii_set_device(u_boot_console):
+ test_mii_list(u_boot_console)
+ f = u_boot_console.config.env.get("env__mii_device_test", None)
+ dev_list = f.get("device_list")
+ output = u_boot_console.run_command("mii device")
+ current_dev = re.search(r"Current device: '(.+?)'", output).groups()[0]
+
+ for dev in dev_list:
+ u_boot_console.run_command(f"mii device {dev}")
+ output = u_boot_console.run_command("echo $?")
+ assert output.endswith("0")
+
+ u_boot_console.run_command(f"mii device {current_dev}")
+ output = u_boot_console.run_command("mii device")
+ dev = re.search(r"Current device: '(.+?)'", output).groups()[0]
+ assert current_dev == dev
+
+@pytest.mark.buildconfigspec("cmd_mii")
+def test_mii_read(u_boot_console):
+ test_mii_list(u_boot_console)
+ output = u_boot_console.run_command("mii info")
+ eth_addr = hex(int(re.search(r"PHY (.+?):", output).groups()[0], 16))
+ u_boot_console.run_command(f"mii read {eth_addr} 0")
+ output = u_boot_console.run_command("echo $?")
+ assert output.endswith("0")
+
+@pytest.mark.buildconfigspec("cmd_mii")
+def test_mii_dump(u_boot_console):
+ test_mii_list(u_boot_console)
+ expected_response = "PHY control register"
+ output = u_boot_console.run_command("mii info")
+ eth_addr = hex(int(re.search(r"PHY (.+?):", output).groups()[0], 16))
+ response = u_boot_console.run_command(f"mii dump {eth_addr} 0")
+ assert expected_response in response
+ output = u_boot_console.run_command("echo $?")
+ assert output.endswith("0")
import u_boot_utils
import uuid
import datetime
+import re
"""
Note: This test relies on boardenv_* containing configuration values to define
# set to False.
env__net_dhcp_server = True
+# False or omitted if a DHCP server is attached to the network, and dhcp abort
+# case should be tested.
+# If DHCP abort testing is not possible or desired, set this variable to True.
+env__dhcp_abort_test_skip = True
+
# True if a DHCPv6 server is attached to the network, and should be tested.
# If DHCPv6 testing is not possible or desired, this variable may be omitted or
# set to False.
if init_pci:
u_boot_console.run_command('pci enum')
+ u_boot_console.run_command('net list')
+
@pytest.mark.buildconfigspec('cmd_dhcp')
def test_net_dhcp(u_boot_console):
"""Test the dhcp command.
global net_set_up
net_set_up = True
+@pytest.mark.buildconfigspec("cmd_dhcp")
+@pytest.mark.buildconfigspec("cmd_mii")
+def test_net_dhcp_abort(u_boot_console):
+ """Test the dhcp command by pressing ctrl+c in the middle of dhcp request
+
+ The boardenv_* file may be used to enable/disable this test; see the
+ comment at the beginning of this file.
+ """
+
+ test_dhcp = u_boot_console.config.env.get("env__net_dhcp_server", False)
+ if not test_dhcp:
+ pytest.skip("No DHCP server available")
+
+ if u_boot_console.config.env.get("env__dhcp_abort_test_skip", False):
+ pytest.skip("DHCP abort test is not enabled!")
+
+ u_boot_console.run_command("setenv autoload no")
+
+ # Phy reset before running dhcp command
+ output = u_boot_console.run_command("mii device")
+ if not re.search(r"Current device: '(.+?)'", output):
+ pytest.skip("PHY device does not exist!")
+ eth_num = re.search(r"Current device: '(.+?)'", output).groups()[0]
+ u_boot_console.run_command(f"mii device {eth_num}")
+ output = u_boot_console.run_command("mii info")
+ eth_addr = hex(int(re.search(r"PHY (.+?):", output).groups()[0], 16))
+ u_boot_console.run_command(f"mii modify {eth_addr} 0 0x8000 0x8000")
+
+ u_boot_console.run_command("dhcp", wait_for_prompt=False)
+ try:
+ u_boot_console.wait_for("Waiting for PHY auto negotiation to complete")
+ except:
+ pytest.skip("Timeout waiting for PHY auto negotiation to complete")
+
+ u_boot_console.wait_for("done")
+
+ # Sending Ctrl-C
+ output = u_boot_console.run_command(
+ chr(3), wait_for_echo=False, send_nl=False
+ )
+
+ assert "TIMEOUT" not in output
+ assert "DHCP client bound to address " not in output
+ assert "Abort" in output
+
+ # Provide a time to recover from Abort - if it is not performed
+ # There is message like: ethernet@ff0e0000: No link.
+ u_boot_console.run_command("sleep 1")
+ # Run the dhcp test to setup the network configuration
+ test_net_dhcp(u_boot_console)
+
@pytest.mark.buildconfigspec('cmd_dhcp6')
def test_net_dhcp6(u_boot_console):
"""Test the dhcp6 command.
This selection does not affect target features, such as runtime FIT
signature verification.
+config TOOLS_KWBIMAGE
+ bool "Enable kwbimage support in host tools"
+ default y
+ select TOOLS_LIBCRYPTO
+
config TOOLS_FIT
def_bool y
help
Support the rsassa-pss signature scheme in the tools builds
config TOOLS_FIT_SIGNATURE
+ depends on TOOLS_LIBCRYPTO
def_bool y
help
Enable signature verification of FIT uImages in the tools builds
generated/lib/fdt-libcrypto.o \
sunxi_toc0.o
+KWB_IMAGE_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := kwbimage.o
+
ROCKCHIP_OBS = generated/lib/rc4.o rkcommon.o rkimage.o rksd.o rkspi.o
# common objs for dumpimage and mkimage
imximage.o \
imx8image.o \
imx8mimage.o \
- kwbimage.o \
+ $(KWB_IMAGE_OBJS-y) \
generated/lib/md5.o \
lpc32xximage.o \
mxsimage.o \
ret = fit_set_timestamp(ptr, 0, time);
}
- if (!ret)
+ if (CONFIG_IS_ENABLED(FIT_SIGNATURE) && !ret)
ret = fit_pre_load_data(params->keydir, dest_blob, ptr);
if (!ret) {
#include <image.h>
#include <version.h>
+#if CONFIG_IS_ENABLED(FIT_SIGNATURE)
#include <openssl/pem.h>
#include <openssl/evp.h>
+#endif
/**
* fit_set_hash_value - set hash value in requested has node
return 0;
}
+#if CONFIG_IS_ENABLED(FIT_SIGNATURE)
/*
* 0) open file (open)
* 1) read certificate (PEM_read_X509)
out:
return ret;
}
+#endif
int fit_cipher_data(const char *keydir, void *keydest, void *fit,
const char *comment, int require_keys,
" -B => align size in hex for FIT structure and header\n"
" -b => append the device tree binary to the FIT\n"
" -t => update the timestamp in the FIT\n");
-#ifdef CONFIG_FIT_SIGNATURE
+#if CONFIG_IS_ENABLED(FIT_SIGNATURE)
fprintf(stderr,
"Signing / verified boot options: [-k keydir] [-K dtb] [ -c <comment>] [-p addr] [-r] [-N engine]\n"
" -k => set directory containing private keys\n"
" -o => algorithm to use for signing\n");
#else
fprintf(stderr,
- "Signing / verified boot not supported (CONFIG_FIT_SIGNATURE undefined)\n");
+ "Signing / verified boot not supported (CONFIG_TOOLS_FIT_SIGNATURE undefined)\n");
#endif
+
fprintf(stderr, " %s -V ==> print version information and exit\n",
params.cmdname);
fprintf(stderr, "Use '-T list' to see a list of available image types\n");
Commit-notes:
Similar, but for a single commit (patch). These notes will appear
- immediately below the --- cut in the patch file::
+ immediately below the ``---`` cut in the patch file::
Commit-notes:
blah blah
projects / thirdparty / u-boot.git / commitdiff
