RISC-V: Dump instruction without checking architecture support as usual.

Since QEMU have supported -Max option to to enable all normal extensions,
the dis-assembler should also add an option, -M,max to do the same thing.
For the instruction, which have overlapped encodings like zfinx, will not
be considered by the -M,max option.

opcodes/
	* riscv-dis.c (all_ext): New static boolean.  If set, disassemble
	without checking architectire string.
	(riscv_disassemble_insn): Likewise.
	(parse_riscv_dis_option_without_args): Recognized -M,max option.
binutils/
	* NEWS: Updated.

diff --git a/binutils/NEWS b/binutils/NEWS
index 50c40afaf576ab0afcb28930618f85e7da82cf1c..92cc9506c80dca184ede2f0f71ad9fe8dc70971e 100644 (file)
--- a/binutils/NEWS
+++ b/binutils/NEWS
@@ -1,5 +1,8 @@
 -*- text -*-
 
+* RISC-V disassembly now supports -M,max option like QEMU to dump instruction
+  without checking architecture support as usual.
+
 Changes in 2.43:
 
 * The MIPS port now supports microMIPS MT Application Specific Extension

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 551d57e4cbadc4d0fb8de558b2ff985a331ee076..80018db837abcdec0bf02493ec37fa32aaa13b3b 100644 (file)
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -80,6 +80,9 @@ static const char (*riscv_fpr_names)[NRC];
 /* If set, disassemble as most general instruction.  */
 static bool no_aliases = false;
 
+/* If set, disassemble without checking architectire string, just like what
+   we did at the beginning.  */
+static bool all_ext = false;
 
 /* Set default RISC-V disassembler options.  */
 
@@ -103,6 +106,8 @@ parse_riscv_dis_option_without_args (const char *option)
       riscv_gpr_names = riscv_gpr_names_numeric;
       riscv_fpr_names = riscv_fpr_names_numeric;
     }
+  else if (strcmp (option, "max") == 0)
+    all_ext = true;
   else
     return false;
   return true;
@@ -968,7 +973,8 @@ riscv_disassemble_insn (bfd_vma memaddr,
          if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
            continue;
          /* Is this instruction supported by the current architecture?  */
-         if (!riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class))
+         if (!all_ext
+             && !riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class))
            continue;
 
          /* It's a match.  */