]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
ARM: uniphier: dts: add more clocks to Denali NAND controller node
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Fri, 20 Jul 2018 08:50:44 +0000 (17:50 +0900)
committerMasahiro Yamada <yamada.masahiro@socionext.com>
Tue, 28 Aug 2018 14:14:50 +0000 (23:14 +0900)
Catch up with the new binding of the Denali IP where three clocks,
"nand", "nand_x", "ecc" are required.

For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they
are both 200MHz.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
arch/arm/boot/dts/uniphier-ld4.dtsi
arch/arm/boot/dts/uniphier-pro4.dtsi
arch/arm/boot/dts/uniphier-pro5.dtsi
arch/arm/boot/dts/uniphier-pxs2.dtsi
arch/arm/boot/dts/uniphier-sld8.dtsi

index 37950ad2de7c81024adc730a10f14b1c2d16488b..2a170667f94e4aa83ecb6fcca2d4fe7b4a547ede 100644 (file)
                        interrupts = <0 65 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand2cs>;
-                       clocks = <&sys_clk 2>;
+                       clock-names = "nand", "nand_x", "ecc";
+                       clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
                        resets = <&sys_rst 2>;
                };
        };
index 49539f0352193cb4e1c768e7f13ee6ce5b5215c8..da88ccc4fc800885a7d64a76abea019f9378f66a 100644 (file)
                        interrupts = <0 65 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand>;
-                       clocks = <&sys_clk 2>;
+                       clock-names = "nand", "nand_x", "ecc";
+                       clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
                        resets = <&sys_rst 2>;
                };
        };
index 06c2cef91ec73aee07d028fb0301ec15192fd2b1..40a84f2c0b8148a3f9ff799216161af78cf6e60b 100644 (file)
                        interrupts = <0 65 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand2cs>;
-                       clocks = <&sys_clk 2>;
+                       clock-names = "nand", "nand_x", "ecc";
+                       clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
                        resets = <&sys_rst 2>;
                };
        };
index e2d1a22c5950d5310838222049891f9ea6fe313d..79f5c2d7ffcf086d1fed3438e80a0ec3d9ddb890 100644 (file)
                        interrupts = <0 65 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand2cs>;
-                       clocks = <&sys_clk 2>;
+                       clock-names = "nand", "nand_x", "ecc";
+                       clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
                        resets = <&sys_rst 2>;
                };
        };
index e9b9b4f3c5581606895467a57bc79eb42534c01b..dc723bf2f8f23bb4a1bfee3837b1f9abfe887fbd 100644 (file)
                        interrupts = <0 65 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand2cs>;
-                       clocks = <&sys_clk 2>;
+                       clock-names = "nand", "nand_x", "ecc";
+                       clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
                        resets = <&sys_rst 2>;
                };
        };