]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
i2c: riic: Use BIT macro consistently
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Mon, 13 Jan 2025 12:26:37 +0000 (12:26 +0000)
committerWolfram Sang <wsa+renesas@sang-engineering.com>
Tue, 14 Jan 2025 12:01:30 +0000 (13:01 +0100)
Easier to read and ensures proper types.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
drivers/i2c/busses/i2c-riic.c

index c555b6220e661bacce26346cb9757d673a81b11e..370cb83bf5ac26faf458bdc7a4829a9d4a09dd17 100644 (file)
@@ -34,6 +34,7 @@
  * Also check the comments in the interrupt routines for some gory details.
  */
 
+#include <linux/bits.h>
 #include <linux/clk.h>
 #include <linux/completion.h>
 #include <linux/err.h>
 #include <linux/pm_runtime.h>
 #include <linux/reset.h>
 
-#define ICCR1_ICE      0x80
-#define ICCR1_IICRST   0x40
-#define ICCR1_SOWP     0x10
+#define ICCR1_ICE      BIT(7)
+#define ICCR1_IICRST   BIT(6)
+#define ICCR1_SOWP     BIT(4)
 
-#define ICCR2_BBSY     0x80
-#define ICCR2_SP       0x08
-#define ICCR2_RS       0x04
-#define ICCR2_ST       0x02
+#define ICCR2_BBSY     BIT(7)
+#define ICCR2_SP       BIT(3)
+#define ICCR2_RS       BIT(2)
+#define ICCR2_ST       BIT(1)
 
 #define ICMR1_CKS_MASK 0x70
-#define ICMR1_BCWP     0x08
+#define ICMR1_BCWP     BIT(3)
 #define ICMR1_CKS(_x)  ((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP)
 
-#define ICMR3_RDRFS    0x20
-#define ICMR3_ACKWP    0x10
-#define ICMR3_ACKBT    0x08
+#define ICMR3_RDRFS    BIT(5)
+#define ICMR3_ACKWP    BIT(4)
+#define ICMR3_ACKBT    BIT(3)
 
-#define ICFER_FMPE     0x80
+#define ICFER_FMPE     BIT(7)
 
-#define ICIER_TIE      0x80
-#define ICIER_TEIE     0x40
-#define ICIER_RIE      0x20
-#define ICIER_NAKIE    0x10
-#define ICIER_SPIE     0x08
+#define ICIER_TIE      BIT(7)
+#define ICIER_TEIE     BIT(6)
+#define ICIER_RIE      BIT(5)
+#define ICIER_NAKIE    BIT(4)
+#define ICIER_SPIE     BIT(3)
 
-#define ICSR2_NACKF    0x10
+#define ICSR2_NACKF    BIT(4)
 
 #define ICBR_RESERVED  0xe0 /* Should be 1 on writes */