]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
riscv: add Andes SoC family Kconfig support
authorBen Zong-You Xie <ben717@andestech.com>
Fri, 11 Jul 2025 13:30:17 +0000 (21:30 +0800)
committerArnd Bergmann <arnd@arndb.de>
Mon, 21 Jul 2025 14:51:52 +0000 (16:51 +0200)
The first SoC in the Andes series is QiLai. It includes a high-performance
quad-core RISC-V AX45MP cluster and one NX27V vector processor.

For further information, refer to [1].

[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-2-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arch/riscv/Kconfig.socs

index a9c3d2f6debca1469f4a912b3414711eb709baab..61ceae0aa27a6fa3a91da6a46becfd96da99fd09 100644 (file)
@@ -1,5 +1,12 @@
 menu "SoC selection"
 
+config ARCH_ANDES
+       bool "Andes SoCs"
+       depends on MMU && !XIP_KERNEL
+       select ERRATA_ANDES
+       help
+         This enables support for Andes SoC platform hardware.
+
 config ARCH_MICROCHIP_POLARFIRE
        def_bool ARCH_MICROCHIP