patches for 5.0

Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/queue-5.0/drm-disable-uncached-dma-optimization-for-arm-and-ar.patch b/queue-5.0/drm-disable-uncached-dma-optimization-for-arm-and-ar.patch
new file mode 100644 (file)
index 0000000..7f68b68
--- /dev/null
+++ b/queue-5.0/drm-disable-uncached-dma-optimization-for-arm-and-ar.patch
@@ -0,0 +1,86 @@
+From 5e332ea06ec327fe75c725f2df55fbf888269ac8 Mon Sep 17 00:00:00 2001
+From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+Date: Thu, 24 Jan 2019 13:06:58 +0100
+Subject: drm: disable uncached DMA optimization for ARM and arm64
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+[ Upstream commit e02f5c1bb2283cfcee68f2f0feddcc06150f13aa ]
+
+The DRM driver stack is designed to work with cache coherent devices
+only, but permits an optimization to be enabled in some cases, where
+for some buffers, both the CPU and the GPU use uncached mappings,
+removing the need for DMA snooping and allocation in the CPU caches.
+
+The use of uncached GPU mappings relies on the correct implementation
+of the PCIe NoSnoop TLP attribute by the platform, otherwise the GPU
+will use cached mappings nonetheless. On x86 platforms, this does not
+seem to matter, as uncached CPU mappings will snoop the caches in any
+case. However, on ARM and arm64, enabling this optimization on a
+platform where NoSnoop is ignored results in loss of coherency, which
+breaks correct operation of the device. Since we have no way of
+detecting whether NoSnoop works or not, just disable this
+optimization entirely for ARM and arm64.
+
+Cc: Christian Koenig <christian.koenig@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: David Zhou <David1.Zhou@amd.com>
+Cc: Huang Rui <ray.huang@amd.com>
+Cc: Junwei Zhang <Jerry.Zhang@amd.com>
+Cc: Michel Daenzer <michel.daenzer@amd.com>
+Cc: David Airlie <airlied@linux.ie>
+Cc: Daniel Vetter <daniel@ffwll.ch>
+Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
+Cc: Maxime Ripard <maxime.ripard@bootlin.com>
+Cc: Sean Paul <sean@poorly.run>
+Cc: Michael Ellerman <mpe@ellerman.id.au>
+Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Cc: Will Deacon <will.deacon@arm.com>
+Cc: Christoph Hellwig <hch@infradead.org>
+Cc: Robin Murphy <robin.murphy@arm.com>
+Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
+Cc: dri-devel <dri-devel@lists.freedesktop.org>
+Reported-by: Carsten Haitzler <Carsten.Haitzler@arm.com>
+Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Link: https://patchwork.kernel.org/patch/10778815/
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/drm/drm_cache.h | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
+index bfe1639df02d..97fc498dc767 100644
+--- a/include/drm/drm_cache.h
++++ b/include/drm/drm_cache.h
+@@ -47,6 +47,24 @@ static inline bool drm_arch_can_wc_memory(void)
+       return false;
+ #elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON3)
+       return false;
++#elif defined(CONFIG_ARM) || defined(CONFIG_ARM64)
++      /*
++       * The DRM driver stack is designed to work with cache coherent devices
++       * only, but permits an optimization to be enabled in some cases, where
++       * for some buffers, both the CPU and the GPU use uncached mappings,
++       * removing the need for DMA snooping and allocation in the CPU caches.
++       *
++       * The use of uncached GPU mappings relies on the correct implementation
++       * of the PCIe NoSnoop TLP attribute by the platform, otherwise the GPU
++       * will use cached mappings nonetheless. On x86 platforms, this does not
++       * seem to matter, as uncached CPU mappings will snoop the caches in any
++       * case. However, on ARM and arm64, enabling this optimization on a
++       * platform where NoSnoop is ignored results in loss of coherency, which
++       * breaks correct operation of the device. Since we have no way of
++       * detecting whether NoSnoop works or not, just disable this
++       * optimization entirely for ARM and arm64.
++       */
++      return false;
+ #else
+       return true;
+ #endif
+-- 
+2.19.1
+

diff --git a/queue-5.0/series b/queue-5.0/series
index 9278e33e01e4bf784957b3cf7e6f529dbc631d77..7c2a5752b42fa2b6787b3fe30d58a987745d41dc 100644 (file)
--- a/queue-5.0/series
+++ b/queue-5.0/series
@@ -10,3 +10,4 @@ arm64-dts-hikey-revert-enable-hs200-mode-on-emmc.patch
 arm-dts-exynos-fix-pinctrl-definition-for-emmc-rtsn-line-on-odroid-x2-u3.patch
 arm-dts-exynos-add-minimal-clkout-parameters-to-exynos3250-pmu.patch
 arm-dts-exynos-fix-max-voltage-for-buck8-regulator-on-odroid-xu3-xu4.patch
+drm-disable-uncached-dma-optimization-for-arm-and-ar.patch