--- /dev/null
+From 57a1592784d622ecee0b71940c65429173996b33 Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Tue, 26 Mar 2024 12:36:59 +0100
+Subject: iio: accel: mxc4005: Interrupt handling fixes
+
+From: Hans de Goede <hdegoede@redhat.com>
+
+commit 57a1592784d622ecee0b71940c65429173996b33 upstream.
+
+There are 2 issues with interrupt handling in the mxc4005 driver:
+
+1. mxc4005_set_trigger_state() writes MXC4005_REG_INT_MASK1_BIT_DRDYE
+(0x01) to INT_MASK1 to enable the interrupt, but to disable the interrupt
+it writes ~MXC4005_REG_INT_MASK1_BIT_DRDYE which is 0xfe, so it enables
+all other interrupt sources in the INT_SRC1 register. On the MXC4005 this
+is not an issue because only bit 0 of the register is used. On the MXC6655
+OTOH this is a problem since bit7 is used as TC (Temperature Compensation)
+disable bit and writing 1 to this disables Temperature Compensation which
+should only be done when running self-tests on the chip.
+
+Write 0 instead of ~MXC4005_REG_INT_MASK1_BIT_DRDYE to disable
+the interrupts to fix this.
+
+2. The datasheets for the MXC4005 / MXC6655 do not state what the reset
+value for the INT_MASK0 and INT_MASK1 registers is and since these are
+write only we also cannot learn this from the hw. Presumably the reset
+value for both is all 0, which means all interrupts disabled.
+
+Explicitly set both registers to 0 from mxc4005_chip_init() to ensure
+both masks are actually set to 0.
+
+Fixes: 79846e33aac1 ("iio: accel: mxc4005: add support for mxc6655")
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+Link: https://lore.kernel.org/r/20240326113700.56725-2-hdegoede@redhat.com
+Cc: <Stable@vger.kernel.org>
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/iio/accel/mxc4005.c | 24 +++++++++++++++++-------
+ 1 file changed, 17 insertions(+), 7 deletions(-)
+
+--- a/drivers/iio/accel/mxc4005.c
++++ b/drivers/iio/accel/mxc4005.c
+@@ -27,9 +27,13 @@
+ #define MXC4005_REG_ZOUT_UPPER 0x07
+ #define MXC4005_REG_ZOUT_LOWER 0x08
+
++#define MXC4005_REG_INT_MASK0 0x0A
++
+ #define MXC4005_REG_INT_MASK1 0x0B
+ #define MXC4005_REG_INT_MASK1_BIT_DRDYE 0x01
+
++#define MXC4005_REG_INT_CLR0 0x00
++
+ #define MXC4005_REG_INT_CLR1 0x01
+ #define MXC4005_REG_INT_CLR1_BIT_DRDYC 0x01
+
+@@ -113,7 +117,9 @@ static bool mxc4005_is_readable_reg(stru
+ static bool mxc4005_is_writeable_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
++ case MXC4005_REG_INT_CLR0:
+ case MXC4005_REG_INT_CLR1:
++ case MXC4005_REG_INT_MASK0:
+ case MXC4005_REG_INT_MASK1:
+ case MXC4005_REG_CONTROL:
+ return true;
+@@ -334,17 +340,13 @@ static int mxc4005_set_trigger_state(str
+ {
+ struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
+ struct mxc4005_data *data = iio_priv(indio_dev);
++ unsigned int val;
+ int ret;
+
+ mutex_lock(&data->mutex);
+- if (state) {
+- ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1,
+- MXC4005_REG_INT_MASK1_BIT_DRDYE);
+- } else {
+- ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1,
+- ~MXC4005_REG_INT_MASK1_BIT_DRDYE);
+- }
+
++ val = state ? MXC4005_REG_INT_MASK1_BIT_DRDYE : 0;
++ ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1, val);
+ if (ret < 0) {
+ mutex_unlock(&data->mutex);
+ dev_err(data->dev, "failed to update reg_int_mask1");
+@@ -386,6 +388,14 @@ static int mxc4005_chip_init(struct mxc4
+
+ dev_dbg(data->dev, "MXC4005 chip id %02x\n", reg);
+
++ ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK0, 0);
++ if (ret < 0)
++ return dev_err_probe(data->dev, ret, "writing INT_MASK0\n");
++
++ ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1, 0);
++ if (ret < 0)
++ return dev_err_probe(data->dev, ret, "writing INT_MASK1\n");
++
+ return 0;
+ }
+
--- /dev/null
+From 74a72baf204fd509bbe8b53eec35e39869d94341 Mon Sep 17 00:00:00 2001
+From: Ramona Gradinariu <ramona.bolboaca13@gmail.com>
+Date: Fri, 5 Apr 2024 07:53:09 +0300
+Subject: iio:imu: adis16475: Fix sync mode setting
+
+From: Ramona Gradinariu <ramona.bolboaca13@gmail.com>
+
+commit 74a72baf204fd509bbe8b53eec35e39869d94341 upstream.
+
+Fix sync mode setting by applying the necessary shift bits.
+
+Fixes: fff7352bf7a3 ("iio: imu: Add support for adis16475")
+Signed-off-by: Ramona Gradinariu <ramona.bolboaca13@gmail.com>
+Reviewed-by: Nuno Sa <nuno.sa@analog.com>
+Link: https://lore.kernel.org/r/20240405045309.816328-2-ramona.bolboaca13@gmail.com
+Cc: <Stable@vger.kernel.org>
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/iio/imu/adis16475.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/drivers/iio/imu/adis16475.c
++++ b/drivers/iio/imu/adis16475.c
+@@ -1070,6 +1070,7 @@ static int adis16475_config_sync_mode(st
+ struct device *dev = &st->adis.spi->dev;
+ const struct adis16475_sync *sync;
+ u32 sync_mode;
++ u16 val;
+
+ /* default to internal clk */
+ st->clk_freq = st->info->int_clk * 1000;
+@@ -1155,8 +1156,9 @@ static int adis16475_config_sync_mode(st
+ * I'm keeping this for simplicity and avoiding extra variables
+ * in chip_info.
+ */
++ val = ADIS16475_SYNC_MODE(sync->sync_mode);
+ ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
+- ADIS16475_SYNC_MODE_MASK, sync->sync_mode);
++ ADIS16475_SYNC_MODE_MASK, val);
+ if (ret)
+ return ret;
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
