3.18-stable patches

added patches:
	pinctrl-mxs-atomically-switch-mux-and-drive-strength-config.patch
	pinctrl-sh-pfc-update-info-pointer-after-soc-specific-init.patch

diff --git a/queue-3.18/pinctrl-mxs-atomically-switch-mux-and-drive-strength-config.patch b/queue-3.18/pinctrl-mxs-atomically-switch-mux-and-drive-strength-config.patch
new file mode 100644 (file)
index 0000000..452412e
--- /dev/null
+++ b/queue-3.18/pinctrl-mxs-atomically-switch-mux-and-drive-strength-config.patch
@@ -0,0 +1,81 @@
+From da6c2addf66d7ff7d0b090d6267d4292f951e4e6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Thu, 18 May 2017 11:23:55 +0200
+Subject: pinctrl: mxs: atomically switch mux and drive strength config
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+
+commit da6c2addf66d7ff7d0b090d6267d4292f951e4e6 upstream.
+
+To set the mux mode of a pin two bits must be set. Up to now this is
+implemented using the following idiom:
+
+       writel(mask, reg + CLR);
+       writel(value, reg + SET);
+
+. This however results in the mux mode being 0 between the two writes.
+
+On my machine there is an IC's reset pin connected to LCD_D20. The
+bootloader configures this pin as GPIO output-high (i.e. not holding the
+IC in reset). When Linux reconfigures the pin to GPIO the short time
+LCD_D20 is muxed as LCD_D20 instead of GPIO_1_20 is enough to confuse
+the connected IC.
+
+The same problem is present for the pin's drive strength setting which is
+reset to low drive strength before using the right value.
+
+So instead of relying on the hardware to modify the register setting
+using two writes implement the bit toggling using read-modify-write.
+
+Fixes: 17723111e64f ("pinctrl: add pinctrl-mxs support")
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Acked-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pinctrl/freescale/pinctrl-mxs.c |   16 ++++++++++++----
+ 1 file changed, 12 insertions(+), 4 deletions(-)
+
+--- a/drivers/pinctrl/freescale/pinctrl-mxs.c
++++ b/drivers/pinctrl/freescale/pinctrl-mxs.c
+@@ -195,6 +195,16 @@ static int mxs_pinctrl_get_func_groups(s
+       return 0;
+ }
+ 
++static void mxs_pinctrl_rmwl(u32 value, u32 mask, u8 shift, void __iomem *reg)
++{
++      u32 tmp;
++
++      tmp = readl(reg);
++      tmp &= ~(mask << shift);
++      tmp |= value << shift;
++      writel(tmp, reg);
++}
++
+ static int mxs_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
+                              unsigned group)
+ {
+@@ -212,8 +222,7 @@ static int mxs_pinctrl_set_mux(struct pi
+               reg += bank * 0x20 + pin / 16 * 0x10;
+               shift = pin % 16 * 2;
+ 
+-              writel(0x3 << shift, reg + CLR);
+-              writel(g->muxsel[i] << shift, reg + SET);
++              mxs_pinctrl_rmwl(g->muxsel[i], 0x3, shift, reg);
+       }
+ 
+       return 0;
+@@ -280,8 +289,7 @@ static int mxs_pinconf_group_set(struct
+                       /* mA */
+                       if (config & MA_PRESENT) {
+                               shift = pin % 8 * 4;
+-                              writel(0x3 << shift, reg + CLR);
+-                              writel(ma << shift, reg + SET);
++                              mxs_pinctrl_rmwl(ma, 0x3, shift, reg);
+                       }
+ 
+                       /* vol */

diff --git a/queue-3.18/pinctrl-sh-pfc-update-info-pointer-after-soc-specific-init.patch b/queue-3.18/pinctrl-sh-pfc-update-info-pointer-after-soc-specific-init.patch
new file mode 100644 (file)
index 0000000..f6c9e1d
--- /dev/null
+++ b/queue-3.18/pinctrl-sh-pfc-update-info-pointer-after-soc-specific-init.patch
@@ -0,0 +1,34 @@
+From 3091ae775fae17084013021d01513bc1ad274e6a Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 9 Mar 2017 19:20:48 +0100
+Subject: pinctrl: sh-pfc: Update info pointer after SoC-specific init
+
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+
+commit 3091ae775fae17084013021d01513bc1ad274e6a upstream.
+
+Update the sh_pfc_soc_info pointer after calling the SoC-specific
+initialization function, as it may have been updated to e.g. handle
+different SoC revisions.  This makes sure the correct subdriver name is
+printed later.
+
+Fixes: 0c151062f32c9db8 ("sh-pfc: Add support for SoC-specific initialization")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pinctrl/sh-pfc/core.c |    3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/pinctrl/sh-pfc/core.c
++++ b/drivers/pinctrl/sh-pfc/core.c
+@@ -529,6 +529,9 @@ static int sh_pfc_probe(struct platform_
+               ret = info->ops->init(pfc);
+               if (ret < 0)
+                       return ret;
++
++              /* .init() may have overridden pfc->info */
++              info = pfc->info;
+       }
+ 
+       pinctrl_provide_dummies();

diff --git a/queue-3.18/series b/queue-3.18/series
index 12383b23f63dd696d391de1b44b7aa0a59e497ab..966057644811bb328344d4374ddf4de498cb24ad 100644 (file)
--- a/queue-3.18/series
+++ b/queue-3.18/series
@@ -10,3 +10,5 @@ usb-serial-cp210x-add-id-for-cel-em3588-usb-zigbee-stick.patch
 add-usb-quirk-for-hvr-950q-to-avoid-intermittent-device-resets.patch
 usb-usbip-set-buffer-pointers-to-null-after-free.patch
 usb-fix-typo-in-the-definition-of-endpointrequest.patch
+pinctrl-mxs-atomically-switch-mux-and-drive-strength-config.patch
+pinctrl-sh-pfc-update-info-pointer-after-soc-specific-init.patch