drm/amd/display: Refactor input mode programming for DIG FIFO

[WHY]
Input mode for the DIG FIFO should be programmed as part of stream
encoder setup.

[HOW]
Pre-calculate the pixels per cycle as part of the pixel clock params,
and program as part of stream encoder setup.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_dio_stream_encoder.c
index be0ebb6a8a556bc4be3b67ac8a0d58083c97d831..1c55ccede09ba1008b9439ba26972639d5893adc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_dio_stream_encoder.c
@@ -228,7 +228,27 @@ static void enc401_stream_encoder_hdmi_set_stream_attribute(
        REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
 }
 
+static void enc401_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container)
+{
+       struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 
+       // The naming of this field is confusing, what it means is the output mode of otg, which
+       // is the input mode of the dig
+       switch (pix_per_container)      {
+       case 2:
+               REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x1);
+               break;
+       case 4:
+               REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x2);
+               break;
+       case 8:
+               REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x3);
+               break;
+       default:
+               REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x0);
+               break;
+       }
+}
 
 static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
 {
@@ -239,68 +259,28 @@ static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
        return two_pix;
 }
 
-static bool is_h_timing_divisible_by_2(const struct dc_crtc_timing *timing)
-{
-       /* math borrowed from function of same name in inc/resource
-        * checks if h_timing is divisible by 2
-        */
-
-       bool divisible = false;
-       uint16_t h_blank_start = 0;
-       uint16_t h_blank_end = 0;
-
-       if (timing) {
-               h_blank_start = timing->h_total - timing->h_front_porch;
-               h_blank_end = h_blank_start - timing->h_addressable;
-
-               /* HTOTAL, Hblank start/end, and Hsync start/end all must be
-                * divisible by 2 in order for the horizontal timing params
-                * to be considered divisible by 2. Hsync start is always 0.
-                */
-               divisible = (timing->h_total % 2 == 0) &&
-                               (h_blank_start % 2 == 0) &&
-                               (h_blank_end % 2 == 0) &&
-                               (timing->h_sync_width % 2 == 0);
-       }
-       return divisible;
-}
-
-static bool is_dp_dig_pixel_rate_div_policy(struct dc *dc, const struct dc_crtc_timing *timing)
-{
-       /* should be functionally the same as dcn32_is_dp_dig_pixel_rate_div_policy for DP encoders*/
-       return is_h_timing_divisible_by_2(timing) &&
-               dc->debug.enable_dp_dig_pixel_rate_div_policy;
-}
-
 static void enc401_stream_encoder_dp_unblank(
                struct dc_link *link,
                struct stream_encoder *enc,
                const struct encoder_unblank_param *param)
 {
        struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
-       struct dc *dc = enc->ctx->dc;
 
        if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
                uint32_t n_vid = 0x8000;
                uint32_t m_vid;
-               uint32_t n_multiply = 0;
-               // TODO: Fix defined but not used
-               //uint32_t pix_per_cycle = 0;
+               uint32_t pix_per_container = 1;
                uint64_t m_vid_l = n_vid;
 
-               /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
-               if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1
-                       || is_dp_dig_pixel_rate_div_policy(dc, &param->timing)) {
-                       /*this logic should be the same in get_pixel_clock_parameters() */
-                       n_multiply = 1;
-                       // TODO: Fix defined but not used
-                       //pix_per_cycle = 1;
+               /* YCbCr 4:2:0 or YCbCr4:2:2 simple + DSC: Computed VID_M will be 2X the input rate */
+               if (is_two_pixels_per_containter(&param->timing)) {
+                       pix_per_container = 2;
                }
+
                /* M / N = Fstream / Flink
                 * m_vid / n_vid = pixel rate / link rate
                 */
-
-               m_vid_l *= param->timing.pix_clk_100hz / 10;
+               m_vid_l *= param->timing.pix_clk_100hz / pix_per_container / 10;
                m_vid_l = div_u64(m_vid_l,
                        param->link_settings.link_rate
                                * LINK_RATE_REF_FREQ_IN_KHZ);
@@ -319,9 +299,23 @@ static void enc401_stream_encoder_dp_unblank(
 
                REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
 
-               REG_UPDATE_2(DP_VID_TIMING,
-                               DP_VID_M_N_GEN_EN, 1,
-                               DP_VID_N_INTERVAL, n_multiply);
+               /* reduce jitter based on read rate */
+               switch (param->pix_per_cycle)   {
+               case 2:
+                       REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x1);
+                       break;
+               case 4:
+                       REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x2);
+                       break;
+               case 8:
+                       REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x3);
+                       break;
+               default:
+                       REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x0);
+                       break;
+               }
+
+               REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
        }
 
        /* make sure stream is disabled before resetting steer fifo */
@@ -413,27 +407,6 @@ static void enc401_read_state(struct stream_encoder *enc, struct enc_state *s)
        }
 }
 
-static void enc401_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container)
-{
-       struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
-
-       // The naming of this field is confusing, what it means is the output mode of otg, which
-       // is the input mode of the dig
-       switch (pix_per_container)      {
-       case 2:
-               REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x1);
-               break;
-       case 4:
-               REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x2);
-               break;
-       case 8:
-               REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x3);
-               break;
-       default:
-               REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x0);
-               break;
-       }
-}
 static void enc401_stream_encoder_enable(
        struct stream_encoder *enc,
        enum signal_type signal,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 2e8a30f5c3d15ff0897e211645dfa67ae77e18f9..5812b0938cd39b1a622b4ffc1b47cae8dc38c8ca 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -2959,9 +2959,6 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
                early_control = lane_count;
 
        tg->funcs->set_early_control(tg, early_control);
-
-       if (dc->hwseq->funcs.set_pixels_per_cycle)
-               dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx);
 }
 
 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
index 0c994b5a48b1bb45ff1ac973c7549b6a445864c5..0b12a69e2df0fa253de583884a9e01531a729612 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
@@ -332,23 +332,6 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig
        return odm_combine_factor;
 }
 
-void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
-{
-       uint32_t pix_per_cycle = 1;
-       uint32_t odm_combine_factor = 1;
-
-       if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc)
-               return;
-
-       odm_combine_factor = get_odm_config(pipe_ctx, NULL);
-       if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&pipe_ctx->stream->timing) || odm_combine_factor > 1)
-               pix_per_cycle = 2;
-
-       if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
-               pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
-                               pix_per_cycle);
-}
-
 void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context)
 {
        unsigned int i;

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h
index eafcc4ea6d2498262863c337572bb2c71d0283c5..f4613d96e0139ba5368e9be89e7d0a505b0c75fd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h
@@ -39,8 +39,6 @@ void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
 
 unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);
 
-void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
-
 void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context);
 
 void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
index 29b56736fa8454f7ec9d94dc7f486dc6dee33a33..9c46b6a7b4dca81fe48885b8c14ed8bf3a2315b6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
@@ -152,7 +152,6 @@ static const struct hwseq_private_funcs dcn314_private_funcs = {
        .set_shaper_3dlut = dcn20_set_shaper_3dlut,
        .setup_hpo_hw_control = dcn31_setup_hpo_hw_control,
        .calculate_dccg_k1_k2_values = dcn314_calculate_dccg_k1_k2_values,
-       .set_pixels_per_cycle = dcn314_set_pixels_per_cycle,
        .resync_fifo_dccg_dio = dcn314_resync_fifo_dccg_dio,
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 4302f9be1a7d28cf3ec95a457670f90b31e6359d..901e3b531a12197d98e5c3dfd7aac8133f38d350 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -1173,24 +1173,6 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsign
        return odm_combine_factor;
 }
 
-void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
-{
-       uint32_t pix_per_cycle = 1;
-       uint32_t odm_combine_factor = 1;
-
-       if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc)
-               return;
-
-       odm_combine_factor = get_odm_config(pipe_ctx, NULL);
-       if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&pipe_ctx->stream->timing) || odm_combine_factor > 1
-               || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
-               pix_per_cycle = 2;
-
-       if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
-               pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
-                               pix_per_cycle);
-}
-
 void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context)
 {
        unsigned int i;

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
index f55c11fc56ec7a7a3d86cff32269a89fb6c5a3d5..c510f3a652adf591f397b517363bf951cfc2cc3d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
@@ -73,8 +73,6 @@ void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *
 
 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);
 
-void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
-
 void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context);
 
 void dcn32_subvp_pipe_control_lock(struct dc *dc,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
index b1f79ca7d77a7720cf4ef09f52e88db6200d39eb..10d2ae99c11842f7071bbb9bbafe8e6fc173da8e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
@@ -158,7 +158,6 @@ static const struct hwseq_private_funcs dcn32_private_funcs = {
        .update_force_pstate = dcn32_update_force_pstate,
        .update_mall_sel = dcn32_update_mall_sel,
        .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,
-       .set_pixels_per_cycle = dcn32_set_pixels_per_cycle,
        .resync_fifo_dccg_dio = dcn32_resync_fifo_dccg_dio,
        .is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,
        .apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
index 8e5b877981923b901c706e2520066cbf4e6ce6a5..663bacd1fafdb7eb67de3822bedb059e7563a422 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
@@ -159,7 +159,6 @@ static const struct hwseq_private_funcs dcn35_private_funcs = {
        .set_mcm_luts = dcn32_set_mcm_luts,
        .setup_hpo_hw_control = dcn35_setup_hpo_hw_control,
        .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,
-       .set_pixels_per_cycle = dcn32_set_pixels_per_cycle,
        .resync_fifo_dccg_dio = dcn314_resync_fifo_dccg_dio,
        .is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,
        .dsc_pg_control = dcn35_dsc_pg_control,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
index 701b66634e2d4764a9d53c2968c6ec49d0514c6e..d8de1c6a84e8d824ae3d1f02f33d9d344bc68351 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
@@ -158,7 +158,6 @@ static const struct hwseq_private_funcs dcn351_private_funcs = {
        .set_mcm_luts = dcn32_set_mcm_luts,
        .setup_hpo_hw_control = dcn35_setup_hpo_hw_control,
        .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,
-       .set_pixels_per_cycle = dcn32_set_pixels_per_cycle,
        .is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,
        .dsc_pg_control = dcn35_dsc_pg_control,
        .dsc_pg_status = dcn32_dsc_pg_status,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index a463a4e8d57d417080badbcd7b4583d06e500f10..d00f5cf255c7946dfc54c2b367fe0e59bbed0b4c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -978,9 +978,6 @@ void dcn401_enable_stream(struct pipe_ctx *pipe_ctx)
                dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
 
        tg->funcs->set_early_control(tg, early_control);
-
-       if (dc->hwseq->funcs.set_pixels_per_cycle)
-               dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx);
 }
 
 void dcn401_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)
@@ -1545,3 +1542,30 @@ void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool en
 
        dc_dmub_srv_fams2_update_config(dc, context, enable && fams2_required);
 }
+
+void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx,
+               struct dc_link_settings *link_settings)
+{
+       struct encoder_unblank_param params = {0};
+       struct dc_stream_state *stream = pipe_ctx->stream;
+       struct dc_link *link = stream->link;
+       struct dce_hwseq *hws = link->dc->hwseq;
+
+       /* calculate parameters for unblank */
+       params.opp_cnt = resource_get_odm_slice_count(pipe_ctx);
+
+       params.timing = pipe_ctx->stream->timing;
+       params.link_settings.link_rate = link_settings->link_rate;
+       params.pix_per_cycle = pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle;
+
+       if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
+               pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
+                               pipe_ctx->stream_res.hpo_dp_stream_enc,
+                               pipe_ctx->stream_res.tg->inst);
+       } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
+               pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
+       }
+
+       if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)
+               hws->funcs.edp_backlight_control(link, true);
+}

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
index e70ac1f6e68b32e7c778792abf7479297a32190e..16084ae1d31d4ef11155b8964d511a302c800571 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
@@ -72,5 +72,6 @@ void dcn401_fams2_global_control_lock(struct dc *dc,
                bool lock);
 void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable);
 void dcn401_fams2_global_control_lock_fast(union block_sequence_params *params);
+void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *link_settings);
 
 #endif /* __DC_HWSS_DCN401_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
index c051c1cd06654a334f476fd432732d7a4848408f..56c4b28c1f2edb3fc90e657bf63782c4f53b7f0e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
@@ -31,7 +31,7 @@ static const struct hw_sequencer_funcs dcn401_funcs = {
        .send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
        .enable_stream = dcn401_enable_stream,
        .disable_stream = dce110_disable_stream,
-       .unblank_stream = dcn32_unblank_stream,
+       .unblank_stream = dcn401_unblank_stream,
        .blank_stream = dce110_blank_stream,
        .enable_audio_stream = dce110_enable_audio_stream,
        .disable_audio_stream = dce110_disable_audio_stream,
@@ -137,8 +137,6 @@ static const struct hwseq_private_funcs dcn401_private_funcs = {
        .update_mall_sel = dcn32_update_mall_sel,
        .setup_hpo_hw_control = dcn401_setup_hpo_hw_control,
        .calculate_dccg_k1_k2_values = NULL,
-       .set_pixels_per_cycle = dcn32_set_pixels_per_cycle,
-       .is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,
        .apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw,
        .reset_back_end_for_pipe = dcn20_reset_back_end_for_pipe,
        .populate_mcm_luts = dcn401_populate_mcm_luts,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
index 7bfb4fb50dadfb7cc6fe7eaaf287091eef5bf167..7ac3f2a094870148bd81102c0907a27f1ca05c7f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
@@ -169,7 +169,6 @@ struct hwseq_private_funcs {
        unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx,
                        unsigned int *k1_div,
                        unsigned int *k2_div);
-       void (*set_pixels_per_cycle)(struct pipe_ctx *pipe_ctx);
        void (*resync_fifo_dccg_dio)(struct dce_hwseq *hws, struct dc *dc,
                        struct dc_state *context);
        enum dc_status (*apply_single_controller_ctx_to_hw)(

diff --git a/drivers/gpu/drm/amd/display/dc/inc/clock_source.h b/drivers/gpu/drm/amd/display/dc/inc/clock_source.h
index 8f8ac8e29ed0897de24636172b7fa3f4746493c0..ed2f8005d85e325ae2de84a29052856f8d25e024 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/clock_source.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/clock_source.h
@@ -96,6 +96,7 @@ struct pixel_clk_params {
 /*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/
        enum dc_pixel_encoding pixel_encoding;
        struct pixel_clk_flags flags;
+       uint32_t dio_se_pix_per_cycle;
 };
 
 /**

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index 75b9ec21f29785c59f414c6db9554a47bf296f7f..60228f5de4d7626c3025ec48e90cf856111963b4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -99,6 +99,7 @@ struct encoder_unblank_param {
        struct dc_link_settings link_settings;
        struct dc_crtc_timing timing;
        int opp_cnt;
+       uint32_t pix_per_cycle;
 };
 
 struct encoder_set_dp_phy_pattern_param {

diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
index 1328a0ade3422d0474d61e64b0eb098ae8cb68fd..16412094c61279a9a4c9576d838544978ce5b5fd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
@@ -49,6 +49,9 @@ void setup_dio_stream_encoder(struct pipe_ctx *pipe_ctx)
        if (stream_enc->funcs->map_stream_to_link)
                stream_enc->funcs->map_stream_to_link(stream_enc,
                                stream_enc->stream_enc_inst, link_enc->transmitter - TRANSMITTER_UNIPHY_A);
+       if (stream_enc->funcs->set_input_mode)
+               stream_enc->funcs->set_input_mode(stream_enc,
+                               pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle);
        if (stream_enc->funcs->enable_fifo)
                stream_enc->funcs->enable_fifo(stream_enc);
 }

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
index cf0929b8bec004cdc0f108186cca9589d5fd2c2d..c78675f8be8af7e164ab3584c4d836ea35d1473d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
@@ -1261,6 +1261,15 @@ static void get_pixel_clock_parameters(
        if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
                pixel_clk_params->requested_pix_clk_100hz *= 2;
 
+       if ((pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container &&
+                       pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&pipe_ctx->stream->timing)) ||
+                       (hws->funcs.is_dp_dig_pixel_rate_div_policy &&
+                       hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) ||
+                       opp_cnt > 1) {
+               pixel_clk_params->dio_se_pix_per_cycle = 2;
+       } else {
+               pixel_clk_params->dio_se_pix_per_cycle = 1;
+       }
 }
 
 static void build_clamping_params(struct dc_stream_state *stream)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index e5c40880b64c1878bbc1e6fa2067d8768437e8a8..75e2c62ae7922da619ab8d3deb4d71be135cec2e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -1645,7 +1645,6 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
        if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
                pixel_clk_params->color_depth = COLOR_DEPTH_888;
 
-       /* TODO: Do we still need this? */
        if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
                pixel_clk_params->requested_pix_clk_100hz *= 2;
        if (dc_is_tmds_signal(stream->signal) &&
@@ -1656,6 +1655,23 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
                        pipe_ctx->clock_source,
                        &pipe_ctx->stream_res.pix_clk_params,
                        &pipe_ctx->pll_settings);
+
+       pixel_clk_params->dio_se_pix_per_cycle = 1;
+       if (dc_is_tmds_signal(stream->signal) &&
+                       stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
+               pixel_clk_params->dio_se_pix_per_cycle = 2;
+       } else if (dc_is_dp_signal(stream->signal)) {
+               /* round up to nearest power of 2, or max at 8 pixels per cycle */
+               if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
+                       pixel_clk_params->dio_se_pix_per_cycle = 8;
+               } else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
+                       pixel_clk_params->dio_se_pix_per_cycle = 4;
+               } else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
+                       pixel_clk_params->dio_se_pix_per_cycle = 2;
+               } else {
+                       pixel_clk_params->dio_se_pix_per_cycle = 1;
+               }
+       }
 }
 
 static struct resource_funcs dcn401_res_pool_funcs = {