drm/i915: Plumb 'dsb' all way to the plane hooks

We need to be able to do both MMIO and DSB based pipe/plane
programming. To that end plumb the 'dsb' all way from the top
into the plane commit hooks.

The compiler appears smart enough to combine the branches from
all the back-to-back register writes into a single branch.
So the generated asm ends up looking more or less like this:
plane_hook()
{
	if (dsb) {
		intel_dsb_reg_write();
		intel_dsb_reg_write();
		...
	} else {
		intel_de_write_fw();
		intel_de_write_fw();
		...
	}
}
which seems like a reasonably efficient way to do this.

An alternative I was also considering is some kind of closure
(register write function + display vs. dsb pointer passed to it).
That does result is smaller code as there are no branches anymore,
but having each register access go via function pointer sounds
less efficient.

Not that I actually measured the overhead of either approach yet.
Also the reg_rw tracepoint seems to be making a huge mess of the
generated code for the mmio path. And additionally there's some
kind of IS_GSI_REG() hack in __raw_uncore_read() which ends up
generating a pointless branch for every mmio register access.
So looks like there might be quite a bit of room for improvement
in the mmio path still.

Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240930170415.23841-12-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 9447f7229b6084d8d82955c031e18fa144654d2c..17a1e3801a85c0af5162fa26adfd22391112b08d 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -416,7 +416,8 @@ static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
        return DIV_ROUND_UP(pixel_rate * num, den);
 }
 
-static void i9xx_plane_update_noarm(struct intel_plane *plane,
+static void i9xx_plane_update_noarm(struct intel_dsb *dsb,
+                                   struct intel_plane *plane,
                                    const struct intel_crtc_state *crtc_state,
                                    const struct intel_plane_state *plane_state)
 {
@@ -444,7 +445,8 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane,
        }
 }
 
-static void i9xx_plane_update_arm(struct intel_plane *plane,
+static void i9xx_plane_update_arm(struct intel_dsb *dsb,
+                                 struct intel_plane *plane,
                                  const struct intel_crtc_state *crtc_state,
                                  const struct intel_plane_state *plane_state)
 {
@@ -507,7 +509,8 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
                                  intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
 }
 
-static void i830_plane_update_arm(struct intel_plane *plane,
+static void i830_plane_update_arm(struct intel_dsb *dsb,
+                                 struct intel_plane *plane,
                                  const struct intel_crtc_state *crtc_state,
                                  const struct intel_plane_state *plane_state)
 {
@@ -517,11 +520,12 @@ static void i830_plane_update_arm(struct intel_plane *plane,
         * Additional breakage on i830 causes register reads to return
         * the last latched value instead of the last written value [ALM026].
         */
-       i9xx_plane_update_noarm(plane, crtc_state, plane_state);
-       i9xx_plane_update_arm(plane, crtc_state, plane_state);
+       i9xx_plane_update_noarm(dsb, plane, crtc_state, plane_state);
+       i9xx_plane_update_arm(dsb, plane, crtc_state, plane_state);
 }
 
-static void i9xx_plane_disable_arm(struct intel_plane *plane,
+static void i9xx_plane_disable_arm(struct intel_dsb *dsb,
+                                  struct intel_plane *plane,
                                   const struct intel_crtc_state *crtc_state)
 {
        struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
@@ -549,7 +553,8 @@ static void i9xx_plane_disable_arm(struct intel_plane *plane,
 }
 
 static void
-g4x_primary_async_flip(struct intel_plane *plane,
+g4x_primary_async_flip(struct intel_dsb *dsb,
+                      struct intel_plane *plane,
                       const struct intel_crtc_state *crtc_state,
                       const struct intel_plane_state *plane_state,
                       bool async_flip)
@@ -569,7 +574,8 @@ g4x_primary_async_flip(struct intel_plane *plane,
 }
 
 static void
-vlv_primary_async_flip(struct intel_plane *plane,
+vlv_primary_async_flip(struct intel_dsb *dsb,
+                      struct intel_plane *plane,
                       const struct intel_crtc_state *crtc_state,
                       const struct intel_plane_state *plane_state,
                       bool async_flip)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 3505a5b52eb9babb58f059ad1a8995746278c7bb..b7e462075ded3ca96be0e22bcc4ed27a12dcab2c 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -774,7 +774,8 @@ skl_next_plane_to_commit(struct intel_atomic_state *state,
        return NULL;
 }
 
-void intel_plane_update_noarm(struct intel_plane *plane,
+void intel_plane_update_noarm(struct intel_dsb *dsb,
+                             struct intel_plane *plane,
                              const struct intel_crtc_state *crtc_state,
                              const struct intel_plane_state *plane_state)
 {
@@ -783,10 +784,11 @@ void intel_plane_update_noarm(struct intel_plane *plane,
        trace_intel_plane_update_noarm(plane, crtc);
 
        if (plane->update_noarm)
-               plane->update_noarm(plane, crtc_state, plane_state);
+               plane->update_noarm(dsb, plane, crtc_state, plane_state);
 }
 
-void intel_plane_async_flip(struct intel_plane *plane,
+void intel_plane_async_flip(struct intel_dsb *dsb,
+                           struct intel_plane *plane,
                            const struct intel_crtc_state *crtc_state,
                            const struct intel_plane_state *plane_state,
                            bool async_flip)
@@ -794,34 +796,37 @@ void intel_plane_async_flip(struct intel_plane *plane,
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
        trace_intel_plane_async_flip(plane, crtc, async_flip);
-       plane->async_flip(plane, crtc_state, plane_state, async_flip);
+       plane->async_flip(dsb, plane, crtc_state, plane_state, async_flip);
 }
 
-void intel_plane_update_arm(struct intel_plane *plane,
+void intel_plane_update_arm(struct intel_dsb *dsb,
+                           struct intel_plane *plane,
                            const struct intel_crtc_state *crtc_state,
                            const struct intel_plane_state *plane_state)
 {
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
        if (crtc_state->do_async_flip && plane->async_flip) {
-               intel_plane_async_flip(plane, crtc_state, plane_state, true);
+               intel_plane_async_flip(dsb, plane, crtc_state, plane_state, true);
                return;
        }
 
        trace_intel_plane_update_arm(plane, crtc);
-       plane->update_arm(plane, crtc_state, plane_state);
+       plane->update_arm(dsb, plane, crtc_state, plane_state);
 }
 
-void intel_plane_disable_arm(struct intel_plane *plane,
+void intel_plane_disable_arm(struct intel_dsb *dsb,
+                            struct intel_plane *plane,
                             const struct intel_crtc_state *crtc_state)
 {
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
        trace_intel_plane_disable_arm(plane, crtc);
-       plane->disable_arm(plane, crtc_state);
+       plane->disable_arm(dsb, plane, crtc_state);
 }
 
-void intel_crtc_planes_update_noarm(struct intel_atomic_state *state,
+void intel_crtc_planes_update_noarm(struct intel_dsb *dsb,
+                                   struct intel_atomic_state *state,
                                    struct intel_crtc *crtc)
 {
        struct intel_crtc_state *new_crtc_state =
@@ -846,11 +851,13 @@ void intel_crtc_planes_update_noarm(struct intel_atomic_state *state,
                /* TODO: for mailbox updates this should be skipped */
                if (new_plane_state->uapi.visible ||
                    new_plane_state->planar_slave)
-                       intel_plane_update_noarm(plane, new_crtc_state, new_plane_state);
+                       intel_plane_update_noarm(dsb, plane,
+                                                new_crtc_state, new_plane_state);
        }
 }
 
-static void skl_crtc_planes_update_arm(struct intel_atomic_state *state,
+static void skl_crtc_planes_update_arm(struct intel_dsb *dsb,
+                                      struct intel_atomic_state *state,
                                       struct intel_crtc *crtc)
 {
        struct intel_crtc_state *old_crtc_state =
@@ -877,13 +884,14 @@ static void skl_crtc_planes_update_arm(struct intel_atomic_state *state,
                 */
                if (new_plane_state->uapi.visible ||
                    new_plane_state->planar_slave)
-                       intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
+                       intel_plane_update_arm(dsb, plane, new_crtc_state, new_plane_state);
                else
-                       intel_plane_disable_arm(plane, new_crtc_state);
+                       intel_plane_disable_arm(dsb, plane, new_crtc_state);
        }
 }
 
-static void i9xx_crtc_planes_update_arm(struct intel_atomic_state *state,
+static void i9xx_crtc_planes_update_arm(struct intel_dsb *dsb,
+                                       struct intel_atomic_state *state,
                                        struct intel_crtc *crtc)
 {
        struct intel_crtc_state *new_crtc_state =
@@ -903,21 +911,22 @@ static void i9xx_crtc_planes_update_arm(struct intel_atomic_state *state,
                 * would have to be called here as well.
                 */
                if (new_plane_state->uapi.visible)
-                       intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
+                       intel_plane_update_arm(dsb, plane, new_crtc_state, new_plane_state);
                else
-                       intel_plane_disable_arm(plane, new_crtc_state);
+                       intel_plane_disable_arm(dsb, plane, new_crtc_state);
        }
 }
 
-void intel_crtc_planes_update_arm(struct intel_atomic_state *state,
+void intel_crtc_planes_update_arm(struct intel_dsb *dsb,
+                                 struct intel_atomic_state *state,
                                  struct intel_crtc *crtc)
 {
        struct drm_i915_private *i915 = to_i915(state->base.dev);
 
        if (DISPLAY_VER(i915) >= 9)
-               skl_crtc_planes_update_arm(state, crtc);
+               skl_crtc_planes_update_arm(dsb, state, crtc);
        else
-               i9xx_crtc_planes_update_arm(state, crtc);
+               i9xx_crtc_planes_update_arm(dsb, state, crtc);
 }
 
 int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 6c4fe359646504b1f47dd0433212dfb9be84588d..0f982f452ff391b5eed1380e2f0716943f14e80e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -14,6 +14,7 @@ struct drm_rect;
 struct intel_atomic_state;
 struct intel_crtc;
 struct intel_crtc_state;
+struct intel_dsb;
 struct intel_plane;
 struct intel_plane_state;
 enum plane_id;
@@ -32,26 +33,32 @@ void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
                                       struct intel_crtc *crtc);
 void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
                               const struct intel_plane_state *from_plane_state);
-void intel_plane_async_flip(struct intel_plane *plane,
+void intel_plane_async_flip(struct intel_dsb *dsb,
+                           struct intel_plane *plane,
                            const struct intel_crtc_state *crtc_state,
                            const struct intel_plane_state *plane_state,
                            bool async_flip);
-void intel_plane_update_noarm(struct intel_plane *plane,
+void intel_plane_update_noarm(struct intel_dsb *dsb,
+                             struct intel_plane *plane,
                              const struct intel_crtc_state *crtc_state,
                              const struct intel_plane_state *plane_state);
-void intel_plane_update_arm(struct intel_plane *plane,
+void intel_plane_update_arm(struct intel_dsb *dsb,
+                           struct intel_plane *plane,
                            const struct intel_crtc_state *crtc_state,
                            const struct intel_plane_state *plane_state);
-void intel_plane_disable_arm(struct intel_plane *plane,
+void intel_plane_disable_arm(struct intel_dsb *dsb,
+                            struct intel_plane *plane,
                             const struct intel_crtc_state *crtc_state);
 struct intel_plane *intel_plane_alloc(void);
 void intel_plane_free(struct intel_plane *plane);
 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
 void intel_plane_destroy_state(struct drm_plane *plane,
                               struct drm_plane_state *state);
-void intel_crtc_planes_update_noarm(struct intel_atomic_state *state,
+void intel_crtc_planes_update_noarm(struct intel_dsb *dsb,
+                                   struct intel_atomic_state *state,
                                    struct intel_crtc *crtc);
-void intel_crtc_planes_update_arm(struct intel_atomic_state *state,
+void intel_crtc_planes_update_arm(struct intel_dsb *dsbx,
+                                 struct intel_atomic_state *state,
                                  struct intel_crtc *crtc);
 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
                                        struct intel_crtc_state *crtc_state,

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 50f41aeb3c28871a445d807d960438fe153aa54b..6175a8e31302c799a33e14afcc84b2f9b2d89535 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1915,7 +1915,7 @@ void intel_color_modeset(const struct intel_crtc_state *crtc_state)
                struct intel_plane *plane = to_intel_plane(crtc->base.primary);
 
                /* update DSPCNTR to configure gamma/csc for pipe bottom color */
-               plane->disable_arm(plane, crtc_state);
+               plane->disable_arm(NULL, plane, crtc_state);
        }
 }
 

diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 050eacc709cc1fac99e072b237b1e5d339e3a7a3..9ba77970dab765d93015105cbc5c12adbdae8e3a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -274,7 +274,8 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state,
 }
 
 /* TODO: split into noarm+arm pair */
-static void i845_cursor_update_arm(struct intel_plane *plane,
+static void i845_cursor_update_arm(struct intel_dsb *dsb,
+                                  struct intel_plane *plane,
                                   const struct intel_crtc_state *crtc_state,
                                   const struct intel_plane_state *plane_state)
 {
@@ -314,10 +315,11 @@ static void i845_cursor_update_arm(struct intel_plane *plane,
        }
 }
 
-static void i845_cursor_disable_arm(struct intel_plane *plane,
+static void i845_cursor_disable_arm(struct intel_dsb *dsb,
+                                   struct intel_plane *plane,
                                    const struct intel_crtc_state *crtc_state)
 {
-       i845_cursor_update_arm(plane, crtc_state, NULL);
+       i845_cursor_update_arm(dsb, plane, crtc_state, NULL);
 }
 
 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
@@ -526,22 +528,25 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
        return 0;
 }
 
-static void i9xx_cursor_disable_sel_fetch_arm(struct intel_plane *plane,
+static void i9xx_cursor_disable_sel_fetch_arm(struct intel_dsb *dsb,
+                                             struct intel_plane *plane,
                                              const struct intel_crtc_state *crtc_state)
 {
-       struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+       struct intel_display *display = to_intel_display(plane->base.dev);
        enum pipe pipe = plane->pipe;
 
        if (!crtc_state->enable_psr2_sel_fetch)
                return;
 
-       intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), 0);
+       intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), 0);
 }
 
-static void wa_16021440873(struct intel_plane *plane,
+static void wa_16021440873(struct intel_dsb *dsb,
+                          struct intel_plane *plane,
                           const struct intel_crtc_state *crtc_state,
                           const struct intel_plane_state *plane_state)
 {
+       struct intel_display *display = to_intel_display(plane->base.dev);
        struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
        u32 ctl = plane_state->ctl;
        int et_y_position = drm_rect_height(&crtc_state->pipe_src) + 1;
@@ -550,16 +555,18 @@ static void wa_16021440873(struct intel_plane *plane,
        ctl &= ~MCURSOR_MODE_MASK;
        ctl |= MCURSOR_MODE_64_2B;
 
-       intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl);
+       intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), ctl);
 
-       intel_de_write(dev_priv, CURPOS_ERLY_TPT(dev_priv, pipe),
-                      CURSOR_POS_Y(et_y_position));
+       intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(dev_priv, pipe),
+                          CURSOR_POS_Y(et_y_position));
 }
 
-static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,
+static void i9xx_cursor_update_sel_fetch_arm(struct intel_dsb *dsb,
+                                            struct intel_plane *plane,
                                             const struct intel_crtc_state *crtc_state,
                                             const struct intel_plane_state *plane_state)
 {
+       struct intel_display *display = to_intel_display(plane->base.dev);
        struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
        enum pipe pipe = plane->pipe;
 
@@ -570,19 +577,17 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,
                if (crtc_state->enable_psr2_su_region_et) {
                        u32 val = intel_cursor_position(crtc_state, plane_state,
                                true);
-                       intel_de_write_fw(dev_priv,
-                                         CURPOS_ERLY_TPT(dev_priv, pipe),
-                                         val);
+
+                       intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(dev_priv, pipe), val);
                }
 
-               intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe),
-                                 plane_state->ctl);
+               intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), plane_state->ctl);
        } else {
                /* Wa_16021440873 */
                if (crtc_state->enable_psr2_su_region_et)
-                       wa_16021440873(plane, crtc_state, plane_state);
+                       wa_16021440873(dsb, plane, crtc_state, plane_state);
                else
-                       i9xx_cursor_disable_sel_fetch_arm(plane, crtc_state);
+                       i9xx_cursor_disable_sel_fetch_arm(dsb, plane, crtc_state);
        }
 }
 
@@ -609,9 +614,11 @@ static u32 skl_cursor_wm_reg_val(const struct skl_wm_level *level)
        return val;
 }
 
-static void skl_write_cursor_wm(struct intel_plane *plane,
+static void skl_write_cursor_wm(struct intel_dsb *dsb,
+                               struct intel_plane *plane,
                                const struct intel_crtc_state *crtc_state)
 {
+       struct intel_display *display = to_intel_display(plane->base.dev);
        struct drm_i915_private *i915 = to_i915(plane->base.dev);
        enum plane_id plane_id = plane->id;
        enum pipe pipe = plane->pipe;
@@ -621,30 +628,32 @@ static void skl_write_cursor_wm(struct intel_plane *plane,
        int level;
 
        for (level = 0; level < i915->display.wm.num_levels; level++)
-               intel_de_write_fw(i915, CUR_WM(pipe, level),
-                                 skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
+               intel_de_write_dsb(display, dsb, CUR_WM(pipe, level),
+                                  skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
 
-       intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
-                         skl_cursor_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
+       intel_de_write_dsb(display, dsb, CUR_WM_TRANS(pipe),
+                          skl_cursor_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
 
        if (HAS_HW_SAGV_WM(i915)) {
                const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
 
-               intel_de_write_fw(i915, CUR_WM_SAGV(pipe),
-                                 skl_cursor_wm_reg_val(&wm->sagv.wm0));
-               intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe),
-                                 skl_cursor_wm_reg_val(&wm->sagv.trans_wm));
+               intel_de_write_dsb(display, dsb, CUR_WM_SAGV(pipe),
+                                  skl_cursor_wm_reg_val(&wm->sagv.wm0));
+               intel_de_write_dsb(display, dsb, CUR_WM_SAGV_TRANS(pipe),
+                                  skl_cursor_wm_reg_val(&wm->sagv.trans_wm));
        }
 
-       intel_de_write_fw(i915, CUR_BUF_CFG(pipe),
-                         skl_cursor_ddb_reg_val(ddb));
+       intel_de_write_dsb(display, dsb, CUR_BUF_CFG(pipe),
+                          skl_cursor_ddb_reg_val(ddb));
 }
 
 /* TODO: split into noarm+arm pair */
-static void i9xx_cursor_update_arm(struct intel_plane *plane,
+static void i9xx_cursor_update_arm(struct intel_dsb *dsb,
+                                  struct intel_plane *plane,
                                   const struct intel_crtc_state *crtc_state,
                                   const struct intel_plane_state *plane_state)
 {
+       struct intel_display *display = to_intel_display(plane->base.dev);
        struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
        enum pipe pipe = plane->pipe;
        u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
@@ -684,38 +693,36 @@ static void i9xx_cursor_update_arm(struct intel_plane *plane,
         */
 
        if (DISPLAY_VER(dev_priv) >= 9)
-               skl_write_cursor_wm(plane, crtc_state);
+               skl_write_cursor_wm(dsb, plane, crtc_state);
 
        if (plane_state)
-               i9xx_cursor_update_sel_fetch_arm(plane, crtc_state,
-                                                plane_state);
+               i9xx_cursor_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);
        else
-               i9xx_cursor_disable_sel_fetch_arm(plane, crtc_state);
+               i9xx_cursor_disable_sel_fetch_arm(dsb, plane, crtc_state);
 
        if (plane->cursor.base != base ||
            plane->cursor.size != fbc_ctl ||
            plane->cursor.cntl != cntl) {
                if (HAS_CUR_FBC(dev_priv))
-                       intel_de_write_fw(dev_priv,
-                                         CUR_FBC_CTL(dev_priv, pipe),
-                                         fbc_ctl);
-               intel_de_write_fw(dev_priv, CURCNTR(dev_priv, pipe), cntl);
-               intel_de_write_fw(dev_priv, CURPOS(dev_priv, pipe), pos);
-               intel_de_write_fw(dev_priv, CURBASE(dev_priv, pipe), base);
+                       intel_de_write_dsb(display, dsb, CUR_FBC_CTL(dev_priv, pipe), fbc_ctl);
+               intel_de_write_dsb(display, dsb, CURCNTR(dev_priv, pipe), cntl);
+               intel_de_write_dsb(display, dsb, CURPOS(dev_priv, pipe), pos);
+               intel_de_write_dsb(display, dsb, CURBASE(dev_priv, pipe), base);
 
                plane->cursor.base = base;
                plane->cursor.size = fbc_ctl;
                plane->cursor.cntl = cntl;
        } else {
-               intel_de_write_fw(dev_priv, CURPOS(dev_priv, pipe), pos);
-               intel_de_write_fw(dev_priv, CURBASE(dev_priv, pipe), base);
+               intel_de_write_dsb(display, dsb, CURPOS(dev_priv, pipe), pos);
+               intel_de_write_dsb(display, dsb, CURBASE(dev_priv, pipe), base);
        }
 }
 
-static void i9xx_cursor_disable_arm(struct intel_plane *plane,
+static void i9xx_cursor_disable_arm(struct intel_dsb *dsb,
+                                   struct intel_plane *plane,
                                    const struct intel_crtc_state *crtc_state)
 {
-       i9xx_cursor_update_arm(plane, crtc_state, NULL);
+       i9xx_cursor_update_arm(dsb, plane, crtc_state, NULL);
 }
 
 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
@@ -904,10 +911,10 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
        }
 
        if (new_plane_state->uapi.visible) {
-               intel_plane_update_noarm(plane, crtc_state, new_plane_state);
-               intel_plane_update_arm(plane, crtc_state, new_plane_state);
+               intel_plane_update_noarm(NULL, plane, crtc_state, new_plane_state);
+               intel_plane_update_arm(NULL, plane, crtc_state, new_plane_state);
        } else {
-               intel_plane_disable_arm(plane, crtc_state);
+               intel_plane_disable_arm(NULL, plane, crtc_state);
        }
 
        local_irq_enable();

diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index e881bfeafb47d7e608eea37a6c4a2b11d2cd8874..e017cd4a81685ab0aee6f8253a7bf24d70afb2c9 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -8,6 +8,7 @@
 
 #include "i915_drv.h"
 #include "i915_trace.h"
+#include "intel_dsb.h"
 #include "intel_uncore.h"
 
 static inline struct intel_uncore *__to_uncore(struct intel_display *display)
@@ -233,4 +234,14 @@ __intel_de_write_notrace(struct intel_display *display, i915_reg_t reg,
 }
 #define intel_de_write_notrace(p,...) __intel_de_write_notrace(__to_intel_display(p), __VA_ARGS__)
 
+static __always_inline void
+intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb,
+                  i915_reg_t reg, u32 val)
+{
+       if (dsb)
+               intel_dsb_reg_write(dsb, reg, val);
+       else
+               intel_de_write_fw(display, reg, val);
+}
+
 #endif /* __INTEL_DE_H__ */

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index dfbe1d4de6270dc06afc876ab08cf07d0e9c6f0e..3f4e629aa88ec54862f6c5ae3525a6444614243d 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -134,7 +134,8 @@
 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
-static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state);
+static void bdw_set_pipe_misc(struct intel_dsb *dsb,
+                             const struct intel_crtc_state *crtc_state);
 
 /* returns HPLL frequency in kHz */
 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
@@ -816,7 +817,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
        if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
                intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
 
-       intel_plane_disable_arm(plane, crtc_state);
+       intel_plane_disable_arm(NULL, plane, crtc_state);
        intel_crtc_wait_for_next_vblank(crtc);
 }
 
@@ -1289,8 +1290,8 @@ static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
                         * Apart from the async flip bit we want to
                         * preserve the old state for the plane.
                         */
-                       intel_plane_async_flip(plane, old_crtc_state,
-                                              old_plane_state, false);
+                       intel_plane_async_flip(NULL, plane,
+                                              old_crtc_state, old_plane_state, false);
                        need_vbl_wait = true;
                }
        }
@@ -1432,7 +1433,7 @@ static void intel_crtc_disable_planes(struct intel_atomic_state *state,
                    !(update_mask & BIT(plane->id)))
                        continue;
 
-               intel_plane_disable_arm(plane, new_crtc_state);
+               intel_plane_disable_arm(NULL, plane, new_crtc_state);
 
                if (old_plane_state->uapi.visible)
                        fb_bits |= plane->frontbuffer_bit;
@@ -1819,7 +1820,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
                intel_set_pipe_src_size(pipe_crtc_state);
 
                if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
-                       bdw_set_pipe_misc(pipe_crtc_state);
+                       bdw_set_pipe_misc(NULL, pipe_crtc_state);
        }
 
        if (!transcoder_is_dsi(cpu_transcoder))
@@ -3334,9 +3335,11 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
        intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
 }
 
-static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state)
+static void bdw_set_pipe_misc(struct intel_dsb *dsb,
+                             const struct intel_crtc_state *crtc_state)
 {
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+       struct intel_display *display = to_intel_display(crtc->base.dev);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        u32 val = 0;
 
@@ -3381,7 +3384,7 @@ static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state)
        if (IS_BROADWELL(dev_priv))
                val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE;
 
-       intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val);
+       intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val);
 }
 
 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc)
@@ -7072,7 +7075,7 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
                        intel_color_commit_arm(new_crtc_state);
 
                if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
-                       bdw_set_pipe_misc(new_crtc_state);
+                       bdw_set_pipe_misc(NULL, new_crtc_state);
 
                if (intel_crtc_needs_fastset(new_crtc_state))
                        intel_pipe_fastset(old_crtc_state, new_crtc_state);
@@ -7172,7 +7175,7 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
            intel_crtc_needs_color_update(new_crtc_state))
                intel_color_commit_noarm(new_crtc_state);
 
-       intel_crtc_planes_update_noarm(state, crtc);
+       intel_crtc_planes_update_noarm(NULL, state, crtc);
 }
 
 static void intel_update_crtc(struct intel_atomic_state *state,
@@ -7188,7 +7191,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 
        commit_pipe_pre_planes(state, crtc);
 
-       intel_crtc_planes_update_arm(state, crtc);
+       intel_crtc_planes_update_arm(NULL, state, crtc);
 
        commit_pipe_post_planes(state, crtc);
 

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e0ec2126604723233e98dad2347bb8fedf97e960..3902b25e7d24188b26fc08f8d3a1e3e049cda2d1 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -909,6 +909,10 @@ struct intel_csc_matrix {
        u16 postoff[3];
 };
 
+void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val);
+
+typedef void (*intel_io_reg_write)(void *ctx, i915_reg_t reg, u32 val);
+
 struct intel_crtc_state {
        /*
         * uapi (drm) state. This is the software state shown to userspace.
@@ -1452,22 +1456,26 @@ struct intel_plane {
                                   u32 pixel_format, u64 modifier,
                                   unsigned int rotation);
        /* Write all non-self arming plane registers */
-       void (*update_noarm)(struct intel_plane *plane,
+       void (*update_noarm)(struct intel_dsb *dsb,
+                            struct intel_plane *plane,
                             const struct intel_crtc_state *crtc_state,
                             const struct intel_plane_state *plane_state);
        /* Write all self-arming plane registers */
-       void (*update_arm)(struct intel_plane *plane,
+       void (*update_arm)(struct intel_dsb *dsb,
+                          struct intel_plane *plane,
                           const struct intel_crtc_state *crtc_state,
                           const struct intel_plane_state *plane_state);
        /* Disable the plane, must arm */
-       void (*disable_arm)(struct intel_plane *plane,
+       void (*disable_arm)(struct intel_dsb *dsb,
+                           struct intel_plane *plane,
                            const struct intel_crtc_state *crtc_state);
        bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
        int (*check_plane)(struct intel_crtc_state *crtc_state,
                           struct intel_plane_state *plane_state);
        int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
                         const struct intel_plane_state *plane_state);
-       void (*async_flip)(struct intel_plane *plane,
+       void (*async_flip)(struct intel_dsb *dsb,
+                          struct intel_plane *plane,
                           const struct intel_crtc_state *crtc_state,
                           const struct intel_plane_state *plane_state,
                           bool async_flip);

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index e657b09ede999b5af73a309e983144005478ac8e..e6fadcef58e06cadeb5ca4389d45dd2e26958720 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -378,7 +378,8 @@ static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state)
 }
 
 static void
-vlv_sprite_update_noarm(struct intel_plane *plane,
+vlv_sprite_update_noarm(struct intel_dsb *dsb,
+                       struct intel_plane *plane,
                        const struct intel_crtc_state *crtc_state,
                        const struct intel_plane_state *plane_state)
 {
@@ -399,7 +400,8 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
 }
 
 static void
-vlv_sprite_update_arm(struct intel_plane *plane,
+vlv_sprite_update_arm(struct intel_dsb *dsb,
+                     struct intel_plane *plane,
                      const struct intel_crtc_state *crtc_state,
                      const struct intel_plane_state *plane_state)
 {
@@ -449,7 +451,8 @@ vlv_sprite_update_arm(struct intel_plane *plane,
 }
 
 static void
-vlv_sprite_disable_arm(struct intel_plane *plane,
+vlv_sprite_disable_arm(struct intel_dsb *dsb,
+                      struct intel_plane *plane,
                       const struct intel_crtc_state *crtc_state)
 {
        struct intel_display *display = to_intel_display(plane->base.dev);
@@ -795,7 +798,8 @@ static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state)
 }
 
 static void
-ivb_sprite_update_noarm(struct intel_plane *plane,
+ivb_sprite_update_noarm(struct intel_dsb *dsb,
+                       struct intel_plane *plane,
                        const struct intel_crtc_state *crtc_state,
                        const struct intel_plane_state *plane_state)
 {
@@ -826,7 +830,8 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
 }
 
 static void
-ivb_sprite_update_arm(struct intel_plane *plane,
+ivb_sprite_update_arm(struct intel_dsb *dsb,
+                     struct intel_plane *plane,
                      const struct intel_crtc_state *crtc_state,
                      const struct intel_plane_state *plane_state)
 {
@@ -874,7 +879,8 @@ ivb_sprite_update_arm(struct intel_plane *plane,
 }
 
 static void
-ivb_sprite_disable_arm(struct intel_plane *plane,
+ivb_sprite_disable_arm(struct intel_dsb *dsb,
+                      struct intel_plane *plane,
                       const struct intel_crtc_state *crtc_state)
 {
        struct intel_display *display = to_intel_display(plane->base.dev);
@@ -1133,7 +1139,8 @@ static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state)
 }
 
 static void
-g4x_sprite_update_noarm(struct intel_plane *plane,
+g4x_sprite_update_noarm(struct intel_dsb *dsb,
+                       struct intel_plane *plane,
                        const struct intel_crtc_state *crtc_state,
                        const struct intel_plane_state *plane_state)
 {
@@ -1162,7 +1169,8 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
 }
 
 static void
-g4x_sprite_update_arm(struct intel_plane *plane,
+g4x_sprite_update_arm(struct intel_dsb *dsb,
+                     struct intel_plane *plane,
                      const struct intel_crtc_state *crtc_state,
                      const struct intel_plane_state *plane_state)
 {
@@ -1206,7 +1214,8 @@ g4x_sprite_update_arm(struct intel_plane *plane,
 }
 
 static void
-g4x_sprite_disable_arm(struct intel_plane *plane,
+g4x_sprite_disable_arm(struct intel_dsb *dsb,
+                      struct intel_plane *plane,
                       const struct intel_crtc_state *crtc_state)
 {
        struct intel_display *display = to_intel_display(plane->base.dev);

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index fdb141cfa4274aa96b28fac1d94371eb89258255..9207b7e96974a9af1595d7c1e0c94b6cca11e605 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -594,11 +594,11 @@ static u32 skl_plane_min_alignment(struct intel_plane *plane,
  * in full-range YCbCr.
  */
 static void
-icl_program_input_csc(struct intel_plane *plane,
-                     const struct intel_crtc_state *crtc_state,
+icl_program_input_csc(struct intel_dsb *dsb,
+                     struct intel_plane *plane,
                      const struct intel_plane_state *plane_state)
 {
-       struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+       struct intel_display *display = to_intel_display(plane->base.dev);
        enum pipe pipe = plane->pipe;
        enum plane_id plane_id = plane->id;
 
@@ -642,31 +642,31 @@ icl_program_input_csc(struct intel_plane *plane,
        };
        const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding];
 
-       intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0),
-                         ROFF(csc[0]) | GOFF(csc[1]));
-       intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1),
-                         BOFF(csc[2]));
-       intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2),
-                         ROFF(csc[3]) | GOFF(csc[4]));
-       intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3),
-                         BOFF(csc[5]));
-       intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4),
-                         ROFF(csc[6]) | GOFF(csc[7]));
-       intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5),
-                         BOFF(csc[8]));
-
-       intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
-                         PREOFF_YUV_TO_RGB_HI);
-       intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
-                         PREOFF_YUV_TO_RGB_ME);
-       intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),
-                         PREOFF_YUV_TO_RGB_LO);
-       intel_de_write_fw(dev_priv,
-                         PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0);
-       intel_de_write_fw(dev_priv,
-                         PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0);
-       intel_de_write_fw(dev_priv,
-                         PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
+       intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0),
+                          ROFF(csc[0]) | GOFF(csc[1]));
+       intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1),
+                          BOFF(csc[2]));
+       intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2),
+                          ROFF(csc[3]) | GOFF(csc[4]));
+       intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3),
+                          BOFF(csc[5]));
+       intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4),
+                          ROFF(csc[6]) | GOFF(csc[7]));
+       intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5),
+                          BOFF(csc[8]));
+
+       intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
+                          PREOFF_YUV_TO_RGB_HI);
+       intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
+                          PREOFF_YUV_TO_RGB_ME);
+       intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),
+                          PREOFF_YUV_TO_RGB_LO);
+       intel_de_write_dsb(display, dsb,
+                          PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0);
+       intel_de_write_dsb(display, dsb,
+                          PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0);
+       intel_de_write_dsb(display, dsb,
+                          PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
 }
 
 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
@@ -720,9 +720,11 @@ static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
        return val;
 }
 
-static void skl_write_plane_wm(struct intel_plane *plane,
+static void skl_write_plane_wm(struct intel_dsb *dsb,
+                              struct intel_plane *plane,
                               const struct intel_crtc_state *crtc_state)
 {
+       struct intel_display *display = to_intel_display(plane->base.dev);
        struct drm_i915_private *i915 = to_i915(plane->base.dev);
        enum plane_id plane_id = plane->id;
        enum pipe pipe = plane->pipe;
@@ -734,71 +736,75 @@ static void skl_write_plane_wm(struct intel_plane *plane,
        int level;
 
        for (level = 0; level < i915->display.wm.num_levels; level++)
-               intel_de_write_fw(i915, PLANE_WM(pipe, plane_id, level),
-                                 skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
+               intel_de_write_dsb(display, dsb, PLANE_WM(pipe, plane_id, level),
+                                  skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
 
-       intel_de_write_fw(i915, PLANE_WM_TRANS(pipe, plane_id),
-                         skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
+       intel_de_write_dsb(display, dsb, PLANE_WM_TRANS(pipe, plane_id),
+                          skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
 
        if (HAS_HW_SAGV_WM(i915)) {
                const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
 
-               intel_de_write_fw(i915, PLANE_WM_SAGV(pipe, plane_id),
-                                 skl_plane_wm_reg_val(&wm->sagv.wm0));
-               intel_de_write_fw(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id),
-                                 skl_plane_wm_reg_val(&wm->sagv.trans_wm));
+               intel_de_write_dsb(display, dsb, PLANE_WM_SAGV(pipe, plane_id),
+                                  skl_plane_wm_reg_val(&wm->sagv.wm0));
+               intel_de_write_dsb(display, dsb, PLANE_WM_SAGV_TRANS(pipe, plane_id),
+                                  skl_plane_wm_reg_val(&wm->sagv.trans_wm));
        }
 
-       intel_de_write_fw(i915, PLANE_BUF_CFG(pipe, plane_id),
-                         skl_plane_ddb_reg_val(ddb));
+       intel_de_write_dsb(display, dsb, PLANE_BUF_CFG(pipe, plane_id),
+                          skl_plane_ddb_reg_val(ddb));
 
        if (DISPLAY_VER(i915) < 11)
-               intel_de_write_fw(i915, PLANE_NV12_BUF_CFG(pipe, plane_id),
-                                 skl_plane_ddb_reg_val(ddb_y));
+               intel_de_write_dsb(display, dsb, PLANE_NV12_BUF_CFG(pipe, plane_id),
+                                  skl_plane_ddb_reg_val(ddb_y));
 }
 
 static void
-skl_plane_disable_arm(struct intel_plane *plane,
+skl_plane_disable_arm(struct intel_dsb *dsb,
+                     struct intel_plane *plane,
                      const struct intel_crtc_state *crtc_state)
 {
-       struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+       struct intel_display *display = to_intel_display(plane->base.dev);
        enum plane_id plane_id = plane->id;
        enum pipe pipe = plane->pipe;
 
-       skl_write_plane_wm(plane, crtc_state);
+       skl_write_plane_wm(dsb, plane, crtc_state);
 
-       intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
-       intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
+       intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);
+       intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0);
 }
 
-static void icl_plane_disable_sel_fetch_arm(struct intel_plane *plane,
+static void icl_plane_disable_sel_fetch_arm(struct intel_dsb *dsb,
+                                           struct intel_plane *plane,
                                            const struct intel_crtc_state *crtc_state)
 {
-       struct drm_i915_private *i915 = to_i915(plane->base.dev);
+       struct intel_display *display = to_intel_display(plane->base.dev);
        enum pipe pipe = plane->pipe;
 
        if (!crtc_state->enable_psr2_sel_fetch)
                return;
 
-       intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);
+       intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);
 }
 
 static void
-icl_plane_disable_arm(struct intel_plane *plane,
+icl_plane_disable_arm(struct intel_dsb *dsb,
+                     struct intel_plane *plane,
                      const struct intel_crtc_state *crtc_state)
 {
+       struct intel_display *display = to_intel_display(plane->base.dev);
        struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
        enum plane_id plane_id = plane->id;
        enum pipe pipe = plane->pipe;
 
        if (icl_is_hdr_plane(dev_priv, plane_id))
-               intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0);
+               intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id), 0);
 
-       skl_write_plane_wm(plane, crtc_state);
+       skl_write_plane_wm(dsb, plane, crtc_state);
 
-       icl_plane_disable_sel_fetch_arm(plane, crtc_state);
-       intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
-       intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
+       icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state);
+       intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);
+       intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0);
 }
 
 static bool
@@ -1235,28 +1241,30 @@ static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state)
        return keymsk;
 }
 
-static void icl_plane_csc_load_black(struct intel_plane *plane)
+static void icl_plane_csc_load_black(struct intel_dsb *dsb,
+                                    struct intel_plane *plane,
+                                    const struct intel_crtc_state *crtc_state)
 {
-       struct drm_i915_private *i915 = to_i915(plane->base.dev);
+       struct intel_display *display = to_intel_display(plane->base.dev);
        enum plane_id plane_id = plane->id;
        enum pipe pipe = plane->pipe;
 
-       intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 0), 0);
-       intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 1), 0);
+       intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 0), 0);
+       intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 1), 0);
 
-       intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 2), 0);
-       intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 3), 0);
+       intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 2), 0);
+       intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 3), 0);
 
-       intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 4), 0);
-       intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 5), 0);
+       intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 4), 0);
+       intel_de_write_dsb(display, dsb, PLANE_CSC_COEFF(pipe, plane_id, 5), 0);
 
-       intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 0), 0);
-       intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 1), 0);
-       intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 2), 0);
+       intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 0), 0);
+       intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 1), 0);
+       intel_de_write_dsb(display, dsb, PLANE_CSC_PREOFF(pipe, plane_id, 2), 0);
 
-       intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 0), 0);
-       intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 1), 0);
-       intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);
+       intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 0), 0);
+       intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 1), 0);
+       intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);
 }
 
 static int icl_plane_color_plane(const struct intel_plane_state *plane_state)
@@ -1269,11 +1277,12 @@ static int icl_plane_color_plane(const struct intel_plane_state *plane_state)
 }
 
 static void
-skl_plane_update_noarm(struct intel_plane *plane,
+skl_plane_update_noarm(struct intel_dsb *dsb,
+                      struct intel_plane *plane,
                       const struct intel_crtc_state *crtc_state,
                       const struct intel_plane_state *plane_state)
 {
-       struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+       struct intel_display *display = to_intel_display(plane->base.dev);
        enum plane_id plane_id = plane->id;
        enum pipe pipe = plane->pipe;
        u32 stride = skl_plane_stride(plane_state, 0);
@@ -1288,21 +1297,23 @@ skl_plane_update_noarm(struct intel_plane *plane,
                crtc_y = 0;
        }
 
-       intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
-                         PLANE_STRIDE_(stride));
-       intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
-                         PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
-       intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
-                         PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
+       intel_de_write_dsb(display, dsb, PLANE_STRIDE(pipe, plane_id),
+                          PLANE_STRIDE_(stride));
+       intel_de_write_dsb(display, dsb, PLANE_POS(pipe, plane_id),
+                          PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
+       intel_de_write_dsb(display, dsb, PLANE_SIZE(pipe, plane_id),
+                          PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
 
-       skl_write_plane_wm(plane, crtc_state);
+       skl_write_plane_wm(dsb, plane, crtc_state);
 }
 
 static void
-skl_plane_update_arm(struct intel_plane *plane,
+skl_plane_update_arm(struct intel_dsb *dsb,
+                    struct intel_plane *plane,
                     const struct intel_crtc_state *crtc_state,
                     const struct intel_plane_state *plane_state)
 {
+       struct intel_display *display = to_intel_display(plane->base.dev);
        struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
        enum plane_id plane_id = plane->id;
        enum pipe pipe = plane->pipe;
@@ -1322,22 +1333,26 @@ skl_plane_update_arm(struct intel_plane *plane,
                plane_color_ctl = plane_state->color_ctl |
                        glk_plane_color_ctl_crtc(crtc_state);
 
-       intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state));
-       intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state));
-       intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state));
+       intel_de_write_dsb(display, dsb, PLANE_KEYVAL(pipe, plane_id),
+                          skl_plane_keyval(plane_state));
+       intel_de_write_dsb(display, dsb, PLANE_KEYMSK(pipe, plane_id),
+                          skl_plane_keymsk(plane_state));
+       intel_de_write_dsb(display, dsb, PLANE_KEYMAX(pipe, plane_id),
+                          skl_plane_keymax(plane_state));
 
-       intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
-                         PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
+       intel_de_write_dsb(display, dsb, PLANE_OFFSET(pipe, plane_id),
+                          PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
 
-       intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
-                         skl_plane_aux_dist(plane_state, 0));
+       intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id),
+                          skl_plane_aux_dist(plane_state, 0));
 
-       intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
-                         PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) |
-                         PLANE_OFFSET_X(plane_state->view.color_plane[1].x));
+       intel_de_write_dsb(display, dsb, PLANE_AUX_OFFSET(pipe, plane_id),
+                          PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) |
+                          PLANE_OFFSET_X(plane_state->view.color_plane[1].x));
 
        if (DISPLAY_VER(dev_priv) >= 10)
-               intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
+               intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id),
+                                  plane_color_ctl);
 
        /*
         * Enable the scaler before the plane so that we don't
@@ -1354,17 +1369,19 @@ skl_plane_update_arm(struct intel_plane *plane,
         * disabled. Try to make the plane enable atomic by writing
         * the control register just before the surface register.
         */
-       intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
-       intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
-                         skl_plane_surf(plane_state, 0));
+       intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),
+                          plane_ctl);
+       intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),
+                          skl_plane_surf(plane_state, 0));
 }
 
-static void icl_plane_update_sel_fetch_noarm(struct intel_plane *plane,
+static void icl_plane_update_sel_fetch_noarm(struct intel_dsb *dsb,
+                                            struct intel_plane *plane,
                                             const struct intel_crtc_state *crtc_state,
                                             const struct intel_plane_state *plane_state,
                                             int color_plane)
 {
-       struct drm_i915_private *i915 = to_i915(plane->base.dev);
+       struct intel_display *display = to_intel_display(plane->base.dev);
        enum pipe pipe = plane->pipe;
        const struct drm_rect *clip;
        u32 val;
@@ -1381,7 +1398,7 @@ static void icl_plane_update_sel_fetch_noarm(struct intel_plane *plane,
                y = (clip->y1 + plane_state->uapi.dst.y1);
        val = y << 16;
        val |= plane_state->uapi.dst.x1;
-       intel_de_write_fw(i915, SEL_FETCH_PLANE_POS(pipe, plane->id), val);
+       intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_POS(pipe, plane->id), val);
 
        x = plane_state->view.color_plane[color_plane].x;
 
@@ -1396,20 +1413,21 @@ static void icl_plane_update_sel_fetch_noarm(struct intel_plane *plane,
 
        val = y << 16 | x;
 
-       intel_de_write_fw(i915, SEL_FETCH_PLANE_OFFSET(pipe, plane->id),
-                         val);
+       intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_OFFSET(pipe, plane->id), val);
 
        /* Sizes are 0 based */
        val = (drm_rect_height(clip) - 1) << 16;
        val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
-       intel_de_write_fw(i915, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val);
+       intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val);
 }
 
 static void
-icl_plane_update_noarm(struct intel_plane *plane,
+icl_plane_update_noarm(struct intel_dsb *dsb,
+                      struct intel_plane *plane,
                       const struct intel_crtc_state *crtc_state,
                       const struct intel_plane_state *plane_state)
 {
+       struct intel_display *display = to_intel_display(plane->base.dev);
        struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
        enum plane_id plane_id = plane->id;
        enum pipe pipe = plane->pipe;
@@ -1433,76 +1451,82 @@ icl_plane_update_noarm(struct intel_plane *plane,
                crtc_y = 0;
        }
 
-       intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
-                         PLANE_STRIDE_(stride));
-       intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
-                         PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
-       intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
-                         PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
+       intel_de_write_dsb(display, dsb, PLANE_STRIDE(pipe, plane_id),
+                          PLANE_STRIDE_(stride));
+       intel_de_write_dsb(display, dsb, PLANE_POS(pipe, plane_id),
+                          PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
+       intel_de_write_dsb(display, dsb, PLANE_SIZE(pipe, plane_id),
+                          PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
 
-       intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state));
-       intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state));
-       intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state));
+       intel_de_write_dsb(display, dsb, PLANE_KEYVAL(pipe, plane_id),
+                          skl_plane_keyval(plane_state));
+       intel_de_write_dsb(display, dsb, PLANE_KEYMSK(pipe, plane_id),
+                          skl_plane_keymsk(plane_state));
+       intel_de_write_dsb(display, dsb, PLANE_KEYMAX(pipe, plane_id),
+                          skl_plane_keymax(plane_state));
 
-       intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
-                         PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
+       intel_de_write_dsb(display, dsb, PLANE_OFFSET(pipe, plane_id),
+                          PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
 
        if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
-               intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
-                                 lower_32_bits(plane_state->ccval));
-               intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 1),
-                                 upper_32_bits(plane_state->ccval));
+               intel_de_write_dsb(display, dsb, PLANE_CC_VAL(pipe, plane_id, 0),
+                                  lower_32_bits(plane_state->ccval));
+               intel_de_write_dsb(display, dsb, PLANE_CC_VAL(pipe, plane_id, 1),
+                                  upper_32_bits(plane_state->ccval));
        }
 
        /* FLAT CCS doesn't need to program AUX_DIST */
        if (!HAS_FLAT_CCS(dev_priv) && DISPLAY_VER(dev_priv) < 20)
-               intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
-                                 skl_plane_aux_dist(plane_state, color_plane));
+               intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id),
+                                  skl_plane_aux_dist(plane_state, color_plane));
 
        if (icl_is_hdr_plane(dev_priv, plane_id))
-               intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
-                                 plane_state->cus_ctl);
+               intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id),
+                                  plane_state->cus_ctl);
 
-       intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
+       intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id),
+                          plane_color_ctl);
 
        if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
-               icl_program_input_csc(plane, crtc_state, plane_state);
+               icl_program_input_csc(dsb, plane, plane_state);
 
-       skl_write_plane_wm(plane, crtc_state);
+       skl_write_plane_wm(dsb, plane, crtc_state);
 
        /*
         * FIXME: pxp session invalidation can hit any time even at time of commit
         * or after the commit, display content will be garbage.
         */
        if (plane_state->force_black)
-               icl_plane_csc_load_black(plane);
+               icl_plane_csc_load_black(dsb, plane, crtc_state);
 
-       icl_plane_update_sel_fetch_noarm(plane, crtc_state, plane_state, color_plane);
+       icl_plane_update_sel_fetch_noarm(dsb, plane, crtc_state, plane_state, color_plane);
 }
 
-static void icl_plane_update_sel_fetch_arm(struct intel_plane *plane,
+static void icl_plane_update_sel_fetch_arm(struct intel_dsb *dsb,
+                                          struct intel_plane *plane,
                                           const struct intel_crtc_state *crtc_state,
                                           const struct intel_plane_state *plane_state)
 {
-       struct drm_i915_private *i915 = to_i915(plane->base.dev);
+       struct intel_display *display = to_intel_display(plane->base.dev);
        enum pipe pipe = plane->pipe;
 
        if (!crtc_state->enable_psr2_sel_fetch)
                return;
 
        if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0)
-               intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id),
-                                 SEL_FETCH_PLANE_CTL_ENABLE);
+               intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id),
+                                  SEL_FETCH_PLANE_CTL_ENABLE);
        else
-               icl_plane_disable_sel_fetch_arm(plane, crtc_state);
+               icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state);
 }
 
 static void
-icl_plane_update_arm(struct intel_plane *plane,
+icl_plane_update_arm(struct intel_dsb *dsb,
+                    struct intel_plane *plane,
                     const struct intel_crtc_state *crtc_state,
                     const struct intel_plane_state *plane_state)
 {
-       struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+       struct intel_display *display = to_intel_display(plane->base.dev);
        enum plane_id plane_id = plane->id;
        enum pipe pipe = plane->pipe;
        int color_plane = icl_plane_color_plane(plane_state);
@@ -1521,25 +1545,27 @@ icl_plane_update_arm(struct intel_plane *plane,
        if (plane_state->scaler_id >= 0)
                skl_program_plane_scaler(plane, crtc_state, plane_state);
 
-       icl_plane_update_sel_fetch_arm(plane, crtc_state, plane_state);
+       icl_plane_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);
 
        /*
         * The control register self-arms if the plane was previously
         * disabled. Try to make the plane enable atomic by writing
         * the control register just before the surface register.
         */
-       intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
-       intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
-                         skl_plane_surf(plane_state, color_plane));
+       intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),
+                          plane_ctl);
+       intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),
+                          skl_plane_surf(plane_state, color_plane));
 }
 
 static void
-skl_plane_async_flip(struct intel_plane *plane,
+skl_plane_async_flip(struct intel_dsb *dsb,
+                    struct intel_plane *plane,
                     const struct intel_crtc_state *crtc_state,
                     const struct intel_plane_state *plane_state,
                     bool async_flip)
 {
-       struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+       struct intel_display *display = to_intel_display(plane->base.dev);
        enum plane_id plane_id = plane->id;
        enum pipe pipe = plane->pipe;
        u32 plane_ctl = plane_state->ctl;
@@ -1549,9 +1575,10 @@ skl_plane_async_flip(struct intel_plane *plane,
        if (async_flip)
                plane_ctl |= PLANE_CTL_ASYNC_FLIP;
 
-       intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
-       intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
-                         skl_plane_surf(plane_state, 0));
+       intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),
+                          plane_ctl);
+       intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),
+                          skl_plane_surf(plane_state, 0));
 }
 
 static bool intel_format_is_p01x(u32 format)

diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c
index 1b10ea499d8c8956993ceb7f2d3e6442ab0920d9..8c113463a3d559995efabdad3fa569b6e77c24af 100644 (file)
--- a/drivers/gpu/drm/xe/display/xe_plane_initial.c
+++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c
@@ -248,7 +248,7 @@ intel_find_initial_plane_obj(struct intel_crtc *crtc,
         * the lookup of sysmem scratch pages.
         */
        plane->check_plane(crtc_state, plane_state);
-       plane->async_flip(plane, crtc_state, plane_state, true);
+       plane->async_flip(NULL, plane, crtc_state, plane_state, true);
        return;
 
 nofb: