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mtd: spi-nor: Move Spansion bits out of core.c
authorBoris Brezillon <bbrezillon@kernel.org>
Fri, 13 Mar 2020 19:42:46 +0000 (19:42 +0000)
committerTudor Ambarus <tudor.ambarus@microchip.com>
Tue, 17 Mar 2020 07:28:05 +0000 (09:28 +0200)
Create a SPI NOR manufacturer driver for Spansion chips, and move the
Spansion definitions outside of core.c.

Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
drivers/mtd/spi-nor/Makefile patch | blob | blame | history
drivers/mtd/spi-nor/core.c patch | blob | blame | history
drivers/mtd/spi-nor/core.h patch | blob | blame | history
drivers/mtd/spi-nor/spansion.c [new file with mode: 0644] patch | blob

diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
index c7e5fb908bece580aff5b2b1fa7b47f04b1cfb1c..cb06ee50bf68a774f4bff9dc7e38a87cab0d365f 100644 (file)
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
@@ -11,4 +11,5 @@ spi-nor-objs                  += intel.o
 spi-nor-objs                   += issi.o
 spi-nor-objs                   += macronix.o
 spi-nor-objs                   += micron-st.o
+spi-nor-objs                   += spansion.o
 obj-$(CONFIG_MTD_SPI_NOR)      += spi-nor.o
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 4885607dc917cf13378b7f89a0df41d369845dc9..1500951254d939827f8f74992a4ecf0276620517 100644 (file)
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -1995,44 +1995,6 @@ int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
  * old entries may be missing 4K flag.
  */
 static const struct flash_info spi_nor_ids[] = {
-       /* Spansion/Cypress -- single (large) sector size only, at least
-        * for the chips listed here (without boot sectors).
-        */
-       { "s25sl032p",  INFO(0x010215, 0x4d00,  64 * 1024,  64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
-       { "s25sl064p",  INFO(0x010216, 0x4d00,  64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
-       { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64,
-                       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
-       { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256,
-                       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
-       { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
-       { "s25fl256s1", INFO(0x010219, 0x4d01,  64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
-       { "s25fl512s",  INFO6(0x010220, 0x4d0080, 256 * 1024, 256,
-                       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
-                       SPI_NOR_HAS_LOCK | USE_CLSR) },
-       { "s25fs512s",  INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
-       { "s70fl01gs",  INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
-       { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024,  64, 0) },
-       { "s25sl12801", INFO(0x012018, 0x0301,  64 * 1024, 256, 0) },
-       { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024,  64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
-       { "s25fl129p1", INFO(0x012018, 0x4d01,  64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
-       { "s25sl004a",  INFO(0x010212,      0,  64 * 1024,   8, 0) },
-       { "s25sl008a",  INFO(0x010213,      0,  64 * 1024,  16, 0) },
-       { "s25sl016a",  INFO(0x010214,      0,  64 * 1024,  32, 0) },
-       { "s25sl032a",  INFO(0x010215,      0,  64 * 1024,  64, 0) },
-       { "s25sl064a",  INFO(0x010216,      0,  64 * 1024, 128, 0) },
-       { "s25fl004k",  INFO(0xef4013,      0,  64 * 1024,   8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
-       { "s25fl008k",  INFO(0xef4014,      0,  64 * 1024,  16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
-       { "s25fl016k",  INFO(0xef4015,      0,  64 * 1024,  32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
-       { "s25fl064k",  INFO(0xef4017,      0,  64 * 1024, 128, SECT_4K) },
-       { "s25fl116k",  INFO(0x014015,      0,  64 * 1024,  32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
-       { "s25fl132k",  INFO(0x014016,      0,  64 * 1024,  64, SECT_4K) },
-       { "s25fl164k",  INFO(0x014017,      0,  64 * 1024, 128, SECT_4K) },
-       { "s25fl204k",  INFO(0x014013,      0,  64 * 1024,   8, SECT_4K | SPI_NOR_DUAL_READ) },
-       { "s25fl208k",  INFO(0x014014,      0,  64 * 1024,  16, SECT_4K | SPI_NOR_DUAL_READ) },
-       { "s25fl064l",  INFO(0x016017,      0,  64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
-       { "s25fl128l",  INFO(0x016018,      0,  64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
-       { "s25fl256l",  INFO(0x016019,      0,  64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
-
        /* SST -- large erase sizes are "overlays", "sectors" are 4K */
        { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024,  8, SECT_4K | SST_WRITE) },
        { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
@@ -2151,6 +2113,7 @@ static const struct spi_nor_manufacturer *manufacturers[] = {
        &spi_nor_macronix,
        &spi_nor_micron,
        &spi_nor_st,
+       &spi_nor_spansion,
 };
 
 static const struct flash_info *
@@ -3084,17 +3047,6 @@ static void spi_nor_info_init_params(struct spi_nor *nor)
        spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
 }
 
-static void spansion_post_sfdp_fixups(struct spi_nor *nor)
-{
-       if (nor->params.size <= SZ_16M)
-               return;
-
-       nor->flags |= SNOR_F_4B_OPCODES;
-       /* No small sector erase for 4-byte command set */
-       nor->erase_opcode = SPINOR_OP_SE;
-       nor->mtd.erasesize = nor->info->sector_size;
-}
-
 static void s3an_post_sfdp_fixups(struct spi_nor *nor)
 {
        nor->params.setup = s3an_nor_setup;
@@ -3112,15 +3064,6 @@ static void s3an_post_sfdp_fixups(struct spi_nor *nor)
  */
 static void spi_nor_post_sfdp_fixups(struct spi_nor *nor)
 {
-       switch (JEDEC_MFR(nor->info)) {
-       case SNOR_MFR_SPANSION:
-               spansion_post_sfdp_fixups(nor);
-               break;
-
-       default:
-               break;
-       }
-
        if (nor->info->flags & SPI_S3AN)
                s3an_post_sfdp_fixups(nor);
 
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index fc4a70d8713c1e36f397e2ffd3f7cd99490c9512..470025131d471249793ce0d6ee611e5e6d52d885 100644 (file)
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -178,6 +178,7 @@ extern const struct spi_nor_manufacturer spi_nor_issi;
 extern const struct spi_nor_manufacturer spi_nor_macronix;
 extern const struct spi_nor_manufacturer spi_nor_micron;
 extern const struct spi_nor_manufacturer spi_nor_st;
+extern const struct spi_nor_manufacturer spi_nor_spansion;
 
 int spi_nor_write_enable(struct spi_nor *nor);
 int spi_nor_write_disable(struct spi_nor *nor);
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
new file mode 100644 (file)
index 0000000..1668398
--- /dev/null
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2005, Intec Automation Inc.
+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
+ */
+
+#include <linux/mtd/spi-nor.h>
+
+#include "core.h"
+
+static const struct flash_info spansion_parts[] = {
+       /* Spansion/Cypress -- single (large) sector size only, at least
+        * for the chips listed here (without boot sectors).
+        */
+       { "s25sl032p",  INFO(0x010215, 0x4d00,  64 * 1024,  64,
+                            SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+       { "s25sl064p",  INFO(0x010216, 0x4d00,  64 * 1024, 128,
+                            SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+       { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64,
+                             SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+                             USE_CLSR) },
+       { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256,
+                             SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+                             USE_CLSR) },
+       { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
+       { "s25fl256s1", INFO(0x010219, 0x4d01,  64 * 1024, 512,
+                            SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+                            USE_CLSR) },
+       { "s25fl512s",  INFO6(0x010220, 0x4d0080, 256 * 1024, 256,
+                             SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+                             SPI_NOR_HAS_LOCK | USE_CLSR) },
+       { "s25fs512s",  INFO6(0x010220, 0x4d0081, 256 * 1024, 256,
+                             SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+                             USE_CLSR) },
+       { "s70fl01gs",  INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
+       { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024,  64, 0) },
+       { "s25sl12801", INFO(0x012018, 0x0301,  64 * 1024, 256, 0) },
+       { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024,  64,
+                            SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+                            USE_CLSR) },
+       { "s25fl129p1", INFO(0x012018, 0x4d01,  64 * 1024, 256,
+                            SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+                            USE_CLSR) },
+       { "s25sl004a",  INFO(0x010212,      0,  64 * 1024,   8, 0) },
+       { "s25sl008a",  INFO(0x010213,      0,  64 * 1024,  16, 0) },
+       { "s25sl016a",  INFO(0x010214,      0,  64 * 1024,  32, 0) },
+       { "s25sl032a",  INFO(0x010215,      0,  64 * 1024,  64, 0) },
+       { "s25sl064a",  INFO(0x010216,      0,  64 * 1024, 128, 0) },
+       { "s25fl004k",  INFO(0xef4013,      0,  64 * 1024,   8,
+                            SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+       { "s25fl008k",  INFO(0xef4014,      0,  64 * 1024,  16,
+                            SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+       { "s25fl016k",  INFO(0xef4015,      0,  64 * 1024,  32,
+                            SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+       { "s25fl064k",  INFO(0xef4017,      0,  64 * 1024, 128, SECT_4K) },
+       { "s25fl116k",  INFO(0x014015,      0,  64 * 1024,  32,
+                            SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+       { "s25fl132k",  INFO(0x014016,      0,  64 * 1024,  64, SECT_4K) },
+       { "s25fl164k",  INFO(0x014017,      0,  64 * 1024, 128, SECT_4K) },
+       { "s25fl204k",  INFO(0x014013,      0,  64 * 1024,   8,
+                            SECT_4K | SPI_NOR_DUAL_READ) },
+       { "s25fl208k",  INFO(0x014014,      0,  64 * 1024,  16,
+                            SECT_4K | SPI_NOR_DUAL_READ) },
+       { "s25fl064l",  INFO(0x016017,      0,  64 * 1024, 128,
+                            SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+                            SPI_NOR_4B_OPCODES) },
+       { "s25fl128l",  INFO(0x016018,      0,  64 * 1024, 256,
+                            SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+                            SPI_NOR_4B_OPCODES) },
+       { "s25fl256l",  INFO(0x016019,      0,  64 * 1024, 512,
+                            SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+                            SPI_NOR_4B_OPCODES) },
+};
+
+static void spansion_post_sfdp_fixups(struct spi_nor *nor)
+{
+       if (nor->params.size <= SZ_16M)
+               return;
+
+       nor->flags |= SNOR_F_4B_OPCODES;
+       /* No small sector erase for 4-byte command set */
+       nor->erase_opcode = SPINOR_OP_SE;
+       nor->mtd.erasesize = nor->info->sector_size;
+}
+
+static const struct spi_nor_fixups spansion_fixups = {
+       .post_sfdp = spansion_post_sfdp_fixups,
+};
+
+const struct spi_nor_manufacturer spi_nor_spansion = {
+       .name = "spansion",
+       .parts = spansion_parts,
+       .nparts = ARRAY_SIZE(spansion_parts),
+       .fixups = &spansion_fixups,
+};
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