arm64: dts: ti: k3-j784s4-main: Add CPSW2G and CPSW9G nodes

J784S4 SoC has MAIN CPSW2G and CPSW9G instances of the CPSW
Ethernet Switch. CPSW2G has 1 external port and 1 host port
while CPSW9G has 8 external ports and 1 host port.

Add device-tree nodes for MAIN CPSW2G and CPSW9G and disable
them by default. MAIN CPSW2G will be enabled in the board file
while device-tree overlays will be used to enable CPSW9G.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
Link: https://lore.kernel.org/r/20240502091002.3659435-3-c-vankar@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 6a4554c6c9c1305127e894cc150bbe3a465ba5d0..e44ae0cfd45729ab9849d3b4113f210121ff9dd0 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -48,6 +48,19 @@
                #size-cells = <1>;
                ranges = <0x00 0x00 0x00100000 0x1c000>;
 
+               cpsw1_phy_gmii_sel: phy@4034 {
+                       compatible = "ti,am654-phy-gmii-sel";
+                       reg = <0x4034 0x4>;
+                       #phy-cells = <1>;
+               };
+
+               cpsw0_phy_gmii_sel: phy@4044 {
+                       compatible = "ti,j784s4-cpsw9g-phy-gmii-sel";
+                       reg = <0x4044 0x20>;
+                       #phy-cells = <1>;
+                       ti,qsgmii-main-ports = <7>, <7>;
+               };
+
                serdes_ln_ctrl: mux-controller@4080 {
                        compatible = "reg-mux";
                        reg = <0x00004080 0x30>;
@@ -1427,6 +1440,180 @@
                };
        };
 
+       main_cpsw0: ethernet@c000000 {
+               compatible = "ti,j784s4-cpswxg-nuss";
+               reg = <0x00 0xc000000 0x00 0x200000>;
+               reg-names = "cpsw_nuss";
+               ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               dma-coherent;
+               clocks = <&k3_clks 64 0>;
+               clock-names = "fck";
+               power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
+
+               dmas = <&main_udmap 0xca00>,
+                      <&main_udmap 0xca01>,
+                      <&main_udmap 0xca02>,
+                      <&main_udmap 0xca03>,
+                      <&main_udmap 0xca04>,
+                      <&main_udmap 0xca05>,
+                      <&main_udmap 0xca06>,
+                      <&main_udmap 0xca07>,
+                      <&main_udmap 0x4a00>;
+               dma-names = "tx0", "tx1", "tx2", "tx3",
+                           "tx4", "tx5", "tx6", "tx7",
+                           "rx";
+
+               status = "disabled";
+
+               ethernet-ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       main_cpsw0_port1: port@1 {
+                               reg = <1>;
+                               label = "port1";
+                               ti,mac-only;
+                               status = "disabled";
+                       };
+
+                       main_cpsw0_port2: port@2 {
+                               reg = <2>;
+                               label = "port2";
+                               ti,mac-only;
+                               status = "disabled";
+                       };
+
+                       main_cpsw0_port3: port@3 {
+                               reg = <3>;
+                               label = "port3";
+                               ti,mac-only;
+                               status = "disabled";
+                       };
+
+                       main_cpsw0_port4: port@4 {
+                               reg = <4>;
+                               label = "port4";
+                               ti,mac-only;
+                               status = "disabled";
+                       };
+
+                       main_cpsw0_port5: port@5 {
+                               reg = <5>;
+                               label = "port5";
+                               ti,mac-only;
+                               status = "disabled";
+                       };
+
+                       main_cpsw0_port6: port@6 {
+                               reg = <6>;
+                               label = "port6";
+                               ti,mac-only;
+                               status = "disabled";
+                       };
+
+                       main_cpsw0_port7: port@7 {
+                               reg = <7>;
+                               label = "port7";
+                               ti,mac-only;
+                               status = "disabled";
+                       };
+
+                       main_cpsw0_port8: port@8 {
+                               reg = <8>;
+                               label = "port8";
+                               ti,mac-only;
+                               status = "disabled";
+                       };
+               };
+
+               main_cpsw0_mdio: mdio@f00 {
+                       compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+                       reg = <0x00 0xf00 0x00 0x100>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&k3_clks 64 0>;
+                       clock-names = "fck";
+                       bus_freq = <1000000>;
+                       status = "disabled";
+               };
+
+               cpts@3d000 {
+                       compatible = "ti,am65-cpts";
+                       reg = <0x00 0x3d000 0x00 0x400>;
+                       clocks = <&k3_clks 64 3>;
+                       clock-names = "cpts";
+                       interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "cpts";
+                       ti,cpts-ext-ts-inputs = <4>;
+                       ti,cpts-periodic-outputs = <2>;
+               };
+       };
+
+       main_cpsw1: ethernet@c200000 {
+               compatible = "ti,j721e-cpsw-nuss";
+               reg = <0x00 0xc200000 0x00 0x200000>;
+               reg-names = "cpsw_nuss";
+               ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               dma-coherent;
+               clocks = <&k3_clks 62 0>;
+               clock-names = "fck";
+               power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
+
+               dmas = <&main_udmap 0xc640>,
+                       <&main_udmap 0xc641>,
+                       <&main_udmap 0xc642>,
+                       <&main_udmap 0xc643>,
+                       <&main_udmap 0xc644>,
+                       <&main_udmap 0xc645>,
+                       <&main_udmap 0xc646>,
+                       <&main_udmap 0xc647>,
+                       <&main_udmap 0x4640>;
+               dma-names = "tx0", "tx1", "tx2", "tx3",
+                               "tx4", "tx5", "tx6", "tx7",
+                               "rx";
+
+               status = "disabled";
+
+               ethernet-ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       main_cpsw1_port1: port@1 {
+                               reg = <1>;
+                               label = "port1";
+                               phys = <&cpsw1_phy_gmii_sel 1>;
+                               ti,mac-only;
+                               status = "disabled";
+                       };
+               };
+
+               main_cpsw1_mdio: mdio@f00 {
+                       compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
+                       reg = <0x00 0xf00 0x00 0x100>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&k3_clks 62 0>;
+                       clock-names = "fck";
+                       bus_freq = <1000000>;
+                       status = "disabled";
+               };
+
+               cpts@3d000 {
+                       compatible = "ti,am65-cpts";
+                       reg = <0x00 0x3d000 0x00 0x400>;
+                       clocks = <&k3_clks 62 3>;
+                       clock-names = "cpts";
+                       interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "cpts";
+                       ti,cpts-ext-ts-inputs = <4>;
+                       ti,cpts-periodic-outputs = <2>;
+               };
+       };
+
        main_mcan0: can@2701000 {
                compatible = "bosch,m_can";
                reg = <0x00 0x02701000 0x00 0x200>,