arm64: dts: ti: k3-j721e-sk: Add support for multiple CAN instances

CAN instance 0 in the mcu domain is brought on the J721E-SK board
through header J1. Thus, add its respective transceiver 1 dt node to add
support for this CAN instance.

CAN instances 0, 5 and 9 in the main domain are brought on the J721E-SK
board through headers J5, J6 and J2 respectively. Thus, add their
respective transceivers 2, 3 and 4 dt nodes to add support for these CAN
instances.

Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Reviewed-by: Bhavya Kapoor <b-kapoor@ti.com>
Link: https://lore.kernel.org/r/20240430131512.1327283-1-b-padhi@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
index a027cf2facee16aabb6921a7d25822da8cde12fe..89fbfb21e5d3b22537e6ad697b1f2c30864b863e 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
@@ -211,6 +211,42 @@
                         <3300000 0x1>;
        };
 
+       transceiver1: can-phy1 {
+               compatible = "ti,tcan1042";
+               #phy-cells = <0>;
+               max-bitrate = <5000000>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
+               standby-gpios = <&wkup_gpio0 3 GPIO_ACTIVE_HIGH>;
+       };
+
+       transceiver2: can-phy2 {
+               compatible = "ti,tcan1042";
+               #phy-cells = <0>;
+               max-bitrate = <5000000>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&main_mcan0_gpio_pins_default>;
+               standby-gpios = <&main_gpio0 65 GPIO_ACTIVE_HIGH>;
+       };
+
+       transceiver3: can-phy3 {
+               compatible = "ti,tcan1042";
+               #phy-cells = <0>;
+               max-bitrate = <5000000>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&main_mcan5_gpio_pins_default>;
+               standby-gpios = <&main_gpio0 66 GPIO_ACTIVE_HIGH>;
+       };
+
+       transceiver4: can-phy4 {
+               compatible = "ti,tcan1042";
+               #phy-cells = <0>;
+               max-bitrate = <5000000>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&main_mcan9_gpio_pins_default>;
+               standby-gpios = <&main_gpio0 67 GPIO_ACTIVE_HIGH>;
+       };
+
        dp_pwr_3v3: fixedregulator-dp-prw {
                compatible = "regulator-fixed";
                regulator-name = "dp-pwr";
@@ -368,6 +404,45 @@
                >;
        };
 
+       main_mcan0_pins_default: main-mcan0-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
+                       J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
+               >;
+       };
+
+       main_mcan0_gpio_pins_default: main-mcan0-gpio-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x108, PIN_INPUT, 7) /* (AD27) PRG0_PRU1_GPO2.GPIO0_65 */
+               >;
+       };
+
+       main_mcan5_pins_default: main-mcan5-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x050, PIN_INPUT, 6) /* (AE21) PRG1_PRU0_GPO18.MCAN5_RX */
+                       J721E_IOPAD(0x04c, PIN_OUTPUT, 6) /* (AJ21) PRG1_PRU0_GPO17.MCAN5_TX */
+               >;
+       };
+
+       main_mcan5_gpio_pins_default: main-mcan5-gpio-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x10c, PIN_INPUT, 7) /* (AC25) PRG0_PRU1_GPO3.GPIO0_66 */
+               >;
+       };
+
+       main_mcan9_pins_default: main-mcan9-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x0d0, PIN_INPUT, 6) /* (AC27) PRG0_PRU0_GPO8.MCAN9_RX */
+                       J721E_IOPAD(0x0cc, PIN_OUTPUT, 6) /* (AC28) PRG0_PRU0_GPO7.MCAN9_TX */
+               >;
+       };
+
+       main_mcan9_gpio_pins_default: main-mcan9-gpio-default-pins {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x110, PIN_INPUT, 7) /* (AD29) PRG0_PRU1_GPO4.GPIO0_67 */
+               >;
+       };
+
        dp0_pins_default: dp0-default-pins {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
@@ -556,6 +631,19 @@
                >;
        };
 
+       mcu_mcan0_pins_default: mcu-mcan0-default-pins {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0x0ac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
+                       J721E_WKUP_IOPAD(0x0a8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
+               >;
+       };
+
+       mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0x0bc, PIN_INPUT, 7) /* (F27) WKUP_GPIO0_3 */
+               >;
+       };
+
        /* Reset for M.2 M Key slot on PCIe1  */
        mkey_reset_pins_default: mkey-reset-pns-default-pins {
                pinctrl-single,pins = <
@@ -1109,6 +1197,34 @@
        num-lanes = <2>;
 };
 
+&mcu_mcan0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcu_mcan0_pins_default>;
+       phys = <&transceiver1>;
+       status = "okay";
+};
+
+&main_mcan0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_mcan0_pins_default>;
+       phys = <&transceiver2>;
+       status = "okay";
+};
+
+&main_mcan5 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_mcan5_pins_default>;
+       phys = <&transceiver3>;
+       status = "okay";
+};
+
+&main_mcan9 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_mcan9_pins_default>;
+       phys = <&transceiver4>;
+       status = "okay";
+};
+
 &ufs_wrapper {
        status = "disabled";
 };