amd-xgbe: align CL37 AN sequence as per databook

[ Upstream commit 42fd432fe6d320323215ebdf4de4d0d7e56e6792 ]

Update the Clause 37 Auto-Negotiation implementation to properly align
with the PCS hardware specifications:
- Fix incorrect bit settings in Link Status and Link Duplex fields
- Implement missing sequence steps 2 and 7

These changes ensure CL37 auto-negotiation protocol follows the exact
sequence patterns as specified in the hardware databook.

Fixes: 1bf40ada6290 ("amd-xgbe: Add support for clause 37 auto-negotiation")
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Link: https://patch.msgid.link/20250630192636.3838291-1-Raju.Rangoju@amd.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-common.h b/drivers/net/ethernet/amd/xgbe/xgbe-common.h
index 533b8519ec352842f7293c5b4a6e606505ff0907..c5dc23906a78d0e9e9a32cf90c730b6a50e8d571 100644 (file)
--- a/drivers/net/ethernet/amd/xgbe/xgbe-common.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-common.h
@@ -1355,6 +1355,8 @@
 #define MDIO_VEND2_CTRL1_SS13          BIT(13)
 #endif
 
+#define XGBE_VEND2_MAC_AUTO_SW         BIT(9)
+
 /* MDIO mask values */
 #define XGBE_AN_CL73_INT_CMPLT         BIT(0)
 #define XGBE_AN_CL73_INC_LINK          BIT(1)

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c
index 0e552022e659a599a1c089db4db257e90cf377a3..3819b23c927d546ba959124bbb2d4857f2b38665 100644 (file)
--- a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c
@@ -363,6 +363,10 @@ static void xgbe_an37_set(struct xgbe_prv_data *pdata, bool enable,
                reg |= MDIO_VEND2_CTRL1_AN_RESTART;
 
        XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg);
+
+       reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_PCS_DIG_CTRL);
+       reg |= XGBE_VEND2_MAC_AUTO_SW;
+       XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_PCS_DIG_CTRL, reg);
 }
 
 static void xgbe_an37_restart(struct xgbe_prv_data *pdata)
@@ -991,6 +995,11 @@ static void xgbe_an37_init(struct xgbe_prv_data *pdata)
 
        netif_dbg(pdata, link, pdata->netdev, "CL37 AN (%s) initialized\n",
                  (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII");
+
+       reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
+       reg &= ~MDIO_AN_CTRL1_ENABLE;
+       XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
+
 }
 
 static void xgbe_an73_init(struct xgbe_prv_data *pdata)

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
index a27979ef7b1cc64376a62c905cf3bbc7f92c1625..536c8495d6afc1a47e957816875b63ebb2365bff 100644 (file)
--- a/drivers/net/ethernet/amd/xgbe/xgbe.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
@@ -292,11 +292,11 @@
 #define XGBE_LINK_TIMEOUT              5
 #define XGBE_KR_TRAINING_WAIT_ITER     50
 
-#define XGBE_SGMII_AN_LINK_STATUS      BIT(1)
+#define XGBE_SGMII_AN_LINK_DUPLEX      BIT(1)
 #define XGBE_SGMII_AN_LINK_SPEED       (BIT(2) | BIT(3))
 #define XGBE_SGMII_AN_LINK_SPEED_100   0x04
 #define XGBE_SGMII_AN_LINK_SPEED_1000  0x08
-#define XGBE_SGMII_AN_LINK_DUPLEX      BIT(4)
+#define XGBE_SGMII_AN_LINK_STATUS      BIT(4)
 
 /* ECC correctable error notification window (seconds) */
 #define XGBE_ECC_LIMIT                 60