drm/xe/vram: Convert register access to use xe_mmio

Stop using GT pointers for register access.  Note that MIRROR_FUSE3 is a
GT register and is accessed via gt->mmio, whereas GSMBASE is an sgunit
register so it is accessed via tile->mmio.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240910234719.3335472-58-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
index 5bcd59190353eab08190febcea5aa1f9c250bc5d..7e765b1499b15aacd1d70c5684baa9054d3fc812 100644 (file)
--- a/drivers/gpu/drm/xe/xe_vram.c
+++ b/drivers/gpu/drm/xe/xe_vram.c
@@ -169,7 +169,7 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
                u64 offset_hi, offset_lo;
                u32 nodes, num_enabled;
 
-               reg = xe_mmio_read32(gt, MIRROR_FUSE3);
+               reg = xe_mmio_read32(&gt->mmio, MIRROR_FUSE3);
                nodes = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, reg);
                num_enabled = hweight32(nodes); /* Number of enabled l3 nodes */
 
@@ -184,7 +184,8 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
                offset *= num_enabled; /* convert to SW view */
 
                /* We don't expect any holes */
-               xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(gt, GSMBASE) - ccs_size),
+               xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(&gt_to_tile(gt)->mmio, GSMBASE) -
+                                            ccs_size),
                              "Hole between CCS and GSM.\n");
        } else {
                reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
@@ -256,7 +257,7 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
        if (xe->info.has_flat_ccs) {
                offset = get_flat_ccs_offset(gt, *tile_size);
        } else {
-               offset = xe_mmio_read64_2x32(gt, GSMBASE);
+               offset = xe_mmio_read64_2x32(&tile->mmio, GSMBASE);
        }
 
        /* remove the tile offset so we have just the available size */