--- /dev/null
+From a7a53fbe96a86c27a6420adbdaf06842b66352eb Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 25 Oct 2024 15:56:28 +0800
+Subject: arm64: dts: mediatek: mt8183: Disable DSI display output by default
+
+From: Chen-Yu Tsai <wenst@chromium.org>
+
+[ Upstream commit 26f6e91fa29a58fdc76b47f94f8f6027944a490c ]
+
+Most SoC dtsi files have the display output interfaces disabled by
+default, and only enabled on boards that utilize them. The MT8183
+has it backwards: the display outputs are left enabled by default,
+and only disabled at the board level.
+
+Reverse the situation for the DSI output so that it follows the
+normal scheme. For ease of backporting the DPI output is handled
+in a separate patch.
+
+Fixes: 88ec840270e6 ("arm64: dts: mt8183: Add dsi node")
+Fixes: 19b6403f1e2a ("arm64: dts: mt8183: add mt8183 pumpkin board")
+Cc: stable@vger.kernel.org
+Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
+Reviewed-by: Fei Shao <fshao@chromium.org>
+Link: https://lore.kernel.org/r/20241025075630.3917458-2-wenst@chromium.org
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+index d1b6355148620..f3a1b96f1ee4d 100644
+--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+@@ -1828,6 +1828,7 @@ dsi0: dsi@14014000 {
+ resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
+ phys = <&mipi_tx0>;
+ phy-names = "dphy";
++ status = "disabled";
+ };
+
+ mutex: mutex@14016000 {
+--
+2.39.5
+
--- /dev/null
+From 491e2a0b4fe8b036ad4b4e0763321eada17fdf13 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 28 Jan 2025 17:22:46 -0800
+Subject: bpf: avoid holding freeze_mutex during mmap operation
+
+From: Andrii Nakryiko <andrii@kernel.org>
+
+[ Upstream commit bc27c52eea189e8f7492d40739b7746d67b65beb ]
+
+We use map->freeze_mutex to prevent races between map_freeze() and
+memory mapping BPF map contents with writable permissions. The way we
+naively do this means we'll hold freeze_mutex for entire duration of all
+the mm and VMA manipulations, which is completely unnecessary. This can
+potentially also lead to deadlocks, as reported by syzbot in [0].
+
+So, instead, hold freeze_mutex only during writeability checks, bump
+(proactively) "write active" count for the map, unlock the mutex and
+proceed with mmap logic. And only if something went wrong during mmap
+logic, then undo that "write active" counter increment.
+
+ [0] https://lore.kernel.org/bpf/678dcbc9.050a0220.303755.0066.GAE@google.com/
+
+Fixes: fc9702273e2e ("bpf: Add mmap() support for BPF_MAP_TYPE_ARRAY")
+Reported-by: syzbot+4dc041c686b7c816a71e@syzkaller.appspotmail.com
+Signed-off-by: Andrii Nakryiko <andrii@kernel.org>
+Link: https://lore.kernel.org/r/20250129012246.1515826-2-andrii@kernel.org
+Signed-off-by: Alexei Starovoitov <ast@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/bpf/syscall.c | 17 ++++++++++-------
+ 1 file changed, 10 insertions(+), 7 deletions(-)
+
+diff --git a/kernel/bpf/syscall.c b/kernel/bpf/syscall.c
+index 98d7558e2f2be..9f791b6b09edc 100644
+--- a/kernel/bpf/syscall.c
++++ b/kernel/bpf/syscall.c
+@@ -882,7 +882,7 @@ static const struct vm_operations_struct bpf_map_default_vmops = {
+ static int bpf_map_mmap(struct file *filp, struct vm_area_struct *vma)
+ {
+ struct bpf_map *map = filp->private_data;
+- int err;
++ int err = 0;
+
+ if (!map->ops->map_mmap || !IS_ERR_OR_NULL(map->record))
+ return -ENOTSUPP;
+@@ -906,7 +906,12 @@ static int bpf_map_mmap(struct file *filp, struct vm_area_struct *vma)
+ err = -EACCES;
+ goto out;
+ }
++ bpf_map_write_active_inc(map);
+ }
++out:
++ mutex_unlock(&map->freeze_mutex);
++ if (err)
++ return err;
+
+ /* set default open/close callbacks */
+ vma->vm_ops = &bpf_map_default_vmops;
+@@ -923,13 +928,11 @@ static int bpf_map_mmap(struct file *filp, struct vm_area_struct *vma)
+ vm_flags_clear(vma, VM_MAYWRITE);
+
+ err = map->ops->map_mmap(map, vma);
+- if (err)
+- goto out;
++ if (err) {
++ if (vma->vm_flags & VM_WRITE)
++ bpf_map_write_active_dec(map);
++ }
+
+- if (vma->vm_flags & VM_WRITE)
+- bpf_map_write_active_inc(map);
+-out:
+- mutex_unlock(&map->freeze_mutex);
+ return err;
+ }
+
+--
+2.39.5
+
--- /dev/null
+From f71318cfccb8c7ab2bea3369ee71e3adbf9e3dab Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 22 Jan 2025 18:09:15 +0800
+Subject: bpf: Disable non stream socket for strparser
+
+From: Jiayuan Chen <mrpre@163.com>
+
+[ Upstream commit 5459cce6bf49e72ee29be21865869c2ac42419f5 ]
+
+Currently, only TCP supports strparser, but sockmap doesn't intercept
+non-TCP connections to attach strparser. For example, with UDP, although
+the read/write handlers are replaced, strparser is not executed due to
+the lack of a read_sock operation.
+
+Furthermore, in udp_bpf_recvmsg(), it checks whether the psock has data,
+and if not, it falls back to the native UDP read interface, making
+UDP + strparser appear to read correctly. According to its commit history,
+this behavior is unexpected.
+
+Moreover, since UDP lacks the concept of streams, we intercept it directly.
+
+Fixes: 1fa1fe8ff161 ("bpf, sockmap: Test shutdown() correctly exits epoll and recv()=0")
+Signed-off-by: Jiayuan Chen <mrpre@163.com>
+Signed-off-by: Martin KaFai Lau <martin.lau@kernel.org>
+Acked-by: Jakub Sitnicki <jakub@cloudflare.com>
+Acked-by: John Fastabend <john.fastabend@gmail.com>
+Link: https://patch.msgid.link/20250122100917.49845-4-mrpre@163.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/core/sock_map.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/net/core/sock_map.c b/net/core/sock_map.c
+index dcc0f31a17a8d..3a53b6a0e76e2 100644
+--- a/net/core/sock_map.c
++++ b/net/core/sock_map.c
+@@ -300,7 +300,10 @@ static int sock_map_link(struct bpf_map *map, struct sock *sk)
+
+ write_lock_bh(&sk->sk_callback_lock);
+ if (stream_parser && stream_verdict && !psock->saved_data_ready) {
+- ret = sk_psock_init_strp(sk, psock);
++ if (sk_is_tcp(sk))
++ ret = sk_psock_init_strp(sk, psock);
++ else
++ ret = -EOPNOTSUPP;
+ if (ret) {
+ write_unlock_bh(&sk->sk_callback_lock);
+ sk_psock_put(sk, psock);
+--
+2.39.5
+
--- /dev/null
+From 3a421d7a48a3a7fc2b5b0867588f1d56bcfb6e82 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 21 Dec 2024 14:10:16 +0800
+Subject: bpf: Fix deadlock when freeing cgroup storage
+
+From: Abel Wu <wuyun.abel@bytedance.com>
+
+[ Upstream commit c78f4afbd962f43a3989f45f3ca04300252b19b5 ]
+
+The following commit
+bc235cdb423a ("bpf: Prevent deadlock from recursive bpf_task_storage_[get|delete]")
+first introduced deadlock prevention for fentry/fexit programs attaching
+on bpf_task_storage helpers. That commit also employed the logic in map
+free path in its v6 version.
+
+Later bpf_cgrp_storage was first introduced in
+c4bcfb38a95e ("bpf: Implement cgroup storage available to non-cgroup-attached bpf progs")
+which faces the same issue as bpf_task_storage, instead of its busy
+counter, NULL was passed to bpf_local_storage_map_free() which opened
+a window to cause deadlock:
+
+ <TASK>
+ (acquiring local_storage->lock)
+ _raw_spin_lock_irqsave+0x3d/0x50
+ bpf_local_storage_update+0xd1/0x460
+ bpf_cgrp_storage_get+0x109/0x130
+ bpf_prog_a4d4a370ba857314_cgrp_ptr+0x139/0x170
+ ? __bpf_prog_enter_recur+0x16/0x80
+ bpf_trampoline_6442485186+0x43/0xa4
+ cgroup_storage_ptr+0x9/0x20
+ (holding local_storage->lock)
+ bpf_selem_unlink_storage_nolock.constprop.0+0x135/0x160
+ bpf_selem_unlink_storage+0x6f/0x110
+ bpf_local_storage_map_free+0xa2/0x110
+ bpf_map_free_deferred+0x5b/0x90
+ process_one_work+0x17c/0x390
+ worker_thread+0x251/0x360
+ kthread+0xd2/0x100
+ ret_from_fork+0x34/0x50
+ ret_from_fork_asm+0x1a/0x30
+ </TASK>
+
+Progs:
+ - A: SEC("fentry/cgroup_storage_ptr")
+ - cgid (BPF_MAP_TYPE_HASH)
+ Record the id of the cgroup the current task belonging
+ to in this hash map, using the address of the cgroup
+ as the map key.
+ - cgrpa (BPF_MAP_TYPE_CGRP_STORAGE)
+ If current task is a kworker, lookup the above hash
+ map using function parameter @owner as the key to get
+ its corresponding cgroup id which is then used to get
+ a trusted pointer to the cgroup through
+ bpf_cgroup_from_id(). This trusted pointer can then
+ be passed to bpf_cgrp_storage_get() to finally trigger
+ the deadlock issue.
+ - B: SEC("tp_btf/sys_enter")
+ - cgrpb (BPF_MAP_TYPE_CGRP_STORAGE)
+ The only purpose of this prog is to fill Prog A's
+ hash map by calling bpf_cgrp_storage_get() for as
+ many userspace tasks as possible.
+
+Steps to reproduce:
+ - Run A;
+ - while (true) { Run B; Destroy B; }
+
+Fix this issue by passing its busy counter to the free procedure so
+it can be properly incremented before storage/smap locking.
+
+Fixes: c4bcfb38a95e ("bpf: Implement cgroup storage available to non-cgroup-attached bpf progs")
+Signed-off-by: Abel Wu <wuyun.abel@bytedance.com>
+Acked-by: Martin KaFai Lau <martin.lau@kernel.org>
+Link: https://lore.kernel.org/r/20241221061018.37717-1-wuyun.abel@bytedance.com
+Signed-off-by: Alexei Starovoitov <ast@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/bpf/bpf_cgrp_storage.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/kernel/bpf/bpf_cgrp_storage.c b/kernel/bpf/bpf_cgrp_storage.c
+index d44fe8dd97329..ee1c7b77096e7 100644
+--- a/kernel/bpf/bpf_cgrp_storage.c
++++ b/kernel/bpf/bpf_cgrp_storage.c
+@@ -154,7 +154,7 @@ static struct bpf_map *cgroup_storage_map_alloc(union bpf_attr *attr)
+
+ static void cgroup_storage_map_free(struct bpf_map *map)
+ {
+- bpf_local_storage_map_free(map, &cgroup_cache, NULL);
++ bpf_local_storage_map_free(map, &cgroup_cache, &bpf_cgrp_storage_busy);
+ }
+
+ /* *gfp_flags* is a hidden argument provided by the verifier */
+--
+2.39.5
+
--- /dev/null
+From 6ed68d1b7972ac3e24a87df0e4061bd972113fff Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 22 Jan 2025 18:09:14 +0800
+Subject: bpf: Fix wrong copied_seq calculation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Jiayuan Chen <mrpre@163.com>
+
+[ Upstream commit 36b62df5683c315ba58c950f1a9c771c796c30ec ]
+
+'sk->copied_seq' was updated in the tcp_eat_skb() function when the action
+of a BPF program was SK_REDIRECT. For other actions, like SK_PASS, the
+update logic for 'sk->copied_seq' was moved to tcp_bpf_recvmsg_parser()
+to ensure the accuracy of the 'fionread' feature.
+
+It works for a single stream_verdict scenario, as it also modified
+sk_data_ready->sk_psock_verdict_data_ready->tcp_read_skb
+to remove updating 'sk->copied_seq'.
+
+However, for programs where both stream_parser and stream_verdict are
+active (strparser purpose), tcp_read_sock() was used instead of
+tcp_read_skb() (sk_data_ready->strp_data_ready->tcp_read_sock).
+tcp_read_sock() now still updates 'sk->copied_seq', leading to duplicate
+updates.
+
+In summary, for strparser + SK_PASS, copied_seq is redundantly calculated
+in both tcp_read_sock() and tcp_bpf_recvmsg_parser().
+
+The issue causes incorrect copied_seq calculations, which prevent
+correct data reads from the recv() interface in user-land.
+
+We do not want to add new proto_ops to implement a new version of
+tcp_read_sock, as this would introduce code complexity [1].
+
+We could have added noack and copied_seq to desc, and then called
+ops->read_sock. However, unfortunately, other modules didn’t fully
+initialize desc to zero. So, for now, we are directly calling
+tcp_read_sock_noack() in tcp_bpf.c.
+
+[1]: https://lore.kernel.org/bpf/20241218053408.437295-1-mrpre@163.com
+
+Fixes: e5c6de5fa025 ("bpf, sockmap: Incorrectly handling copied_seq")
+Suggested-by: Jakub Sitnicki <jakub@cloudflare.com>
+Signed-off-by: Jiayuan Chen <mrpre@163.com>
+Signed-off-by: Martin KaFai Lau <martin.lau@kernel.org>
+Reviewed-by: Jakub Sitnicki <jakub@cloudflare.com>
+Acked-by: John Fastabend <john.fastabend@gmail.com>
+Link: https://patch.msgid.link/20250122100917.49845-3-mrpre@163.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/skmsg.h | 2 ++
+ include/net/tcp.h | 8 ++++++++
+ net/core/skmsg.c | 7 +++++++
+ net/ipv4/tcp.c | 29 ++++++++++++++++++++++++-----
+ net/ipv4/tcp_bpf.c | 36 ++++++++++++++++++++++++++++++++++++
+ 5 files changed, 77 insertions(+), 5 deletions(-)
+
+diff --git a/include/linux/skmsg.h b/include/linux/skmsg.h
+index 6ccfd9236387c..32bbebf5b71e3 100644
+--- a/include/linux/skmsg.h
++++ b/include/linux/skmsg.h
+@@ -87,6 +87,8 @@ struct sk_psock {
+ struct sk_psock_progs progs;
+ #if IS_ENABLED(CONFIG_BPF_STREAM_PARSER)
+ struct strparser strp;
++ u32 copied_seq;
++ u32 ingress_bytes;
+ #endif
+ struct sk_buff_head ingress_skb;
+ struct list_head ingress_msg;
+diff --git a/include/net/tcp.h b/include/net/tcp.h
+index 78c755414fa87..a6def0aab3ed3 100644
+--- a/include/net/tcp.h
++++ b/include/net/tcp.h
+@@ -690,6 +690,9 @@ void tcp_get_info(struct sock *, struct tcp_info *);
+ /* Read 'sendfile()'-style from a TCP socket */
+ int tcp_read_sock(struct sock *sk, read_descriptor_t *desc,
+ sk_read_actor_t recv_actor);
++int tcp_read_sock_noack(struct sock *sk, read_descriptor_t *desc,
++ sk_read_actor_t recv_actor, bool noack,
++ u32 *copied_seq);
+ int tcp_read_skb(struct sock *sk, skb_read_actor_t recv_actor);
+ struct sk_buff *tcp_recv_skb(struct sock *sk, u32 seq, u32 *off);
+ void tcp_read_done(struct sock *sk, size_t len);
+@@ -2404,6 +2407,11 @@ struct sk_psock;
+ #ifdef CONFIG_BPF_SYSCALL
+ int tcp_bpf_update_proto(struct sock *sk, struct sk_psock *psock, bool restore);
+ void tcp_bpf_clone(const struct sock *sk, struct sock *newsk);
++#ifdef CONFIG_BPF_STREAM_PARSER
++struct strparser;
++int tcp_bpf_strp_read_sock(struct strparser *strp, read_descriptor_t *desc,
++ sk_read_actor_t recv_actor);
++#endif /* CONFIG_BPF_STREAM_PARSER */
+ #endif /* CONFIG_BPF_SYSCALL */
+
+ #ifdef CONFIG_INET
+diff --git a/net/core/skmsg.c b/net/core/skmsg.c
+index 902098e221b39..b9b941c487c8a 100644
+--- a/net/core/skmsg.c
++++ b/net/core/skmsg.c
+@@ -548,6 +548,9 @@ static int sk_psock_skb_ingress_enqueue(struct sk_buff *skb,
+ return num_sge;
+ }
+
++#if IS_ENABLED(CONFIG_BPF_STREAM_PARSER)
++ psock->ingress_bytes += len;
++#endif
+ copied = len;
+ msg->sg.start = 0;
+ msg->sg.size = copied;
+@@ -1143,6 +1146,10 @@ int sk_psock_init_strp(struct sock *sk, struct sk_psock *psock)
+ if (!ret)
+ sk_psock_set_state(psock, SK_PSOCK_RX_STRP_ENABLED);
+
++ if (sk_is_tcp(sk)) {
++ psock->strp.cb.read_sock = tcp_bpf_strp_read_sock;
++ psock->copied_seq = tcp_sk(sk)->copied_seq;
++ }
+ return ret;
+ }
+
+diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c
+index 5e6615f69f175..7ad82be40f348 100644
+--- a/net/ipv4/tcp.c
++++ b/net/ipv4/tcp.c
+@@ -1553,12 +1553,13 @@ EXPORT_SYMBOL(tcp_recv_skb);
+ * or for 'peeking' the socket using this routine
+ * (although both would be easy to implement).
+ */
+-int tcp_read_sock(struct sock *sk, read_descriptor_t *desc,
+- sk_read_actor_t recv_actor)
++static int __tcp_read_sock(struct sock *sk, read_descriptor_t *desc,
++ sk_read_actor_t recv_actor, bool noack,
++ u32 *copied_seq)
+ {
+ struct sk_buff *skb;
+ struct tcp_sock *tp = tcp_sk(sk);
+- u32 seq = tp->copied_seq;
++ u32 seq = *copied_seq;
+ u32 offset;
+ int copied = 0;
+
+@@ -1612,9 +1613,12 @@ int tcp_read_sock(struct sock *sk, read_descriptor_t *desc,
+ tcp_eat_recv_skb(sk, skb);
+ if (!desc->count)
+ break;
+- WRITE_ONCE(tp->copied_seq, seq);
++ WRITE_ONCE(*copied_seq, seq);
+ }
+- WRITE_ONCE(tp->copied_seq, seq);
++ WRITE_ONCE(*copied_seq, seq);
++
++ if (noack)
++ goto out;
+
+ tcp_rcv_space_adjust(sk);
+
+@@ -1623,10 +1627,25 @@ int tcp_read_sock(struct sock *sk, read_descriptor_t *desc,
+ tcp_recv_skb(sk, seq, &offset);
+ tcp_cleanup_rbuf(sk, copied);
+ }
++out:
+ return copied;
+ }
++
++int tcp_read_sock(struct sock *sk, read_descriptor_t *desc,
++ sk_read_actor_t recv_actor)
++{
++ return __tcp_read_sock(sk, desc, recv_actor, false,
++ &tcp_sk(sk)->copied_seq);
++}
+ EXPORT_SYMBOL(tcp_read_sock);
+
++int tcp_read_sock_noack(struct sock *sk, read_descriptor_t *desc,
++ sk_read_actor_t recv_actor, bool noack,
++ u32 *copied_seq)
++{
++ return __tcp_read_sock(sk, desc, recv_actor, noack, copied_seq);
++}
++
+ int tcp_read_skb(struct sock *sk, skb_read_actor_t recv_actor)
+ {
+ struct sk_buff *skb;
+diff --git a/net/ipv4/tcp_bpf.c b/net/ipv4/tcp_bpf.c
+index f882054fae5ee..5312237e80409 100644
+--- a/net/ipv4/tcp_bpf.c
++++ b/net/ipv4/tcp_bpf.c
+@@ -646,6 +646,42 @@ static int tcp_bpf_assert_proto_ops(struct proto *ops)
+ ops->sendmsg == tcp_sendmsg ? 0 : -ENOTSUPP;
+ }
+
++#if IS_ENABLED(CONFIG_BPF_STREAM_PARSER)
++int tcp_bpf_strp_read_sock(struct strparser *strp, read_descriptor_t *desc,
++ sk_read_actor_t recv_actor)
++{
++ struct sock *sk = strp->sk;
++ struct sk_psock *psock;
++ struct tcp_sock *tp;
++ int copied = 0;
++
++ tp = tcp_sk(sk);
++ rcu_read_lock();
++ psock = sk_psock(sk);
++ if (WARN_ON_ONCE(!psock)) {
++ desc->error = -EINVAL;
++ goto out;
++ }
++
++ psock->ingress_bytes = 0;
++ copied = tcp_read_sock_noack(sk, desc, recv_actor, true,
++ &psock->copied_seq);
++ if (copied < 0)
++ goto out;
++ /* recv_actor may redirect skb to another socket (SK_REDIRECT) or
++ * just put skb into ingress queue of current socket (SK_PASS).
++ * For SK_REDIRECT, we need to ack the frame immediately but for
++ * SK_PASS, we want to delay the ack until tcp_bpf_recvmsg_parser().
++ */
++ tp->copied_seq = psock->copied_seq - psock->ingress_bytes;
++ tcp_rcv_space_adjust(sk);
++ __tcp_cleanup_rbuf(sk, copied - psock->ingress_bytes);
++out:
++ rcu_read_unlock();
++ return copied;
++}
++#endif /* CONFIG_BPF_STREAM_PARSER */
++
+ int tcp_bpf_update_proto(struct sock *sk, struct sk_psock *psock, bool restore)
+ {
+ int family = sk->sk_family == AF_INET6 ? TCP_BPF_IPV6 : TCP_BPF_IPV4;
+--
+2.39.5
+
--- /dev/null
+From f5f0afe9e33290826824330918e017a1e1c89001 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 9 Feb 2025 23:22:35 -0800
+Subject: bpf: skip non exist keys in generic_map_lookup_batch
+
+From: Yan Zhai <yan@cloudflare.com>
+
+[ Upstream commit 5644c6b50ffee0a56c1e01430a8c88e34decb120 ]
+
+The generic_map_lookup_batch currently returns EINTR if it fails with
+ENOENT and retries several times on bpf_map_copy_value. The next batch
+would start from the same location, presuming it's a transient issue.
+This is incorrect if a map can actually have "holes", i.e.
+"get_next_key" can return a key that does not point to a valid value. At
+least the array of maps type may contain such holes legitly. Right now
+these holes show up, generic batch lookup cannot proceed any more. It
+will always fail with EINTR errors.
+
+Rather, do not retry in generic_map_lookup_batch. If it finds a non
+existing element, skip to the next key. This simple solution comes with
+a price that transient errors may not be recovered, and the iteration
+might cycle back to the first key under parallel deletion. For example,
+Hou Tao <houtao@huaweicloud.com> pointed out a following scenario:
+
+For LPM trie map:
+(1) ->map_get_next_key(map, prev_key, key) returns a valid key
+
+(2) bpf_map_copy_value() return -ENOMENT
+It means the key must be deleted concurrently.
+
+(3) goto next_key
+It swaps the prev_key and key
+
+(4) ->map_get_next_key(map, prev_key, key) again
+prev_key points to a non-existing key, for LPM trie it will treat just
+like prev_key=NULL case, the returned key will be duplicated.
+
+With the retry logic, the iteration can continue to the key next to the
+deleted one. But if we directly skip to the next key, the iteration loop
+would restart from the first key for the lpm_trie type.
+
+However, not all races may be recovered. For example, if current key is
+deleted after instead of before bpf_map_copy_value, or if the prev_key
+also gets deleted, then the loop will still restart from the first key
+for lpm_tire anyway. For generic lookup it might be better to stay
+simple, i.e. just skip to the next key. To guarantee that the output
+keys are not duplicated, it is better to implement map type specific
+batch operations, which can properly lock the trie and synchronize with
+concurrent mutators.
+
+Fixes: cb4d03ab499d ("bpf: Add generic support for lookup batch op")
+Closes: https://lore.kernel.org/bpf/Z6JXtA1M5jAZx8xD@debian.debian/
+Signed-off-by: Yan Zhai <yan@cloudflare.com>
+Acked-by: Hou Tao <houtao1@huawei.com>
+Link: https://lore.kernel.org/r/85618439eea75930630685c467ccefeac0942e2b.1739171594.git.yan@cloudflare.com
+Signed-off-by: Alexei Starovoitov <ast@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/bpf/syscall.c | 18 +++++-------------
+ 1 file changed, 5 insertions(+), 13 deletions(-)
+
+diff --git a/kernel/bpf/syscall.c b/kernel/bpf/syscall.c
+index 9f791b6b09edc..f089a61630111 100644
+--- a/kernel/bpf/syscall.c
++++ b/kernel/bpf/syscall.c
+@@ -1807,8 +1807,6 @@ int generic_map_update_batch(struct bpf_map *map, struct file *map_file,
+ return err;
+ }
+
+-#define MAP_LOOKUP_RETRIES 3
+-
+ int generic_map_lookup_batch(struct bpf_map *map,
+ const union bpf_attr *attr,
+ union bpf_attr __user *uattr)
+@@ -1818,8 +1816,8 @@ int generic_map_lookup_batch(struct bpf_map *map,
+ void __user *values = u64_to_user_ptr(attr->batch.values);
+ void __user *keys = u64_to_user_ptr(attr->batch.keys);
+ void *buf, *buf_prevkey, *prev_key, *key, *value;
+- int err, retry = MAP_LOOKUP_RETRIES;
+ u32 value_size, cp, max_count;
++ int err;
+
+ if (attr->batch.elem_flags & ~BPF_F_LOCK)
+ return -EINVAL;
+@@ -1865,14 +1863,8 @@ int generic_map_lookup_batch(struct bpf_map *map,
+ err = bpf_map_copy_value(map, key, value,
+ attr->batch.elem_flags);
+
+- if (err == -ENOENT) {
+- if (retry) {
+- retry--;
+- continue;
+- }
+- err = -EINTR;
+- break;
+- }
++ if (err == -ENOENT)
++ goto next_key;
+
+ if (err)
+ goto free_buf;
+@@ -1887,12 +1879,12 @@ int generic_map_lookup_batch(struct bpf_map *map,
+ goto free_buf;
+ }
+
++ cp++;
++next_key:
+ if (!prev_key)
+ prev_key = buf_prevkey;
+
+ swap(prev_key, key);
+- retry = MAP_LOOKUP_RETRIES;
+- cp++;
+ cond_resched();
+ }
+
+--
+2.39.5
+
--- /dev/null
+From 2d3c9628945d3ca74a456fcd9d0c22e2694d035e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 22 Jan 2025 00:06:42 +0900
+Subject: bpf, test_run: Fix use-after-free issue in eth_skb_pkt_type()
+
+From: Shigeru Yoshida <syoshida@redhat.com>
+
+[ Upstream commit 6b3d638ca897e099fa99bd6d02189d3176f80a47 ]
+
+KMSAN reported a use-after-free issue in eth_skb_pkt_type()[1]. The
+cause of the issue was that eth_skb_pkt_type() accessed skb's data
+that didn't contain an Ethernet header. This occurs when
+bpf_prog_test_run_xdp() passes an invalid value as the user_data
+argument to bpf_test_init().
+
+Fix this by returning an error when user_data is less than ETH_HLEN in
+bpf_test_init(). Additionally, remove the check for "if (user_size >
+size)" as it is unnecessary.
+
+[1]
+BUG: KMSAN: use-after-free in eth_skb_pkt_type include/linux/etherdevice.h:627 [inline]
+BUG: KMSAN: use-after-free in eth_type_trans+0x4ee/0x980 net/ethernet/eth.c:165
+ eth_skb_pkt_type include/linux/etherdevice.h:627 [inline]
+ eth_type_trans+0x4ee/0x980 net/ethernet/eth.c:165
+ __xdp_build_skb_from_frame+0x5a8/0xa50 net/core/xdp.c:635
+ xdp_recv_frames net/bpf/test_run.c:272 [inline]
+ xdp_test_run_batch net/bpf/test_run.c:361 [inline]
+ bpf_test_run_xdp_live+0x2954/0x3330 net/bpf/test_run.c:390
+ bpf_prog_test_run_xdp+0x148e/0x1b10 net/bpf/test_run.c:1318
+ bpf_prog_test_run+0x5b7/0xa30 kernel/bpf/syscall.c:4371
+ __sys_bpf+0x6a6/0xe20 kernel/bpf/syscall.c:5777
+ __do_sys_bpf kernel/bpf/syscall.c:5866 [inline]
+ __se_sys_bpf kernel/bpf/syscall.c:5864 [inline]
+ __x64_sys_bpf+0xa4/0xf0 kernel/bpf/syscall.c:5864
+ x64_sys_call+0x2ea0/0x3d90 arch/x86/include/generated/asm/syscalls_64.h:322
+ do_syscall_x64 arch/x86/entry/common.c:52 [inline]
+ do_syscall_64+0xd9/0x1d0 arch/x86/entry/common.c:83
+ entry_SYSCALL_64_after_hwframe+0x77/0x7f
+
+Uninit was created at:
+ free_pages_prepare mm/page_alloc.c:1056 [inline]
+ free_unref_page+0x156/0x1320 mm/page_alloc.c:2657
+ __free_pages+0xa3/0x1b0 mm/page_alloc.c:4838
+ bpf_ringbuf_free kernel/bpf/ringbuf.c:226 [inline]
+ ringbuf_map_free+0xff/0x1e0 kernel/bpf/ringbuf.c:235
+ bpf_map_free kernel/bpf/syscall.c:838 [inline]
+ bpf_map_free_deferred+0x17c/0x310 kernel/bpf/syscall.c:862
+ process_one_work kernel/workqueue.c:3229 [inline]
+ process_scheduled_works+0xa2b/0x1b60 kernel/workqueue.c:3310
+ worker_thread+0xedf/0x1550 kernel/workqueue.c:3391
+ kthread+0x535/0x6b0 kernel/kthread.c:389
+ ret_from_fork+0x6e/0x90 arch/x86/kernel/process.c:147
+ ret_from_fork_asm+0x1a/0x30 arch/x86/entry/entry_64.S:244
+
+CPU: 1 UID: 0 PID: 17276 Comm: syz.1.16450 Not tainted 6.12.0-05490-g9bb88c659673 #8
+Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.16.3-3.fc41 04/01/2014
+
+Fixes: be3d72a2896c ("bpf: move user_size out of bpf_test_init")
+Reported-by: syzkaller <syzkaller@googlegroups.com>
+Suggested-by: Martin KaFai Lau <martin.lau@linux.dev>
+Signed-off-by: Shigeru Yoshida <syoshida@redhat.com>
+Signed-off-by: Martin KaFai Lau <martin.lau@kernel.org>
+Acked-by: Stanislav Fomichev <sdf@fomichev.me>
+Acked-by: Daniel Borkmann <daniel@iogearbox.net>
+Link: https://patch.msgid.link/20250121150643.671650-1-syoshida@redhat.com
+Signed-off-by: Alexei Starovoitov <ast@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/bpf/test_run.c | 5 +----
+ 1 file changed, 1 insertion(+), 4 deletions(-)
+
+diff --git a/net/bpf/test_run.c b/net/bpf/test_run.c
+index 905de361f8623..73fb9db55798c 100644
+--- a/net/bpf/test_run.c
++++ b/net/bpf/test_run.c
+@@ -630,12 +630,9 @@ static void *bpf_test_init(const union bpf_attr *kattr, u32 user_size,
+ void __user *data_in = u64_to_user_ptr(kattr->test.data_in);
+ void *data;
+
+- if (size < ETH_HLEN || size > PAGE_SIZE - headroom - tailroom)
++ if (user_size < ETH_HLEN || user_size > PAGE_SIZE - headroom - tailroom)
+ return ERR_PTR(-EINVAL);
+
+- if (user_size > size)
+- return ERR_PTR(-EMSGSIZE);
+-
+ size = SKB_DATA_ALIGN(size);
+ data = kzalloc(size + headroom + tailroom, GFP_USER);
+ if (!data)
+--
+2.39.5
+
--- /dev/null
+From 6abd2942dd466a7e7a22f6f2da19dc5ba7cb37a7 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 28 Jan 2025 17:22:45 -0800
+Subject: bpf: unify VM_WRITE vs VM_MAYWRITE use in BPF map mmaping logic
+
+From: Andrii Nakryiko <andrii@kernel.org>
+
+[ Upstream commit 98671a0fd1f14e4a518ee06b19037c20014900eb ]
+
+For all BPF maps we ensure that VM_MAYWRITE is cleared when
+memory-mapping BPF map contents as initially read-only VMA. This is
+because in some cases BPF verifier relies on the underlying data to not
+be modified afterwards by user space, so once something is mapped
+read-only, it shouldn't be re-mmap'ed as read-write.
+
+As such, it's not necessary to check VM_MAYWRITE in bpf_map_mmap() and
+map->ops->map_mmap() callbacks: VM_WRITE should be consistently set for
+read-write mappings, and if VM_WRITE is not set, there is no way for
+user space to upgrade read-only mapping to read-write one.
+
+This patch cleans up this VM_WRITE vs VM_MAYWRITE handling within
+bpf_map_mmap(), which is an entry point for any BPF map mmap()-ing
+logic. We also drop unnecessary sanitization of VM_MAYWRITE in BPF
+ringbuf's map_mmap() callback implementation, as it is already performed
+by common code in bpf_map_mmap().
+
+Note, though, that in bpf_map_mmap_{open,close}() callbacks we can't
+drop VM_MAYWRITE use, because it's possible (and is outside of
+subsystem's control) to have initially read-write memory mapping, which
+is subsequently dropped to read-only by user space through mprotect().
+In such case, from BPF verifier POV it's read-write data throughout the
+lifetime of BPF map, and is counted as "active writer".
+
+But its VMAs will start out as VM_WRITE|VM_MAYWRITE, then mprotect() can
+change it to just VM_MAYWRITE (and no VM_WRITE), so when its finally
+munmap()'ed and bpf_map_mmap_close() is called, vm_flags will be just
+VM_MAYWRITE, but we still need to decrement active writer count with
+bpf_map_write_active_dec() as it's still considered to be a read-write
+mapping by the rest of BPF subsystem.
+
+Similar reasoning applies to bpf_map_mmap_open(), which is called
+whenever mmap(), munmap(), and/or mprotect() forces mm subsystem to
+split original VMA into multiple discontiguous VMAs.
+
+Memory-mapping handling is a bit tricky, yes.
+
+Cc: Jann Horn <jannh@google.com>
+Cc: Suren Baghdasaryan <surenb@google.com>
+Cc: Shakeel Butt <shakeel.butt@linux.dev>
+Signed-off-by: Andrii Nakryiko <andrii@kernel.org>
+Link: https://lore.kernel.org/r/20250129012246.1515826-1-andrii@kernel.org
+Signed-off-by: Alexei Starovoitov <ast@kernel.org>
+Stable-dep-of: bc27c52eea18 ("bpf: avoid holding freeze_mutex during mmap operation")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/bpf/ringbuf.c | 4 ----
+ kernel/bpf/syscall.c | 10 ++++++++--
+ 2 files changed, 8 insertions(+), 6 deletions(-)
+
+diff --git a/kernel/bpf/ringbuf.c b/kernel/bpf/ringbuf.c
+index 246559c3e93d0..528f4d6342262 100644
+--- a/kernel/bpf/ringbuf.c
++++ b/kernel/bpf/ringbuf.c
+@@ -268,8 +268,6 @@ static int ringbuf_map_mmap_kern(struct bpf_map *map, struct vm_area_struct *vma
+ /* allow writable mapping for the consumer_pos only */
+ if (vma->vm_pgoff != 0 || vma->vm_end - vma->vm_start != PAGE_SIZE)
+ return -EPERM;
+- } else {
+- vm_flags_clear(vma, VM_MAYWRITE);
+ }
+ /* remap_vmalloc_range() checks size and offset constraints */
+ return remap_vmalloc_range(vma, rb_map->rb,
+@@ -289,8 +287,6 @@ static int ringbuf_map_mmap_user(struct bpf_map *map, struct vm_area_struct *vma
+ * position, and the ring buffer data itself.
+ */
+ return -EPERM;
+- } else {
+- vm_flags_clear(vma, VM_MAYWRITE);
+ }
+ /* remap_vmalloc_range() checks size and offset constraints */
+ return remap_vmalloc_range(vma, rb_map->rb, vma->vm_pgoff + RINGBUF_PGOFF);
+diff --git a/kernel/bpf/syscall.c b/kernel/bpf/syscall.c
+index ba38c08a9a059..98d7558e2f2be 100644
+--- a/kernel/bpf/syscall.c
++++ b/kernel/bpf/syscall.c
+@@ -912,15 +912,21 @@ static int bpf_map_mmap(struct file *filp, struct vm_area_struct *vma)
+ vma->vm_ops = &bpf_map_default_vmops;
+ vma->vm_private_data = map;
+ vm_flags_clear(vma, VM_MAYEXEC);
++ /* If mapping is read-only, then disallow potentially re-mapping with
++ * PROT_WRITE by dropping VM_MAYWRITE flag. This VM_MAYWRITE clearing
++ * means that as far as BPF map's memory-mapped VMAs are concerned,
++ * VM_WRITE and VM_MAYWRITE and equivalent, if one of them is set,
++ * both should be set, so we can forget about VM_MAYWRITE and always
++ * check just VM_WRITE
++ */
+ if (!(vma->vm_flags & VM_WRITE))
+- /* disallow re-mapping with PROT_WRITE */
+ vm_flags_clear(vma, VM_MAYWRITE);
+
+ err = map->ops->map_mmap(map, vma);
+ if (err)
+ goto out;
+
+- if (vma->vm_flags & VM_MAYWRITE)
++ if (vma->vm_flags & VM_WRITE)
+ bpf_map_write_active_inc(map);
+ out:
+ mutex_unlock(&map->freeze_mutex);
+--
+2.39.5
+
--- /dev/null
+From 3a197c505b29dc93529d7249ac6f661527ade17c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 13 Jan 2025 07:48:41 -0800
+Subject: drm/msm: Avoid rounding up to one jiffy
+
+From: Rob Clark <robdclark@chromium.org>
+
+[ Upstream commit 669c285620231786fffe9d87ab432e08a6ed922b ]
+
+If userspace is trying to achieve a timeout of zero, let 'em have it.
+Only round up if the timeout is greater than zero.
+
+Fixes: 4969bccd5f4e ("drm/msm: Avoid rounding down to zero jiffies")
+Signed-off-by: Rob Clark <robdclark@chromium.org>
+Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
+Patchwork: https://patchwork.freedesktop.org/patch/632264/
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/msm_drv.h | 11 ++++-------
+ 1 file changed, 4 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
+index 48e1a8c6942c9..223bf904235a8 100644
+--- a/drivers/gpu/drm/msm/msm_drv.h
++++ b/drivers/gpu/drm/msm/msm_drv.h
+@@ -533,15 +533,12 @@ static inline int align_pitch(int width, int bpp)
+ static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
+ {
+ ktime_t now = ktime_get();
+- s64 remaining_jiffies;
+
+- if (ktime_compare(*timeout, now) < 0) {
+- remaining_jiffies = 0;
+- } else {
+- ktime_t rem = ktime_sub(*timeout, now);
+- remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
+- }
++ if (ktime_compare(*timeout, now) <= 0)
++ return 0;
+
++ ktime_t rem = ktime_sub(*timeout, now);
++ s64 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
+ return clamp(remaining_jiffies, 1LL, (s64)INT_MAX);
+ }
+
+--
+2.39.5
+
--- /dev/null
+From 8a0a45ce4f024478195c1d2e93fca2e785189652 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 11 Feb 2025 00:19:32 +0100
+Subject: drm/msm/dpu: Don't leak bits_per_component into random DSC_ENC fields
+
+From: Marijn Suijten <marijn.suijten@somainline.org>
+
+[ Upstream commit 144429831f447223253a0e4376489f84ff37d1a7 ]
+
+What used to be the input_10_bits boolean - feeding into the lowest
+bit of DSC_ENC - on MSM downstream turned into an accidental OR with
+the full bits_per_component number when it was ported to the upstream
+kernel.
+
+On typical bpc=8 setups we don't notice this because line_buf_depth is
+always an odd value (it contains bpc+1) and will also set the 4th bit
+after left-shifting by 3 (hence this |= bits_per_component is a no-op).
+
+Now that guards are being removed to allow more bits_per_component
+values besides 8 (possible since commit 49fd30a7153b ("drm/msm/dsi: use
+DRM DSC helpers for DSC setup")), a bpc of 10 will instead clash with
+the 5th bit which is convert_rgb. This is "fortunately" also always set
+to true by MSM's dsi_populate_dsc_params() already, but once a bpc of 12
+starts being used it'll write into simple_422 which is normally false.
+
+To solve all these overlaps, simply replicate downstream code and only
+set this lowest bit if bits_per_component is equal to 10. It is unclear
+why DSC requires this only for bpc=10 but not bpc=12, and also notice
+that this lowest bit wasn't set previously despite having a panel and
+patch on the list using it without any mentioned issues.
+
+Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC")
+Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
+Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Patchwork: https://patchwork.freedesktop.org/patch/636311/
+Link: https://lore.kernel.org/r/20250211-dsc-10-bit-v1-1-1c85a9430d9a@somainline.org
+Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
+index 509dbaa51d878..12e79a71ae4cd 100644
+--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
+@@ -50,6 +50,7 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
+ u32 slice_last_group_size;
+ u32 det_thresh_flatness;
+ bool is_cmd_mode = !(mode & DSC_MODE_VIDEO);
++ bool input_10_bits = dsc->bits_per_component == 10;
+
+ DPU_REG_WRITE(c, DSC_COMMON_MODE, mode);
+
+@@ -66,7 +67,7 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
+ data |= (dsc->line_buf_depth << 3);
+ data |= (dsc->simple_422 << 2);
+ data |= (dsc->convert_rgb << 1);
+- data |= dsc->bits_per_component;
++ data |= input_10_bits;
+
+ DPU_REG_WRITE(c, DSC_ENC, data);
+
+--
+2.39.5
+
--- /dev/null
+From 0725c195726daf14d2b53c3afe904ff4a8f802f8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 13 Jun 2024 20:05:11 +0300
+Subject: drm/msm/dpu: rename dpu_hw_setup_vsync_source functions
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 8ba16ca8cc96dfe2e2f09146fd386acc3390931c ]
+
+Rename dpu_hw_setup_vsync_source functions to make the names match the
+implementation: on DPU 5.x the TOP only contains timer setup, while 3.x
+and 4.x used MDP_VSYNC_SEL register to select TE source.
+
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
+Patchwork: https://patchwork.freedesktop.org/patch/598745/
+Link: https://lore.kernel.org/r/20240613-dpu-handle-te-signal-v2-8-67a0116b5366@linaro.org
+Stable-dep-of: 2f69e5458447 ("drm/msm/dpu: skip watchdog timer programming through TOP on >= SM8450")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+index cff48763ce25e..fb0f5df70421f 100644
+--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+@@ -126,8 +126,8 @@ static void dpu_hw_get_danger_status(struct dpu_hw_mdp *mdp,
+ status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x3;
+ }
+
+-static void dpu_hw_setup_vsync_source(struct dpu_hw_mdp *mdp,
+- struct dpu_vsync_source_cfg *cfg)
++static void dpu_hw_setup_wd_timer(struct dpu_hw_mdp *mdp,
++ struct dpu_vsync_source_cfg *cfg)
+ {
+ struct dpu_hw_blk_reg_map *c;
+ u32 reg, wd_load_value, wd_ctl, wd_ctl2;
+@@ -182,8 +182,8 @@ static void dpu_hw_setup_vsync_source(struct dpu_hw_mdp *mdp,
+ }
+ }
+
+-static void dpu_hw_setup_vsync_source_and_vsync_sel(struct dpu_hw_mdp *mdp,
+- struct dpu_vsync_source_cfg *cfg)
++static void dpu_hw_setup_vsync_sel(struct dpu_hw_mdp *mdp,
++ struct dpu_vsync_source_cfg *cfg)
+ {
+ struct dpu_hw_blk_reg_map *c;
+ u32 reg, i;
+@@ -206,7 +206,7 @@ static void dpu_hw_setup_vsync_source_and_vsync_sel(struct dpu_hw_mdp *mdp,
+ }
+ DPU_REG_WRITE(c, MDP_VSYNC_SEL, reg);
+
+- dpu_hw_setup_vsync_source(mdp, cfg);
++ dpu_hw_setup_wd_timer(mdp, cfg);
+ }
+
+ static void dpu_hw_get_safe_status(struct dpu_hw_mdp *mdp,
+@@ -258,9 +258,9 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
+ ops->get_danger_status = dpu_hw_get_danger_status;
+
+ if (cap & BIT(DPU_MDP_VSYNC_SEL))
+- ops->setup_vsync_source = dpu_hw_setup_vsync_source_and_vsync_sel;
++ ops->setup_vsync_source = dpu_hw_setup_vsync_sel;
+ else
+- ops->setup_vsync_source = dpu_hw_setup_vsync_source;
++ ops->setup_vsync_source = dpu_hw_setup_wd_timer;
+
+ ops->get_safe_status = dpu_hw_get_safe_status;
+
+--
+2.39.5
+
--- /dev/null
+From 5bc18192340b893d56ac95adbaa40c1b27c68616 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 14 Dec 2024 00:14:17 +0200
+Subject: drm/msm/dpu: skip watchdog timer programming through TOP on >= SM8450
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 2f69e54584475ac85ea0e3407c9198ac7c6ea8ad ]
+
+The SM8450 and later chips have DPU_MDP_PERIPH_0_REMOVED feature bit
+set, which means that those platforms have dropped some of the
+registers, including the WD TIMER-related ones. Stop providing the
+callback to program WD timer on those platforms.
+
+Fixes: 100d7ef6995d ("drm/msm/dpu: add support for SM8450")
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
+Patchwork: https://patchwork.freedesktop.org/patch/628874/
+Link: https://lore.kernel.org/r/20241214-dpu-drop-features-v1-1-988f0662cb7e@linaro.org
+Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+index fb0f5df70421f..597aa05efd843 100644
+--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+@@ -259,7 +259,7 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
+
+ if (cap & BIT(DPU_MDP_VSYNC_SEL))
+ ops->setup_vsync_source = dpu_hw_setup_vsync_sel;
+- else
++ else if (!(cap & BIT(DPU_MDP_PERIPH_0_REMOVED)))
+ ops->setup_vsync_source = dpu_hw_setup_wd_timer;
+
+ ops->get_safe_status = dpu_hw_get_safe_status;
+--
+2.39.5
+
--- /dev/null
+From 7496ca7e98a0bea483beb993af836bf76c17c826 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 10 Apr 2024 23:52:52 +0200
+Subject: drm/msm: Drop msm_read/writel
+
+From: Konrad Dybcio <konrad.dybcio@linaro.org>
+
+[ Upstream commit 0efadfb0050e1b65c14650406d8c7e5126c08b69 ]
+
+Totally useless.
+
+Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
+Patchwork: https://patchwork.freedesktop.org/patch/588804/
+Link: https://lore.kernel.org/r/20240410-topic-msm_rw-v1-1-e1fede9ffaba@linaro.org
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Stable-dep-of: 588257897058 ("drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG0 updated from driver side")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
+ drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 12 ++++++------
+ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++--
+ drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 4 ++--
+ drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h | 4 ++--
+ drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h | 4 ++--
+ drivers/gpu/drm/msm/dsi/dsi_host.c | 10 +++++-----
+ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 8 ++++----
+ drivers/gpu/drm/msm/hdmi/hdmi.h | 10 +++++-----
+ drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c | 6 +++---
+ drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c | 4 ++--
+ drivers/gpu/drm/msm/msm_drv.h | 7 ++-----
+ drivers/gpu/drm/msm/msm_gpu.h | 12 ++++++------
+ 13 files changed, 42 insertions(+), 45 deletions(-)
+
+diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+index 9009442b543dd..ac6aace4439d5 100644
+--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
++++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+@@ -501,7 +501,7 @@ static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
+
+ static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
+ {
+- msm_writel(value, ptr + (offset << 2));
++ writel(value, ptr + (offset << 2));
+ }
+
+ static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
+diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
+index 236f81a43caa6..3de610eff6480 100644
+--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
++++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
+@@ -100,12 +100,12 @@ struct a6xx_gmu {
+
+ static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
+ {
+- return msm_readl(gmu->mmio + (offset << 2));
++ return readl(gmu->mmio + (offset << 2));
+ }
+
+ static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
+ {
+- msm_writel(value, gmu->mmio + (offset << 2));
++ writel(value, gmu->mmio + (offset << 2));
+ }
+
+ static inline void
+@@ -128,8 +128,8 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
+ {
+ u64 val;
+
+- val = (u64) msm_readl(gmu->mmio + (lo << 2));
+- val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32);
++ val = (u64) readl(gmu->mmio + (lo << 2));
++ val |= ((u64) readl(gmu->mmio + (hi << 2)) << 32);
+
+ return val;
+ }
+@@ -140,12 +140,12 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
+
+ static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)
+ {
+- return msm_readl(gmu->rscc + (offset << 2));
++ return readl(gmu->rscc + (offset << 2));
+ }
+
+ static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)
+ {
+- msm_writel(value, gmu->rscc + (offset << 2));
++ writel(value, gmu->rscc + (offset << 2));
+ }
+
+ #define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \
+diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+index 34822b0807593..8917032b75156 100644
+--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
++++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+@@ -69,12 +69,12 @@ static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u3
+
+ static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)
+ {
+- return msm_readl(a6xx_gpu->llc_mmio + (reg << 2));
++ return readl(a6xx_gpu->llc_mmio + (reg << 2));
+ }
+
+ static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
+ {
+- msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
++ writel(value, a6xx_gpu->llc_mmio + (reg << 2));
+ }
+
+ #define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \
+diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+index 4e5d650578c60..ee2a095cec83b 100644
+--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
++++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+@@ -181,10 +181,10 @@ static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset,
+ }
+
+ #define cxdbg_write(ptr, offset, val) \
+- msm_writel((val), (ptr) + ((offset) << 2))
++ writel((val), (ptr) + ((offset) << 2))
+
+ #define cxdbg_read(ptr, offset) \
+- msm_readl((ptr) + ((offset) << 2))
++ readl((ptr) + ((offset) << 2))
+
+ /* read a value from the CX debug bus */
+ static int cx_debugbus_read(void __iomem *cxdbg, u32 block, u32 offset,
+diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
+index 01179e764a294..94b1ba92785fe 100644
+--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
++++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
+@@ -44,12 +44,12 @@ struct mdp4_kms {
+
+ static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
+ {
+- msm_writel(data, mdp4_kms->mmio + reg);
++ writel(data, mdp4_kms->mmio + reg);
+ }
+
+ static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
+ {
+- return msm_readl(mdp4_kms->mmio + reg);
++ return readl(mdp4_kms->mmio + reg);
+ }
+
+ static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
+diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
+index 29bf11f086011..a61fad926d65e 100644
+--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
++++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
+@@ -172,13 +172,13 @@ struct mdp5_encoder {
+ static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)
+ {
+ WARN_ON(mdp5_kms->enable_count <= 0);
+- msm_writel(data, mdp5_kms->mmio + reg);
++ writel(data, mdp5_kms->mmio + reg);
+ }
+
+ static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)
+ {
+ WARN_ON(mdp5_kms->enable_count <= 0);
+- return msm_readl(mdp5_kms->mmio + reg);
++ return readl(mdp5_kms->mmio + reg);
+ }
+
+ static inline const char *stage2name(enum mdp_mixer_stage_id stage)
+diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
+index f920329fe2e09..4c3c04d65faa6 100644
+--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
++++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
+@@ -55,7 +55,7 @@ static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
+ * scratch register which we never touch)
+ */
+
+- ver = msm_readl(base + REG_DSI_VERSION);
++ ver = readl(base + REG_DSI_VERSION);
+ if (ver) {
+ /* older dsi host, there is no register shift */
+ ver = FIELD(ver, DSI_VERSION_MAJOR);
+@@ -73,12 +73,12 @@ static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
+ * registers are shifted down, read DSI_VERSION again with
+ * the shifted offset
+ */
+- ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
++ ver = readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
+ ver = FIELD(ver, DSI_VERSION_MAJOR);
+ if (ver == MSM_DSI_VER_MAJOR_6G) {
+ /* 6G version */
+ *major = ver;
+- *minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
++ *minor = readl(base + REG_DSI_6G_HW_VERSION);
+ return 0;
+ } else {
+ return -EINVAL;
+@@ -196,11 +196,11 @@ static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
+
+ static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
+ {
+- return msm_readl(msm_host->ctrl_base + reg);
++ return readl(msm_host->ctrl_base + reg);
+ }
+ static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
+ {
+- msm_writel(data, msm_host->ctrl_base + reg);
++ writel(data, msm_host->ctrl_base + reg);
+ }
+
+ static const struct msm_dsi_cfg_handler *dsi_get_config(
+diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+index 8b640d1747851..1ff74689eefa0 100644
+--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
++++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+@@ -12,10 +12,10 @@
+
+ #include "dsi.h"
+
+-#define dsi_phy_read(offset) msm_readl((offset))
+-#define dsi_phy_write(offset, data) msm_writel((data), (offset))
+-#define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_us); }
+-#define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data), (offset)); ndelay(delay_ns); }
++#define dsi_phy_read(offset) readl((offset))
++#define dsi_phy_write(offset, data) writel((data), (offset))
++#define dsi_phy_write_udelay(offset, data, delay_us) { writel((data), (offset)); udelay(delay_us); }
++#define dsi_phy_write_ndelay(offset, data, delay_ns) { writel((data), (offset)); ndelay(delay_ns); }
+
+ struct msm_dsi_phy_ops {
+ int (*pll_init)(struct msm_dsi_phy *phy);
+diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
+index e8dbee50637fa..0a21f9e691948 100644
+--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
++++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
+@@ -115,17 +115,17 @@ void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on);
+
+ static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data)
+ {
+- msm_writel(data, hdmi->mmio + reg);
++ writel(data, hdmi->mmio + reg);
+ }
+
+ static inline u32 hdmi_read(struct hdmi *hdmi, u32 reg)
+ {
+- return msm_readl(hdmi->mmio + reg);
++ return readl(hdmi->mmio + reg);
+ }
+
+ static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg)
+ {
+- return msm_readl(hdmi->qfprom_mmio + reg);
++ return readl(hdmi->qfprom_mmio + reg);
+ }
+
+ /*
+@@ -166,12 +166,12 @@ struct hdmi_phy {
+
+ static inline void hdmi_phy_write(struct hdmi_phy *phy, u32 reg, u32 data)
+ {
+- msm_writel(data, phy->mmio + reg);
++ writel(data, phy->mmio + reg);
+ }
+
+ static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u32 reg)
+ {
+- return msm_readl(phy->mmio + reg);
++ return readl(phy->mmio + reg);
+ }
+
+ int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy);
+diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
+index 4dd0554166204..8c8d80b59573a 100644
+--- a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
++++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
+@@ -86,18 +86,18 @@ static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8996 *pll)
+ static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset,
+ u32 data)
+ {
+- msm_writel(data, pll->mmio_qserdes_com + offset);
++ writel(data, pll->mmio_qserdes_com + offset);
+ }
+
+ static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset)
+ {
+- return msm_readl(pll->mmio_qserdes_com + offset);
++ return readl(pll->mmio_qserdes_com + offset);
+ }
+
+ static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel,
+ int offset, int data)
+ {
+- msm_writel(data, pll->mmio_qserdes_tx[channel] + offset);
++ writel(data, pll->mmio_qserdes_tx[channel] + offset);
+ }
+
+ static inline u32 pll_get_cpctrl(u64 frac_start, unsigned long ref_clk,
+diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c b/drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
+index cb35a297afbd1..83c8781fcc3f6 100644
+--- a/drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
++++ b/drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
+@@ -236,12 +236,12 @@ static const struct pll_rate freqtbl[] = {
+
+ static inline void pll_write(struct hdmi_pll_8960 *pll, u32 reg, u32 data)
+ {
+- msm_writel(data, pll->mmio + reg);
++ writel(data, pll->mmio + reg);
+ }
+
+ static inline u32 pll_read(struct hdmi_pll_8960 *pll, u32 reg)
+ {
+- return msm_readl(pll->mmio + reg);
++ return readl(pll->mmio + reg);
+ }
+
+ static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8960 *pll)
+diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
+index 223bf904235a8..4a33d39a1c3d5 100644
+--- a/drivers/gpu/drm/msm/msm_drv.h
++++ b/drivers/gpu/drm/msm/msm_drv.h
+@@ -476,15 +476,12 @@ void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name);
+
+ struct icc_path *msm_icc_get(struct device *dev, const char *name);
+
+-#define msm_writel(data, addr) writel((data), (addr))
+-#define msm_readl(addr) readl((addr))
+-
+ static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or)
+ {
+- u32 val = msm_readl(addr);
++ u32 val = readl(addr);
+
+ val &= ~mask;
+- msm_writel(val | or, addr);
++ writel(val | or, addr);
+ }
+
+ /**
+diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
+index 4252e3839fbc8..1fdf6ef63f179 100644
+--- a/drivers/gpu/drm/msm/msm_gpu.h
++++ b/drivers/gpu/drm/msm/msm_gpu.h
+@@ -555,12 +555,12 @@ struct msm_gpu_state {
+
+ static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
+ {
+- msm_writel(data, gpu->mmio + (reg << 2));
++ writel(data, gpu->mmio + (reg << 2));
+ }
+
+ static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
+ {
+- return msm_readl(gpu->mmio + (reg << 2));
++ return readl(gpu->mmio + (reg << 2));
+ }
+
+ static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
+@@ -586,8 +586,8 @@ static inline u64 gpu_read64(struct msm_gpu *gpu, u32 reg)
+ * when the lo is read, so make sure to read the lo first to trigger
+ * that
+ */
+- val = (u64) msm_readl(gpu->mmio + (reg << 2));
+- val |= ((u64) msm_readl(gpu->mmio + ((reg + 1) << 2)) << 32);
++ val = (u64) readl(gpu->mmio + (reg << 2));
++ val |= ((u64) readl(gpu->mmio + ((reg + 1) << 2)) << 32);
+
+ return val;
+ }
+@@ -595,8 +595,8 @@ static inline u64 gpu_read64(struct msm_gpu *gpu, u32 reg)
+ static inline void gpu_write64(struct msm_gpu *gpu, u32 reg, u64 val)
+ {
+ /* Why not a writeq here? Read the screed above */
+- msm_writel(lower_32_bits(val), gpu->mmio + (reg << 2));
+- msm_writel(upper_32_bits(val), gpu->mmio + ((reg + 1) << 2));
++ writel(lower_32_bits(val), gpu->mmio + (reg << 2));
++ writel(upper_32_bits(val), gpu->mmio + ((reg + 1) << 2));
+ }
+
+ int msm_gpu_pm_suspend(struct msm_gpu *gpu);
+--
+2.39.5
+
--- /dev/null
+From a471ddc170c31f06a19092fcd2c478e176c4d04c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 14 Feb 2025 16:08:43 +0100
+Subject: drm/msm/dsi/phy: Do not overwite PHY_CMN_CLK_CFG1 when choosing
+ bitclk source
+
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+[ Upstream commit 73f69c6be2a9f22c31c775ec03c6c286bfe12cfa ]
+
+PHY_CMN_CLK_CFG1 register has four fields being used in the driver: DSI
+clock divider, source of bitclk and two for enabling the DSI PHY PLL
+clocks.
+
+dsi_7nm_set_usecase() sets only the source of bitclk, so should leave
+all other bits untouched. Use newly introduced
+dsi_pll_cmn_clk_cfg1_update() to update respective bits without
+overwriting the rest.
+
+While shuffling the code, define and use PHY_CMN_CLK_CFG1 bitfields to
+make the code more readable and obvious.
+
+Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
+Patchwork: https://patchwork.freedesktop.org/patch/637380/
+Link: https://lore.kernel.org/r/20250214-drm-msm-phy-pll-cfg-reg-v3-3-0943b850722c@linaro.org
+Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 4 ++--
+ drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 1 +
+ 2 files changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+index 991bf10a64248..ad4b3b5cc4944 100644
+--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
++++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+@@ -617,7 +617,6 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy)
+ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
+ {
+ struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
+- void __iomem *base = phy->base;
+ u32 data = 0x0; /* internal PLL */
+
+ DBG("DSI PLL%d", pll_7nm->phy->id);
+@@ -636,7 +635,8 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
+ }
+
+ /* set PLL src */
+- writel(data << 2, base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
++ dsi_pll_cmn_clk_cfg1_update(pll_7nm, DSI_7nm_PHY_CMN_CLK_CFG1_BITCLK_SEL__MASK,
++ DSI_7nm_PHY_CMN_CLK_CFG1_BITCLK_SEL(data));
+
+ return 0;
+ }
+diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
+index cfaf78c028b13..35f7f40e405b7 100644
+--- a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
++++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
+@@ -16,6 +16,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+ <reg32 offset="0x00014" name="CLK_CFG1">
+ <bitfield name="CLK_EN" pos="5" type="boolean"/>
+ <bitfield name="CLK_EN_SEL" pos="4" type="boolean"/>
++ <bitfield name="BITCLK_SEL" low="2" high="3" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00018" name="GLBL_CTRL"/>
+ <reg32 offset="0x0001c" name="RBUF_CTRL"/>
+--
+2.39.5
+
--- /dev/null
+From 0f62618f50d551a0f3753233604158540491fa19 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 14 Feb 2025 16:08:41 +0100
+Subject: drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG0 updated from driver side
+
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+[ Upstream commit 588257897058a0b1aa47912db4fe93c6ff5e3887 ]
+
+PHY_CMN_CLK_CFG0 register is updated by the PHY driver and by two
+divider clocks from Common Clock Framework:
+devm_clk_hw_register_divider_parent_hw(). Concurrent access by the
+clocks side is protected with spinlock, however driver's side in
+restoring state is not. Restoring state is called from
+msm_dsi_phy_enable(), so there could be a path leading to concurrent and
+conflicting updates with clock framework.
+
+Add missing lock usage on the PHY driver side, encapsulated in its own
+function so the code will be still readable.
+
+While shuffling the code, define and use PHY_CMN_CLK_CFG0 bitfields to
+make the code more readable and obvious.
+
+Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Patchwork: https://patchwork.freedesktop.org/patch/637376/
+Link: https://lore.kernel.org/r/20250214-drm-msm-phy-pll-cfg-reg-v3-1-0943b850722c@linaro.org
+Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 14 ++++++++++++--
+ .../gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 5 ++++-
+ 2 files changed, 16 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+index 8e2af844d240d..31818549fedc1 100644
+--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
++++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+@@ -372,6 +372,15 @@ static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll)
+ ndelay(250);
+ }
+
++static void dsi_pll_cmn_clk_cfg0_write(struct dsi_pll_7nm *pll, u32 val)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&pll->postdiv_lock, flags);
++ writel(val, pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
++ spin_unlock_irqrestore(&pll->postdiv_lock, flags);
++}
++
+ static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
+ {
+ u32 data;
+@@ -574,8 +583,9 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy)
+ val |= cached->pll_out_div;
+ writel(val, pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
+
+- writel(cached->bit_clk_div | (cached->pix_clk_div << 4),
+- phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
++ dsi_pll_cmn_clk_cfg0_write(pll_7nm,
++ DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(cached->bit_clk_div) |
++ DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(cached->pix_clk_div));
+
+ val = readl(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+ val &= ~0x3;
+diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
+index d54b72f924493..e0bf6e016b4ce 100644
+--- a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
++++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
+@@ -9,7 +9,10 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+ <reg32 offset="0x00004" name="REVISION_ID1"/>
+ <reg32 offset="0x00008" name="REVISION_ID2"/>
+ <reg32 offset="0x0000c" name="REVISION_ID3"/>
+- <reg32 offset="0x00010" name="CLK_CFG0"/>
++ <reg32 offset="0x00010" name="CLK_CFG0">
++ <bitfield name="DIV_CTRL_3_0" low="0" high="3" type="uint"/>
++ <bitfield name="DIV_CTRL_7_4" low="4" high="7" type="uint"/>
++ </reg32>
+ <reg32 offset="0x00014" name="CLK_CFG1"/>
+ <reg32 offset="0x00018" name="GLBL_CTRL"/>
+ <reg32 offset="0x0001c" name="RBUF_CTRL"/>
+--
+2.39.5
+
--- /dev/null
+From caa3fad17c9d98695ae4fe0bb11662163eedfb23 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 14 Feb 2025 16:08:42 +0100
+Subject: drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver
+
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+[ Upstream commit 5a97bc924ae0804b8dbf627e357acaa5ef761483 ]
+
+PHY_CMN_CLK_CFG1 register is updated by the PHY driver and by a mux
+clock from Common Clock Framework:
+devm_clk_hw_register_mux_parent_hws(). There could be a path leading to
+concurrent and conflicting updates between PHY driver and clock
+framework, e.g. changing the mux and enabling PLL clocks.
+
+Add dedicated spinlock to be sure all PHY_CMN_CLK_CFG1 updates are
+synchronized.
+
+While shuffling the code, define and use PHY_CMN_CLK_CFG1 bitfields to
+make the code more readable and obvious.
+
+Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
+Patchwork: https://patchwork.freedesktop.org/patch/637378/
+Link: https://lore.kernel.org/r/20250214-drm-msm-phy-pll-cfg-reg-v3-2-0943b850722c@linaro.org
+Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 35 ++++++++++++-------
+ .../drm/msm/registers/display/dsi_phy_7nm.xml | 5 ++-
+ 2 files changed, 26 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+index 31818549fedc1..991bf10a64248 100644
+--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
++++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+@@ -83,6 +83,9 @@ struct dsi_pll_7nm {
+ /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */
+ spinlock_t postdiv_lock;
+
++ /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG1 register */
++ spinlock_t pclk_mux_lock;
++
+ struct pll_7nm_cached_state cached_state;
+
+ struct dsi_pll_7nm *slave;
+@@ -381,22 +384,32 @@ static void dsi_pll_cmn_clk_cfg0_write(struct dsi_pll_7nm *pll, u32 val)
+ spin_unlock_irqrestore(&pll->postdiv_lock, flags);
+ }
+
+-static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
++static void dsi_pll_cmn_clk_cfg1_update(struct dsi_pll_7nm *pll, u32 mask,
++ u32 val)
+ {
++ unsigned long flags;
+ u32 data;
+
++ spin_lock_irqsave(&pll->pclk_mux_lock, flags);
+ data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+- writel(data & ~BIT(5), pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
++ data &= ~mask;
++ data |= val & mask;
++
++ writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
++ spin_unlock_irqrestore(&pll->pclk_mux_lock, flags);
++}
++
++static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
++{
++ dsi_pll_cmn_clk_cfg1_update(pll, DSI_7nm_PHY_CMN_CLK_CFG1_CLK_EN, 0);
+ }
+
+ static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll)
+ {
+- u32 data;
++ u32 cfg_1 = DSI_7nm_PHY_CMN_CLK_CFG1_CLK_EN | DSI_7nm_PHY_CMN_CLK_CFG1_CLK_EN_SEL;
+
+ writel(0x04, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3);
+-
+- data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+- writel(data | BIT(5) | BIT(4), pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
++ dsi_pll_cmn_clk_cfg1_update(pll, cfg_1, cfg_1);
+ }
+
+ static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll)
+@@ -574,7 +587,6 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy)
+ {
+ struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
+ struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
+- void __iomem *phy_base = pll_7nm->phy->base;
+ u32 val;
+ int ret;
+
+@@ -586,11 +598,7 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy)
+ dsi_pll_cmn_clk_cfg0_write(pll_7nm,
+ DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(cached->bit_clk_div) |
+ DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(cached->pix_clk_div));
+-
+- val = readl(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+- val &= ~0x3;
+- val |= cached->pll_mux;
+- writel(val, phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
++ dsi_pll_cmn_clk_cfg1_update(pll_7nm, 0x3, cached->pll_mux);
+
+ ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw,
+ pll_7nm->vco_current_rate,
+@@ -743,7 +751,7 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
+ pll_by_2_bit,
+ }), 2, 0, pll_7nm->phy->base +
+ REG_DSI_7nm_PHY_CMN_CLK_CFG1,
+- 0, 1, 0, NULL);
++ 0, 1, 0, &pll_7nm->pclk_mux_lock);
+ if (IS_ERR(hw)) {
+ ret = PTR_ERR(hw);
+ goto fail;
+@@ -788,6 +796,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
+ pll_7nm_list[phy->id] = pll_7nm;
+
+ spin_lock_init(&pll_7nm->postdiv_lock);
++ spin_lock_init(&pll_7nm->pclk_mux_lock);
+
+ pll_7nm->phy = phy;
+
+diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
+index e0bf6e016b4ce..cfaf78c028b13 100644
+--- a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
++++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
+@@ -13,7 +13,10 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+ <bitfield name="DIV_CTRL_3_0" low="0" high="3" type="uint"/>
+ <bitfield name="DIV_CTRL_7_4" low="4" high="7" type="uint"/>
+ </reg32>
+- <reg32 offset="0x00014" name="CLK_CFG1"/>
++ <reg32 offset="0x00014" name="CLK_CFG1">
++ <bitfield name="CLK_EN" pos="5" type="boolean"/>
++ <bitfield name="CLK_EN_SEL" pos="4" type="boolean"/>
++ </reg32>
+ <reg32 offset="0x00018" name="GLBL_CTRL"/>
+ <reg32 offset="0x0001c" name="RBUF_CTRL"/>
+ <reg32 offset="0x00020" name="VREG_CTRL_0"/>
+--
+2.39.5
+
--- /dev/null
+From 77afa715d224fbe18133d4b0ae3004bebb246a98 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 23 Apr 2024 00:36:59 +0200
+Subject: drm/msm/dsi: Remove dsi_phy_read/write()
+
+From: Konrad Dybcio <konrad.dybcio@linaro.org>
+
+[ Upstream commit 8fd6f64ddba041c3cf252f928b8c446a37996f39 ]
+
+These are dummy wrappers that do literally nothing interesting.
+Remove them.
+
+Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Patchwork: https://patchwork.freedesktop.org/patch/590700/
+Link: https://lore.kernel.org/r/20240423-topic-msm_cleanup-v1-1-b30f39f43b90@linaro.org
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Stable-dep-of: 588257897058 ("drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG0 updated from driver side")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 -
+ drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 273 +++++++--------
+ drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 215 ++++++------
+ drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 109 +++---
+ drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 224 ++++++------
+ .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 205 ++++++-----
+ drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 320 +++++++++---------
+ 7 files changed, 645 insertions(+), 703 deletions(-)
+
+diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+index 1ff74689eefa0..31a481d02d8cc 100644
+--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
++++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+@@ -12,8 +12,6 @@
+
+ #include "dsi.h"
+
+-#define dsi_phy_read(offset) readl((offset))
+-#define dsi_phy_write(offset, data) writel((data), (offset))
+ #define dsi_phy_write_udelay(offset, data, delay_us) { writel((data), (offset)); udelay(delay_us); }
+ #define dsi_phy_write_ndelay(offset, data, delay_ns) { writel((data), (offset)); ndelay(delay_ns); }
+
+diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+index 27b592c776a30..677c625718119 100644
+--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
++++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+@@ -187,20 +187,20 @@ static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll, struct dsi_pll_config *
+ if (config->enable_ssc) {
+ pr_debug("SSC is enabled\n");
+
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
+- config->ssc_stepsize & 0xff);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
+- config->ssc_stepsize >> 8);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1,
+- config->ssc_div_per & 0xff);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
+- config->ssc_div_per >> 8);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1,
+- config->ssc_adj_per & 0xff);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1,
+- config->ssc_adj_per >> 8);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL,
+- SSC_EN | (config->ssc_center ? SSC_CENTER : 0));
++ writel(config->ssc_stepsize & 0xff,
++ base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1);
++ writel(config->ssc_stepsize >> 8,
++ base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1);
++ writel(config->ssc_div_per & 0xff,
++ base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1);
++ writel(config->ssc_div_per >> 8,
++ base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1);
++ writel(config->ssc_adj_per & 0xff,
++ base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1);
++ writel(config->ssc_adj_per >> 8,
++ base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1);
++ writel(SSC_EN | (config->ssc_center ? SSC_CENTER : 0),
++ base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL);
+ }
+ }
+
+@@ -208,49 +208,43 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll)
+ {
+ void __iomem *base = pll->phy->pll_base;
+
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_DSM_DIVIDER, 0x00);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE,
+- 0xba);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE,
+- 0x0c);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_OUTDIV, 0x00);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE, 0x00);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO,
+- 0x08);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x08);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1, 0xc0);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1,
+- 0xfa);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1,
+- 0x4c);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PFILT, 0x29);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f);
++ writel(0x80, base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE);
++ writel(0x03, base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO);
++ writel(0x00, base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE);
++ writel(0x00, base + REG_DSI_10nm_PHY_PLL_DSM_DIVIDER);
++ writel(0x4e, base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER);
++ writel(0x40, base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS);
++ writel(0xba, base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE);
++ writel(0x0c, base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE);
++ writel(0x00, base + REG_DSI_10nm_PHY_PLL_OUTDIV);
++ writel(0x00, base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE);
++ writel(0x08, base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO);
++ writel(0x08, base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1);
++ writel(0xc0, base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1);
++ writel(0xfa, base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1);
++ writel(0x4c, base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1);
++ writel(0x80, base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE);
++ writel(0x29, base + REG_DSI_10nm_PHY_PLL_PFILT);
++ writel(0x3f, base + REG_DSI_10nm_PHY_PLL_IFILT);
+ }
+
+ static void dsi_pll_commit(struct dsi_pll_10nm *pll, struct dsi_pll_config *config)
+ {
+ void __iomem *base = pll->phy->pll_base;
+
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1,
+- config->decimal_div_start);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1,
+- config->frac_div_start & 0xff);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1,
+- (config->frac_div_start & 0xff00) >> 8);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
+- (config->frac_div_start & 0x30000) >> 16);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1, 64);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS,
+- config->pll_clock_inverters);
++ writel(0x12, base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE);
++ writel(config->decimal_div_start,
++ base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1);
++ writel(config->frac_div_start & 0xff,
++ base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1);
++ writel((config->frac_div_start & 0xff00) >> 8,
++ base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1);
++ writel((config->frac_div_start & 0x30000) >> 16,
++ base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1);
++ writel(64, base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1);
++ writel(0x06, base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY);
++ writel(0x10, base + REG_DSI_10nm_PHY_PLL_CMODE);
++ writel(config->pll_clock_inverters, base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS);
+ }
+
+ static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
+@@ -305,21 +299,19 @@ static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll)
+
+ static void dsi_pll_disable_pll_bias(struct dsi_pll_10nm *pll)
+ {
+- u32 data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
++ u32 data = readl(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
+
+- dsi_phy_write(pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0);
+- dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0,
+- data & ~BIT(5));
++ writel(0, pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES);
++ writel(data & ~BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
+ ndelay(250);
+ }
+
+ static void dsi_pll_enable_pll_bias(struct dsi_pll_10nm *pll)
+ {
+- u32 data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
++ u32 data = readl(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
+
+- dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0,
+- data | BIT(5));
+- dsi_phy_write(pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
++ writel(data | BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
++ writel(0xc0, pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES);
+ ndelay(250);
+ }
+
+@@ -327,18 +319,16 @@ static void dsi_pll_disable_global_clk(struct dsi_pll_10nm *pll)
+ {
+ u32 data;
+
+- data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
+- dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
+- data & ~BIT(5));
++ data = readl(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
++ writel(data & ~BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
+ }
+
+ static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll)
+ {
+ u32 data;
+
+- data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
+- dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
+- data | BIT(5));
++ data = readl(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
++ writel(data | BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
+ }
+
+ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
+@@ -358,8 +348,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
+ }
+
+ /* Start PLL */
+- dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL,
+- 0x01);
++ writel(0x01, pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL);
+
+ /*
+ * ensure all PLL configurations are written prior to checking
+@@ -380,11 +369,9 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
+ if (pll_10nm->slave)
+ dsi_pll_enable_global_clk(pll_10nm->slave);
+
+- dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL,
+- 0x01);
++ writel(0x01, pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL);
+ if (pll_10nm->slave)
+- dsi_phy_write(pll_10nm->slave->phy->base +
+- REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x01);
++ writel(0x01, pll_10nm->slave->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL);
+
+ error:
+ return rc;
+@@ -392,7 +379,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
+
+ static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll)
+ {
+- dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0);
++ writel(0, pll->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL);
+ dsi_pll_disable_pll_bias(pll);
+ }
+
+@@ -406,7 +393,7 @@ static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw)
+ * powering down the PLL
+ */
+ dsi_pll_disable_global_clk(pll_10nm);
+- dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0);
++ writel(0, pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL);
+ dsi_pll_disable_sub(pll_10nm);
+ if (pll_10nm->slave) {
+ dsi_pll_disable_global_clk(pll_10nm->slave);
+@@ -429,13 +416,13 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
+ u32 dec;
+ u64 pll_freq, tmp64;
+
+- dec = dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1);
++ dec = readl(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1);
+ dec &= 0xff;
+
+- frac = dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1);
+- frac |= ((dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1) &
++ frac = readl(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1);
++ frac |= ((readl(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1) &
+ 0xff) << 8);
+- frac |= ((dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
++ frac |= ((readl(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
+ 0x3) << 16);
+
+ /*
+@@ -488,15 +475,15 @@ static void dsi_10nm_pll_save_state(struct msm_dsi_phy *phy)
+ void __iomem *phy_base = pll_10nm->phy->base;
+ u32 cmn_clk_cfg0, cmn_clk_cfg1;
+
+- cached->pll_out_div = dsi_phy_read(pll_10nm->phy->pll_base +
++ cached->pll_out_div = readl(pll_10nm->phy->pll_base +
+ REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
+ cached->pll_out_div &= 0x3;
+
+- cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0);
++ cmn_clk_cfg0 = readl(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0);
+ cached->bit_clk_div = cmn_clk_cfg0 & 0xf;
+ cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4;
+
+- cmn_clk_cfg1 = dsi_phy_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
++ cmn_clk_cfg1 = readl(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
+ cached->pll_mux = cmn_clk_cfg1 & 0x3;
+
+ DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
+@@ -512,18 +499,18 @@ static int dsi_10nm_pll_restore_state(struct msm_dsi_phy *phy)
+ u32 val;
+ int ret;
+
+- val = dsi_phy_read(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
++ val = readl(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
+ val &= ~0x3;
+ val |= cached->pll_out_div;
+- dsi_phy_write(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val);
++ writel(val, pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
+
+- dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,
+- cached->bit_clk_div | (cached->pix_clk_div << 4));
++ writel(cached->bit_clk_div | (cached->pix_clk_div << 4),
++ phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0);
+
+- val = dsi_phy_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
++ val = readl(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
+ val &= ~0x3;
+ val |= cached->pll_mux;
+- dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);
++ writel(val, phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
+
+ ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw,
+ pll_10nm->vco_current_rate,
+@@ -561,7 +548,7 @@ static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy)
+ }
+
+ /* set PLL src */
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2));
++ writel(data << 2, base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
+
+ return 0;
+ }
+@@ -724,7 +711,7 @@ static int dsi_phy_hw_v3_0_is_pll_on(struct msm_dsi_phy *phy)
+ void __iomem *base = phy->base;
+ u32 data = 0;
+
+- data = dsi_phy_read(base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL);
++ data = readl(base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL);
+ mb(); /* make sure read happened */
+
+ return (data & BIT(0));
+@@ -740,11 +727,9 @@ static void dsi_phy_hw_v3_0_config_lpcdrx(struct msm_dsi_phy *phy, bool enable)
+ * corresponding to the logical data lane 0
+ */
+ if (enable)
+- dsi_phy_write(lane_base +
+- REG_DSI_10nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0x3);
++ writel(0x3, lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(phy_lane_0));
+ else
+- dsi_phy_write(lane_base +
+- REG_DSI_10nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0);
++ writel(0, lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(phy_lane_0));
+ }
+
+ static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy)
+@@ -759,43 +744,40 @@ static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy)
+
+ /* Strength ctrl settings */
+ for (i = 0; i < 5; i++) {
+- dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(i),
+- 0x55);
++ writel(0x55, lane_base + REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(i));
+ /*
+ * Disable LPRX and CDRX for all lanes. And later on, it will
+ * be only enabled for the physical data lane corresponding
+ * to the logical data lane 0
+ */
+- dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(i), 0);
+- dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_PIN_SWAP(i), 0x0);
+- dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(i),
+- 0x88);
++ writel(0, lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(i));
++ writel(0x0, lane_base + REG_DSI_10nm_PHY_LN_PIN_SWAP(i));
++ writel(0x88, lane_base + REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(i));
+ }
+
+ dsi_phy_hw_v3_0_config_lpcdrx(phy, true);
+
+ /* other settings */
+ for (i = 0; i < 5; i++) {
+- dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG0(i), 0x0);
+- dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG1(i), 0x0);
+- dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG2(i), 0x0);
+- dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG3(i),
+- i == 4 ? 0x80 : 0x0);
++ writel(0, lane_base + REG_DSI_10nm_PHY_LN_CFG0(i));
++ writel(0, lane_base + REG_DSI_10nm_PHY_LN_CFG1(i));
++ writel(0, lane_base + REG_DSI_10nm_PHY_LN_CFG2(i));
++ writel(i == 4 ? 0x80 : 0x0, lane_base + REG_DSI_10nm_PHY_LN_CFG3(i));
+
+ /* platform specific dsi phy drive strength adjustment */
+- dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(i),
+- tuning_cfg->rescode_offset_top[i]);
+- dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(i),
+- tuning_cfg->rescode_offset_bot[i]);
++ writel(tuning_cfg->rescode_offset_top[i],
++ lane_base + REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(i));
++ writel(tuning_cfg->rescode_offset_bot[i],
++ lane_base + REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(i));
+
+- dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(i),
+- tx_dctrl[i]);
++ writel(tx_dctrl[i],
++ lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(i));
+ }
+
+ if (!(phy->cfg->quirks & DSI_PHY_10NM_QUIRK_OLD_TIMINGS)) {
+ /* Toggle BIT 0 to release freeze I/0 */
+- dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x05);
+- dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x04);
++ writel(0x05, lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3));
++ writel(0x04, lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3));
+ }
+ }
+
+@@ -833,64 +815,51 @@ static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy,
+
+ /* de-assert digital and pll power down */
+ data = BIT(6) | BIT(5);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, data);
++ writel(data, base + REG_DSI_10nm_PHY_CMN_CTRL_0);
+
+ /* Assert PLL core reset */
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0x00);
++ writel(0x00, base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL);
+
+ /* turn off resync FIFO */
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x00);
++ writel(0x00, base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL);
+
+ /* Select MS1 byte-clk */
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_GLBL_CTRL, 0x10);
++ writel(0x10, base + REG_DSI_10nm_PHY_CMN_GLBL_CTRL);
+
+ /* Enable LDO with platform specific drive level/amplitude adjustment */
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_VREG_CTRL,
+- tuning_cfg->vreg_ctrl);
++ writel(tuning_cfg->vreg_ctrl, base + REG_DSI_10nm_PHY_CMN_VREG_CTRL);
+
+ /* Configure PHY lane swap (TODO: we need to calculate this) */
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CFG0, 0x21);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CFG1, 0x84);
++ writel(0x21, base + REG_DSI_10nm_PHY_CMN_LANE_CFG0);
++ writel(0x84, base + REG_DSI_10nm_PHY_CMN_LANE_CFG1);
+
+ /* DSI PHY timings */
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0,
+- timing->hs_halfbyte_en);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1,
+- timing->clk_zero);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2,
+- timing->clk_prepare);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3,
+- timing->clk_trail);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4,
+- timing->hs_exit);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5,
+- timing->hs_zero);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6,
+- timing->hs_prepare);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7,
+- timing->hs_trail);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8,
+- timing->hs_rqst);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9,
+- timing->ta_go | (timing->ta_sure << 3));
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10,
+- timing->ta_get);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11,
+- 0x00);
++ writel(timing->hs_halfbyte_en, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0);
++ writel(timing->clk_zero, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1);
++ writel(timing->clk_prepare, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2);
++ writel(timing->clk_trail, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3);
++ writel(timing->hs_exit, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4);
++ writel(timing->hs_zero, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5);
++ writel(timing->hs_prepare, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6);
++ writel(timing->hs_trail, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7);
++ writel(timing->hs_rqst, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8);
++ writel(timing->ta_go | (timing->ta_sure << 3), base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9);
++ writel(timing->ta_get, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10);
++ writel(0x00, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11);
+
+ /* Remove power down from all blocks */
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, 0x7f);
++ writel(0x7f, base + REG_DSI_10nm_PHY_CMN_CTRL_0);
+
+ /* power up lanes */
+- data = dsi_phy_read(base + REG_DSI_10nm_PHY_CMN_CTRL_0);
++ data = readl(base + REG_DSI_10nm_PHY_CMN_CTRL_0);
+
+ /* TODO: only power up lanes that are used */
+ data |= 0x1F;
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, data);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CTRL0, 0x1F);
++ writel(data, base + REG_DSI_10nm_PHY_CMN_CTRL_0);
++ writel(0x1F, base + REG_DSI_10nm_PHY_CMN_LANE_CTRL0);
+
+ /* Select full-rate mode */
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_2, 0x40);
++ writel(0x40, base + REG_DSI_10nm_PHY_CMN_CTRL_2);
+
+ ret = dsi_10nm_set_usecase(phy);
+ if (ret) {
+@@ -918,15 +887,15 @@ static void dsi_10nm_phy_disable(struct msm_dsi_phy *phy)
+ pr_warn("Turning OFF PHY while PLL is on\n");
+
+ dsi_phy_hw_v3_0_config_lpcdrx(phy, false);
+- data = dsi_phy_read(base + REG_DSI_10nm_PHY_CMN_CTRL_0);
++ data = readl(base + REG_DSI_10nm_PHY_CMN_CTRL_0);
+
+ /* disable all lanes */
+ data &= ~0x1F;
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, data);
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CTRL0, 0);
++ writel(data, base + REG_DSI_10nm_PHY_CMN_CTRL_0);
++ writel(0, base + REG_DSI_10nm_PHY_CMN_LANE_CTRL0);
+
+ /* Turn off all PHY blocks */
+- dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, 0x00);
++ writel(0x00, base + REG_DSI_10nm_PHY_CMN_CTRL_0);
+ /* make sure phy is turned off */
+ wmb();
+
+diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+index 31deda1c664ad..b128c4acea239 100644
+--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
++++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+@@ -116,7 +116,7 @@ static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm,
+
+ tries = nb_tries;
+ while (tries--) {
+- val = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
++ val = readl(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
+ pll_locked = !!(val & BIT(5));
+
+ if (pll_locked)
+@@ -130,7 +130,7 @@ static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm,
+
+ tries = nb_tries;
+ while (tries--) {
+- val = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
++ val = readl(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
+ pll_ready = !!(val & BIT(0));
+
+ if (pll_ready)
+@@ -288,29 +288,29 @@ static void pll_db_commit_ssc(struct dsi_pll_14nm *pll, struct dsi_pll_config *p
+
+ data = pconf->ssc_adj_period;
+ data &= 0x0ff;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1);
+ data = (pconf->ssc_adj_period >> 8);
+ data &= 0x03;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2);
+
+ data = pconf->ssc_period;
+ data &= 0x0ff;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_PER1);
+ data = (pconf->ssc_period >> 8);
+ data &= 0x0ff;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_PER2);
+
+ data = pconf->ssc_step_size;
+ data &= 0x0ff;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1);
+ data = (pconf->ssc_step_size >> 8);
+ data &= 0x0ff;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2);
+
+ data = (pconf->ssc_center & 0x01);
+ data <<= 1;
+ data |= 0x01; /* enable */
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER);
+
+ wmb(); /* make sure register committed */
+ }
+@@ -323,43 +323,45 @@ static void pll_db_commit_common(struct dsi_pll_14nm *pll,
+
+ /* confgiure the non frequency dependent pll registers */
+ data = 0;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET);
+
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, 1);
++ writel(1, base + REG_DSI_14nm_PHY_PLL_TXCLK_EN);
+
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, 48);
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, 4 << 3); /* bandgap_timer */
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, 5); /* pll_wakeup_timer */
++ writel(48, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL);
++ /* bandgap_timer */
++ writel(4 << 3, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2);
++ /* pll_wakeup_timer */
++ writel(5, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5);
+
+ data = pconf->pll_vco_div_ref & 0xff;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1);
+ data = (pconf->pll_vco_div_ref >> 8) & 0x3;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2);
+
+ data = pconf->pll_kvco_div_ref & 0xff;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1);
+ data = (pconf->pll_kvco_div_ref >> 8) & 0x3;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2);
+
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, 16);
++ writel(16, base + REG_DSI_14nm_PHY_PLL_PLL_MISC1);
+
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, 4);
++ writel(4, base + REG_DSI_14nm_PHY_PLL_IE_TRIM);
+
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, 4);
++ writel(4, base + REG_DSI_14nm_PHY_PLL_IP_TRIM);
+
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, 1 << 3 | 1);
++ writel(1 << 3 | 1, base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR);
+
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, 0 << 3 | 0);
++ writel(0 << 3 | 0, base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET);
+
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, 0 << 3 | 0);
++ writel(0 << 3 | 0, base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET);
+
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, 4 << 3 | 4);
++ writel(4 << 3 | 4, base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET);
+
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, 1 << 4 | 11);
++ writel(1 << 4 | 11, base + REG_DSI_14nm_PHY_PLL_PLL_LPF1);
+
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, 7);
++ writel(7, base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM);
+
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, 1 << 4 | 2);
++ writel(1 << 4 | 2, base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL);
+ }
+
+ static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
+@@ -369,13 +371,13 @@ static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
+ /* de assert pll start and apply pll sw reset */
+
+ /* stop pll */
+- dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
++ writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL);
+
+ /* pll sw reset */
+ dsi_phy_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10);
+ wmb(); /* make sure register committed */
+
+- dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0);
++ writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1);
+ wmb(); /* make sure register committed */
+ }
+
+@@ -388,50 +390,50 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
+
+ DBG("DSI%d PLL", pll->phy->id);
+
+- dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, 0x3c);
++ writel(0x3c, cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL);
+
+ pll_db_commit_common(pll, pconf);
+
+ pll_14nm_software_reset(pll);
+
+ /* Use the /2 path in Mux */
+- dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, 1);
++ writel(1, cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1);
+
+ data = 0xff; /* data, clk, pll normal operation */
+- dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data);
++ writel(data, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0);
+
+ /* configure the frequency dependent pll registers */
+ data = pconf->dec_start;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_DEC_START);
+
+ data = pconf->div_frac_start & 0xff;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1);
+ data = (pconf->div_frac_start >> 8) & 0xff;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2);
+ data = (pconf->div_frac_start >> 16) & 0xf;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3);
+
+ data = pconf->plllock_cmp & 0xff;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1);
+
+ data = (pconf->plllock_cmp >> 8) & 0xff;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2);
+
+ data = (pconf->plllock_cmp >> 16) & 0x3;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3);
+
+ data = pconf->plllock_cnt << 1 | 0 << 3; /* plllock_rng */
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN);
+
+ data = pconf->pll_vco_count & 0xff;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1);
+ data = (pconf->pll_vco_count >> 8) & 0xff;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2);
+
+ data = pconf->pll_kvco_count & 0xff;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1);
+ data = (pconf->pll_kvco_count >> 8) & 0x3;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data);
++ writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2);
+
+ /*
+ * High nibble configures the post divider internal to the VCO. It's
+@@ -442,7 +444,7 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
+ * 2: divided by 4
+ * 3: divided by 8
+ */
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, 0 << 4 | 3);
++ writel(0 << 4 | 3, base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV);
+
+ if (pconf->ssc_en)
+ pll_db_commit_ssc(pll, pconf);
+@@ -497,16 +499,16 @@ static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
+ u32 dec_start;
+ u64 ref_clk = parent_rate;
+
+- dec_start = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DEC_START);
++ dec_start = readl(base + REG_DSI_14nm_PHY_PLL_DEC_START);
+ dec_start &= 0x0ff;
+
+ DBG("dec_start = %x", dec_start);
+
+- div_frac_start = (dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3)
++ div_frac_start = (readl(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3)
+ & 0xf) << 16;
+- div_frac_start |= (dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2)
++ div_frac_start |= (readl(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2)
+ & 0xff) << 8;
+- div_frac_start |= dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1)
++ div_frac_start |= readl(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1)
+ & 0xff;
+
+ DBG("div_frac_start = %x", div_frac_start);
+@@ -542,8 +544,8 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
+ if (dsi_pll_14nm_vco_recalc_rate(hw, VCO_REF_CLK_RATE) == 0)
+ dsi_pll_14nm_vco_set_rate(hw, pll_14nm->phy->cfg->min_pll_rate, VCO_REF_CLK_RATE);
+
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
+- dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
++ writel(0x10, base + REG_DSI_14nm_PHY_PLL_VREF_CFG1);
++ writel(1, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL);
+
+ locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS,
+ POLL_TIMEOUT_US);
+@@ -569,7 +571,7 @@ static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw)
+ if (unlikely(!pll_14nm->phy->pll_on))
+ return;
+
+- dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
++ writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL);
+
+ pll_14nm->phy->pll_on = false;
+ }
+@@ -611,7 +613,7 @@ static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw,
+
+ DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, parent_rate);
+
+- val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift;
++ val = readl(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift;
+ val &= div_mask(width);
+
+ return divider_recalc_rate(hw, parent_rate, val, NULL,
+@@ -653,11 +655,11 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
+
+ spin_lock_irqsave(lock, flags);
+
+- val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
++ val = readl(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
+ val &= ~(div_mask(width) << shift);
+
+ val |= value << shift;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
++ writel(val, base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
+
+ /* If we're master in bonded DSI mode, then the slave PLL's post-dividers
+ * follow the master's post dividers
+@@ -666,7 +668,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
+ struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
+ void __iomem *slave_base = pll_14nm_slave->phy->base;
+
+- dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
++ writel(val, slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
+ }
+
+ spin_unlock_irqrestore(lock, flags);
+@@ -691,7 +693,7 @@ static void dsi_14nm_pll_save_state(struct msm_dsi_phy *phy)
+ void __iomem *cmn_base = pll_14nm->phy->base;
+ u32 data;
+
+- data = dsi_phy_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
++ data = readl(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
+
+ cached_state->n1postdiv = data & 0xf;
+ cached_state->n2postdiv = (data >> 4) & 0xf;
+@@ -723,14 +725,14 @@ static int dsi_14nm_pll_restore_state(struct msm_dsi_phy *phy)
+ DBG("DSI%d PLL restore state %x %x", pll_14nm->phy->id,
+ cached_state->n1postdiv, cached_state->n2postdiv);
+
+- dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
++ writel(data, cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
+
+ /* also restore post-dividers for slave DSI PLL */
+ if (phy->usecase == MSM_DSI_PHY_MASTER) {
+ struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
+ void __iomem *slave_base = pll_14nm_slave->phy->base;
+
+- dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
++ writel(data, slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
+ }
+
+ return 0;
+@@ -758,9 +760,9 @@ static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy)
+ return -EINVAL;
+ }
+
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN, clkbuflr_en);
++ writel(clkbuflr_en, base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN);
+ if (bandgap)
+- dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap);
++ writel(bandgap, base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP);
+
+ return 0;
+ }
+@@ -917,27 +919,27 @@ static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy,
+ u32 halfbyte_en = clk_ln ? timing->hs_halfbyte_en_ckln :
+ timing->hs_halfbyte_en;
+
+- dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(lane_idx),
+- DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit));
+- dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(lane_idx),
+- DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(zero));
+- dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(lane_idx),
+- DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(prepare));
+- dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(lane_idx),
+- DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(trail));
+- dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(lane_idx),
+- DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(rqst));
+- dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG0(lane_idx),
+- DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(prep_dly));
+- dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG1(lane_idx),
+- halfbyte_en ? DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN : 0);
+- dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(lane_idx),
+- DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(timing->ta_go) |
+- DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(timing->ta_sure));
+- dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(lane_idx),
+- DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(timing->ta_get));
+- dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(lane_idx),
+- DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(0xa0));
++ writel(DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit),
++ base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(lane_idx));
++ writel(DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(zero),
++ base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(lane_idx));
++ writel(DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(prepare),
++ base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(lane_idx));
++ writel(DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(trail),
++ base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(lane_idx));
++ writel(DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(rqst),
++ base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(lane_idx));
++ writel(DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(prep_dly),
++ base + REG_DSI_14nm_PHY_LN_CFG0(lane_idx));
++ writel(halfbyte_en ? DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN : 0,
++ base + REG_DSI_14nm_PHY_LN_CFG1(lane_idx));
++ writel(DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(timing->ta_go) |
++ DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(timing->ta_sure),
++ base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(lane_idx));
++ writel(DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(timing->ta_get),
++ base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(lane_idx));
++ writel(DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(0xa0),
++ base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(lane_idx));
+ }
+
+ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy,
+@@ -961,49 +963,44 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy,
+ data = 0x1c;
+ if (phy->usecase != MSM_DSI_PHY_STANDALONE)
+ data |= DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(32);
+- dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data);
++ writel(data, base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL);
+
+- dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0x1);
++ writel(0x1, base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
+
+ /* 4 data lanes + 1 clk lane configuration */
+ for (i = 0; i < 5; i++) {
+- dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_VREG_CNTRL(i),
+- 0x1d);
+-
+- dsi_phy_write(lane_base +
+- REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(i), 0xff);
+- dsi_phy_write(lane_base +
+- REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(i),
+- (i == PHY_14NM_CKLN_IDX) ? 0x00 : 0x06);
+-
+- dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG3(i),
+- (i == PHY_14NM_CKLN_IDX) ? 0x8f : 0x0f);
+- dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG2(i), 0x10);
+- dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_DATAPATH(i),
+- 0);
+- dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_STR(i),
+- 0x88);
++ writel(0x1d, lane_base + REG_DSI_14nm_PHY_LN_VREG_CNTRL(i));
++
++ writel(0xff, lane_base + REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(i));
++ writel(i == PHY_14NM_CKLN_IDX ? 0x00 : 0x06,
++ lane_base + REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(i));
++
++ writel(i == PHY_14NM_CKLN_IDX ? 0x8f : 0x0f,
++ lane_base + REG_DSI_14nm_PHY_LN_CFG3(i));
++ writel(0x10, lane_base + REG_DSI_14nm_PHY_LN_CFG2(i));
++ writel(0, lane_base + REG_DSI_14nm_PHY_LN_TEST_DATAPATH(i));
++ writel(0x88, lane_base + REG_DSI_14nm_PHY_LN_TEST_STR(i));
+
+ dsi_14nm_dphy_set_timing(phy, timing, i);
+ }
+
+ /* Make sure PLL is not start */
+- dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0x00);
++ writel(0x00, base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL);
+
+ wmb(); /* make sure everything is written before reset and enable */
+
+ /* reset digital block */
+- dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x80);
++ writel(0x80, base + REG_DSI_14nm_PHY_CMN_CTRL_1);
+ wmb(); /* ensure reset is asserted */
+ udelay(100);
+- dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00);
++ writel(0x00, base + REG_DSI_14nm_PHY_CMN_CTRL_1);
+
+- glbl_test_ctrl = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
++ glbl_test_ctrl = readl(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
+ if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_SLAVE)
+ glbl_test_ctrl |= DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
+ else
+ glbl_test_ctrl &= ~DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
+- dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, glbl_test_ctrl);
++ writel(glbl_test_ctrl, base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
+ ret = dsi_14nm_set_usecase(phy);
+ if (ret) {
+ DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
+@@ -1012,15 +1009,15 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy,
+ }
+
+ /* Remove power down from PLL and all lanes */
+- dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0xff);
++ writel(0xff, base + REG_DSI_14nm_PHY_CMN_CTRL_0);
+
+ return 0;
+ }
+
+ static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy)
+ {
+- dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0);
+- dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0);
++ writel(0, phy->base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
++ writel(0, phy->base + REG_DSI_14nm_PHY_CMN_CTRL_0);
+
+ /* ensure that the phy is completely disabled */
+ wmb();
+diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
+index c9752b9917445..cee34b76c3d21 100644
+--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
++++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
+@@ -12,32 +12,32 @@ static void dsi_20nm_dphy_set_timing(struct msm_dsi_phy *phy,
+ {
+ void __iomem *base = phy->base;
+
+- dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0,
+- DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero));
+- dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1,
+- DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail));
+- dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2,
+- DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare));
++ writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero),
++ base + REG_DSI_20nm_PHY_TIMING_CTRL_0);
++ writel(DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail),
++ base + REG_DSI_20nm_PHY_TIMING_CTRL_1);
++ writel(DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare),
++ base + REG_DSI_20nm_PHY_TIMING_CTRL_2);
+ if (timing->clk_zero & BIT(8))
+- dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3,
+- DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8);
+- dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4,
+- DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit));
+- dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5,
+- DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero));
+- dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6,
+- DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare));
+- dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7,
+- DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail));
+- dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_8,
+- DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst));
+- dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_9,
+- DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
+- DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure));
+- dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_10,
+- DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get));
+- dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_11,
+- DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0));
++ writel(DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8,
++ base + REG_DSI_20nm_PHY_TIMING_CTRL_3);
++ writel(DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit),
++ base + REG_DSI_20nm_PHY_TIMING_CTRL_4);
++ writel(DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero),
++ base + REG_DSI_20nm_PHY_TIMING_CTRL_5);
++ writel(DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare),
++ base + REG_DSI_20nm_PHY_TIMING_CTRL_6);
++ writel(DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail),
++ base + REG_DSI_20nm_PHY_TIMING_CTRL_7);
++ writel(DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst),
++ base + REG_DSI_20nm_PHY_TIMING_CTRL_8);
++ writel(DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
++ DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure),
++ base + REG_DSI_20nm_PHY_TIMING_CTRL_9);
++ writel(DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get),
++ base + REG_DSI_20nm_PHY_TIMING_CTRL_10);
++ writel(DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0),
++ base + REG_DSI_20nm_PHY_TIMING_CTRL_11);
+ }
+
+ static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
+@@ -45,23 +45,23 @@ static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
+ void __iomem *base = phy->reg_base;
+
+ if (!enable) {
+- dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0);
++ writel(0, base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG);
+ return;
+ }
+
+ if (phy->regulator_ldo_mode) {
+- dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x1d);
++ writel(0x1d, phy->base + REG_DSI_20nm_PHY_LDO_CNTRL);
+ return;
+ }
+
+ /* non LDO mode */
+- dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_1, 0x03);
+- dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_2, 0x03);
+- dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_3, 0x00);
+- dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_4, 0x20);
+- dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0x01);
+- dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x00);
+- dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0, 0x03);
++ writel(0x03, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_1);
++ writel(0x03, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_2);
++ writel(0x00, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_3);
++ writel(0x20, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_4);
++ writel(0x01, base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG);
++ writel(0x00, phy->base + REG_DSI_20nm_PHY_LDO_CNTRL);
++ writel(0x03, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0);
+ }
+
+ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy,
+@@ -83,49 +83,48 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy,
+
+ dsi_20nm_phy_regulator_ctrl(phy, true);
+
+- dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff);
++ writel(0xff, base + REG_DSI_20nm_PHY_STRENGTH_0);
+
+- val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);
++ val = readl(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);
+ if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_STANDALONE)
+ val |= DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
+ else
+ val &= ~DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
+- dsi_phy_write(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL, val);
++ writel(val, base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);
+
+ for (i = 0; i < 4; i++) {
+- dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i),
+- (i >> 1) * 0x40);
+- dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_0(i), 0x01);
+- dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_1(i), 0x46);
+- dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_0(i), 0x02);
+- dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_1(i), 0xa0);
+- dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_4(i), cfg_4[i]);
++ writel((i >> 1) * 0x40, base + REG_DSI_20nm_PHY_LN_CFG_3(i));
++ writel(0x01, base + REG_DSI_20nm_PHY_LN_TEST_STR_0(i));
++ writel(0x46, base + REG_DSI_20nm_PHY_LN_TEST_STR_1(i));
++ writel(0x02, base + REG_DSI_20nm_PHY_LN_CFG_0(i));
++ writel(0xa0, base + REG_DSI_20nm_PHY_LN_CFG_1(i));
++ writel(cfg_4[i], base + REG_DSI_20nm_PHY_LN_CFG_4(i));
+ }
+
+- dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_3, 0x80);
+- dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR0, 0x01);
+- dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR1, 0x46);
+- dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_0, 0x00);
+- dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_1, 0xa0);
+- dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_2, 0x00);
+- dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_4, 0x00);
++ writel(0x80, base + REG_DSI_20nm_PHY_LNCK_CFG_3);
++ writel(0x01, base + REG_DSI_20nm_PHY_LNCK_TEST_STR0);
++ writel(0x46, base + REG_DSI_20nm_PHY_LNCK_TEST_STR1);
++ writel(0x00, base + REG_DSI_20nm_PHY_LNCK_CFG_0);
++ writel(0xa0, base + REG_DSI_20nm_PHY_LNCK_CFG_1);
++ writel(0x00, base + REG_DSI_20nm_PHY_LNCK_CFG_2);
++ writel(0x00, base + REG_DSI_20nm_PHY_LNCK_CFG_4);
+
+ dsi_20nm_dphy_set_timing(phy, timing);
+
+- dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_1, 0x00);
++ writel(0x00, base + REG_DSI_20nm_PHY_CTRL_1);
+
+- dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_1, 0x06);
++ writel(0x06, base + REG_DSI_20nm_PHY_STRENGTH_1);
+
+ /* make sure everything is written before enable */
+ wmb();
+- dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_0, 0x7f);
++ writel(0x7f, base + REG_DSI_20nm_PHY_CTRL_0);
+
+ return 0;
+ }
+
+ static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy)
+ {
+- dsi_phy_write(phy->base + REG_DSI_20nm_PHY_CTRL_0, 0);
++ writel(0, phy->base + REG_DSI_20nm_PHY_CTRL_0);
+ dsi_20nm_phy_regulator_ctrl(phy, false);
+ }
+
+diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+index ceec7bb87bf13..b3e914954f4a4 100644
+--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
++++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+@@ -83,7 +83,7 @@ static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,
+ u32 val;
+
+ while (nb_tries--) {
+- val = dsi_phy_read(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_STATUS);
++ val = readl(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_STATUS);
+ pll_locked = !!(val & DSI_28nm_PHY_PLL_STATUS_PLL_RDY);
+
+ if (pll_locked)
+@@ -128,7 +128,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ VERB("rate=%lu, parent's=%lu", rate, parent_rate);
+
+ /* Force postdiv2 to be div-4 */
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3);
++ writel(3, base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG);
+
+ /* Configure the Loop filter resistance */
+ for (i = 0; i < LPFR_LUT_SIZE; i++)
+@@ -139,11 +139,11 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ rate);
+ return -EINVAL;
+ }
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance);
++ writel(lpfr_lut[i].resistance, base + REG_DSI_28nm_PHY_PLL_LPFR_CFG);
+
+ /* Loop filter capacitance values : c1 and c2 */
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
++ writel(0x70, base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG);
++ writel(0x15, base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG);
+
+ rem = rate % VCO_REF_CLK_RATE;
+ if (rem) {
+@@ -168,7 +168,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+
+ DBG("Generated VCO Clock: %lu", gen_vco_clk);
+ rem = 0;
+- sdm_cfg1 = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1);
++ sdm_cfg1 = readl(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1);
+ sdm_cfg1 &= ~DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
+ if (frac_n_mode) {
+ sdm_cfg0 = 0x0;
+@@ -195,17 +195,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ cal_cfg10 = (u32)((gen_vco_clk % (256 * 1000000)) / 1000000);
+ DBG("cal_cfg10=%d, cal_cfg11=%d", cal_cfg10, cal_cfg11);
+
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG4, 0x06);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
++ writel(0x02, base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG);
++ writel(0x2b, base + REG_DSI_28nm_PHY_PLL_CAL_CFG3);
++ writel(0x06, base + REG_DSI_28nm_PHY_PLL_CAL_CFG4);
++ writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);
+
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2,
+- DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(sdm_cfg2));
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3,
+- DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(sdm_cfg3));
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00);
++ writel(sdm_cfg1, base + REG_DSI_28nm_PHY_PLL_SDM_CFG1);
++ writel(DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(sdm_cfg2),
++ base + REG_DSI_28nm_PHY_PLL_SDM_CFG2);
++ writel(DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(sdm_cfg3),
++ base + REG_DSI_28nm_PHY_PLL_SDM_CFG3);
++ writel(0, base + REG_DSI_28nm_PHY_PLL_SDM_CFG4);
+
+ /* Add hardware recommended delay for correct PLL configuration */
+ if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
+@@ -213,18 +213,18 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ else
+ udelay(1);
+
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG, 0x31);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG0, 0x12);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG6, 0x30);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG7, 0x00);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG8, 0x60);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG9, 0x00);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG10, cal_cfg10 & 0xff);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG11, cal_cfg11 & 0xff);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG, 0x20);
++ writel(refclk_cfg, base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG);
++ writel(0x00, base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG);
++ writel(0x31, base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG);
++ writel(sdm_cfg0, base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
++ writel(0x12, base + REG_DSI_28nm_PHY_PLL_CAL_CFG0);
++ writel(0x30, base + REG_DSI_28nm_PHY_PLL_CAL_CFG6);
++ writel(0x00, base + REG_DSI_28nm_PHY_PLL_CAL_CFG7);
++ writel(0x60, base + REG_DSI_28nm_PHY_PLL_CAL_CFG8);
++ writel(0x00, base + REG_DSI_28nm_PHY_PLL_CAL_CFG9);
++ writel(cal_cfg10 & 0xff, base + REG_DSI_28nm_PHY_PLL_CAL_CFG10);
++ writel(cal_cfg11 & 0xff, base + REG_DSI_28nm_PHY_PLL_CAL_CFG11);
++ writel(0x20, base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG);
+
+ return 0;
+ }
+@@ -250,27 +250,27 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
+ VERB("parent_rate=%lu", parent_rate);
+
+ /* Check to see if the ref clk doubler is enabled */
+- doubler = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
++ doubler = readl(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
+ DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
+ ref_clk += (doubler * VCO_REF_CLK_RATE);
+
+ /* see if it is integer mode or sdm mode */
+- sdm0 = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
++ sdm0 = readl(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
+ if (sdm0 & DSI_28nm_PHY_PLL_SDM_CFG0_BYP) {
+ /* integer mode */
+ sdm_byp_div = FIELD(
+- dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0),
++ readl(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0),
+ DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV) + 1;
+ vco_rate = ref_clk * sdm_byp_div;
+ } else {
+ /* sdm mode */
+ sdm_dc_off = FIELD(
+- dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1),
++ readl(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1),
+ DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET);
+ DBG("sdm_dc_off = %d", sdm_dc_off);
+- sdm2 = FIELD(dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2),
++ sdm2 = FIELD(readl(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2),
+ DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0);
+- sdm3 = FIELD(dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3),
++ sdm3 = FIELD(readl(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3),
+ DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8);
+ sdm_freq_seed = (sdm3 << 8) | sdm2;
+ DBG("sdm_freq_seed = %d", sdm_freq_seed);
+@@ -318,7 +318,7 @@ static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm *pll_28nm)
+ /* DSI Uniphy lock detect setting */
+ dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2,
+ 0x0c, 100);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
++ writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);
+
+ /* poll for PLL ready status */
+ locked = pll_28nm_poll_for_ready(pll_28nm, max_reads,
+@@ -396,7 +396,7 @@ static int dsi_pll_28nm_vco_prepare_8226(struct clk_hw *hw)
+ * PLL power up sequence.
+ * Add necessary delays recommended by hardware.
+ */
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34);
++ writel(0x34, base + REG_DSI_28nm_PHY_PLL_CAL_CFG1);
+
+ val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
+ dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
+@@ -410,10 +410,10 @@ static int dsi_pll_28nm_vco_prepare_8226(struct clk_hw *hw)
+
+ for (i = 0; i < 7; i++) {
+ /* DSI Uniphy lock detect setting */
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
++ writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);
+ dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2,
+ 0x0c, 100);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
++ writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);
+
+ /* poll for PLL ready status */
+ locked = pll_28nm_poll_for_ready(pll_28nm,
+@@ -504,7 +504,7 @@ static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
+ if (unlikely(!pll_28nm->phy->pll_on))
+ return;
+
+- dsi_phy_write(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);
++ writel(0, pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
+
+ pll_28nm->phy->pll_on = false;
+ }
+@@ -560,10 +560,10 @@ static void dsi_28nm_pll_save_state(struct msm_dsi_phy *phy)
+ void __iomem *base = pll_28nm->phy->pll_base;
+
+ cached_state->postdiv3 =
+- dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG);
++ readl(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG);
+ cached_state->postdiv1 =
+- dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG);
+- cached_state->byte_mux = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG);
++ readl(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG);
++ cached_state->byte_mux = readl(base + REG_DSI_28nm_PHY_PLL_VREG_CFG);
+ if (dsi_pll_28nm_clk_is_enabled(phy->vco_hw))
+ cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
+ else
+@@ -585,12 +585,9 @@ static int dsi_28nm_pll_restore_state(struct msm_dsi_phy *phy)
+ return ret;
+ }
+
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
+- cached_state->postdiv3);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG,
+- cached_state->postdiv1);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_VREG_CFG,
+- cached_state->byte_mux);
++ writel(cached_state->postdiv3, base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG);
++ writel(cached_state->postdiv1, base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG);
++ writel(cached_state->byte_mux, base + REG_DSI_28nm_PHY_PLL_VREG_CFG);
+
+ return 0;
+ }
+@@ -700,72 +697,71 @@ static void dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy,
+ {
+ void __iomem *base = phy->base;
+
+- dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_0,
+- DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero));
+- dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_1,
+- DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail));
+- dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_2,
+- DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare));
++ writel(DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero),
++ base + REG_DSI_28nm_PHY_TIMING_CTRL_0);
++ writel(DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail),
++ base + REG_DSI_28nm_PHY_TIMING_CTRL_1);
++ writel(DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare),
++ base + REG_DSI_28nm_PHY_TIMING_CTRL_2);
+ if (timing->clk_zero & BIT(8))
+- dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_3,
+- DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_4,
+- DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit));
+- dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_5,
+- DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero));
+- dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_6,
+- DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare));
+- dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_7,
+- DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail));
+- dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_8,
+- DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst));
+- dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_9,
+- DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
+- DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure));
+- dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_10,
+- DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get));
+- dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_11,
+- DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0));
++ writel(DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8,
++ base + REG_DSI_28nm_PHY_TIMING_CTRL_3);
++ writel(DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit),
++ base + REG_DSI_28nm_PHY_TIMING_CTRL_4);
++ writel(DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero),
++ base + REG_DSI_28nm_PHY_TIMING_CTRL_5);
++ writel(DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare),
++ base + REG_DSI_28nm_PHY_TIMING_CTRL_6);
++ writel(DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail),
++ base + REG_DSI_28nm_PHY_TIMING_CTRL_7);
++ writel(DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst),
++ base + REG_DSI_28nm_PHY_TIMING_CTRL_8);
++ writel(DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
++ DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure),
++ base + REG_DSI_28nm_PHY_TIMING_CTRL_9);
++ writel(DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get),
++ base + REG_DSI_28nm_PHY_TIMING_CTRL_10);
++ writel(DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0),
++ base + REG_DSI_28nm_PHY_TIMING_CTRL_11);
+ }
+
+ static void dsi_28nm_phy_regulator_enable_dcdc(struct msm_dsi_phy *phy)
+ {
+ void __iomem *base = phy->reg_base;
+
+- dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 1);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x3);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x9);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x7);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20);
+- dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x00);
++ writel(0x0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0);
++ writel(1, base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG);
++ writel(0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5);
++ writel(0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3);
++ writel(0x3, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2);
++ writel(0x9, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1);
++ writel(0x7, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0);
++ writel(0x20, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4);
++ writel(0x00, phy->base + REG_DSI_28nm_PHY_LDO_CNTRL);
+ }
+
+ static void dsi_28nm_phy_regulator_enable_ldo(struct msm_dsi_phy *phy)
+ {
+ void __iomem *base = phy->reg_base;
+
+- dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0x7);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x1);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x1);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20);
++ writel(0x0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0);
++ writel(0, base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG);
++ writel(0x7, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5);
++ writel(0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3);
++ writel(0x1, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2);
++ writel(0x1, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1);
++ writel(0x20, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4);
+
+ if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
+- dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x05);
++ writel(0x05, phy->base + REG_DSI_28nm_PHY_LDO_CNTRL);
+ else
+- dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x0d);
++ writel(0x0d, phy->base + REG_DSI_28nm_PHY_LDO_CNTRL);
+ }
+
+ static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
+ {
+ if (!enable) {
+- dsi_phy_write(phy->reg_base +
+- REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0);
++ writel(0, phy->reg_base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG);
+ return;
+ }
+
+@@ -792,49 +788,49 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy,
+ return -EINVAL;
+ }
+
+- dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_0, 0xff);
++ writel(0xff, base + REG_DSI_28nm_PHY_STRENGTH_0);
+
+ dsi_28nm_phy_regulator_ctrl(phy, true);
+
+ dsi_28nm_dphy_set_timing(phy, timing);
+
+- dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_1, 0x00);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f);
++ writel(0x00, base + REG_DSI_28nm_PHY_CTRL_1);
++ writel(0x5f, base + REG_DSI_28nm_PHY_CTRL_0);
+
+- dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_1, 0x6);
++ writel(0x6, base + REG_DSI_28nm_PHY_STRENGTH_1);
+
+ for (i = 0; i < 4; i++) {
+- dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_0(i), 0);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_1(i), 0);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_2(i), 0);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_3(i), 0);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(i), 0);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i), 0);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i), 0);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i), 0x1);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i), 0x97);
++ writel(0, base + REG_DSI_28nm_PHY_LN_CFG_0(i));
++ writel(0, base + REG_DSI_28nm_PHY_LN_CFG_1(i));
++ writel(0, base + REG_DSI_28nm_PHY_LN_CFG_2(i));
++ writel(0, base + REG_DSI_28nm_PHY_LN_CFG_3(i));
++ writel(0, base + REG_DSI_28nm_PHY_LN_CFG_4(i));
++ writel(0, base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i));
++ writel(0, base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i));
++ writel(0x1, base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i));
++ writel(0x97, base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i));
+ }
+
+- dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_4, 0);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_1, 0xc0);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR0, 0x1);
+- dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR1, 0xbb);
++ writel(0, base + REG_DSI_28nm_PHY_LNCK_CFG_4);
++ writel(0xc0, base + REG_DSI_28nm_PHY_LNCK_CFG_1);
++ writel(0x1, base + REG_DSI_28nm_PHY_LNCK_TEST_STR0);
++ writel(0xbb, base + REG_DSI_28nm_PHY_LNCK_TEST_STR1);
+
+- dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f);
++ writel(0x5f, base + REG_DSI_28nm_PHY_CTRL_0);
+
+- val = dsi_phy_read(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL);
++ val = readl(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL);
+ if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_SLAVE)
+ val &= ~DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
+ else
+ val |= DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
+- dsi_phy_write(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL, val);
++ writel(val, base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL);
+
+ return 0;
+ }
+
+ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
+ {
+- dsi_phy_write(phy->base + REG_DSI_28nm_PHY_CTRL_0, 0);
++ writel(0, phy->base + REG_DSI_28nm_PHY_CTRL_0);
+ dsi_28nm_phy_regulator_ctrl(phy, false);
+
+ /*
+diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+index 26c08047e20c8..5311ab7f3c709 100644
+--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
++++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+@@ -74,7 +74,7 @@ static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,
+ u32 val;
+
+ while (nb_tries--) {
+- val = dsi_phy_read(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_RDY);
++ val = readl(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_RDY);
+ pll_locked = !!(val & DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY);
+
+ if (pll_locked)
+@@ -103,30 +103,25 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ val = VCO_REF_CLK_RATE / 10;
+ fb_divider = (temp * VCO_PREF_DIV_RATIO) / val;
+ fb_divider = fb_divider / 2 - 1;
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1,
+- fb_divider & 0xff);
++ writel(fb_divider & 0xff, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1);
+
+- val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2);
++ val = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2);
+
+ val |= (fb_divider >> 8) & 0x07;
+
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2,
+- val);
++ writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2);
+
+- val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
++ val = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
+
+ val |= (VCO_PREF_DIV_RATIO - 1) & 0x3f;
+
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3,
+- val);
++ writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
+
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6,
+- 0xf);
++ writel(0xf, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6);
+
+- val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
++ val = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
+ val |= 0x7 << 4;
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8,
+- val);
++ writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
+
+ return 0;
+ }
+@@ -149,16 +144,16 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
+
+ VERB("parent_rate=%lu", parent_rate);
+
+- status = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0);
++ status = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0);
+
+ if (status & DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE) {
+- fb_divider = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1);
++ fb_divider = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1);
+ fb_divider &= 0xff;
+- temp = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07;
++ temp = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07;
+ fb_divider = (temp << 8) | fb_divider;
+ fb_divider += 1;
+
+- ref_divider = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
++ ref_divider = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
+ ref_divider &= 0x3f;
+ ref_divider += 1;
+
+@@ -195,18 +190,18 @@ static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw)
+ * 2: divide by 8 to get bit clock divider
+ * 3: write it to POSTDIV1
+ */
+- val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
++ val = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
+ byte_div = val + 1;
+ bit_div = byte_div / 8;
+
+- val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
++ val = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
+ val &= ~0xf;
+ val |= (bit_div - 1);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val);
++ writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
+
+ /* enable the PLL */
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0,
+- DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE);
++ writel(DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE,
++ base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0);
+
+ locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
+
+@@ -230,7 +225,7 @@ static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw)
+ if (unlikely(!pll_28nm->phy->pll_on))
+ return;
+
+- dsi_phy_write(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00);
++ writel(0x00, pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0);
+
+ pll_28nm->phy->pll_on = false;
+ }
+@@ -277,7 +272,7 @@ static unsigned long clk_bytediv_recalc_rate(struct clk_hw *hw,
+ struct clk_bytediv *bytediv = to_clk_bytediv(hw);
+ unsigned int div;
+
+- div = dsi_phy_read(bytediv->reg) & 0xff;
++ div = readl(bytediv->reg) & 0xff;
+
+ return parent_rate / (div + 1);
+ }
+@@ -323,9 +318,9 @@ static int clk_bytediv_set_rate(struct clk_hw *hw, unsigned long rate,
+
+ factor = get_vco_mul_factor(rate);
+
+- val = dsi_phy_read(bytediv->reg);
++ val = readl(bytediv->reg);
+ val |= (factor - 1) & 0xff;
+- dsi_phy_write(bytediv->reg, val);
++ writel(val, bytediv->reg);
+
+ return 0;
+ }
+@@ -347,11 +342,11 @@ static void dsi_28nm_pll_save_state(struct msm_dsi_phy *phy)
+ void __iomem *base = pll_28nm->phy->pll_base;
+
+ cached_state->postdiv3 =
+- dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10);
++ readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10);
+ cached_state->postdiv2 =
+- dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
++ readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
+ cached_state->postdiv1 =
+- dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
++ readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
+
+ cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
+ }
+@@ -371,12 +366,9 @@ static int dsi_28nm_pll_restore_state(struct msm_dsi_phy *phy)
+ return ret;
+ }
+
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10,
+- cached_state->postdiv3);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9,
+- cached_state->postdiv2);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8,
+- cached_state->postdiv1);
++ writel(cached_state->postdiv3, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10);
++ writel(cached_state->postdiv2, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
++ writel(cached_state->postdiv1, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
+
+ return 0;
+ }
+@@ -477,53 +469,52 @@ static void dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy,
+ {
+ void __iomem *base = phy->base;
+
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_0,
+- DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero));
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_1,
+- DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail));
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_2,
+- DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare));
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_3, 0x0);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_4,
+- DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit));
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_5,
+- DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero));
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_6,
+- DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare));
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_7,
+- DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail));
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_8,
+- DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst));
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_9,
+- DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
+- DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure));
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_10,
+- DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get));
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_11,
+- DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(0));
++ writel(DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero),
++ base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_0);
++ writel(DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail),
++ base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_1);
++ writel(DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare),
++ base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_2);
++ writel(0, base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_3);
++ writel(DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit),
++ base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_4);
++ writel(DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero),
++ base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_5);
++ writel(DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare),
++ base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_6);
++ writel(DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail),
++ base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_7);
++ writel(DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst),
++ base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_8);
++ writel(DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
++ DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure),
++ base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_9);
++ writel(DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get),
++ base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_10);
++ writel(DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(0),
++ base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_11);
+ }
+
+ static void dsi_28nm_phy_regulator_init(struct msm_dsi_phy *phy)
+ {
+ void __iomem *base = phy->reg_base;
+
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0, 0x3);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1, 1);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2, 1);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3, 0);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4,
+- 0x100);
++ writel(0x3, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0);
++ writel(1, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1);
++ writel(1, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2);
++ writel(0, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3);
++ writel(0x100, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4);
+ }
+
+ static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy)
+ {
+ void __iomem *base = phy->reg_base;
+
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0, 0x3);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1, 0xa);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2, 0x4);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3, 0x0);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4, 0x20);
++ writel(0x3, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0);
++ writel(0xa, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1);
++ writel(0x4, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2);
++ writel(0x0, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3);
++ writel(0x20, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4);
+ }
+
+ static void dsi_28nm_phy_calibration(struct msm_dsi_phy *phy)
+@@ -532,21 +523,20 @@ static void dsi_28nm_phy_calibration(struct msm_dsi_phy *phy)
+ u32 status;
+ int i = 5000;
+
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG,
+- 0x3);
++ writel(0x3, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG);
+
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2, 0x0);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1, 0x5a);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3, 0x10);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4, 0x1);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0, 0x1);
++ writel(0x0, base + REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2);
++ writel(0x5a, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1);
++ writel(0x10, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3);
++ writel(0x1, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4);
++ writel(0x1, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0);
+
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER, 0x1);
++ writel(0x1, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER);
+ usleep_range(5000, 6000);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER, 0x0);
++ writel(0x0, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER);
+
+ do {
+- status = dsi_phy_read(base +
++ status = readl(base +
+ REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS);
+
+ if (!(status & DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY))
+@@ -562,23 +552,20 @@ static void dsi_28nm_phy_lane_config(struct msm_dsi_phy *phy)
+ int i;
+
+ for (i = 0; i < 4; i++) {
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_CFG_0(i), 0x80);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_CFG_1(i), 0x45);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_CFG_2(i), 0x00);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(i),
+- 0x00);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(i),
+- 0x01);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(i),
+- 0x66);
++ writel(0x80, base + REG_DSI_28nm_8960_PHY_LN_CFG_0(i));
++ writel(0x45, base + REG_DSI_28nm_8960_PHY_LN_CFG_1(i));
++ writel(0x00, base + REG_DSI_28nm_8960_PHY_LN_CFG_2(i));
++ writel(0x00, base + REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(i));
++ writel(0x01, base + REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(i));
++ writel(0x66, base + REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(i));
+ }
+
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_CFG_0, 0x40);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_CFG_1, 0x67);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_CFG_2, 0x0);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH, 0x0);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0, 0x1);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1, 0x88);
++ writel(0x40, base + REG_DSI_28nm_8960_PHY_LNCK_CFG_0);
++ writel(0x67, base + REG_DSI_28nm_8960_PHY_LNCK_CFG_1);
++ writel(0x0, base + REG_DSI_28nm_8960_PHY_LNCK_CFG_2);
++ writel(0x0, base + REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH);
++ writel(0x1, base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0);
++ writel(0x88, base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1);
+ }
+
+ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy,
+@@ -598,18 +585,18 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy,
+
+ dsi_28nm_phy_regulator_init(phy);
+
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LDO_CTRL, 0x04);
++ writel(0x04, base + REG_DSI_28nm_8960_PHY_LDO_CTRL);
+
+ /* strength control */
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_STRENGTH_0, 0xff);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_STRENGTH_1, 0x00);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_STRENGTH_2, 0x06);
++ writel(0xff, base + REG_DSI_28nm_8960_PHY_STRENGTH_0);
++ writel(0x00, base + REG_DSI_28nm_8960_PHY_STRENGTH_1);
++ writel(0x06, base + REG_DSI_28nm_8960_PHY_STRENGTH_2);
+
+ /* phy ctrl */
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_0, 0x5f);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_1, 0x00);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_2, 0x00);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_3, 0x10);
++ writel(0x5f, base + REG_DSI_28nm_8960_PHY_CTRL_0);
++ writel(0x00, base + REG_DSI_28nm_8960_PHY_CTRL_1);
++ writel(0x00, base + REG_DSI_28nm_8960_PHY_CTRL_2);
++ writel(0x10, base + REG_DSI_28nm_8960_PHY_CTRL_3);
+
+ dsi_28nm_phy_regulator_ctrl(phy);
+
+@@ -617,10 +604,10 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy,
+
+ dsi_28nm_phy_lane_config(phy);
+
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_4, 0x0f);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_1, 0x03);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_0, 0x03);
+- dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_4, 0x0);
++ writel(0x0f, base + REG_DSI_28nm_8960_PHY_BIST_CTRL_4);
++ writel(0x03, base + REG_DSI_28nm_8960_PHY_BIST_CTRL_1);
++ writel(0x03, base + REG_DSI_28nm_8960_PHY_BIST_CTRL_0);
++ writel(0x0, base + REG_DSI_28nm_8960_PHY_BIST_CTRL_4);
+
+ dsi_28nm_dphy_set_timing(phy, timing);
+
+@@ -629,7 +616,7 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy,
+
+ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
+ {
+- dsi_phy_write(phy->base + REG_DSI_28nm_8960_PHY_CTRL_0, 0x0);
++ writel(0x0, phy->base + REG_DSI_28nm_8960_PHY_CTRL_0);
+
+ /*
+ * Wait for the registers writes to complete in order to
+diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+index f72ce6a3c456d..8e2af844d240d 100644
+--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
++++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+@@ -204,20 +204,20 @@ static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *c
+ if (config->enable_ssc) {
+ pr_debug("SSC is enabled\n");
+
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
+- config->ssc_stepsize & 0xff);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
+- config->ssc_stepsize >> 8);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1,
+- config->ssc_div_per & 0xff);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
+- config->ssc_div_per >> 8);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1,
+- config->ssc_adj_per & 0xff);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1,
+- config->ssc_adj_per >> 8);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL,
+- SSC_EN | (config->ssc_center ? SSC_CENTER : 0));
++ writel(config->ssc_stepsize & 0xff,
++ base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1);
++ writel(config->ssc_stepsize >> 8,
++ base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1);
++ writel(config->ssc_div_per & 0xff,
++ base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1);
++ writel(config->ssc_div_per >> 8,
++ base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1);
++ writel(config->ssc_adj_per & 0xff,
++ base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1);
++ writel(config->ssc_adj_per >> 8,
++ base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1);
++ writel(SSC_EN | (config->ssc_center ? SSC_CENTER : 0),
++ base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL);
+ }
+ }
+
+@@ -252,36 +252,35 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
+ vco_config_1 = 0x01;
+ }
+
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
+- analog_controls_five_1);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE, 0x01);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER, 0x00);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_OUTDIV, 0x00);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE, 0x00);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x0a);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1, 0xc0);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x84);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x29);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
+- !(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? 0x3f : 0x22);
++ writel(analog_controls_five_1, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1);
++ writel(vco_config_1, base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1);
++ writel(0x01, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE);
++ writel(0x03, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO);
++ writel(0x00, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE);
++ writel(0x00, base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER);
++ writel(0x4e, base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER);
++ writel(0x40, base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS);
++ writel(0xba, base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE);
++ writel(0x0c, base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE);
++ writel(0x00, base + REG_DSI_7nm_PHY_PLL_OUTDIV);
++ writel(0x00, base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE);
++ writel(0x08, base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO);
++ writel(0x0a, base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1);
++ writel(0xc0, base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1);
++ writel(0x84, base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1);
++ writel(0x82, base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1);
++ writel(0x4c, base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1);
++ writel(0x80, base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE);
++ writel(0x29, base + REG_DSI_7nm_PHY_PLL_PFILT);
++ writel(0x2f, base + REG_DSI_7nm_PHY_PLL_PFILT);
++ writel(0x2a, base + REG_DSI_7nm_PHY_PLL_IFILT);
++ writel(!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? 0x3f : 0x22,
++ base + REG_DSI_7nm_PHY_PLL_IFILT);
+
+ if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) {
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
++ writel(0x22, base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE);
+ if (pll->slave)
+- dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
++ writel(0x22, pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE);
+ }
+ }
+
+@@ -289,21 +288,21 @@ static void dsi_pll_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *confi
+ {
+ void __iomem *base = pll->phy->pll_base;
+
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1,
+- config->decimal_div_start);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1,
+- config->frac_div_start & 0xff);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1,
+- (config->frac_div_start & 0xff00) >> 8);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
+- (config->frac_div_start & 0x30000) >> 16);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1,
+- pll->phy->cphy_mode ? 0x00 : 0x10);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS,
+- config->pll_clock_inverters);
++ writel(0x12, base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE);
++ writel(config->decimal_div_start,
++ base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1);
++ writel(config->frac_div_start & 0xff,
++ base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1);
++ writel((config->frac_div_start & 0xff00) >> 8,
++ base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1);
++ writel((config->frac_div_start & 0x30000) >> 16,
++ base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1);
++ writel(0x40, base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1);
++ writel(0x06, base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY);
++ writel(pll->phy->cphy_mode ? 0x00 : 0x10,
++ base + REG_DSI_7nm_PHY_PLL_CMODE_1);
++ writel(config->pll_clock_inverters,
++ base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS);
+ }
+
+ static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
+@@ -357,19 +356,19 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
+
+ static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
+ {
+- u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
++ u32 data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
+
+- dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0);
+- dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5));
++ writel(0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES);
++ writel(data & ~BIT(5), pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
+ ndelay(250);
+ }
+
+ static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll)
+ {
+- u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
++ u32 data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
+
+- dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5));
+- dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
++ writel(data | BIT(5), pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
++ writel(0xc0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES);
+ ndelay(250);
+ }
+
+@@ -377,19 +376,18 @@ static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
+ {
+ u32 data;
+
+- data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+- dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5));
++ data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
++ writel(data & ~BIT(5), pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+ }
+
+ static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll)
+ {
+ u32 data;
+
+- dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04);
++ writel(0x04, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3);
+
+- data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+- dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1,
+- data | BIT(5) | BIT(4));
++ data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
++ writel(data | BIT(5) | BIT(4), pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+ }
+
+ static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll)
+@@ -399,9 +397,9 @@ static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll)
+ * coming out of a CX or analog rail power collapse while
+ * ensuring that the pads maintain LP00 or LP11 state
+ */
+- dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0));
++ writel(BIT(0), pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4);
+ wmb(); /* Ensure that the reset is deasserted */
+- dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0);
++ writel(0, pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4);
+ wmb(); /* Ensure that the reset is deasserted */
+ }
+
+@@ -415,7 +413,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
+ dsi_pll_enable_pll_bias(pll_7nm->slave);
+
+ /* Start PLL */
+- dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01);
++ writel(BIT(0), pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL);
+
+ /*
+ * ensure all PLL configurations are written prior to checking
+@@ -451,7 +449,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
+
+ static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll)
+ {
+- dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0);
++ writel(0, pll->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL);
+ dsi_pll_disable_pll_bias(pll);
+ }
+
+@@ -465,7 +463,7 @@ static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw)
+ * powering down the PLL
+ */
+ dsi_pll_disable_global_clk(pll_7nm);
+- dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0);
++ writel(0, pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL);
+ dsi_pll_disable_sub(pll_7nm);
+ if (pll_7nm->slave) {
+ dsi_pll_disable_global_clk(pll_7nm->slave);
+@@ -488,13 +486,13 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
+ u32 dec;
+ u64 pll_freq, tmp64;
+
+- dec = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1);
++ dec = readl(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1);
+ dec &= 0xff;
+
+- frac = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1);
+- frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) &
++ frac = readl(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1);
++ frac |= ((readl(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) &
+ 0xff) << 8);
+- frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
++ frac |= ((readl(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
+ 0x3) << 16);
+
+ /*
+@@ -547,15 +545,15 @@ static void dsi_7nm_pll_save_state(struct msm_dsi_phy *phy)
+ void __iomem *phy_base = pll_7nm->phy->base;
+ u32 cmn_clk_cfg0, cmn_clk_cfg1;
+
+- cached->pll_out_div = dsi_phy_read(pll_7nm->phy->pll_base +
++ cached->pll_out_div = readl(pll_7nm->phy->pll_base +
+ REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
+ cached->pll_out_div &= 0x3;
+
+- cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
++ cmn_clk_cfg0 = readl(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
+ cached->bit_clk_div = cmn_clk_cfg0 & 0xf;
+ cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4;
+
+- cmn_clk_cfg1 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
++ cmn_clk_cfg1 = readl(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+ cached->pll_mux = cmn_clk_cfg1 & 0x3;
+
+ DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
+@@ -571,18 +569,18 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy)
+ u32 val;
+ int ret;
+
+- val = dsi_phy_read(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
++ val = readl(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
+ val &= ~0x3;
+ val |= cached->pll_out_div;
+- dsi_phy_write(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val);
++ writel(val, pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
+
+- dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
+- cached->bit_clk_div | (cached->pix_clk_div << 4));
++ writel(cached->bit_clk_div | (cached->pix_clk_div << 4),
++ phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
+
+- val = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
++ val = readl(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+ val &= ~0x3;
+ val |= cached->pll_mux;
+- dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
++ writel(val, phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+
+ ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw,
+ pll_7nm->vco_current_rate,
+@@ -620,7 +618,7 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
+ }
+
+ /* set PLL src */
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2));
++ writel(data << 2, base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+
+ return 0;
+ }
+@@ -722,8 +720,8 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
+ if (pll_7nm->phy->cphy_mode) {
+ u32 data;
+
+- data = dsi_phy_read(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+- dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data | 3);
++ data = readl(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
++ writel(data | 3, pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
+
+ phy_pll_out_dsi_parent = pll_post_out_div;
+ } else {
+@@ -802,7 +800,7 @@ static int dsi_phy_hw_v4_0_is_pll_on(struct msm_dsi_phy *phy)
+ void __iomem *base = phy->base;
+ u32 data = 0;
+
+- data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL);
++ data = readl(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL);
+ mb(); /* make sure read happened */
+
+ return (data & BIT(0));
+@@ -818,11 +816,9 @@ static void dsi_phy_hw_v4_0_config_lpcdrx(struct msm_dsi_phy *phy, bool enable)
+ * corresponding to the logical data lane 0
+ */
+ if (enable)
+- dsi_phy_write(lane_base +
+- REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0x3);
++ writel(0x3, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0));
+ else
+- dsi_phy_write(lane_base +
+- REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0);
++ writel(0, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0));
+ }
+
+ static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy)
+@@ -843,18 +839,18 @@ static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy)
+ * be only enabled for the physical data lane corresponding
+ * to the logical data lane 0
+ */
+- dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(i), 0);
+- dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_PIN_SWAP(i), 0x0);
++ writel(0, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(i));
++ writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_PIN_SWAP(i));
+ }
+
+ dsi_phy_hw_v4_0_config_lpcdrx(phy, true);
+
+ /* other settings */
+ for (i = 0; i < 5; i++) {
+- dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG0(i), 0x0);
+- dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG1(i), 0x0);
+- dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG2(i), i == 4 ? 0x8a : 0xa);
+- dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_TX_DCTRL(i), tx_dctrl[i]);
++ writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_CFG0(i));
++ writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_CFG1(i));
++ writel(i == 4 ? 0x8a : 0xa, lane_base + REG_DSI_7nm_PHY_LN_CFG2(i));
++ writel(tx_dctrl[i], lane_base + REG_DSI_7nm_PHY_LN_TX_DCTRL(i));
+ }
+ }
+
+@@ -892,7 +888,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
+ /* Request for REFGEN READY */
+ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
+ (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
+- dsi_phy_write(phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1);
++ writel(0x1, phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10);
+ udelay(500);
+ }
+
+@@ -977,53 +973,53 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
+
+ /* de-assert digital and pll power down */
+ data = BIT(6) | BIT(5);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data);
++ writel(data, base + REG_DSI_7nm_PHY_CMN_CTRL_0);
+
+ /* Assert PLL core reset */
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x00);
++ writel(0x00, base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL);
+
+ /* turn off resync FIFO */
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0x00);
++ writel(0x00, base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL);
+
+ /* program CMN_CTRL_4 for minor_ver 2 chipsets*/
+ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
+- (dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) == 0x20)
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_4, 0x04);
++ (readl(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) == 0x20)
++ writel(0x04, base + REG_DSI_7nm_PHY_CMN_CTRL_4);
+
+ /* Configure PHY lane swap (TODO: we need to calculate this) */
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG0, 0x21);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG1, 0x84);
++ writel(0x21, base + REG_DSI_7nm_PHY_CMN_LANE_CFG0);
++ writel(0x84, base + REG_DSI_7nm_PHY_CMN_LANE_CFG1);
+
+ if (phy->cphy_mode)
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_CTRL, BIT(6));
++ writel(BIT(6), base + REG_DSI_7nm_PHY_CMN_GLBL_CTRL);
+
+ /* Enable LDO */
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_0, vreg_ctrl_0);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_1, vreg_ctrl_1);
+-
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x00);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL,
+- glbl_str_swi_cal_sel_ctrl);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0,
+- glbl_hstx_str_ctrl_0);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0,
+- glbl_pemph_ctrl_0);
++ writel(vreg_ctrl_0, base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_0);
++ writel(vreg_ctrl_1, base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_1);
++
++ writel(0x00, base + REG_DSI_7nm_PHY_CMN_CTRL_3);
++ writel(glbl_str_swi_cal_sel_ctrl,
++ base + REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL);
++ writel(glbl_hstx_str_ctrl_0,
++ base + REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0);
++ writel(glbl_pemph_ctrl_0,
++ base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0);
+ if (phy->cphy_mode)
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1, 0x01);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL,
+- glbl_rescode_top_ctrl);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL,
+- glbl_rescode_bot_ctrl);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL, 0x55);
++ writel(0x01, base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1);
++ writel(glbl_rescode_top_ctrl,
++ base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL);
++ writel(glbl_rescode_bot_ctrl,
++ base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL);
++ writel(0x55, base + REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL);
+
+ /* Remove power down from all blocks */
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x7f);
++ writel(0x7f, base + REG_DSI_7nm_PHY_CMN_CTRL_0);
+
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, lane_ctrl0);
++ writel(lane_ctrl0, base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0);
+
+ /* Select full-rate mode */
+ if (!phy->cphy_mode)
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_2, 0x40);
++ writel(0x40, base + REG_DSI_7nm_PHY_CMN_CTRL_2);
+
+ ret = dsi_7nm_set_usecase(phy);
+ if (ret) {
+@@ -1034,34 +1030,34 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
+
+ /* DSI PHY timings */
+ if (phy->cphy_mode) {
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0, 0x00);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4, timing->hs_exit);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5,
+- timing->shared_timings.clk_pre);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6, timing->clk_prepare);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7,
+- timing->shared_timings.clk_post);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8, timing->hs_rqst);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9, 0x02);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10, 0x04);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11, 0x00);
++ writel(0x00, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0);
++ writel(timing->hs_exit, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4);
++ writel(timing->shared_timings.clk_pre,
++ base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5);
++ writel(timing->clk_prepare, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6);
++ writel(timing->shared_timings.clk_post,
++ base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7);
++ writel(timing->hs_rqst, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8);
++ writel(0x02, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9);
++ writel(0x04, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10);
++ writel(0x00, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11);
+ } else {
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0, 0x00);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1, timing->clk_zero);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2, timing->clk_prepare);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3, timing->clk_trail);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4, timing->hs_exit);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5, timing->hs_zero);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6, timing->hs_prepare);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7, timing->hs_trail);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8, timing->hs_rqst);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9, 0x02);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10, 0x04);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11, 0x00);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12,
+- timing->shared_timings.clk_pre);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13,
+- timing->shared_timings.clk_post);
++ writel(0x00, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0);
++ writel(timing->clk_zero, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1);
++ writel(timing->clk_prepare, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2);
++ writel(timing->clk_trail, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3);
++ writel(timing->hs_exit, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4);
++ writel(timing->hs_zero, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5);
++ writel(timing->hs_prepare, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6);
++ writel(timing->hs_trail, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7);
++ writel(timing->hs_rqst, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8);
++ writel(0x02, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9);
++ writel(0x04, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10);
++ writel(0x00, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11);
++ writel(timing->shared_timings.clk_pre,
++ base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12);
++ writel(timing->shared_timings.clk_post,
++ base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13);
+ }
+
+ /* DSI lane settings */
+@@ -1077,12 +1073,12 @@ static bool dsi_7nm_set_continuous_clock(struct msm_dsi_phy *phy, bool enable)
+ void __iomem *base = phy->base;
+ u32 data;
+
+- data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL1);
++ data = readl(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL1);
+ if (enable)
+ data |= BIT(5) | BIT(6);
+ else
+ data &= ~(BIT(5) | BIT(6));
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL1, data);
++ writel(data, base + REG_DSI_7nm_PHY_CMN_LANE_CTRL1);
+
+ return enable;
+ }
+@@ -1102,21 +1098,21 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
+ /* Turn off REFGEN Vote */
+ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
+ (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0);
++ writel(0x0, base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10);
+ wmb();
+ /* Delay to ensure HW removes vote before PHY shut down */
+ udelay(2);
+ }
+
+- data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0);
++ data = readl(base + REG_DSI_7nm_PHY_CMN_CTRL_0);
+
+ /* disable all lanes */
+ data &= ~0x1F;
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data);
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, 0);
++ writel(data, base + REG_DSI_7nm_PHY_CMN_CTRL_0);
++ writel(0, base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0);
+
+ /* Turn off all PHY blocks */
+- dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x00);
++ writel(0x00, base + REG_DSI_7nm_PHY_CMN_CTRL_0);
+ /* make sure phy is turned off */
+ wmb();
+
+--
+2.39.5
+
--- /dev/null
+From a9ad28eb1ce68329995d7890f218a1b5216bb394 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 24 Oct 2023 10:08:04 -0700
+Subject: drm/msm/gem: Demote userspace errors to DRM_UT_DRIVER
+
+From: Rob Clark <robdclark@chromium.org>
+
+[ Upstream commit b2acb89af1a400be721bcb14f137aa22b509caba ]
+
+Error messages resulting from incorrect usage of the kernel uabi should
+not spam dmesg by default. But it is useful to enable them to debug
+userspace. So demote to DRM_UT_DRIVER.
+
+Signed-off-by: Rob Clark <robdclark@chromium.org>
+Patchwork: https://patchwork.freedesktop.org/patch/564189/
+Stable-dep-of: 3a47f4b439be ("drm/msm/gem: prevent integer overflow in msm_ioctl_gem_submit()")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/msm_gem.c | 6 ++---
+ drivers/gpu/drm/msm/msm_gem_submit.c | 36 ++++++++++++++++------------
+ 2 files changed, 24 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
+index db1e748daa753..1113e6b2ec8ec 100644
+--- a/drivers/gpu/drm/msm/msm_gem.c
++++ b/drivers/gpu/drm/msm/msm_gem.c
+@@ -226,9 +226,9 @@ static struct page **msm_gem_pin_pages_locked(struct drm_gem_object *obj,
+
+ msm_gem_assert_locked(obj);
+
+- if (GEM_WARN_ON(msm_obj->madv > madv)) {
+- DRM_DEV_ERROR(obj->dev->dev, "Invalid madv state: %u vs %u\n",
+- msm_obj->madv, madv);
++ if (msm_obj->madv > madv) {
++ DRM_DEV_DEBUG_DRIVER(obj->dev->dev, "Invalid madv state: %u vs %u\n",
++ msm_obj->madv, madv);
+ return ERR_PTR(-EBUSY);
+ }
+
+diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c
+index 99744de6c05a1..207b6ba1565d8 100644
+--- a/drivers/gpu/drm/msm/msm_gem_submit.c
++++ b/drivers/gpu/drm/msm/msm_gem_submit.c
+@@ -17,6 +17,12 @@
+ #include "msm_gem.h"
+ #include "msm_gpu_trace.h"
+
++/* For userspace errors, use DRM_UT_DRIVER.. so that userspace can enable
++ * error msgs for debugging, but we don't spam dmesg by default
++ */
++#define SUBMIT_ERROR(submit, fmt, ...) \
++ DRM_DEV_DEBUG_DRIVER((submit)->dev->dev, fmt, ##__VA_ARGS__)
++
+ /*
+ * Cmdstream submission:
+ */
+@@ -136,7 +142,7 @@ static int submit_lookup_objects(struct msm_gem_submit *submit,
+
+ if ((submit_bo.flags & ~MSM_SUBMIT_BO_FLAGS) ||
+ !(submit_bo.flags & MANDATORY_FLAGS)) {
+- DRM_ERROR("invalid flags: %x\n", submit_bo.flags);
++ SUBMIT_ERROR(submit, "invalid flags: %x\n", submit_bo.flags);
+ ret = -EINVAL;
+ i = 0;
+ goto out;
+@@ -158,7 +164,7 @@ static int submit_lookup_objects(struct msm_gem_submit *submit,
+ */
+ obj = idr_find(&file->object_idr, submit->bos[i].handle);
+ if (!obj) {
+- DRM_ERROR("invalid handle %u at index %u\n", submit->bos[i].handle, i);
++ SUBMIT_ERROR(submit, "invalid handle %u at index %u\n", submit->bos[i].handle, i);
+ ret = -EINVAL;
+ goto out_unlock;
+ }
+@@ -202,13 +208,13 @@ static int submit_lookup_cmds(struct msm_gem_submit *submit,
+ case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
+ break;
+ default:
+- DRM_ERROR("invalid type: %08x\n", submit_cmd.type);
++ SUBMIT_ERROR(submit, "invalid type: %08x\n", submit_cmd.type);
+ return -EINVAL;
+ }
+
+ if (submit_cmd.size % 4) {
+- DRM_ERROR("non-aligned cmdstream buffer size: %u\n",
+- submit_cmd.size);
++ SUBMIT_ERROR(submit, "non-aligned cmdstream buffer size: %u\n",
++ submit_cmd.size);
+ ret = -EINVAL;
+ goto out;
+ }
+@@ -306,8 +312,8 @@ static int submit_lock_objects(struct msm_gem_submit *submit)
+
+ fail:
+ if (ret == -EALREADY) {
+- DRM_ERROR("handle %u at index %u already on submit list\n",
+- submit->bos[i].handle, i);
++ SUBMIT_ERROR(submit, "handle %u at index %u already on submit list\n",
++ submit->bos[i].handle, i);
+ ret = -EINVAL;
+ }
+
+@@ -448,8 +454,8 @@ static int submit_bo(struct msm_gem_submit *submit, uint32_t idx,
+ struct drm_gem_object **obj, uint64_t *iova, bool *valid)
+ {
+ if (idx >= submit->nr_bos) {
+- DRM_ERROR("invalid buffer index: %u (out of %u)\n",
+- idx, submit->nr_bos);
++ SUBMIT_ERROR(submit, "invalid buffer index: %u (out of %u)\n",
++ idx, submit->nr_bos);
+ return -EINVAL;
+ }
+
+@@ -475,7 +481,7 @@ static int submit_reloc(struct msm_gem_submit *submit, struct drm_gem_object *ob
+ return 0;
+
+ if (offset % 4) {
+- DRM_ERROR("non-aligned cmdstream buffer: %u\n", offset);
++ SUBMIT_ERROR(submit, "non-aligned cmdstream buffer: %u\n", offset);
+ return -EINVAL;
+ }
+
+@@ -497,8 +503,8 @@ static int submit_reloc(struct msm_gem_submit *submit, struct drm_gem_object *ob
+ bool valid;
+
+ if (submit_reloc.submit_offset % 4) {
+- DRM_ERROR("non-aligned reloc offset: %u\n",
+- submit_reloc.submit_offset);
++ SUBMIT_ERROR(submit, "non-aligned reloc offset: %u\n",
++ submit_reloc.submit_offset);
+ ret = -EINVAL;
+ goto out;
+ }
+@@ -508,7 +514,7 @@ static int submit_reloc(struct msm_gem_submit *submit, struct drm_gem_object *ob
+
+ if ((off >= (obj->size / 4)) ||
+ (off < last_offset)) {
+- DRM_ERROR("invalid offset %u at reloc %u\n", off, i);
++ SUBMIT_ERROR(submit, "invalid offset %u at reloc %u\n", off, i);
+ ret = -EINVAL;
+ goto out;
+ }
+@@ -881,7 +887,7 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
+ if (!submit->cmd[i].size ||
+ ((submit->cmd[i].size + submit->cmd[i].offset) >
+ obj->size / 4)) {
+- DRM_ERROR("invalid cmdstream size: %u\n", submit->cmd[i].size * 4);
++ SUBMIT_ERROR(submit, "invalid cmdstream size: %u\n", submit->cmd[i].size * 4);
+ ret = -EINVAL;
+ goto out;
+ }
+@@ -893,7 +899,7 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
+
+ if (!gpu->allow_relocs) {
+ if (submit->cmd[i].nr_relocs) {
+- DRM_ERROR("relocs not allowed\n");
++ SUBMIT_ERROR(submit, "relocs not allowed\n");
+ ret = -EINVAL;
+ goto out;
+ }
+--
+2.39.5
+
--- /dev/null
+From ad2ce946e7fb77599314bcf2a5e1b6b9ead8c8c4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 15 Nov 2024 17:50:08 +0300
+Subject: drm/msm/gem: prevent integer overflow in msm_ioctl_gem_submit()
+
+From: Dan Carpenter <dan.carpenter@linaro.org>
+
+[ Upstream commit 3a47f4b439beb98e955d501c609dfd12b7836d61 ]
+
+The "submit->cmd[i].size" and "submit->cmd[i].offset" variables are u32
+values that come from the user via the submit_lookup_cmds() function.
+This addition could lead to an integer wrapping bug so use size_add()
+to prevent that.
+
+Fixes: 198725337ef1 ("drm/msm: fix cmdstream size check")
+Cc: stable@vger.kernel.org
+Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
+Patchwork: https://patchwork.freedesktop.org/patch/624696/
+Signed-off-by: Rob Clark <robdclark@chromium.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/msm_gem_submit.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c
+index 207b6ba1565d8..018b39546fc1d 100644
+--- a/drivers/gpu/drm/msm/msm_gem_submit.c
++++ b/drivers/gpu/drm/msm/msm_gem_submit.c
+@@ -885,8 +885,7 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
+ goto out;
+
+ if (!submit->cmd[i].size ||
+- ((submit->cmd[i].size + submit->cmd[i].offset) >
+- obj->size / 4)) {
++ (size_add(submit->cmd[i].size, submit->cmd[i].offset) > obj->size / 4)) {
+ SUBMIT_ERROR(submit, "invalid cmdstream size: %u\n", submit->cmd[i].size * 4);
+ ret = -EINVAL;
+ goto out;
+--
+2.39.5
+
--- /dev/null
+From 033c44b0461d42697677c63d65c48d29145ee065 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 1 Apr 2024 05:42:41 +0300
+Subject: drm/msm: generate headers on the fly
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 0fddd045f88e34d6160785a3a5e506d374566454 ]
+
+Generate DRM/MSM headers on the fly during kernel build. This removes a
+need to push register changes to Mesa with the following manual
+synchronization step. Existing headers will be removed in the following
+commits (split away to ease reviews).
+
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Patchwork: https://patchwork.freedesktop.org/patch/585862/
+Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-11-4bdb277a85a1@linaro.org
+Stable-dep-of: 588257897058 ("drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG0 updated from driver side")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/.gitignore | 1 +
+ drivers/gpu/drm/msm/Makefile | 97 ++++++++++++++++++++++++++--------
+ 2 files changed, 77 insertions(+), 21 deletions(-)
+ create mode 100644 drivers/gpu/drm/msm/.gitignore
+
+diff --git a/drivers/gpu/drm/msm/.gitignore b/drivers/gpu/drm/msm/.gitignore
+new file mode 100644
+index 0000000000000..9ab870da897d6
+--- /dev/null
++++ b/drivers/gpu/drm/msm/.gitignore
+@@ -0,0 +1 @@
++generated/
+diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
+index 8d02d8c330695..0893f44468dd6 100644
+--- a/drivers/gpu/drm/msm/Makefile
++++ b/drivers/gpu/drm/msm/Makefile
+@@ -1,10 +1,11 @@
+ # SPDX-License-Identifier: GPL-2.0
+ ccflags-y := -I $(srctree)/$(src)
++ccflags-y += -I $(obj)/generated
+ ccflags-y += -I $(srctree)/$(src)/disp/dpu1
+ ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(srctree)/$(src)/dsi
+ ccflags-$(CONFIG_DRM_MSM_DP) += -I $(srctree)/$(src)/dp
+
+-msm-y := \
++adreno-y := \
+ adreno/adreno_device.o \
+ adreno/adreno_gpu.o \
+ adreno/a2xx_gpu.o \
+@@ -17,7 +18,11 @@ msm-y := \
+ adreno/a6xx_gmu.o \
+ adreno/a6xx_hfi.o \
+
+-msm-$(CONFIG_DRM_MSM_HDMI) += \
++adreno-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \
++
++adreno-$(CONFIG_DRM_MSM_GPU_STATE) += adreno/a6xx_gpu_state.o
++
++msm-display-$(CONFIG_DRM_MSM_HDMI) += \
+ hdmi/hdmi.o \
+ hdmi/hdmi_audio.o \
+ hdmi/hdmi_bridge.o \
+@@ -30,7 +35,7 @@ msm-$(CONFIG_DRM_MSM_HDMI) += \
+ hdmi/hdmi_phy_8x74.o \
+ hdmi/hdmi_pll_8960.o \
+
+-msm-$(CONFIG_DRM_MSM_MDP4) += \
++msm-display-$(CONFIG_DRM_MSM_MDP4) += \
+ disp/mdp4/mdp4_crtc.o \
+ disp/mdp4/mdp4_dsi_encoder.o \
+ disp/mdp4/mdp4_dtv_encoder.o \
+@@ -41,7 +46,7 @@ msm-$(CONFIG_DRM_MSM_MDP4) += \
+ disp/mdp4/mdp4_kms.o \
+ disp/mdp4/mdp4_plane.o \
+
+-msm-$(CONFIG_DRM_MSM_MDP5) += \
++msm-display-$(CONFIG_DRM_MSM_MDP5) += \
+ disp/mdp5/mdp5_cfg.o \
+ disp/mdp5/mdp5_cmd_encoder.o \
+ disp/mdp5/mdp5_ctl.o \
+@@ -54,7 +59,7 @@ msm-$(CONFIG_DRM_MSM_MDP5) += \
+ disp/mdp5/mdp5_plane.o \
+ disp/mdp5/mdp5_smp.o \
+
+-msm-$(CONFIG_DRM_MSM_DPU) += \
++msm-display-$(CONFIG_DRM_MSM_DPU) += \
+ disp/dpu1/dpu_core_perf.o \
+ disp/dpu1/dpu_crtc.o \
+ disp/dpu1/dpu_encoder.o \
+@@ -83,14 +88,16 @@ msm-$(CONFIG_DRM_MSM_DPU) += \
+ disp/dpu1/dpu_vbif.o \
+ disp/dpu1/dpu_writeback.o
+
+-msm-$(CONFIG_DRM_MSM_MDSS) += \
++msm-display-$(CONFIG_DRM_MSM_MDSS) += \
+ msm_mdss.o \
+
+-msm-y += \
++msm-display-y += \
+ disp/mdp_format.o \
+ disp/mdp_kms.o \
+ disp/msm_disp_snapshot.o \
+ disp/msm_disp_snapshot_util.o \
++
++msm-y += \
+ msm_atomic.o \
+ msm_atomic_tracepoints.o \
+ msm_debugfs.o \
+@@ -113,12 +120,12 @@ msm-y += \
+ msm_gpu_tracepoints.o \
+ msm_gpummu.o
+
+-msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \
+- dp/dp_debug.o
++msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
+
+-msm-$(CONFIG_DRM_MSM_GPU_STATE) += adreno/a6xx_gpu_state.o
++msm-display-$(CONFIG_DEBUG_FS) += \
++ dp/dp_debug.o
+
+-msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
++msm-display-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
+ dp/dp_catalog.o \
+ dp/dp_ctrl.o \
+ dp/dp_display.o \
+@@ -129,21 +136,69 @@ msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
+ dp/dp_power.o \
+ dp/dp_audio.o
+
+-msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
+-
+-msm-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o
++msm-display-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o
+
+-msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
++msm-display-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
+ dsi/dsi_cfg.o \
+ dsi/dsi_host.o \
+ dsi/dsi_manager.o \
+ dsi/phy/dsi_phy.o
+
+-msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o
+-msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o
+-msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o
+-msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o
+-msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o
+-msm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o
++msm-display-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o
++msm-display-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o
++msm-display-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o
++msm-display-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o
++msm-display-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o
++msm-display-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o
++
++msm-y += $(adreno-y) $(msm-display-y)
+
+ obj-$(CONFIG_DRM_MSM) += msm.o
++
++quiet_cmd_headergen = GENHDR $@
++ cmd_headergen = mkdir -p $(obj)/generated && $(PYTHON3) $(srctree)/$(src)/registers/gen_header.py --rnn $(srctree)/$(src)/registers --xml $< c-defines > $@
++
++$(obj)/generated/%.xml.h: $(src)/registers/adreno/%.xml \
++ $(src)/registers/adreno/adreno_common.xml \
++ $(src)/registers/adreno/adreno_pm4.xml \
++ $(src)/registers/freedreno_copyright.xml \
++ $(src)/registers/gen_header.py \
++ $(src)/registers/rules-fd.xsd \
++ FORCE
++ $(call if_changed,headergen)
++
++$(obj)/generated/%.xml.h: $(src)/registers/display/%.xml \
++ $(src)/registers/freedreno_copyright.xml \
++ $(src)/registers/gen_header.py \
++ $(src)/registers/rules-fd.xsd \
++ FORCE
++ $(call if_changed,headergen)
++
++ADRENO_HEADERS = \
++ generated/a2xx.xml.h \
++ generated/a3xx.xml.h \
++ generated/a4xx.xml.h \
++ generated/a5xx.xml.h \
++ generated/a6xx.xml.h \
++ generated/a6xx_gmu.xml.h \
++ generated/adreno_common.xml.h \
++ generated/adreno_pm4.xml.h \
++
++DISPLAY_HEADERS = \
++ generated/dsi_phy_7nm.xml.h \
++ generated/dsi_phy_10nm.xml.h \
++ generated/dsi_phy_14nm.xml.h \
++ generated/dsi_phy_20nm.xml.h \
++ generated/dsi_phy_28nm_8960.xml.h \
++ generated/dsi_phy_28nm.xml.h \
++ generated/dsi.xml.h \
++ generated/hdmi.xml.h \
++ generated/mdp4.xml.h \
++ generated/mdp5.xml.h \
++ generated/mdp_common.xml.h \
++ generated/sfpb.xml.h
++
++$(addprefix $(obj)/,$(adreno-y)): $(addprefix $(obj)/,$(ADRENO_HEADERS))
++$(addprefix $(obj)/,$(msm-display-y)): $(addprefix $(obj)/,$(DISPLAY_HEADERS))
++
++targets += $(ADRENO_HEADERS) $(DISPLAY_HEADERS)
+--
+2.39.5
+
--- /dev/null
+From ddf38f66393fed30cdd24d7d6c3c9ac37a51617a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 1 Apr 2024 05:42:37 +0300
+Subject: drm/msm: import A2xx-A4xx XML display registers database
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit ae22a94997b8a03dcb3c922857c203246711f9d4 ]
+
+Import Adreno registers database for A2xx-A4xx from the Mesa, commit
+639488f924d9 ("freedreno/registers: limit the rules schema").
+
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Patchwork: https://patchwork.freedesktop.org/patch/585854/
+Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-7-4bdb277a85a1@linaro.org
+Stable-dep-of: 588257897058 ("drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG0 updated from driver side")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/registers/adreno/a2xx.xml | 1865 +++++++++++++
+ drivers/gpu/drm/msm/registers/adreno/a3xx.xml | 1751 ++++++++++++
+ drivers/gpu/drm/msm/registers/adreno/a4xx.xml | 2409 +++++++++++++++++
+ .../msm/registers/adreno/adreno_common.xml | 400 +++
+ .../drm/msm/registers/adreno/adreno_pm4.xml | 2268 ++++++++++++++++
+ 5 files changed, 8693 insertions(+)
+ create mode 100644 drivers/gpu/drm/msm/registers/adreno/a2xx.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/adreno/a3xx.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/adreno/a4xx.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/adreno/adreno_common.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml
+
+diff --git a/drivers/gpu/drm/msm/registers/adreno/a2xx.xml b/drivers/gpu/drm/msm/registers/adreno/a2xx.xml
+new file mode 100644
+index 0000000000000..22caddaa0db94
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/adreno/a2xx.xml
+@@ -0,0 +1,1865 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++<import file="adreno/adreno_common.xml"/>
++<import file="adreno/adreno_pm4.xml"/>
++
++
++<enum name="a2xx_rb_dither_type">
++ <value name="DITHER_PIXEL" value="0"/>
++ <value name="DITHER_SUBPIXEL" value="1"/>
++</enum>
++
++<enum name="a2xx_colorformatx">
++ <value name="COLORX_4_4_4_4" value="0"/>
++ <value name="COLORX_1_5_5_5" value="1"/>
++ <value name="COLORX_5_6_5" value="2"/>
++ <value name="COLORX_8" value="3"/>
++ <value name="COLORX_8_8" value="4"/>
++ <value name="COLORX_8_8_8_8" value="5"/>
++ <value name="COLORX_S8_8_8_8" value="6"/>
++ <value name="COLORX_16_FLOAT" value="7"/>
++ <value name="COLORX_16_16_FLOAT" value="8"/>
++ <value name="COLORX_16_16_16_16_FLOAT" value="9"/>
++ <value name="COLORX_32_FLOAT" value="10"/>
++ <value name="COLORX_32_32_FLOAT" value="11"/>
++ <value name="COLORX_32_32_32_32_FLOAT" value="12"/>
++ <value name="COLORX_2_3_3" value="13"/>
++ <value name="COLORX_8_8_8" value="14"/>
++</enum>
++
++<enum name="a2xx_sq_surfaceformat">
++ <value name="FMT_1_REVERSE" value="0"/>
++ <value name="FMT_1" value="1"/>
++ <value name="FMT_8" value="2"/>
++ <value name="FMT_1_5_5_5" value="3"/>
++ <value name="FMT_5_6_5" value="4"/>
++ <value name="FMT_6_5_5" value="5"/>
++ <value name="FMT_8_8_8_8" value="6"/>
++ <value name="FMT_2_10_10_10" value="7"/>
++ <value name="FMT_8_A" value="8"/>
++ <value name="FMT_8_B" value="9"/>
++ <value name="FMT_8_8" value="10"/>
++ <value name="FMT_Cr_Y1_Cb_Y0" value="11"/>
++ <value name="FMT_Y1_Cr_Y0_Cb" value="12"/>
++ <value name="FMT_5_5_5_1" value="13"/>
++ <value name="FMT_8_8_8_8_A" value="14"/>
++ <value name="FMT_4_4_4_4" value="15"/>
++ <value name="FMT_8_8_8" value="16"/>
++ <value name="FMT_DXT1" value="18"/>
++ <value name="FMT_DXT2_3" value="19"/>
++ <value name="FMT_DXT4_5" value="20"/>
++ <value name="FMT_10_10_10_2" value="21"/>
++ <value name="FMT_24_8" value="22"/>
++ <value name="FMT_16" value="24"/>
++ <value name="FMT_16_16" value="25"/>
++ <value name="FMT_16_16_16_16" value="26"/>
++ <value name="FMT_16_EXPAND" value="27"/>
++ <value name="FMT_16_16_EXPAND" value="28"/>
++ <value name="FMT_16_16_16_16_EXPAND" value="29"/>
++ <value name="FMT_16_FLOAT" value="30"/>
++ <value name="FMT_16_16_FLOAT" value="31"/>
++ <value name="FMT_16_16_16_16_FLOAT" value="32"/>
++ <value name="FMT_32" value="33"/>
++ <value name="FMT_32_32" value="34"/>
++ <value name="FMT_32_32_32_32" value="35"/>
++ <value name="FMT_32_FLOAT" value="36"/>
++ <value name="FMT_32_32_FLOAT" value="37"/>
++ <value name="FMT_32_32_32_32_FLOAT" value="38"/>
++ <value name="FMT_ATI_TC_RGB" value="39"/>
++ <value name="FMT_ATI_TC_RGBA" value="40"/>
++ <value name="FMT_ATI_TC_555_565_RGB" value="41"/>
++ <value name="FMT_ATI_TC_555_565_RGBA" value="42"/>
++ <value name="FMT_ATI_TC_RGBA_INTERP" value="43"/>
++ <value name="FMT_ATI_TC_555_565_RGBA_INTERP" value="44"/>
++ <value name="FMT_ETC1_RGBA_INTERP" value="46"/>
++ <value name="FMT_ETC1_RGB" value="47"/>
++ <value name="FMT_ETC1_RGBA" value="48"/>
++ <value name="FMT_DXN" value="49"/>
++ <value name="FMT_2_3_3" value="51"/>
++ <value name="FMT_2_10_10_10_AS_16_16_16_16" value="54"/>
++ <value name="FMT_10_10_10_2_AS_16_16_16_16" value="55"/>
++ <value name="FMT_32_32_32_FLOAT" value="57"/>
++ <value name="FMT_DXT3A" value="58"/>
++ <value name="FMT_DXT5A" value="59"/>
++ <value name="FMT_CTX1" value="60"/>
++</enum>
++
++<enum name="a2xx_sq_ps_vtx_mode">
++ <value name="POSITION_1_VECTOR" value="0"/>
++ <value name="POSITION_2_VECTORS_UNUSED" value="1"/>
++ <value name="POSITION_2_VECTORS_SPRITE" value="2"/>
++ <value name="POSITION_2_VECTORS_EDGE" value="3"/>
++ <value name="POSITION_2_VECTORS_KILL" value="4"/>
++ <value name="POSITION_2_VECTORS_SPRITE_KILL" value="5"/>
++ <value name="POSITION_2_VECTORS_EDGE_KILL" value="6"/>
++ <value name="MULTIPASS" value="7"/>
++</enum>
++
++<enum name="a2xx_sq_sample_cntl">
++ <value name="CENTROIDS_ONLY" value="0"/>
++ <value name="CENTERS_ONLY" value="1"/>
++ <value name="CENTROIDS_AND_CENTERS" value="2"/>
++</enum>
++
++<enum name="a2xx_dx_clip_space">
++ <value name="DXCLIP_OPENGL" value="0"/>
++ <value name="DXCLIP_DIRECTX" value="1"/>
++</enum>
++
++<enum name="a2xx_pa_su_sc_polymode">
++ <value name="POLY_DISABLED" value="0"/>
++ <value name="POLY_DUALMODE" value="1"/>
++</enum>
++
++<enum name="a2xx_rb_edram_mode">
++ <value name="EDRAM_NOP" value="0"/>
++ <value name="COLOR_DEPTH" value="4"/>
++ <value name="DEPTH_ONLY" value="5"/>
++ <value name="EDRAM_COPY" value="6"/>
++</enum>
++
++<enum name="a2xx_pa_sc_pattern_bit_order">
++ <value name="LITTLE" value="0"/>
++ <value name="BIG" value="1"/>
++</enum>
++
++<enum name="a2xx_pa_sc_auto_reset_cntl">
++ <value name="NEVER" value="0"/>
++ <value name="EACH_PRIMITIVE" value="1"/>
++ <value name="EACH_PACKET" value="2"/>
++</enum>
++
++<enum name="a2xx_pa_pixcenter">
++ <value name="PIXCENTER_D3D" value="0"/>
++ <value name="PIXCENTER_OGL" value="1"/>
++</enum>
++
++<enum name="a2xx_pa_roundmode">
++ <value name="TRUNCATE" value="0"/>
++ <value name="ROUND" value="1"/>
++ <value name="ROUNDTOEVEN" value="2"/>
++ <value name="ROUNDTOODD" value="3"/>
++</enum>
++
++<enum name="a2xx_pa_quantmode">
++ <value name="ONE_SIXTEENTH" value="0"/>
++ <value name="ONE_EIGTH" value="1"/>
++ <value name="ONE_QUARTER" value="2"/>
++ <value name="ONE_HALF" value="3"/>
++ <value name="ONE" value="4"/>
++</enum>
++
++<enum name="a2xx_rb_copy_sample_select">
++ <value name="SAMPLE_0" value="0"/>
++ <value name="SAMPLE_1" value="1"/>
++ <value name="SAMPLE_2" value="2"/>
++ <value name="SAMPLE_3" value="3"/>
++ <value name="SAMPLE_01" value="4"/>
++ <value name="SAMPLE_23" value="5"/>
++ <value name="SAMPLE_0123" value="6"/>
++</enum>
++
++<enum name="a2xx_rb_blend_opcode">
++ <value name="BLEND2_DST_PLUS_SRC" value="0"/>
++ <value name="BLEND2_SRC_MINUS_DST" value="1"/>
++ <value name="BLEND2_MIN_DST_SRC" value="2"/>
++ <value name="BLEND2_MAX_DST_SRC" value="3"/>
++ <value name="BLEND2_DST_MINUS_SRC" value="4"/>
++ <value name="BLEND2_DST_PLUS_SRC_BIAS" value="5"/>
++</enum>
++
++<enum name="a2xx_su_perfcnt_select">
++ <value value="0" name="PERF_PAPC_PASX_REQ"/>
++ <value value="2" name="PERF_PAPC_PASX_FIRST_VECTOR"/>
++ <value value="3" name="PERF_PAPC_PASX_SECOND_VECTOR"/>
++ <value value="4" name="PERF_PAPC_PASX_FIRST_DEAD"/>
++ <value value="5" name="PERF_PAPC_PASX_SECOND_DEAD"/>
++ <value value="6" name="PERF_PAPC_PASX_VTX_KILL_DISCARD"/>
++ <value value="7" name="PERF_PAPC_PASX_VTX_NAN_DISCARD"/>
++ <value value="8" name="PERF_PAPC_PA_INPUT_PRIM"/>
++ <value value="9" name="PERF_PAPC_PA_INPUT_NULL_PRIM"/>
++ <value value="10" name="PERF_PAPC_PA_INPUT_EVENT_FLAG"/>
++ <value value="11" name="PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT"/>
++ <value value="12" name="PERF_PAPC_PA_INPUT_END_OF_PACKET"/>
++ <value value="13" name="PERF_PAPC_CLPR_CULL_PRIM"/>
++ <value value="15" name="PERF_PAPC_CLPR_VV_CULL_PRIM"/>
++ <value value="17" name="PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM"/>
++ <value value="18" name="PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM"/>
++ <value value="19" name="PERF_PAPC_CLPR_CULL_TO_NULL_PRIM"/>
++ <value value="21" name="PERF_PAPC_CLPR_VV_CLIP_PRIM"/>
++ <value value="23" name="PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE"/>
++ <value value="24" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_1"/>
++ <value value="25" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_2"/>
++ <value value="26" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_3"/>
++ <value value="27" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_4"/>
++ <value value="28" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_5"/>
++ <value value="29" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_6"/>
++ <value value="30" name="PERF_PAPC_CLPR_CLIP_PLANE_NEAR"/>
++ <value value="31" name="PERF_PAPC_CLPR_CLIP_PLANE_FAR"/>
++ <value value="32" name="PERF_PAPC_CLPR_CLIP_PLANE_LEFT"/>
++ <value value="33" name="PERF_PAPC_CLPR_CLIP_PLANE_RIGHT"/>
++ <value value="34" name="PERF_PAPC_CLPR_CLIP_PLANE_TOP"/>
++ <value value="35" name="PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM"/>
++ <value value="36" name="PERF_PAPC_CLSM_NULL_PRIM"/>
++ <value value="37" name="PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM"/>
++ <value value="38" name="PERF_PAPC_CLSM_CLIP_PRIM"/>
++ <value value="39" name="PERF_PAPC_CLSM_CULL_TO_NULL_PRIM"/>
++ <value value="40" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_1"/>
++ <value value="41" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_2"/>
++ <value value="42" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_3"/>
++ <value value="43" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_4"/>
++ <value value="44" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_5"/>
++ <value value="45" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7"/>
++ <value value="46" name="PERF_PAPC_CLSM_NON_TRIVIAL_CULL"/>
++ <value value="47" name="PERF_PAPC_SU_INPUT_PRIM"/>
++ <value value="48" name="PERF_PAPC_SU_INPUT_CLIP_PRIM"/>
++ <value value="49" name="PERF_PAPC_SU_INPUT_NULL_PRIM"/>
++ <value value="50" name="PERF_PAPC_SU_ZERO_AREA_CULL_PRIM"/>
++ <value value="51" name="PERF_PAPC_SU_BACK_FACE_CULL_PRIM"/>
++ <value value="52" name="PERF_PAPC_SU_FRONT_FACE_CULL_PRIM"/>
++ <value value="53" name="PERF_PAPC_SU_POLYMODE_FACE_CULL"/>
++ <value value="54" name="PERF_PAPC_SU_POLYMODE_BACK_CULL"/>
++ <value value="55" name="PERF_PAPC_SU_POLYMODE_FRONT_CULL"/>
++ <value value="56" name="PERF_PAPC_SU_POLYMODE_INVALID_FILL"/>
++ <value value="57" name="PERF_PAPC_SU_OUTPUT_PRIM"/>
++ <value value="58" name="PERF_PAPC_SU_OUTPUT_CLIP_PRIM"/>
++ <value value="59" name="PERF_PAPC_SU_OUTPUT_NULL_PRIM"/>
++ <value value="60" name="PERF_PAPC_SU_OUTPUT_EVENT_FLAG"/>
++ <value value="61" name="PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT"/>
++ <value value="62" name="PERF_PAPC_SU_OUTPUT_END_OF_PACKET"/>
++ <value value="63" name="PERF_PAPC_SU_OUTPUT_POLYMODE_FACE"/>
++ <value value="64" name="PERF_PAPC_SU_OUTPUT_POLYMODE_BACK"/>
++ <value value="65" name="PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT"/>
++ <value value="66" name="PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE"/>
++ <value value="67" name="PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK"/>
++ <value value="68" name="PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT"/>
++ <value value="69" name="PERF_PAPC_PASX_REQ_IDLE"/>
++ <value value="70" name="PERF_PAPC_PASX_REQ_BUSY"/>
++ <value value="71" name="PERF_PAPC_PASX_REQ_STALLED"/>
++ <value value="72" name="PERF_PAPC_PASX_REC_IDLE"/>
++ <value value="73" name="PERF_PAPC_PASX_REC_BUSY"/>
++ <value value="74" name="PERF_PAPC_PASX_REC_STARVED_SX"/>
++ <value value="75" name="PERF_PAPC_PASX_REC_STALLED"/>
++ <value value="76" name="PERF_PAPC_PASX_REC_STALLED_POS_MEM"/>
++ <value value="77" name="PERF_PAPC_PASX_REC_STALLED_CCGSM_IN"/>
++ <value value="78" name="PERF_PAPC_CCGSM_IDLE"/>
++ <value value="79" name="PERF_PAPC_CCGSM_BUSY"/>
++ <value value="80" name="PERF_PAPC_CCGSM_STALLED"/>
++ <value value="81" name="PERF_PAPC_CLPRIM_IDLE"/>
++ <value value="82" name="PERF_PAPC_CLPRIM_BUSY"/>
++ <value value="83" name="PERF_PAPC_CLPRIM_STALLED"/>
++ <value value="84" name="PERF_PAPC_CLPRIM_STARVED_CCGSM"/>
++ <value value="85" name="PERF_PAPC_CLIPSM_IDLE"/>
++ <value value="86" name="PERF_PAPC_CLIPSM_BUSY"/>
++ <value value="87" name="PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH"/>
++ <value value="88" name="PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ"/>
++ <value value="89" name="PERF_PAPC_CLIPSM_WAIT_CLIPGA"/>
++ <value value="90" name="PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP"/>
++ <value value="91" name="PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM"/>
++ <value value="92" name="PERF_PAPC_CLIPGA_IDLE"/>
++ <value value="93" name="PERF_PAPC_CLIPGA_BUSY"/>
++ <value value="94" name="PERF_PAPC_CLIPGA_STARVED_VTE_CLIP"/>
++ <value value="95" name="PERF_PAPC_CLIPGA_STALLED"/>
++ <value value="96" name="PERF_PAPC_CLIP_IDLE"/>
++ <value value="97" name="PERF_PAPC_CLIP_BUSY"/>
++ <value value="98" name="PERF_PAPC_SU_IDLE"/>
++ <value value="99" name="PERF_PAPC_SU_BUSY"/>
++ <value value="100" name="PERF_PAPC_SU_STARVED_CLIP"/>
++ <value value="101" name="PERF_PAPC_SU_STALLED_SC"/>
++ <value value="102" name="PERF_PAPC_SU_FACENESS_CULL"/>
++</enum>
++
++<enum name="a2xx_sc_perfcnt_select">
++ <value value="0" name="SC_SR_WINDOW_VALID"/>
++ <value value="1" name="SC_CW_WINDOW_VALID"/>
++ <value value="2" name="SC_QM_WINDOW_VALID"/>
++ <value value="3" name="SC_FW_WINDOW_VALID"/>
++ <value value="4" name="SC_EZ_WINDOW_VALID"/>
++ <value value="5" name="SC_IT_WINDOW_VALID"/>
++ <value value="6" name="SC_STARVED_BY_PA"/>
++ <value value="7" name="SC_STALLED_BY_RB_TILE"/>
++ <value value="8" name="SC_STALLED_BY_RB_SAMP"/>
++ <value value="9" name="SC_STARVED_BY_RB_EZ"/>
++ <value value="10" name="SC_STALLED_BY_SAMPLE_FF"/>
++ <value value="11" name="SC_STALLED_BY_SQ"/>
++ <value value="12" name="SC_STALLED_BY_SP"/>
++ <value value="13" name="SC_TOTAL_NO_PRIMS"/>
++ <value value="14" name="SC_NON_EMPTY_PRIMS"/>
++ <value value="15" name="SC_NO_TILES_PASSING_QM"/>
++ <value value="16" name="SC_NO_PIXELS_PRE_EZ"/>
++ <value value="17" name="SC_NO_PIXELS_POST_EZ"/>
++</enum>
++
++<enum name="a2xx_vgt_perfcount_select">
++ <value value="0" name="VGT_SQ_EVENT_WINDOW_ACTIVE"/>
++ <value value="1" name="VGT_SQ_SEND"/>
++ <value value="2" name="VGT_SQ_STALLED"/>
++ <value value="3" name="VGT_SQ_STARVED_BUSY"/>
++ <value value="4" name="VGT_SQ_STARVED_IDLE"/>
++ <value value="5" name="VGT_SQ_STATIC"/>
++ <value value="6" name="VGT_PA_EVENT_WINDOW_ACTIVE"/>
++ <value value="7" name="VGT_PA_CLIP_V_SEND"/>
++ <value value="8" name="VGT_PA_CLIP_V_STALLED"/>
++ <value value="9" name="VGT_PA_CLIP_V_STARVED_BUSY"/>
++ <value value="10" name="VGT_PA_CLIP_V_STARVED_IDLE"/>
++ <value value="11" name="VGT_PA_CLIP_V_STATIC"/>
++ <value value="12" name="VGT_PA_CLIP_P_SEND"/>
++ <value value="13" name="VGT_PA_CLIP_P_STALLED"/>
++ <value value="14" name="VGT_PA_CLIP_P_STARVED_BUSY"/>
++ <value value="15" name="VGT_PA_CLIP_P_STARVED_IDLE"/>
++ <value value="16" name="VGT_PA_CLIP_P_STATIC"/>
++ <value value="17" name="VGT_PA_CLIP_S_SEND"/>
++ <value value="18" name="VGT_PA_CLIP_S_STALLED"/>
++ <value value="19" name="VGT_PA_CLIP_S_STARVED_BUSY"/>
++ <value value="20" name="VGT_PA_CLIP_S_STARVED_IDLE"/>
++ <value value="21" name="VGT_PA_CLIP_S_STATIC"/>
++ <value value="22" name="RBIU_FIFOS_EVENT_WINDOW_ACTIVE"/>
++ <value value="23" name="RBIU_IMMED_DATA_FIFO_STARVED"/>
++ <value value="24" name="RBIU_IMMED_DATA_FIFO_STALLED"/>
++ <value value="25" name="RBIU_DMA_REQUEST_FIFO_STARVED"/>
++ <value value="26" name="RBIU_DMA_REQUEST_FIFO_STALLED"/>
++ <value value="27" name="RBIU_DRAW_INITIATOR_FIFO_STARVED"/>
++ <value value="28" name="RBIU_DRAW_INITIATOR_FIFO_STALLED"/>
++ <value value="29" name="BIN_PRIM_NEAR_CULL"/>
++ <value value="30" name="BIN_PRIM_ZERO_CULL"/>
++ <value value="31" name="BIN_PRIM_FAR_CULL"/>
++ <value value="32" name="BIN_PRIM_BIN_CULL"/>
++ <value value="33" name="BIN_PRIM_FACE_CULL"/>
++ <value value="34" name="SPARE34"/>
++ <value value="35" name="SPARE35"/>
++ <value value="36" name="SPARE36"/>
++ <value value="37" name="SPARE37"/>
++ <value value="38" name="SPARE38"/>
++ <value value="39" name="SPARE39"/>
++ <value value="40" name="TE_SU_IN_VALID"/>
++ <value value="41" name="TE_SU_IN_READ"/>
++ <value value="42" name="TE_SU_IN_PRIM"/>
++ <value value="43" name="TE_SU_IN_EOP"/>
++ <value value="44" name="TE_SU_IN_NULL_PRIM"/>
++ <value value="45" name="TE_WK_IN_VALID"/>
++ <value value="46" name="TE_WK_IN_READ"/>
++ <value value="47" name="TE_OUT_PRIM_VALID"/>
++ <value value="48" name="TE_OUT_PRIM_READ"/>
++</enum>
++
++<enum name="a2xx_tcr_perfcount_select">
++ <value value="0" name="DGMMPD_IPMUX0_STALL"/>
++ <value value="4" name="DGMMPD_IPMUX_ALL_STALL"/>
++ <value value="5" name="OPMUX0_L2_WRITES"/>
++</enum>
++
++<enum name="a2xx_tp_perfcount_select">
++ <value value="0" name="POINT_QUADS"/>
++ <value value="1" name="BILIN_QUADS"/>
++ <value value="2" name="ANISO_QUADS"/>
++ <value value="3" name="MIP_QUADS"/>
++ <value value="4" name="VOL_QUADS"/>
++ <value value="5" name="MIP_VOL_QUADS"/>
++ <value value="6" name="MIP_ANISO_QUADS"/>
++ <value value="7" name="VOL_ANISO_QUADS"/>
++ <value value="8" name="ANISO_2_1_QUADS"/>
++ <value value="9" name="ANISO_4_1_QUADS"/>
++ <value value="10" name="ANISO_6_1_QUADS"/>
++ <value value="11" name="ANISO_8_1_QUADS"/>
++ <value value="12" name="ANISO_10_1_QUADS"/>
++ <value value="13" name="ANISO_12_1_QUADS"/>
++ <value value="14" name="ANISO_14_1_QUADS"/>
++ <value value="15" name="ANISO_16_1_QUADS"/>
++ <value value="16" name="MIP_VOL_ANISO_QUADS"/>
++ <value value="17" name="ALIGN_2_QUADS"/>
++ <value value="18" name="ALIGN_4_QUADS"/>
++ <value value="19" name="PIX_0_QUAD"/>
++ <value value="20" name="PIX_1_QUAD"/>
++ <value value="21" name="PIX_2_QUAD"/>
++ <value value="22" name="PIX_3_QUAD"/>
++ <value value="23" name="PIX_4_QUAD"/>
++ <value value="24" name="TP_MIPMAP_LOD0"/>
++ <value value="25" name="TP_MIPMAP_LOD1"/>
++ <value value="26" name="TP_MIPMAP_LOD2"/>
++ <value value="27" name="TP_MIPMAP_LOD3"/>
++ <value value="28" name="TP_MIPMAP_LOD4"/>
++ <value value="29" name="TP_MIPMAP_LOD5"/>
++ <value value="30" name="TP_MIPMAP_LOD6"/>
++ <value value="31" name="TP_MIPMAP_LOD7"/>
++ <value value="32" name="TP_MIPMAP_LOD8"/>
++ <value value="33" name="TP_MIPMAP_LOD9"/>
++ <value value="34" name="TP_MIPMAP_LOD10"/>
++ <value value="35" name="TP_MIPMAP_LOD11"/>
++ <value value="36" name="TP_MIPMAP_LOD12"/>
++ <value value="37" name="TP_MIPMAP_LOD13"/>
++ <value value="38" name="TP_MIPMAP_LOD14"/>
++</enum>
++
++<enum name="a2xx_tcm_perfcount_select">
++ <value value="0" name="QUAD0_RD_LAT_FIFO_EMPTY"/>
++ <value value="3" name="QUAD0_RD_LAT_FIFO_4TH_FULL"/>
++ <value value="4" name="QUAD0_RD_LAT_FIFO_HALF_FULL"/>
++ <value value="5" name="QUAD0_RD_LAT_FIFO_FULL"/>
++ <value value="6" name="QUAD0_RD_LAT_FIFO_LT_4TH_FULL"/>
++ <value value="28" name="READ_STARVED_QUAD0"/>
++ <value value="32" name="READ_STARVED"/>
++ <value value="33" name="READ_STALLED_QUAD0"/>
++ <value value="37" name="READ_STALLED"/>
++ <value value="38" name="VALID_READ_QUAD0"/>
++ <value value="42" name="TC_TP_STARVED_QUAD0"/>
++ <value value="46" name="TC_TP_STARVED"/>
++</enum>
++
++<enum name="a2xx_tcf_perfcount_select">
++ <value value="0" name="VALID_CYCLES"/>
++ <value value="1" name="SINGLE_PHASES"/>
++ <value value="2" name="ANISO_PHASES"/>
++ <value value="3" name="MIP_PHASES"/>
++ <value value="4" name="VOL_PHASES"/>
++ <value value="5" name="MIP_VOL_PHASES"/>
++ <value value="6" name="MIP_ANISO_PHASES"/>
++ <value value="7" name="VOL_ANISO_PHASES"/>
++ <value value="8" name="ANISO_2_1_PHASES"/>
++ <value value="9" name="ANISO_4_1_PHASES"/>
++ <value value="10" name="ANISO_6_1_PHASES"/>
++ <value value="11" name="ANISO_8_1_PHASES"/>
++ <value value="12" name="ANISO_10_1_PHASES"/>
++ <value value="13" name="ANISO_12_1_PHASES"/>
++ <value value="14" name="ANISO_14_1_PHASES"/>
++ <value value="15" name="ANISO_16_1_PHASES"/>
++ <value value="16" name="MIP_VOL_ANISO_PHASES"/>
++ <value value="17" name="ALIGN_2_PHASES"/>
++ <value value="18" name="ALIGN_4_PHASES"/>
++ <value value="19" name="TPC_BUSY"/>
++ <value value="20" name="TPC_STALLED"/>
++ <value value="21" name="TPC_STARVED"/>
++ <value value="22" name="TPC_WORKING"/>
++ <value value="23" name="TPC_WALKER_BUSY"/>
++ <value value="24" name="TPC_WALKER_STALLED"/>
++ <value value="25" name="TPC_WALKER_WORKING"/>
++ <value value="26" name="TPC_ALIGNER_BUSY"/>
++ <value value="27" name="TPC_ALIGNER_STALLED"/>
++ <value value="28" name="TPC_ALIGNER_STALLED_BY_BLEND"/>
++ <value value="29" name="TPC_ALIGNER_STALLED_BY_CACHE"/>
++ <value value="30" name="TPC_ALIGNER_WORKING"/>
++ <value value="31" name="TPC_BLEND_BUSY"/>
++ <value value="32" name="TPC_BLEND_SYNC"/>
++ <value value="33" name="TPC_BLEND_STARVED"/>
++ <value value="34" name="TPC_BLEND_WORKING"/>
++ <value value="35" name="OPCODE_0x00"/>
++ <value value="36" name="OPCODE_0x01"/>
++ <value value="37" name="OPCODE_0x04"/>
++ <value value="38" name="OPCODE_0x10"/>
++ <value value="39" name="OPCODE_0x11"/>
++ <value value="40" name="OPCODE_0x12"/>
++ <value value="41" name="OPCODE_0x13"/>
++ <value value="42" name="OPCODE_0x18"/>
++ <value value="43" name="OPCODE_0x19"/>
++ <value value="44" name="OPCODE_0x1A"/>
++ <value value="45" name="OPCODE_OTHER"/>
++ <value value="56" name="IN_FIFO_0_EMPTY"/>
++ <value value="57" name="IN_FIFO_0_LT_HALF_FULL"/>
++ <value value="58" name="IN_FIFO_0_HALF_FULL"/>
++ <value value="59" name="IN_FIFO_0_FULL"/>
++ <value value="72" name="IN_FIFO_TPC_EMPTY"/>
++ <value value="73" name="IN_FIFO_TPC_LT_HALF_FULL"/>
++ <value value="74" name="IN_FIFO_TPC_HALF_FULL"/>
++ <value value="75" name="IN_FIFO_TPC_FULL"/>
++ <value value="76" name="TPC_TC_XFC"/>
++ <value value="77" name="TPC_TC_STATE"/>
++ <value value="78" name="TC_STALL"/>
++ <value value="79" name="QUAD0_TAPS"/>
++ <value value="83" name="QUADS"/>
++ <value value="84" name="TCA_SYNC_STALL"/>
++ <value value="85" name="TAG_STALL"/>
++ <value value="88" name="TCB_SYNC_STALL"/>
++ <value value="89" name="TCA_VALID"/>
++ <value value="90" name="PROBES_VALID"/>
++ <value value="91" name="MISS_STALL"/>
++ <value value="92" name="FETCH_FIFO_STALL"/>
++ <value value="93" name="TCO_STALL"/>
++ <value value="94" name="ANY_STALL"/>
++ <value value="95" name="TAG_MISSES"/>
++ <value value="96" name="TAG_HITS"/>
++ <value value="97" name="SUB_TAG_MISSES"/>
++ <value value="98" name="SET0_INVALIDATES"/>
++ <value value="99" name="SET1_INVALIDATES"/>
++ <value value="100" name="SET2_INVALIDATES"/>
++ <value value="101" name="SET3_INVALIDATES"/>
++ <value value="102" name="SET0_TAG_MISSES"/>
++ <value value="103" name="SET1_TAG_MISSES"/>
++ <value value="104" name="SET2_TAG_MISSES"/>
++ <value value="105" name="SET3_TAG_MISSES"/>
++ <value value="106" name="SET0_TAG_HITS"/>
++ <value value="107" name="SET1_TAG_HITS"/>
++ <value value="108" name="SET2_TAG_HITS"/>
++ <value value="109" name="SET3_TAG_HITS"/>
++ <value value="110" name="SET0_SUB_TAG_MISSES"/>
++ <value value="111" name="SET1_SUB_TAG_MISSES"/>
++ <value value="112" name="SET2_SUB_TAG_MISSES"/>
++ <value value="113" name="SET3_SUB_TAG_MISSES"/>
++ <value value="114" name="SET0_EVICT1"/>
++ <value value="115" name="SET0_EVICT2"/>
++ <value value="116" name="SET0_EVICT3"/>
++ <value value="117" name="SET0_EVICT4"/>
++ <value value="118" name="SET0_EVICT5"/>
++ <value value="119" name="SET0_EVICT6"/>
++ <value value="120" name="SET0_EVICT7"/>
++ <value value="121" name="SET0_EVICT8"/>
++ <value value="130" name="SET1_EVICT1"/>
++ <value value="131" name="SET1_EVICT2"/>
++ <value value="132" name="SET1_EVICT3"/>
++ <value value="133" name="SET1_EVICT4"/>
++ <value value="134" name="SET1_EVICT5"/>
++ <value value="135" name="SET1_EVICT6"/>
++ <value value="136" name="SET1_EVICT7"/>
++ <value value="137" name="SET1_EVICT8"/>
++ <value value="146" name="SET2_EVICT1"/>
++ <value value="147" name="SET2_EVICT2"/>
++ <value value="148" name="SET2_EVICT3"/>
++ <value value="149" name="SET2_EVICT4"/>
++ <value value="150" name="SET2_EVICT5"/>
++ <value value="151" name="SET2_EVICT6"/>
++ <value value="152" name="SET2_EVICT7"/>
++ <value value="153" name="SET2_EVICT8"/>
++ <value value="162" name="SET3_EVICT1"/>
++ <value value="163" name="SET3_EVICT2"/>
++ <value value="164" name="SET3_EVICT3"/>
++ <value value="165" name="SET3_EVICT4"/>
++ <value value="166" name="SET3_EVICT5"/>
++ <value value="167" name="SET3_EVICT6"/>
++ <value value="168" name="SET3_EVICT7"/>
++ <value value="169" name="SET3_EVICT8"/>
++ <value value="178" name="FF_EMPTY"/>
++ <value value="179" name="FF_LT_HALF_FULL"/>
++ <value value="180" name="FF_HALF_FULL"/>
++ <value value="181" name="FF_FULL"/>
++ <value value="182" name="FF_XFC"/>
++ <value value="183" name="FF_STALLED"/>
++ <value value="184" name="FG_MASKS"/>
++ <value value="185" name="FG_LEFT_MASKS"/>
++ <value value="186" name="FG_LEFT_MASK_STALLED"/>
++ <value value="187" name="FG_LEFT_NOT_DONE_STALL"/>
++ <value value="188" name="FG_LEFT_FG_STALL"/>
++ <value value="189" name="FG_LEFT_SECTORS"/>
++ <value value="195" name="FG0_REQUESTS"/>
++ <value value="196" name="FG0_STALLED"/>
++ <value value="199" name="MEM_REQ512"/>
++ <value value="200" name="MEM_REQ_SENT"/>
++ <value value="202" name="MEM_LOCAL_READ_REQ"/>
++ <value value="203" name="TC0_MH_STALLED"/>
++</enum>
++
++<enum name="a2xx_sq_perfcnt_select">
++ <value value="0" name="SQ_PIXEL_VECTORS_SUB"/>
++ <value value="1" name="SQ_VERTEX_VECTORS_SUB"/>
++ <value value="2" name="SQ_ALU0_ACTIVE_VTX_SIMD0"/>
++ <value value="3" name="SQ_ALU1_ACTIVE_VTX_SIMD0"/>
++ <value value="4" name="SQ_ALU0_ACTIVE_PIX_SIMD0"/>
++ <value value="5" name="SQ_ALU1_ACTIVE_PIX_SIMD0"/>
++ <value value="6" name="SQ_ALU0_ACTIVE_VTX_SIMD1"/>
++ <value value="7" name="SQ_ALU1_ACTIVE_VTX_SIMD1"/>
++ <value value="8" name="SQ_ALU0_ACTIVE_PIX_SIMD1"/>
++ <value value="9" name="SQ_ALU1_ACTIVE_PIX_SIMD1"/>
++ <value value="10" name="SQ_EXPORT_CYCLES"/>
++ <value value="11" name="SQ_ALU_CST_WRITTEN"/>
++ <value value="12" name="SQ_TEX_CST_WRITTEN"/>
++ <value value="13" name="SQ_ALU_CST_STALL"/>
++ <value value="14" name="SQ_ALU_TEX_STALL"/>
++ <value value="15" name="SQ_INST_WRITTEN"/>
++ <value value="16" name="SQ_BOOLEAN_WRITTEN"/>
++ <value value="17" name="SQ_LOOPS_WRITTEN"/>
++ <value value="18" name="SQ_PIXEL_SWAP_IN"/>
++ <value value="19" name="SQ_PIXEL_SWAP_OUT"/>
++ <value value="20" name="SQ_VERTEX_SWAP_IN"/>
++ <value value="21" name="SQ_VERTEX_SWAP_OUT"/>
++ <value value="22" name="SQ_ALU_VTX_INST_ISSUED"/>
++ <value value="23" name="SQ_TEX_VTX_INST_ISSUED"/>
++ <value value="24" name="SQ_VC_VTX_INST_ISSUED"/>
++ <value value="25" name="SQ_CF_VTX_INST_ISSUED"/>
++ <value value="26" name="SQ_ALU_PIX_INST_ISSUED"/>
++ <value value="27" name="SQ_TEX_PIX_INST_ISSUED"/>
++ <value value="28" name="SQ_VC_PIX_INST_ISSUED"/>
++ <value value="29" name="SQ_CF_PIX_INST_ISSUED"/>
++ <value value="30" name="SQ_ALU0_FIFO_EMPTY_SIMD0"/>
++ <value value="31" name="SQ_ALU1_FIFO_EMPTY_SIMD0"/>
++ <value value="32" name="SQ_ALU0_FIFO_EMPTY_SIMD1"/>
++ <value value="33" name="SQ_ALU1_FIFO_EMPTY_SIMD1"/>
++ <value value="34" name="SQ_ALU_NOPS"/>
++ <value value="35" name="SQ_PRED_SKIP"/>
++ <value value="36" name="SQ_SYNC_ALU_STALL_SIMD0_VTX"/>
++ <value value="37" name="SQ_SYNC_ALU_STALL_SIMD1_VTX"/>
++ <value value="38" name="SQ_SYNC_TEX_STALL_VTX"/>
++ <value value="39" name="SQ_SYNC_VC_STALL_VTX"/>
++ <value value="40" name="SQ_CONSTANTS_USED_SIMD0"/>
++ <value value="41" name="SQ_CONSTANTS_SENT_SP_SIMD0"/>
++ <value value="42" name="SQ_GPR_STALL_VTX"/>
++ <value value="43" name="SQ_GPR_STALL_PIX"/>
++ <value value="44" name="SQ_VTX_RS_STALL"/>
++ <value value="45" name="SQ_PIX_RS_STALL"/>
++ <value value="46" name="SQ_SX_PC_FULL"/>
++ <value value="47" name="SQ_SX_EXP_BUFF_FULL"/>
++ <value value="48" name="SQ_SX_POS_BUFF_FULL"/>
++ <value value="49" name="SQ_INTERP_QUADS"/>
++ <value value="50" name="SQ_INTERP_ACTIVE"/>
++ <value value="51" name="SQ_IN_PIXEL_STALL"/>
++ <value value="52" name="SQ_IN_VTX_STALL"/>
++ <value value="53" name="SQ_VTX_CNT"/>
++ <value value="54" name="SQ_VTX_VECTOR2"/>
++ <value value="55" name="SQ_VTX_VECTOR3"/>
++ <value value="56" name="SQ_VTX_VECTOR4"/>
++ <value value="57" name="SQ_PIXEL_VECTOR1"/>
++ <value value="58" name="SQ_PIXEL_VECTOR23"/>
++ <value value="59" name="SQ_PIXEL_VECTOR4"/>
++ <value value="60" name="SQ_CONSTANTS_USED_SIMD1"/>
++ <value value="61" name="SQ_CONSTANTS_SENT_SP_SIMD1"/>
++ <value value="62" name="SQ_SX_MEM_EXP_FULL"/>
++ <value value="63" name="SQ_ALU0_ACTIVE_VTX_SIMD2"/>
++ <value value="64" name="SQ_ALU1_ACTIVE_VTX_SIMD2"/>
++ <value value="65" name="SQ_ALU0_ACTIVE_PIX_SIMD2"/>
++ <value value="66" name="SQ_ALU1_ACTIVE_PIX_SIMD2"/>
++ <value value="67" name="SQ_ALU0_ACTIVE_VTX_SIMD3"/>
++ <value value="68" name="SQ_PERFCOUNT_VTX_QUAL_TP_DONE"/>
++ <value value="69" name="SQ_ALU0_ACTIVE_PIX_SIMD3"/>
++ <value value="70" name="SQ_PERFCOUNT_PIX_QUAL_TP_DONE"/>
++ <value value="71" name="SQ_ALU0_FIFO_EMPTY_SIMD2"/>
++ <value value="72" name="SQ_ALU1_FIFO_EMPTY_SIMD2"/>
++ <value value="73" name="SQ_ALU0_FIFO_EMPTY_SIMD3"/>
++ <value value="74" name="SQ_ALU1_FIFO_EMPTY_SIMD3"/>
++ <value value="75" name="SQ_SYNC_ALU_STALL_SIMD2_VTX"/>
++ <value value="76" name="SQ_PERFCOUNT_VTX_POP_THREAD"/>
++ <value value="77" name="SQ_SYNC_ALU_STALL_SIMD0_PIX"/>
++ <value value="78" name="SQ_SYNC_ALU_STALL_SIMD1_PIX"/>
++ <value value="79" name="SQ_SYNC_ALU_STALL_SIMD2_PIX"/>
++ <value value="80" name="SQ_PERFCOUNT_PIX_POP_THREAD"/>
++ <value value="81" name="SQ_SYNC_TEX_STALL_PIX"/>
++ <value value="82" name="SQ_SYNC_VC_STALL_PIX"/>
++ <value value="83" name="SQ_CONSTANTS_USED_SIMD2"/>
++ <value value="84" name="SQ_CONSTANTS_SENT_SP_SIMD2"/>
++ <value value="85" name="SQ_PERFCOUNT_VTX_DEALLOC_ACK"/>
++ <value value="86" name="SQ_PERFCOUNT_PIX_DEALLOC_ACK"/>
++ <value value="87" name="SQ_ALU0_FIFO_FULL_SIMD0"/>
++ <value value="88" name="SQ_ALU1_FIFO_FULL_SIMD0"/>
++ <value value="89" name="SQ_ALU0_FIFO_FULL_SIMD1"/>
++ <value value="90" name="SQ_ALU1_FIFO_FULL_SIMD1"/>
++ <value value="91" name="SQ_ALU0_FIFO_FULL_SIMD2"/>
++ <value value="92" name="SQ_ALU1_FIFO_FULL_SIMD2"/>
++ <value value="93" name="SQ_ALU0_FIFO_FULL_SIMD3"/>
++ <value value="94" name="SQ_ALU1_FIFO_FULL_SIMD3"/>
++ <value value="95" name="VC_PERF_STATIC"/>
++ <value value="96" name="VC_PERF_STALLED"/>
++ <value value="97" name="VC_PERF_STARVED"/>
++ <value value="98" name="VC_PERF_SEND"/>
++ <value value="99" name="VC_PERF_ACTUAL_STARVED"/>
++ <value value="100" name="PIXEL_THREAD_0_ACTIVE"/>
++ <value value="101" name="VERTEX_THREAD_0_ACTIVE"/>
++ <value value="102" name="PIXEL_THREAD_0_NUMBER"/>
++ <value value="103" name="VERTEX_THREAD_0_NUMBER"/>
++ <value value="104" name="VERTEX_EVENT_NUMBER"/>
++ <value value="105" name="PIXEL_EVENT_NUMBER"/>
++ <value value="106" name="PTRBUFF_EF_PUSH"/>
++ <value value="107" name="PTRBUFF_EF_POP_EVENT"/>
++ <value value="108" name="PTRBUFF_EF_POP_NEW_VTX"/>
++ <value value="109" name="PTRBUFF_EF_POP_DEALLOC"/>
++ <value value="110" name="PTRBUFF_EF_POP_PVECTOR"/>
++ <value value="111" name="PTRBUFF_EF_POP_PVECTOR_X"/>
++ <value value="112" name="PTRBUFF_EF_POP_PVECTOR_VNZ"/>
++ <value value="113" name="PTRBUFF_PB_DEALLOC"/>
++ <value value="114" name="PTRBUFF_PI_STATE_PPB_POP"/>
++ <value value="115" name="PTRBUFF_PI_RTR"/>
++ <value value="116" name="PTRBUFF_PI_READ_EN"/>
++ <value value="117" name="PTRBUFF_PI_BUFF_SWAP"/>
++ <value value="118" name="PTRBUFF_SQ_FREE_BUFF"/>
++ <value value="119" name="PTRBUFF_SQ_DEC"/>
++ <value value="120" name="PTRBUFF_SC_VALID_CNTL_EVENT"/>
++ <value value="121" name="PTRBUFF_SC_VALID_IJ_XFER"/>
++ <value value="122" name="PTRBUFF_SC_NEW_VECTOR_1_Q"/>
++ <value value="123" name="PTRBUFF_QUAL_NEW_VECTOR"/>
++ <value value="124" name="PTRBUFF_QUAL_EVENT"/>
++ <value value="125" name="PTRBUFF_END_BUFFER"/>
++ <value value="126" name="PTRBUFF_FILL_QUAD"/>
++ <value value="127" name="VERTS_WRITTEN_SPI"/>
++ <value value="128" name="TP_FETCH_INSTR_EXEC"/>
++ <value value="129" name="TP_FETCH_INSTR_REQ"/>
++ <value value="130" name="TP_DATA_RETURN"/>
++ <value value="131" name="SPI_WRITE_CYCLES_SP"/>
++ <value value="132" name="SPI_WRITES_SP"/>
++ <value value="133" name="SP_ALU_INSTR_EXEC"/>
++ <value value="134" name="SP_CONST_ADDR_TO_SQ"/>
++ <value value="135" name="SP_PRED_KILLS_TO_SQ"/>
++ <value value="136" name="SP_EXPORT_CYCLES_TO_SX"/>
++ <value value="137" name="SP_EXPORTS_TO_SX"/>
++ <value value="138" name="SQ_CYCLES_ELAPSED"/>
++ <value value="139" name="SQ_TCFS_OPT_ALLOC_EXEC"/>
++ <value value="140" name="SQ_TCFS_NO_OPT_ALLOC"/>
++ <value value="141" name="SQ_ALU0_NO_OPT_ALLOC"/>
++ <value value="142" name="SQ_ALU1_NO_OPT_ALLOC"/>
++ <value value="143" name="SQ_TCFS_ARB_XFC_CNT"/>
++ <value value="144" name="SQ_ALU0_ARB_XFC_CNT"/>
++ <value value="145" name="SQ_ALU1_ARB_XFC_CNT"/>
++ <value value="146" name="SQ_TCFS_CFS_UPDATE_CNT"/>
++ <value value="147" name="SQ_ALU0_CFS_UPDATE_CNT"/>
++ <value value="148" name="SQ_ALU1_CFS_UPDATE_CNT"/>
++ <value value="149" name="SQ_VTX_PUSH_THREAD_CNT"/>
++ <value value="150" name="SQ_VTX_POP_THREAD_CNT"/>
++ <value value="151" name="SQ_PIX_PUSH_THREAD_CNT"/>
++ <value value="152" name="SQ_PIX_POP_THREAD_CNT"/>
++ <value value="153" name="SQ_PIX_TOTAL"/>
++ <value value="154" name="SQ_PIX_KILLED"/>
++</enum>
++
++<enum name="a2xx_sx_perfcnt_select">
++ <value value="0" name="SX_EXPORT_VECTORS"/>
++ <value value="1" name="SX_DUMMY_QUADS"/>
++ <value value="2" name="SX_ALPHA_FAIL"/>
++ <value value="3" name="SX_RB_QUAD_BUSY"/>
++ <value value="4" name="SX_RB_COLOR_BUSY"/>
++ <value value="5" name="SX_RB_QUAD_STALL"/>
++ <value value="6" name="SX_RB_COLOR_STALL"/>
++</enum>
++
++<enum name="a2xx_rbbm_perfcount1_sel">
++ <value value="0" name="RBBM1_COUNT"/>
++ <value value="1" name="RBBM1_NRT_BUSY"/>
++ <value value="2" name="RBBM1_RB_BUSY"/>
++ <value value="3" name="RBBM1_SQ_CNTX0_BUSY"/>
++ <value value="4" name="RBBM1_SQ_CNTX17_BUSY"/>
++ <value value="5" name="RBBM1_VGT_BUSY"/>
++ <value value="6" name="RBBM1_VGT_NODMA_BUSY"/>
++ <value value="7" name="RBBM1_PA_BUSY"/>
++ <value value="8" name="RBBM1_SC_CNTX_BUSY"/>
++ <value value="9" name="RBBM1_TPC_BUSY"/>
++ <value value="10" name="RBBM1_TC_BUSY"/>
++ <value value="11" name="RBBM1_SX_BUSY"/>
++ <value value="12" name="RBBM1_CP_COHER_BUSY"/>
++ <value value="13" name="RBBM1_CP_NRT_BUSY"/>
++ <value value="14" name="RBBM1_GFX_IDLE_STALL"/>
++ <value value="15" name="RBBM1_INTERRUPT"/>
++</enum>
++
++<enum name="a2xx_cp_perfcount_sel">
++ <value value="0" name="ALWAYS_COUNT"/>
++ <value value="1" name="TRANS_FIFO_FULL"/>
++ <value value="2" name="TRANS_FIFO_AF"/>
++ <value value="3" name="RCIU_PFPTRANS_WAIT"/>
++ <value value="6" name="RCIU_NRTTRANS_WAIT"/>
++ <value value="8" name="CSF_NRT_READ_WAIT"/>
++ <value value="9" name="CSF_I1_FIFO_FULL"/>
++ <value value="10" name="CSF_I2_FIFO_FULL"/>
++ <value value="11" name="CSF_ST_FIFO_FULL"/>
++ <value value="13" name="CSF_RING_ROQ_FULL"/>
++ <value value="14" name="CSF_I1_ROQ_FULL"/>
++ <value value="15" name="CSF_I2_ROQ_FULL"/>
++ <value value="16" name="CSF_ST_ROQ_FULL"/>
++ <value value="18" name="MIU_TAG_MEM_FULL"/>
++ <value value="19" name="MIU_WRITECLEAN"/>
++ <value value="22" name="MIU_NRT_WRITE_STALLED"/>
++ <value value="23" name="MIU_NRT_READ_STALLED"/>
++ <value value="24" name="ME_WRITE_CONFIRM_FIFO_FULL"/>
++ <value value="25" name="ME_VS_DEALLOC_FIFO_FULL"/>
++ <value value="26" name="ME_PS_DEALLOC_FIFO_FULL"/>
++ <value value="27" name="ME_REGS_VS_EVENT_FIFO_FULL"/>
++ <value value="28" name="ME_REGS_PS_EVENT_FIFO_FULL"/>
++ <value value="29" name="ME_REGS_CF_EVENT_FIFO_FULL"/>
++ <value value="30" name="ME_MICRO_RB_STARVED"/>
++ <value value="31" name="ME_MICRO_I1_STARVED"/>
++ <value value="32" name="ME_MICRO_I2_STARVED"/>
++ <value value="33" name="ME_MICRO_ST_STARVED"/>
++ <value value="40" name="RCIU_RBBM_DWORD_SENT"/>
++ <value value="41" name="ME_BUSY_CLOCKS"/>
++ <value value="42" name="ME_WAIT_CONTEXT_AVAIL"/>
++ <value value="43" name="PFP_TYPE0_PACKET"/>
++ <value value="44" name="PFP_TYPE3_PACKET"/>
++ <value value="45" name="CSF_RB_WPTR_NEQ_RPTR"/>
++ <value value="46" name="CSF_I1_SIZE_NEQ_ZERO"/>
++ <value value="47" name="CSF_I2_SIZE_NEQ_ZERO"/>
++ <value value="48" name="CSF_RBI1I2_FETCHING"/>
++</enum>
++
++<enum name="a2xx_rb_perfcnt_select">
++ <value value="0" name="RBPERF_CNTX_BUSY"/>
++ <value value="1" name="RBPERF_CNTX_BUSY_MAX"/>
++ <value value="2" name="RBPERF_SX_QUAD_STARVED"/>
++ <value value="3" name="RBPERF_SX_QUAD_STARVED_MAX"/>
++ <value value="4" name="RBPERF_GA_GC_CH0_SYS_REQ"/>
++ <value value="5" name="RBPERF_GA_GC_CH0_SYS_REQ_MAX"/>
++ <value value="6" name="RBPERF_GA_GC_CH1_SYS_REQ"/>
++ <value value="7" name="RBPERF_GA_GC_CH1_SYS_REQ_MAX"/>
++ <value value="8" name="RBPERF_MH_STARVED"/>
++ <value value="9" name="RBPERF_MH_STARVED_MAX"/>
++ <value value="10" name="RBPERF_AZ_BC_COLOR_BUSY"/>
++ <value value="11" name="RBPERF_AZ_BC_COLOR_BUSY_MAX"/>
++ <value value="12" name="RBPERF_AZ_BC_Z_BUSY"/>
++ <value value="13" name="RBPERF_AZ_BC_Z_BUSY_MAX"/>
++ <value value="14" name="RBPERF_RB_SC_TILE_RTR_N"/>
++ <value value="15" name="RBPERF_RB_SC_TILE_RTR_N_MAX"/>
++ <value value="16" name="RBPERF_RB_SC_SAMP_RTR_N"/>
++ <value value="17" name="RBPERF_RB_SC_SAMP_RTR_N_MAX"/>
++ <value value="18" name="RBPERF_RB_SX_QUAD_RTR_N"/>
++ <value value="19" name="RBPERF_RB_SX_QUAD_RTR_N_MAX"/>
++ <value value="20" name="RBPERF_RB_SX_COLOR_RTR_N"/>
++ <value value="21" name="RBPERF_RB_SX_COLOR_RTR_N_MAX"/>
++ <value value="22" name="RBPERF_RB_SC_SAMP_LZ_BUSY"/>
++ <value value="23" name="RBPERF_RB_SC_SAMP_LZ_BUSY_MAX"/>
++ <value value="24" name="RBPERF_ZXP_STALL"/>
++ <value value="25" name="RBPERF_ZXP_STALL_MAX"/>
++ <value value="26" name="RBPERF_EVENT_PENDING"/>
++ <value value="27" name="RBPERF_EVENT_PENDING_MAX"/>
++ <value value="28" name="RBPERF_RB_MH_VALID"/>
++ <value value="29" name="RBPERF_RB_MH_VALID_MAX"/>
++ <value value="30" name="RBPERF_SX_RB_QUAD_SEND"/>
++ <value value="31" name="RBPERF_SX_RB_COLOR_SEND"/>
++ <value value="32" name="RBPERF_SC_RB_TILE_SEND"/>
++ <value value="33" name="RBPERF_SC_RB_SAMPLE_SEND"/>
++ <value value="34" name="RBPERF_SX_RB_MEM_EXPORT"/>
++ <value value="35" name="RBPERF_SX_RB_QUAD_EVENT"/>
++ <value value="36" name="RBPERF_SC_RB_TILE_EVENT_FILTERED"/>
++ <value value="37" name="RBPERF_SC_RB_TILE_EVENT_ALL"/>
++ <value value="38" name="RBPERF_RB_SC_EZ_SEND"/>
++ <value value="39" name="RBPERF_RB_SX_INDEX_SEND"/>
++ <value value="40" name="RBPERF_GMEM_INTFO_RD"/>
++ <value value="41" name="RBPERF_GMEM_INTF1_RD"/>
++ <value value="42" name="RBPERF_GMEM_INTFO_WR"/>
++ <value value="43" name="RBPERF_GMEM_INTF1_WR"/>
++ <value value="44" name="RBPERF_RB_CP_CONTEXT_DONE"/>
++ <value value="45" name="RBPERF_RB_CP_CACHE_FLUSH"/>
++ <value value="46" name="RBPERF_ZPASS_DONE"/>
++ <value value="47" name="RBPERF_ZCMD_VALID"/>
++ <value value="48" name="RBPERF_CCMD_VALID"/>
++ <value value="49" name="RBPERF_ACCUM_GRANT"/>
++ <value value="50" name="RBPERF_ACCUM_C0_GRANT"/>
++ <value value="51" name="RBPERF_ACCUM_C1_GRANT"/>
++ <value value="52" name="RBPERF_ACCUM_FULL_BE_WR"/>
++ <value value="53" name="RBPERF_ACCUM_REQUEST_NO_GRANT"/>
++ <value value="54" name="RBPERF_ACCUM_TIMEOUT_PULSE"/>
++ <value value="55" name="RBPERF_ACCUM_LIN_TIMEOUT_PULSE"/>
++ <value value="56" name="RBPERF_ACCUM_CAM_HIT_FLUSHING"/>
++</enum>
++
++<enum name="a2xx_mh_perfcnt_select">
++ <value value="0" name="CP_R0_REQUESTS"/>
++ <value value="1" name="CP_R1_REQUESTS"/>
++ <value value="2" name="CP_R2_REQUESTS"/>
++ <value value="3" name="CP_R3_REQUESTS"/>
++ <value value="4" name="CP_R4_REQUESTS"/>
++ <value value="5" name="CP_TOTAL_READ_REQUESTS"/>
++ <value value="6" name="CP_TOTAL_WRITE_REQUESTS"/>
++ <value value="7" name="CP_TOTAL_REQUESTS"/>
++ <value value="8" name="CP_DATA_BYTES_WRITTEN"/>
++ <value value="9" name="CP_WRITE_CLEAN_RESPONSES"/>
++ <value value="10" name="CP_R0_READ_BURSTS_RECEIVED"/>
++ <value value="11" name="CP_R1_READ_BURSTS_RECEIVED"/>
++ <value value="12" name="CP_R2_READ_BURSTS_RECEIVED"/>
++ <value value="13" name="CP_R3_READ_BURSTS_RECEIVED"/>
++ <value value="14" name="CP_R4_READ_BURSTS_RECEIVED"/>
++ <value value="15" name="CP_TOTAL_READ_BURSTS_RECEIVED"/>
++ <value value="16" name="CP_R0_DATA_BEATS_READ"/>
++ <value value="17" name="CP_R1_DATA_BEATS_READ"/>
++ <value value="18" name="CP_R2_DATA_BEATS_READ"/>
++ <value value="19" name="CP_R3_DATA_BEATS_READ"/>
++ <value value="20" name="CP_R4_DATA_BEATS_READ"/>
++ <value value="21" name="CP_TOTAL_DATA_BEATS_READ"/>
++ <value value="22" name="VGT_R0_REQUESTS"/>
++ <value value="23" name="VGT_R1_REQUESTS"/>
++ <value value="24" name="VGT_TOTAL_REQUESTS"/>
++ <value value="25" name="VGT_R0_READ_BURSTS_RECEIVED"/>
++ <value value="26" name="VGT_R1_READ_BURSTS_RECEIVED"/>
++ <value value="27" name="VGT_TOTAL_READ_BURSTS_RECEIVED"/>
++ <value value="28" name="VGT_R0_DATA_BEATS_READ"/>
++ <value value="29" name="VGT_R1_DATA_BEATS_READ"/>
++ <value value="30" name="VGT_TOTAL_DATA_BEATS_READ"/>
++ <value value="31" name="TC_TOTAL_REQUESTS"/>
++ <value value="32" name="TC_ROQ_REQUESTS"/>
++ <value value="33" name="TC_INFO_SENT"/>
++ <value value="34" name="TC_READ_BURSTS_RECEIVED"/>
++ <value value="35" name="TC_DATA_BEATS_READ"/>
++ <value value="36" name="TCD_BURSTS_READ"/>
++ <value value="37" name="RB_REQUESTS"/>
++ <value value="38" name="RB_DATA_BYTES_WRITTEN"/>
++ <value value="39" name="RB_WRITE_CLEAN_RESPONSES"/>
++ <value value="40" name="AXI_READ_REQUESTS_ID_0"/>
++ <value value="41" name="AXI_READ_REQUESTS_ID_1"/>
++ <value value="42" name="AXI_READ_REQUESTS_ID_2"/>
++ <value value="43" name="AXI_READ_REQUESTS_ID_3"/>
++ <value value="44" name="AXI_READ_REQUESTS_ID_4"/>
++ <value value="45" name="AXI_READ_REQUESTS_ID_5"/>
++ <value value="46" name="AXI_READ_REQUESTS_ID_6"/>
++ <value value="47" name="AXI_READ_REQUESTS_ID_7"/>
++ <value value="48" name="AXI_TOTAL_READ_REQUESTS"/>
++ <value value="49" name="AXI_WRITE_REQUESTS_ID_0"/>
++ <value value="50" name="AXI_WRITE_REQUESTS_ID_1"/>
++ <value value="51" name="AXI_WRITE_REQUESTS_ID_2"/>
++ <value value="52" name="AXI_WRITE_REQUESTS_ID_3"/>
++ <value value="53" name="AXI_WRITE_REQUESTS_ID_4"/>
++ <value value="54" name="AXI_WRITE_REQUESTS_ID_5"/>
++ <value value="55" name="AXI_WRITE_REQUESTS_ID_6"/>
++ <value value="56" name="AXI_WRITE_REQUESTS_ID_7"/>
++ <value value="57" name="AXI_TOTAL_WRITE_REQUESTS"/>
++ <value value="58" name="AXI_TOTAL_REQUESTS_ID_0"/>
++ <value value="59" name="AXI_TOTAL_REQUESTS_ID_1"/>
++ <value value="60" name="AXI_TOTAL_REQUESTS_ID_2"/>
++ <value value="61" name="AXI_TOTAL_REQUESTS_ID_3"/>
++ <value value="62" name="AXI_TOTAL_REQUESTS_ID_4"/>
++ <value value="63" name="AXI_TOTAL_REQUESTS_ID_5"/>
++ <value value="64" name="AXI_TOTAL_REQUESTS_ID_6"/>
++ <value value="65" name="AXI_TOTAL_REQUESTS_ID_7"/>
++ <value value="66" name="AXI_TOTAL_REQUESTS"/>
++ <value value="67" name="AXI_READ_CHANNEL_BURSTS_ID_0"/>
++ <value value="68" name="AXI_READ_CHANNEL_BURSTS_ID_1"/>
++ <value value="69" name="AXI_READ_CHANNEL_BURSTS_ID_2"/>
++ <value value="70" name="AXI_READ_CHANNEL_BURSTS_ID_3"/>
++ <value value="71" name="AXI_READ_CHANNEL_BURSTS_ID_4"/>
++ <value value="72" name="AXI_READ_CHANNEL_BURSTS_ID_5"/>
++ <value value="73" name="AXI_READ_CHANNEL_BURSTS_ID_6"/>
++ <value value="74" name="AXI_READ_CHANNEL_BURSTS_ID_7"/>
++ <value value="75" name="AXI_READ_CHANNEL_TOTAL_BURSTS"/>
++ <value value="76" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0"/>
++ <value value="77" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1"/>
++ <value value="78" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2"/>
++ <value value="79" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3"/>
++ <value value="80" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4"/>
++ <value value="81" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5"/>
++ <value value="82" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6"/>
++ <value value="83" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7"/>
++ <value value="84" name="AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ"/>
++ <value value="85" name="AXI_WRITE_CHANNEL_BURSTS_ID_0"/>
++ <value value="86" name="AXI_WRITE_CHANNEL_BURSTS_ID_1"/>
++ <value value="87" name="AXI_WRITE_CHANNEL_BURSTS_ID_2"/>
++ <value value="88" name="AXI_WRITE_CHANNEL_BURSTS_ID_3"/>
++ <value value="89" name="AXI_WRITE_CHANNEL_BURSTS_ID_4"/>
++ <value value="90" name="AXI_WRITE_CHANNEL_BURSTS_ID_5"/>
++ <value value="91" name="AXI_WRITE_CHANNEL_BURSTS_ID_6"/>
++ <value value="92" name="AXI_WRITE_CHANNEL_BURSTS_ID_7"/>
++ <value value="93" name="AXI_WRITE_CHANNEL_TOTAL_BURSTS"/>
++ <value value="94" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0"/>
++ <value value="95" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1"/>
++ <value value="96" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2"/>
++ <value value="97" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3"/>
++ <value value="98" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4"/>
++ <value value="99" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5"/>
++ <value value="100" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6"/>
++ <value value="101" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7"/>
++ <value value="102" name="AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN"/>
++ <value value="103" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0"/>
++ <value value="104" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1"/>
++ <value value="105" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2"/>
++ <value value="106" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3"/>
++ <value value="107" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4"/>
++ <value value="108" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5"/>
++ <value value="109" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6"/>
++ <value value="110" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7"/>
++ <value value="111" name="AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES"/>
++ <value value="112" name="TOTAL_MMU_MISSES"/>
++ <value value="113" name="MMU_READ_MISSES"/>
++ <value value="114" name="MMU_WRITE_MISSES"/>
++ <value value="115" name="TOTAL_MMU_HITS"/>
++ <value value="116" name="MMU_READ_HITS"/>
++ <value value="117" name="MMU_WRITE_HITS"/>
++ <value value="118" name="SPLIT_MODE_TC_HITS"/>
++ <value value="119" name="SPLIT_MODE_TC_MISSES"/>
++ <value value="120" name="SPLIT_MODE_NON_TC_HITS"/>
++ <value value="121" name="SPLIT_MODE_NON_TC_MISSES"/>
++ <value value="122" name="STALL_AWAITING_TLB_MISS_FETCH"/>
++ <value value="123" name="MMU_TLB_MISS_READ_BURSTS_RECEIVED"/>
++ <value value="124" name="MMU_TLB_MISS_DATA_BEATS_READ"/>
++ <value value="125" name="CP_CYCLES_HELD_OFF"/>
++ <value value="126" name="VGT_CYCLES_HELD_OFF"/>
++ <value value="127" name="TC_CYCLES_HELD_OFF"/>
++ <value value="128" name="TC_ROQ_CYCLES_HELD_OFF"/>
++ <value value="129" name="TC_CYCLES_HELD_OFF_TCD_FULL"/>
++ <value value="130" name="RB_CYCLES_HELD_OFF"/>
++ <value value="131" name="TOTAL_CYCLES_ANY_CLNT_HELD_OFF"/>
++ <value value="132" name="TLB_MISS_CYCLES_HELD_OFF"/>
++ <value value="133" name="AXI_READ_REQUEST_HELD_OFF"/>
++ <value value="134" name="AXI_WRITE_REQUEST_HELD_OFF"/>
++ <value value="135" name="AXI_REQUEST_HELD_OFF"/>
++ <value value="136" name="AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT"/>
++ <value value="137" name="AXI_WRITE_DATA_HELD_OFF"/>
++ <value value="138" name="CP_SAME_PAGE_BANK_REQUESTS"/>
++ <value value="139" name="VGT_SAME_PAGE_BANK_REQUESTS"/>
++ <value value="140" name="TC_SAME_PAGE_BANK_REQUESTS"/>
++ <value value="141" name="TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS"/>
++ <value value="142" name="RB_SAME_PAGE_BANK_REQUESTS"/>
++ <value value="143" name="TOTAL_SAME_PAGE_BANK_REQUESTS"/>
++ <value value="144" name="CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
++ <value value="145" name="VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
++ <value value="146" name="TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
++ <value value="147" name="RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
++ <value value="148" name="TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT"/>
++ <value value="149" name="TOTAL_MH_READ_REQUESTS"/>
++ <value value="150" name="TOTAL_MH_WRITE_REQUESTS"/>
++ <value value="151" name="TOTAL_MH_REQUESTS"/>
++ <value value="152" name="MH_BUSY"/>
++ <value value="153" name="CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
++ <value value="154" name="VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
++ <value value="155" name="TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
++ <value value="156" name="RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
++ <value value="157" name="TC_ROQ_N_VALID_ENTRIES"/>
++ <value value="158" name="ARQ_N_ENTRIES"/>
++ <value value="159" name="WDB_N_ENTRIES"/>
++ <value value="160" name="MH_READ_LATENCY_OUTST_REQ_SUM"/>
++ <value value="161" name="MC_READ_LATENCY_OUTST_REQ_SUM"/>
++ <value value="162" name="MC_TOTAL_READ_REQUESTS"/>
++ <value value="163" name="ELAPSED_CYCLES_MH_GATED_CLK"/>
++ <value value="164" name="ELAPSED_CLK_CYCLES"/>
++ <value value="165" name="CP_W_16B_REQUESTS"/>
++ <value value="166" name="CP_W_32B_REQUESTS"/>
++ <value value="167" name="TC_16B_REQUESTS"/>
++ <value value="168" name="TC_32B_REQUESTS"/>
++ <value value="169" name="PA_REQUESTS"/>
++ <value value="170" name="PA_DATA_BYTES_WRITTEN"/>
++ <value value="171" name="PA_WRITE_CLEAN_RESPONSES"/>
++ <value value="172" name="PA_CYCLES_HELD_OFF"/>
++ <value value="173" name="AXI_READ_REQUEST_DATA_BEATS_ID_0"/>
++ <value value="174" name="AXI_READ_REQUEST_DATA_BEATS_ID_1"/>
++ <value value="175" name="AXI_READ_REQUEST_DATA_BEATS_ID_2"/>
++ <value value="176" name="AXI_READ_REQUEST_DATA_BEATS_ID_3"/>
++ <value value="177" name="AXI_READ_REQUEST_DATA_BEATS_ID_4"/>
++ <value value="178" name="AXI_READ_REQUEST_DATA_BEATS_ID_5"/>
++ <value value="179" name="AXI_READ_REQUEST_DATA_BEATS_ID_6"/>
++ <value value="180" name="AXI_READ_REQUEST_DATA_BEATS_ID_7"/>
++ <value value="181" name="AXI_TOTAL_READ_REQUEST_DATA_BEATS"/>
++</enum>
++
++<enum name="perf_mode_cnt">
++ <value name="PERF_STATE_RESET" value="0"/>
++ <value name="PERF_STATE_ENABLE" value="1"/>
++ <value name="PERF_STATE_FREEZE" value="2"/>
++</enum>
++
++<domain name="A2XX" width="32">
++
++ <bitset name="a2xx_vgt_current_bin_id_min_max" inline="yes">
++ <bitfield name="COLUMN" low="0" high="2" type="uint"/>
++ <bitfield name="ROW" low="3" high="5" type="uint"/>
++ <bitfield name="GUARD_BAND_MASK" low="6" high="8" type="uint"/>
++ </bitset>
++
++ <reg32 offset="0x0001" name="RBBM_PATCH_RELEASE"/>
++ <reg32 offset="0x003b" name="RBBM_CNTL"/>
++ <reg32 offset="0x003c" name="RBBM_SOFT_RESET"/>
++ <reg32 offset="0x00c0" name="CP_PFP_UCODE_ADDR"/>
++ <reg32 offset="0x00c1" name="CP_PFP_UCODE_DATA"/>
++
++ <enum name="adreno_mmu_clnt_beh">
++ <value name="BEH_NEVR" value="0"/>
++ <value name="BEH_TRAN_RNG" value="1"/>
++ <value name="BEH_TRAN_FLT" value="2"/>
++ </enum>
++
++ <!--
++ Note: these seem applicable only for a2xx devices with gpummu? At
++ any rate, MH_MMU_CONFIG shows up in places in a3xx firmware where
++ it doesn't make sense, so I think offset 0x40 must be a different
++ register on a3xx.. so moving this back into A2XX domain:
++ -->
++ <reg32 offset="0x0040" name="MH_MMU_CONFIG">
++ <bitfield name="MMU_ENABLE" pos="0" type="boolean"/>
++ <bitfield name="SPLIT_MODE_ENABLE" pos="1" type="boolean"/>
++ <bitfield name="RB_W_CLNT_BEHAVIOR" low="4" high="5" type="adreno_mmu_clnt_beh"/>
++ <bitfield name="CP_W_CLNT_BEHAVIOR" low="6" high="7" type="adreno_mmu_clnt_beh"/>
++ <bitfield name="CP_R0_CLNT_BEHAVIOR" low="8" high="9" type="adreno_mmu_clnt_beh"/>
++ <bitfield name="CP_R1_CLNT_BEHAVIOR" low="10" high="11" type="adreno_mmu_clnt_beh"/>
++ <bitfield name="CP_R2_CLNT_BEHAVIOR" low="12" high="13" type="adreno_mmu_clnt_beh"/>
++ <bitfield name="CP_R3_CLNT_BEHAVIOR" low="14" high="15" type="adreno_mmu_clnt_beh"/>
++ <bitfield name="CP_R4_CLNT_BEHAVIOR" low="16" high="17" type="adreno_mmu_clnt_beh"/>
++ <bitfield name="VGT_R0_CLNT_BEHAVIOR" low="18" high="19" type="adreno_mmu_clnt_beh"/>
++ <bitfield name="VGT_R1_CLNT_BEHAVIOR" low="20" high="21" type="adreno_mmu_clnt_beh"/>
++ <bitfield name="TC_R_CLNT_BEHAVIOR" low="22" high="23" type="adreno_mmu_clnt_beh"/>
++ <bitfield name="PA_W_CLNT_BEHAVIOR" low="24" high="25" type="adreno_mmu_clnt_beh"/>
++ </reg32>
++ <reg32 offset="0x0041" name="MH_MMU_VA_RANGE">
++ <bitfield name="NUM_64KB_REGIONS" low="0" high="11" type="uint"/>
++ <bitfield name="VA_BASE" low="12" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0042" name="MH_MMU_PT_BASE"/>
++ <reg32 offset="0x0043" name="MH_MMU_PAGE_FAULT"/>
++ <reg32 offset="0x0044" name="MH_MMU_TRAN_ERROR"/>
++ <reg32 offset="0x0045" name="MH_MMU_INVALIDATE">
++ <bitfield name="INVALIDATE_ALL" pos="0" type="boolean"/>
++ <bitfield name="INVALIDATE_TC" pos="1" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0046" name="MH_MMU_MPU_BASE"/>
++ <reg32 offset="0x0047" name="MH_MMU_MPU_END"/>
++
++ <reg32 offset="0x0394" name="NQWAIT_UNTIL"/>
++ <reg32 offset="0x0395" name="RBBM_PERFCOUNTER0_SELECT"/>
++ <reg32 offset="0x0396" name="RBBM_PERFCOUNTER1_SELECT"/>
++ <reg32 offset="0x0397" name="RBBM_PERFCOUNTER0_LO"/>
++ <reg32 offset="0x0398" name="RBBM_PERFCOUNTER0_HI"/>
++ <reg32 offset="0x0399" name="RBBM_PERFCOUNTER1_LO"/>
++ <reg32 offset="0x039a" name="RBBM_PERFCOUNTER1_HI"/>
++ <reg32 offset="0x039b" name="RBBM_DEBUG"/>
++ <reg32 offset="0x039c" name="RBBM_PM_OVERRIDE1">
++ <bitfield name="RBBM_AHBCLK_PM_OVERRIDE" pos="0" type="boolean"/>
++ <bitfield name="SC_REG_SCLK_PM_OVERRIDE" pos="1" type="boolean"/>
++ <bitfield name="SC_SCLK_PM_OVERRIDE" pos="2" type="boolean"/>
++ <bitfield name="SP_TOP_SCLK_PM_OVERRIDE" pos="3" type="boolean"/>
++ <bitfield name="SP_V0_SCLK_PM_OVERRIDE" pos="4" type="boolean"/>
++ <bitfield name="SQ_REG_SCLK_PM_OVERRIDE" pos="5" type="boolean"/>
++ <bitfield name="SQ_REG_FIFOS_SCLK_PM_OVERRIDE" pos="6" type="boolean"/>
++ <bitfield name="SQ_CONST_MEM_SCLK_PM_OVERRIDE" pos="7" type="boolean"/>
++ <bitfield name="SQ_SQ_SCLK_PM_OVERRIDE" pos="8" type="boolean"/>
++ <bitfield name="SX_SCLK_PM_OVERRIDE" pos="9" type="boolean"/>
++ <bitfield name="SX_REG_SCLK_PM_OVERRIDE" pos="10" type="boolean"/>
++ <bitfield name="TCM_TCO_SCLK_PM_OVERRIDE" pos="11" type="boolean"/>
++ <bitfield name="TCM_TCM_SCLK_PM_OVERRIDE" pos="12" type="boolean"/>
++ <bitfield name="TCM_TCD_SCLK_PM_OVERRIDE" pos="13" type="boolean"/>
++ <bitfield name="TCM_REG_SCLK_PM_OVERRIDE" pos="14" type="boolean"/>
++ <bitfield name="TPC_TPC_SCLK_PM_OVERRIDE" pos="15" type="boolean"/>
++ <bitfield name="TPC_REG_SCLK_PM_OVERRIDE" pos="16" type="boolean"/>
++ <bitfield name="TCF_TCA_SCLK_PM_OVERRIDE" pos="17" type="boolean"/>
++ <bitfield name="TCF_TCB_SCLK_PM_OVERRIDE" pos="18" type="boolean"/>
++ <bitfield name="TCF_TCB_READ_SCLK_PM_OVERRIDE" pos="19" type="boolean"/>
++ <bitfield name="TP_TP_SCLK_PM_OVERRIDE" pos="20" type="boolean"/>
++ <bitfield name="TP_REG_SCLK_PM_OVERRIDE" pos="21" type="boolean"/>
++ <bitfield name="CP_G_SCLK_PM_OVERRIDE" pos="22" type="boolean"/>
++ <bitfield name="CP_REG_SCLK_PM_OVERRIDE" pos="23" type="boolean"/>
++ <bitfield name="CP_G_REG_SCLK_PM_OVERRIDE" pos="24" type="boolean"/>
++ <bitfield name="SPI_SCLK_PM_OVERRIDE" pos="25" type="boolean"/>
++ <bitfield name="RB_REG_SCLK_PM_OVERRIDE" pos="26" type="boolean"/>
++ <bitfield name="RB_SCLK_PM_OVERRIDE" pos="27" type="boolean"/>
++ <bitfield name="MH_MH_SCLK_PM_OVERRIDE" pos="28" type="boolean"/>
++ <bitfield name="MH_REG_SCLK_PM_OVERRIDE" pos="29" type="boolean"/>
++ <bitfield name="MH_MMU_SCLK_PM_OVERRIDE" pos="30" type="boolean"/>
++ <bitfield name="MH_TCROQ_SCLK_PM_OVERRIDE" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x039d" name="RBBM_PM_OVERRIDE2">
++ <bitfield name="PA_REG_SCLK_PM_OVERRIDE" pos="0" type="boolean"/>
++ <bitfield name="PA_PA_SCLK_PM_OVERRIDE" pos="1" type="boolean"/>
++ <bitfield name="PA_AG_SCLK_PM_OVERRIDE" pos="2" type="boolean"/>
++ <bitfield name="VGT_REG_SCLK_PM_OVERRIDE" pos="3" type="boolean"/>
++ <bitfield name="VGT_FIFOS_SCLK_PM_OVERRIDE" pos="4" type="boolean"/>
++ <bitfield name="VGT_VGT_SCLK_PM_OVERRIDE" pos="5" type="boolean"/>
++ <bitfield name="DEBUG_PERF_SCLK_PM_OVERRIDE" pos="6" type="boolean"/>
++ <bitfield name="PERM_SCLK_PM_OVERRIDE" pos="7" type="boolean"/>
++ <bitfield name="GC_GA_GMEM0_PM_OVERRIDE" pos="8" type="boolean"/>
++ <bitfield name="GC_GA_GMEM1_PM_OVERRIDE" pos="9" type="boolean"/>
++ <bitfield name="GC_GA_GMEM2_PM_OVERRIDE" pos="10" type="boolean"/>
++ <bitfield name="GC_GA_GMEM3_PM_OVERRIDE" pos="11" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x03a0" name="RBBM_DEBUG_OUT"/>
++ <reg32 offset="0x03a1" name="RBBM_DEBUG_CNTL"/>
++ <reg32 offset="0x03b3" name="RBBM_READ_ERROR"/>
++ <reg32 offset="0x03b4" name="RBBM_INT_CNTL">
++ <bitfield name="RDERR_INT_MASK" pos="0" type="boolean"/>
++ <bitfield name="DISPLAY_UPDATE_INT_MASK" pos="1" type="boolean"/>
++ <bitfield name="GUI_IDLE_INT_MASK" pos="19" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x03b5" name="RBBM_INT_STATUS"/>
++ <reg32 offset="0x03b6" name="RBBM_INT_ACK"/>
++ <reg32 offset="0x03b7" name="MASTER_INT_SIGNAL">
++ <bitfield name="MH_INT_STAT" pos="5" type="boolean"/>
++ <bitfield name="SQ_INT_STAT" pos="26" type="boolean"/>
++ <bitfield name="CP_INT_STAT" pos="30" type="boolean"/>
++ <bitfield name="RBBM_INT_STAT" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x03f9" name="RBBM_PERIPHID1"/>
++ <reg32 offset="0x03fa" name="RBBM_PERIPHID2"/>
++ <reg32 offset="0x0444" name="CP_PERFMON_CNTL">
++ <!-- The width is uncertain -->
++ <bitfield name="PERF_MODE_CNT" low="0" high="2" type="perf_mode_cnt"/>
++ </reg32>
++ <reg32 offset="0x0445" name="CP_PERFCOUNTER_SELECT"/>
++ <reg32 offset="0x0446" name="CP_PERFCOUNTER_LO"/>
++ <reg32 offset="0x0447" name="CP_PERFCOUNTER_HI"/>
++ <reg32 offset="0x05d0" name="RBBM_STATUS">
++ <bitfield name="CMDFIFO_AVAIL" low="0" high="4" type="uint"/>
++ <bitfield name="TC_BUSY" pos="5" type="boolean"/>
++ <bitfield name="HIRQ_PENDING" pos="8" type="boolean"/>
++ <bitfield name="CPRQ_PENDING" pos="9" type="boolean"/>
++ <bitfield name="CFRQ_PENDING" pos="10" type="boolean"/>
++ <bitfield name="PFRQ_PENDING" pos="11" type="boolean"/>
++ <bitfield name="VGT_BUSY_NO_DMA" pos="12" type="boolean"/>
++ <bitfield name="RBBM_WU_BUSY" pos="14" type="boolean"/>
++ <bitfield name="CP_NRT_BUSY" pos="16" type="boolean"/>
++ <bitfield name="MH_BUSY" pos="18" type="boolean"/>
++ <bitfield name="MH_COHERENCY_BUSY" pos="19" type="boolean"/>
++ <bitfield name="SX_BUSY" pos="21" type="boolean"/>
++ <bitfield name="TPC_BUSY" pos="22" type="boolean"/>
++ <bitfield name="SC_CNTX_BUSY" pos="24" type="boolean"/>
++ <bitfield name="PA_BUSY" pos="25" type="boolean"/>
++ <bitfield name="VGT_BUSY" pos="26" type="boolean"/>
++ <bitfield name="SQ_CNTX17_BUSY" pos="27" type="boolean"/>
++ <bitfield name="SQ_CNTX0_BUSY" pos="28" type="boolean"/>
++ <bitfield name="RB_CNTX_BUSY" pos="30" type="boolean"/>
++ <bitfield name="GUI_ACTIVE" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0a40" name="MH_ARBITER_CONFIG">
++ <bitfield name="SAME_PAGE_LIMIT" low="0" high="5" type="uint"/>
++ <bitfield name="SAME_PAGE_GRANULARITY" pos="6" type="boolean"/>
++ <bitfield name="L1_ARB_ENABLE" pos="7" type="boolean"/>
++ <bitfield name="L1_ARB_HOLD_ENABLE" pos="8" type="boolean"/>
++ <bitfield name="L2_ARB_CONTROL" pos="9" type="boolean"/>
++ <bitfield name="PAGE_SIZE" low="10" high="12" type="uint"/>
++ <bitfield name="TC_REORDER_ENABLE" pos="13" type="boolean"/>
++ <bitfield name="TC_ARB_HOLD_ENABLE" pos="14" type="boolean"/>
++ <bitfield name="IN_FLIGHT_LIMIT_ENABLE" pos="15" type="boolean"/>
++ <bitfield name="IN_FLIGHT_LIMIT" low="16" high="21" type="uint"/>
++ <bitfield name="CP_CLNT_ENABLE" pos="22" type="boolean"/>
++ <bitfield name="VGT_CLNT_ENABLE" pos="23" type="boolean"/>
++ <bitfield name="TC_CLNT_ENABLE" pos="24" type="boolean"/>
++ <bitfield name="RB_CLNT_ENABLE" pos="25" type="boolean"/>
++ <bitfield name="PA_CLNT_ENABLE" pos="26" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0a42" name="MH_INTERRUPT_MASK">
++ <bitfield name="AXI_READ_ERROR" pos="0" type="boolean"/>
++ <bitfield name="AXI_WRITE_ERROR" pos="1" type="boolean"/>
++ <bitfield name="MMU_PAGE_FAULT" pos="2" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0a43" name="MH_INTERRUPT_STATUS"/>
++ <reg32 offset="0x0a44" name="MH_INTERRUPT_CLEAR"/>
++ <reg32 offset="0x0a54" name="MH_CLNT_INTF_CTRL_CONFIG1"/>
++ <reg32 offset="0x0a55" name="MH_CLNT_INTF_CTRL_CONFIG2"/>
++ <reg32 offset="0x0c01" name="A220_VSC_BIN_SIZE">
++ <bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/>
++ <bitfield name="HEIGHT" low="5" high="9" shr="5" type="uint"/>
++ </reg32>
++ <array offset="0x0c06" name="VSC_PIPE" stride="3" length="8">
++ <reg32 offset="0x0" name="CONFIG"/>
++ <reg32 offset="0x1" name="DATA_ADDRESS"/>
++ <reg32 offset="0x2" name="DATA_LENGTH"/>
++ </array>
++ <reg32 offset="0x0c38" name="PC_DEBUG_CNTL"/>
++ <reg32 offset="0x0c39" name="PC_DEBUG_DATA"/>
++ <reg32 offset="0x0c44" name="PA_SC_VIZ_QUERY_STATUS"/>
++ <reg32 offset="0x0c80" name="GRAS_DEBUG_CNTL"/>
++ <reg32 offset="0x0c80" name="PA_SU_DEBUG_CNTL"/>
++ <reg32 offset="0x0c81" name="GRAS_DEBUG_DATA"/>
++ <reg32 offset="0x0c81" name="PA_SU_DEBUG_DATA"/>
++ <reg32 offset="0x0c86" name="PA_SU_FACE_DATA">
++ <bitfield name="BASE_ADDR" low="5" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0d00" name="SQ_GPR_MANAGEMENT">
++ <bitfield name="REG_DYNAMIC" pos="0" type="boolean"/>
++ <bitfield name="REG_SIZE_PIX" low="4" high="11" type="uint"/>
++ <bitfield name="REG_SIZE_VTX" low="12" high="19" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0d01" name="SQ_FLOW_CONTROL"/>
++ <reg32 offset="0x0d02" name="SQ_INST_STORE_MANAGMENT">
++ <bitfield name="INST_BASE_PIX" low="0" high="11" type="uint"/>
++ <bitfield name="INST_BASE_VTX" low="16" high="27" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0d05" name="SQ_DEBUG_MISC"/>
++ <reg32 offset="0x0d34" name="SQ_INT_CNTL"/>
++ <reg32 offset="0x0d35" name="SQ_INT_STATUS"/>
++ <reg32 offset="0x0d36" name="SQ_INT_ACK"/>
++ <reg32 offset="0x0dae" name="SQ_DEBUG_INPUT_FSM"/>
++ <reg32 offset="0x0daf" name="SQ_DEBUG_CONST_MGR_FSM"/>
++ <reg32 offset="0x0db0" name="SQ_DEBUG_TP_FSM"/>
++ <reg32 offset="0x0db1" name="SQ_DEBUG_FSM_ALU_0"/>
++ <reg32 offset="0x0db2" name="SQ_DEBUG_FSM_ALU_1"/>
++ <reg32 offset="0x0db3" name="SQ_DEBUG_EXP_ALLOC"/>
++ <reg32 offset="0x0db4" name="SQ_DEBUG_PTR_BUFF"/>
++ <reg32 offset="0x0db5" name="SQ_DEBUG_GPR_VTX"/>
++ <reg32 offset="0x0db6" name="SQ_DEBUG_GPR_PIX"/>
++ <reg32 offset="0x0db7" name="SQ_DEBUG_TB_STATUS_SEL"/>
++ <reg32 offset="0x0db8" name="SQ_DEBUG_VTX_TB_0"/>
++ <reg32 offset="0x0db9" name="SQ_DEBUG_VTX_TB_1"/>
++ <reg32 offset="0x0dba" name="SQ_DEBUG_VTX_TB_STATUS_REG"/>
++ <reg32 offset="0x0dbb" name="SQ_DEBUG_VTX_TB_STATE_MEM"/>
++ <reg32 offset="0x0dbc" name="SQ_DEBUG_PIX_TB_0"/>
++ <reg32 offset="0x0dbd" name="SQ_DEBUG_PIX_TB_STATUS_REG_0"/>
++ <reg32 offset="0x0dbe" name="SQ_DEBUG_PIX_TB_STATUS_REG_1"/>
++ <reg32 offset="0x0dbf" name="SQ_DEBUG_PIX_TB_STATUS_REG_2"/>
++ <reg32 offset="0x0dc0" name="SQ_DEBUG_PIX_TB_STATUS_REG_3"/>
++ <reg32 offset="0x0dc1" name="SQ_DEBUG_PIX_TB_STATE_MEM"/>
++ <reg32 offset="0x0e00" name="TC_CNTL_STATUS">
++ <bitfield name="L2_INVALIDATE" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0e1e" name="TP0_CHICKEN"/>
++ <reg32 offset="0x0f01" name="RB_BC_CONTROL">
++ <bitfield name="ACCUM_LINEAR_MODE_ENABLE" pos="0" type="boolean"/>
++ <bitfield name="ACCUM_TIMEOUT_SELECT" low="1" high="2" type="uint"/>
++ <bitfield name="DISABLE_EDRAM_CAM" pos="3" type="boolean"/>
++ <bitfield name="DISABLE_EZ_FAST_CONTEXT_SWITCH" pos="4" type="boolean"/>
++ <bitfield name="DISABLE_EZ_NULL_ZCMD_DROP" pos="5" type="boolean"/>
++ <bitfield name="DISABLE_LZ_NULL_ZCMD_DROP" pos="6" type="boolean"/>
++ <bitfield name="ENABLE_AZ_THROTTLE" pos="7" type="boolean"/>
++ <bitfield name="AZ_THROTTLE_COUNT" low="8" high="12" type="uint"/>
++ <bitfield name="ENABLE_CRC_UPDATE" pos="14" type="boolean"/>
++ <bitfield name="CRC_MODE" pos="15" type="boolean"/>
++ <bitfield name="DISABLE_SAMPLE_COUNTERS" pos="16" type="boolean"/>
++ <bitfield name="DISABLE_ACCUM" pos="17" type="boolean"/>
++ <bitfield name="ACCUM_ALLOC_MASK" low="18" high="21" type="uint"/>
++ <bitfield name="LINEAR_PERFORMANCE_ENABLE" pos="22" type="boolean"/>
++ <bitfield name="ACCUM_DATA_FIFO_LIMIT" low="23" high="26" type="uint"/>
++ <bitfield name="MEM_EXPORT_TIMEOUT_SELECT" low="27" high="28" type="uint"/>
++ <bitfield name="MEM_EXPORT_LINEAR_MODE_ENABLE" pos="29" type="boolean"/>
++ <bitfield name="CRC_SYSTEM" pos="30" type="boolean"/>
++ <bitfield name="RESERVED6" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0f02" name="RB_EDRAM_INFO"/>
++ <reg32 offset="0x0f26" name="RB_DEBUG_CNTL"/>
++ <reg32 offset="0x0f27" name="RB_DEBUG_DATA"/>
++ <reg32 offset="0x2000" name="RB_SURFACE_INFO">
++ <bitfield name="SURFACE_PITCH" low="0" high="13" type="uint"/>
++ <bitfield name="MSAA_SAMPLES" low="14" high="15" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2001" name="RB_COLOR_INFO">
++ <bitfield name="FORMAT" low="0" high="3" type="a2xx_colorformatx"/>
++ <bitfield name="ROUND_MODE" low="4" high="5" type="uint"/>
++ <bitfield name="LINEAR" pos="6" type="boolean"/>
++ <bitfield name="ENDIAN" low="7" high="8" type="uint"/>
++ <bitfield name="SWAP" low="9" high="10" type="uint"/>
++ <bitfield name="BASE" low="12" high="31" shr="12"/>
++ </reg32>
++ <reg32 offset="0x2002" name="RB_DEPTH_INFO">
++ <bitfield name="DEPTH_FORMAT" pos="0" type="adreno_rb_depth_format"/>
++ <bitfield name="DEPTH_BASE" low="12" high="31" type="uint" shr="12"/>
++ </reg32>
++ <reg32 offset="0x2005" name="A225_RB_COLOR_INFO3"/>
++ <reg32 offset="0x2006" name="COHER_DEST_BASE_0"/>
++ <reg32 offset="0x200e" name="PA_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/>
++ <reg32 offset="0x200f" name="PA_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/>
++ <reg32 offset="0x2080" name="PA_SC_WINDOW_OFFSET">
++ <bitfield name="X" low="0" high="14" type="int"/>
++ <bitfield name="Y" low="16" high="30" type="int"/>
++ <bitfield name="DISABLE" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2081" name="PA_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
++ <reg32 offset="0x2082" name="PA_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
++ <reg32 offset="0x2010" name="UNKNOWN_2010"/>
++ <reg32 offset="0x2100" name="VGT_MAX_VTX_INDX"/>
++ <reg32 offset="0x2101" name="VGT_MIN_VTX_INDX"/>
++ <reg32 offset="0x2102" name="VGT_INDX_OFFSET"/>
++ <reg32 offset="0x2103" name="A225_PC_MULTI_PRIM_IB_RESET_INDX"/>
++ <reg32 offset="0x2104" name="RB_COLOR_MASK">
++ <bitfield name="WRITE_RED" pos="0" type="boolean"/>
++ <bitfield name="WRITE_GREEN" pos="1" type="boolean"/>
++ <bitfield name="WRITE_BLUE" pos="2" type="boolean"/>
++ <bitfield name="WRITE_ALPHA" pos="3" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2105" name="RB_BLEND_RED"/>
++ <reg32 offset="0x2106" name="RB_BLEND_GREEN"/>
++ <reg32 offset="0x2107" name="RB_BLEND_BLUE"/>
++ <reg32 offset="0x2108" name="RB_BLEND_ALPHA"/>
++ <reg32 offset="0x2109" name="RB_FOG_COLOR">
++ <bitfield name="FOG_RED" low="0" high="7" type="uint"/>
++ <bitfield name="FOG_GREEN" low="8" high="15" type="uint"/>
++ <bitfield name="FOG_BLUE" low="16" high="23" type="uint"/>
++ </reg32>
++ <reg32 offset="0x210c" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
++ <reg32 offset="0x210d" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
++ <reg32 offset="0x210e" name="RB_ALPHA_REF"/>
++ <reg32 offset="0x210f" name="PA_CL_VPORT_XSCALE" type="float"/>
++ <reg32 offset="0x2110" name="PA_CL_VPORT_XOFFSET" type="float"/>
++ <reg32 offset="0x2111" name="PA_CL_VPORT_YSCALE" type="float"/>
++ <reg32 offset="0x2112" name="PA_CL_VPORT_YOFFSET" type="float"/>
++ <reg32 offset="0x2113" name="PA_CL_VPORT_ZSCALE" type="float"/>
++ <reg32 offset="0x2114" name="PA_CL_VPORT_ZOFFSET" type="float"/>
++ <reg32 offset="0x2180" name="SQ_PROGRAM_CNTL">
++ <doc>
++ note: only 0x3f worth of valid register values for VS_REGS and
++ PS_REGS, but high bit is set to indicate '0 registers used':
++ </doc>
++ <bitfield name="VS_REGS" low="0" high="7" type="uint"/>
++ <bitfield name="PS_REGS" low="8" high="15" type="uint"/>
++ <bitfield name="VS_RESOURCE" pos="16" type="boolean"/>
++ <bitfield name="PS_RESOURCE" pos="17" type="boolean"/>
++ <bitfield name="PARAM_GEN" pos="18" type="boolean"/>
++ <bitfield name="GEN_INDEX_PIX" pos="19" type="boolean"/>
++ <bitfield name="VS_EXPORT_COUNT" low="20" high="23" type="uint"/>
++ <bitfield name="VS_EXPORT_MODE" low="24" high="26" type="a2xx_sq_ps_vtx_mode"/>
++ <bitfield name="PS_EXPORT_MODE" low="27" high="30" type="uint"/>
++ <bitfield name="GEN_INDEX_VTX" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2181" name="SQ_CONTEXT_MISC">
++ <bitfield name="INST_PRED_OPTIMIZE" pos="0" type="boolean"/>
++ <bitfield name="SC_OUTPUT_SCREEN_XY" pos="1" type="boolean"/>
++ <bitfield name="SC_SAMPLE_CNTL" low="2" high="3" type="a2xx_sq_sample_cntl"/>
++ <bitfield name="PARAM_GEN_POS" low="8" high="15" type="uint"/>
++ <bitfield name="PERFCOUNTER_REF" pos="16" type="boolean"/>
++ <bitfield name="YEILD_OPTIMIZE" pos="17" type="boolean"/>
++ <bitfield name="TX_CACHE_SEL" pos="18" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2182" name="SQ_INTERPOLATOR_CNTL">
++ <bitfield name="PARAM_SHADE" low="0" high="15" type="uint"/>
++ <bitfield name="SAMPLING_PATTERN" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2183" name="SQ_WRAPPING_0">
++ <bitfield name="PARAM_WRAP_0" low="0" high="3" type="uint"/>
++ <bitfield name="PARAM_WRAP_1" low="4" high="7" type="uint"/>
++ <bitfield name="PARAM_WRAP_2" low="8" high="11" type="uint"/>
++ <bitfield name="PARAM_WRAP_3" low="12" high="15" type="uint"/>
++ <bitfield name="PARAM_WRAP_4" low="16" high="19" type="uint"/>
++ <bitfield name="PARAM_WRAP_5" low="20" high="23" type="uint"/>
++ <bitfield name="PARAM_WRAP_6" low="24" high="27" type="uint"/>
++ <bitfield name="PARAM_WRAP_7" low="28" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2184" name="SQ_WRAPPING_1">
++ <bitfield name="PARAM_WRAP_8" low="0" high="3" type="uint"/>
++ <bitfield name="PARAM_WRAP_9" low="4" high="7" type="uint"/>
++ <bitfield name="PARAM_WRAP_10" low="8" high="11" type="uint"/>
++ <bitfield name="PARAM_WRAP_11" low="12" high="15" type="uint"/>
++ <bitfield name="PARAM_WRAP_12" low="16" high="19" type="uint"/>
++ <bitfield name="PARAM_WRAP_13" low="20" high="23" type="uint"/>
++ <bitfield name="PARAM_WRAP_14" low="24" high="27" type="uint"/>
++ <bitfield name="PARAM_WRAP_15" low="28" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x21f6" name="SQ_PS_PROGRAM">
++ <bitfield name="BASE" low="0" high="11" type="uint"/>
++ <bitfield name="SIZE" low="12" high="23" type="uint"/>
++ </reg32>
++ <reg32 offset="0x21f7" name="SQ_VS_PROGRAM">
++ <bitfield name="BASE" low="0" high="11" type="uint"/>
++ <bitfield name="SIZE" low="12" high="23" type="uint"/>
++ </reg32>
++ <reg32 offset="0x21f9" name="VGT_EVENT_INITIATOR"/>
++ <reg32 offset="0x21fc" name="VGT_DRAW_INITIATOR" type="vgt_draw_initiator"/>
++ <reg32 offset="0x21fd" name="VGT_IMMED_DATA"/>
++ <reg32 offset="0x2200" name="RB_DEPTHCONTROL">
++ <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
++ <bitfield name="Z_ENABLE" pos="1" type="boolean"/>
++ <bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/>
++ <bitfield name="EARLY_Z_ENABLE" pos="3" type="boolean"/>
++ <bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/>
++ <bitfield name="BACKFACE_ENABLE" pos="7" type="boolean"/>
++ <bitfield name="STENCILFUNC" low="8" high="10" type="adreno_compare_func"/>
++ <bitfield name="STENCILFAIL" low="11" high="13" type="adreno_stencil_op"/>
++ <bitfield name="STENCILZPASS" low="14" high="16" type="adreno_stencil_op"/>
++ <bitfield name="STENCILZFAIL" low="17" high="19" type="adreno_stencil_op"/>
++ <bitfield name="STENCILFUNC_BF" low="20" high="22" type="adreno_compare_func"/>
++ <bitfield name="STENCILFAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
++ <bitfield name="STENCILZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
++ <bitfield name="STENCILZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
++ </reg32>
++ <reg32 offset="0x2201" name="RB_BLEND_CONTROL">
++ <bitfield name="COLOR_SRCBLEND" low="0" high="4" type="adreno_rb_blend_factor"/>
++ <bitfield name="COLOR_COMB_FCN" low="5" high="7" type="a2xx_rb_blend_opcode"/>
++ <bitfield name="COLOR_DESTBLEND" low="8" high="12" type="adreno_rb_blend_factor"/>
++ <bitfield name="ALPHA_SRCBLEND" low="16" high="20" type="adreno_rb_blend_factor"/>
++ <bitfield name="ALPHA_COMB_FCN" low="21" high="23" type="a2xx_rb_blend_opcode"/>
++ <bitfield name="ALPHA_DESTBLEND" low="24" high="28" type="adreno_rb_blend_factor"/>
++ <bitfield name="BLEND_FORCE_ENABLE" pos="29" type="boolean"/>
++ <bitfield name="BLEND_FORCE" pos="30" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2202" name="RB_COLORCONTROL">
++ <bitfield name="ALPHA_FUNC" low="0" high="2" type="adreno_compare_func"/>
++ <bitfield name="ALPHA_TEST_ENABLE" pos="3" type="boolean"/>
++ <bitfield name="ALPHA_TO_MASK_ENABLE" pos="4" type="boolean"/>
++ <bitfield name="BLEND_DISABLE" pos="5" type="boolean"/>
++ <bitfield name="VOB_ENABLE" pos="6" type="boolean"/>
++ <bitfield name="VS_EXPORTS_FOG" pos="7" type="boolean"/>
++ <bitfield name="ROP_CODE" low="8" high="11" type="uint"/>
++ <bitfield name="DITHER_MODE" low="12" high="13" type="adreno_rb_dither_mode"/>
++ <bitfield name="DITHER_TYPE" low="14" high="15" type="a2xx_rb_dither_type"/>
++ <bitfield name="PIXEL_FOG" pos="16" type="boolean"/>
++ <bitfield name="ALPHA_TO_MASK_OFFSET0" low="24" high="25" type="uint"/>
++ <bitfield name="ALPHA_TO_MASK_OFFSET1" low="26" high="27" type="uint"/>
++ <bitfield name="ALPHA_TO_MASK_OFFSET2" low="28" high="29" type="uint"/>
++ <bitfield name="ALPHA_TO_MASK_OFFSET3" low="30" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2203" name="VGT_CURRENT_BIN_ID_MAX" type="a2xx_vgt_current_bin_id_min_max"/>
++ <reg32 offset="0x2204" name="PA_CL_CLIP_CNTL">
++ <bitfield name="CLIP_DISABLE" pos="16" type="boolean"/>
++ <bitfield name="BOUNDARY_EDGE_FLAG_ENA" pos="18" type="boolean"/>
++ <bitfield name="DX_CLIP_SPACE_DEF" pos="19" type="a2xx_dx_clip_space"/>
++ <bitfield name="DIS_CLIP_ERR_DETECT" pos="20" type="boolean"/>
++ <bitfield name="VTX_KILL_OR" pos="21" type="boolean"/>
++ <bitfield name="XY_NAN_RETAIN" pos="22" type="boolean"/>
++ <bitfield name="Z_NAN_RETAIN" pos="23" type="boolean"/>
++ <bitfield name="W_NAN_RETAIN" pos="24" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2205" name="PA_SU_SC_MODE_CNTL">
++ <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
++ <bitfield name="CULL_BACK" pos="1" type="boolean"/>
++ <bitfield name="FACE" pos="2" type="boolean"/>
++ <bitfield name="POLYMODE" low="3" high="4" type="a2xx_pa_su_sc_polymode"/>
++ <bitfield name="FRONT_PTYPE" low="5" high="7" type="adreno_pa_su_sc_draw"/>
++ <bitfield name="BACK_PTYPE" low="8" high="10" type="adreno_pa_su_sc_draw"/>
++ <bitfield name="POLY_OFFSET_FRONT_ENABLE" pos="11" type="boolean"/>
++ <bitfield name="POLY_OFFSET_BACK_ENABLE" pos="12" type="boolean"/>
++ <bitfield name="POLY_OFFSET_PARA_ENABLE" pos="13" type="boolean"/>
++ <bitfield name="MSAA_ENABLE" pos="15" type="boolean"/>
++ <bitfield name="VTX_WINDOW_OFFSET_ENABLE" pos="16" type="boolean"/>
++ <bitfield name="LINE_STIPPLE_ENABLE" pos="18" type="boolean"/>
++ <bitfield name="PROVOKING_VTX_LAST" pos="19" type="boolean"/>
++ <bitfield name="PERSP_CORR_DIS" pos="20" type="boolean"/>
++ <bitfield name="MULTI_PRIM_IB_ENA" pos="21" type="boolean"/>
++ <bitfield name="QUAD_ORDER_ENABLE" pos="23" type="boolean"/>
++ <bitfield name="WAIT_RB_IDLE_ALL_TRI" pos="25" type="boolean"/>
++ <bitfield name="WAIT_RB_IDLE_FIRST_TRI_NEW_STATE" pos="26" type="boolean"/>
++ <bitfield name="CLAMPED_FACENESS" pos="28" type="boolean"/>
++ <bitfield name="ZERO_AREA_FACENESS" pos="29" type="boolean"/>
++ <bitfield name="FACE_KILL_ENABLE" pos="30" type="boolean"/>
++ <bitfield name="FACE_WRITE_ENABLE" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2206" name="PA_CL_VTE_CNTL">
++ <bitfield name="VPORT_X_SCALE_ENA" pos="0" type="boolean"/>
++ <bitfield name="VPORT_X_OFFSET_ENA" pos="1" type="boolean"/>
++ <bitfield name="VPORT_Y_SCALE_ENA" pos="2" type="boolean"/>
++ <bitfield name="VPORT_Y_OFFSET_ENA" pos="3" type="boolean"/>
++ <bitfield name="VPORT_Z_SCALE_ENA" pos="4" type="boolean"/>
++ <bitfield name="VPORT_Z_OFFSET_ENA" pos="5" type="boolean"/>
++ <bitfield name="VTX_XY_FMT" pos="8" type="boolean"/>
++ <bitfield name="VTX_Z_FMT" pos="9" type="boolean"/>
++ <bitfield name="VTX_W0_FMT" pos="10" type="boolean"/>
++ <bitfield name="PERFCOUNTER_REF" pos="11" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2207" name="VGT_CURRENT_BIN_ID_MIN" type="a2xx_vgt_current_bin_id_min_max"/>
++ <reg32 offset="0x2208" name="RB_MODECONTROL">
++ <bitfield name="EDRAM_MODE" low="0" high="2" type="a2xx_rb_edram_mode"/>
++ </reg32>
++ <reg32 offset="0x2209" name="A220_RB_LRZ_VSC_CONTROL"/>
++ <reg32 offset="0x220a" name="RB_SAMPLE_POS"/>
++ <reg32 offset="0x220b" name="CLEAR_COLOR">
++ <bitfield name="RED" low="0" high="7"/>
++ <bitfield name="GREEN" low="8" high="15"/>
++ <bitfield name="BLUE" low="16" high="23"/>
++ <bitfield name="ALPHA" low="24" high="31"/>
++ </reg32>
++ <reg32 offset="0x2210" name="A220_GRAS_CONTROL"/>
++ <reg32 offset="0x2280" name="PA_SU_POINT_SIZE">
++ <bitfield name="HEIGHT" low="0" high="15" type="ufixed" radix="4"/>
++ <bitfield name="WIDTH" low="16" high="31" type="ufixed" radix="4"/>
++ </reg32>
++ <reg32 offset="0x2281" name="PA_SU_POINT_MINMAX">
++ <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
++ <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
++ </reg32>
++ <reg32 offset="0x2282" name="PA_SU_LINE_CNTL">
++ <bitfield name="WIDTH" low="0" high="15" type="ufixed" radix="4"/>
++ </reg32>
++ <reg32 offset="0x2283" name="PA_SC_LINE_STIPPLE">
++ <bitfield name="LINE_PATTERN" low="0" high="15" type="hex"/>
++ <bitfield name="REPEAT_COUNT" low="16" high="23" type="uint"/>
++ <bitfield name="PATTERN_BIT_ORDER" pos="28" type="a2xx_pa_sc_pattern_bit_order"/>
++ <bitfield name="AUTO_RESET_CNTL" low="29" high="30" type="a2xx_pa_sc_auto_reset_cntl"/>
++ </reg32>
++ <reg32 offset="0x2293" name="PA_SC_VIZ_QUERY">
++ <bitfield name="VIZ_QUERY_ENA" pos="0" type="boolean"/>
++ <bitfield name="VIZ_QUERY_ID" low="1" high="6" type="uint"/>
++ <bitfield name="KILL_PIX_POST_EARLY_Z" pos="8" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2294" name="VGT_ENHANCE"/>
++ <reg32 offset="0x2300" name="PA_SC_LINE_CNTL">
++ <bitfield name="BRES_CNTL" low="0" high="15" type="uint"/>
++ <bitfield name="USE_BRES_CNTL" pos="8" type="boolean"/>
++ <bitfield name="EXPAND_LINE_WIDTH" pos="9" type="boolean"/>
++ <bitfield name="LAST_PIXEL" pos="10" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2301" name="PA_SC_AA_CONFIG">
++ <bitfield name="MSAA_NUM_SAMPLES" low="0" high="2" type="uint"/>
++ <bitfield name="MAX_SAMPLE_DIST" low="13" high="16" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2302" name="PA_SU_VTX_CNTL">
++ <bitfield name="PIX_CENTER" pos="0" type="a2xx_pa_pixcenter"/>
++ <bitfield name="ROUND_MODE" low="1" high="2" type="a2xx_pa_roundmode"/>
++ <bitfield name="QUANT_MODE" low="7" high="9" type="a2xx_pa_quantmode"/>
++ </reg32>
++ <reg32 offset="0x2303" name="PA_CL_GB_VERT_CLIP_ADJ" type="float"/>
++ <reg32 offset="0x2304" name="PA_CL_GB_VERT_DISC_ADJ" type="float"/>
++ <reg32 offset="0x2305" name="PA_CL_GB_HORZ_CLIP_ADJ" type="float"/>
++ <reg32 offset="0x2306" name="PA_CL_GB_HORZ_DISC_ADJ" type="float"/>
++ <reg32 offset="0x2307" name="SQ_VS_CONST">
++ <bitfield name="BASE" low="0" high="8" type="uint"/>
++ <bitfield name="SIZE" low="12" high="20" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2308" name="SQ_PS_CONST">
++ <bitfield name="BASE" low="0" high="8" type="uint"/>
++ <bitfield name="SIZE" low="12" high="20" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2309" name="SQ_DEBUG_MISC_0"/>
++ <reg32 offset="0x230a" name="SQ_DEBUG_MISC_1"/>
++ <reg32 offset="0x2312" name="PA_SC_AA_MASK"/>
++ <reg32 offset="0x2316" name="VGT_VERTEX_REUSE_BLOCK_CNTL">
++ <bitfield name="VTX_REUSE_DEPTH" low="0" high="2" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2317" name="VGT_OUT_DEALLOC_CNTL">
++ <bitfield name="DEALLOC_DIST" low="0" high="1" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2318" name="RB_COPY_CONTROL">
++ <bitfield name="COPY_SAMPLE_SELECT" low="0" high="2" type="a2xx_rb_copy_sample_select"/>
++ <bitfield name="DEPTH_CLEAR_ENABLE" pos="3" type="boolean"/>
++ <bitfield name="CLEAR_MASK" low="4" high="7" type="hex"/>
++ </reg32>
++ <reg32 offset="0x2319" name="RB_COPY_DEST_BASE"/>
++ <reg32 offset="0x231a" name="RB_COPY_DEST_PITCH" shr="5" type="uint"/>
++ <reg32 offset="0x231b" name="RB_COPY_DEST_INFO">
++ <bitfield name="DEST_ENDIAN" low="0" high="2" type="adreno_rb_surface_endian"/>
++ <bitfield name="LINEAR" pos="3" type="boolean"/>
++ <bitfield name="FORMAT" low="4" high="7" type="a2xx_colorformatx"/>
++ <bitfield name="SWAP" low="8" high="9" type="uint"/>
++ <bitfield name="DITHER_MODE" low="10" high="11" type="adreno_rb_dither_mode"/>
++ <bitfield name="DITHER_TYPE" low="12" high="13" type="a2xx_rb_dither_type"/>
++ <bitfield name="WRITE_RED" pos="14" type="boolean"/>
++ <bitfield name="WRITE_GREEN" pos="15" type="boolean"/>
++ <bitfield name="WRITE_BLUE" pos="16" type="boolean"/>
++ <bitfield name="WRITE_ALPHA" pos="17" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x231c" name="RB_COPY_DEST_OFFSET">
++ <bitfield name="X" low="0" high="12" type="uint"/>
++ <bitfield name="Y" low="13" high="25" type="uint"/>
++ </reg32>
++ <reg32 offset="0x231d" name="RB_DEPTH_CLEAR"/>
++ <reg32 offset="0x2324" name="RB_SAMPLE_COUNT_CTL"/>
++ <reg32 offset="0x2326" name="RB_COLOR_DEST_MASK"/>
++ <reg32 offset="0x2340" name="A225_GRAS_UCP0X"/>
++ <reg32 offset="0x2357" name="A225_GRAS_UCP5W"/>
++ <reg32 offset="0x2360" name="A225_GRAS_UCP_ENABLED"/>
++ <reg32 offset="0x2380" name="PA_SU_POLY_OFFSET_FRONT_SCALE"/>
++ <reg32 offset="0x2381" name="PA_SU_POLY_OFFSET_FRONT_OFFSET"/>
++ <reg32 offset="0x2382" name="PA_SU_POLY_OFFSET_BACK_SCALE"/>
++ <reg32 offset="0x2383" name="PA_SU_POLY_OFFSET_BACK_OFFSET"/>
++ <reg32 offset="0x4000" name="SQ_CONSTANT_0"/>
++ <reg32 offset="0x4800" name="SQ_FETCH_0"/>
++ <reg32 offset="0x4900" name="SQ_CF_BOOLEANS"/>
++ <reg32 offset="0x4908" name="SQ_CF_LOOP"/>
++ <reg32 offset="0xa29" name="COHER_SIZE_PM4"/>
++ <reg32 offset="0xa2a" name="COHER_BASE_PM4"/>
++ <reg32 offset="0xa2b" name="COHER_STATUS_PM4"/>
++
++ <reg32 offset="0x0c88" name="PA_SU_PERFCOUNTER0_SELECT"/>
++ <reg32 offset="0x0c89" name="PA_SU_PERFCOUNTER1_SELECT"/>
++ <reg32 offset="0x0c8a" name="PA_SU_PERFCOUNTER2_SELECT"/>
++ <reg32 offset="0x0c8b" name="PA_SU_PERFCOUNTER3_SELECT"/>
++ <reg32 offset="0x0c8c" name="PA_SU_PERFCOUNTER0_LOW"/>
++ <reg32 offset="0x0c8d" name="PA_SU_PERFCOUNTER0_HI"/>
++ <reg32 offset="0x0c8e" name="PA_SU_PERFCOUNTER1_LOW"/>
++ <reg32 offset="0x0c8f" name="PA_SU_PERFCOUNTER1_HI"/>
++ <reg32 offset="0x0c90" name="PA_SU_PERFCOUNTER2_LOW"/>
++ <reg32 offset="0x0c91" name="PA_SU_PERFCOUNTER2_HI"/>
++ <reg32 offset="0x0c92" name="PA_SU_PERFCOUNTER3_LOW"/>
++ <reg32 offset="0x0c93" name="PA_SU_PERFCOUNTER3_HI"/>
++ <reg32 offset="0x0c98" name="PA_SC_PERFCOUNTER0_SELECT"/>
++ <reg32 offset="0x0c99" name="PA_SC_PERFCOUNTER0_LOW"/>
++ <reg32 offset="0x0c9a" name="PA_SC_PERFCOUNTER0_HI"/>
++ <reg32 offset="0x0c48" name="VGT_PERFCOUNTER0_SELECT"/>
++ <reg32 offset="0x0c49" name="VGT_PERFCOUNTER1_SELECT"/>
++ <reg32 offset="0x0c4a" name="VGT_PERFCOUNTER2_SELECT"/>
++ <reg32 offset="0x0c4b" name="VGT_PERFCOUNTER3_SELECT"/>
++ <reg32 offset="0x0c4c" name="VGT_PERFCOUNTER0_LOW"/>
++ <reg32 offset="0x0c4e" name="VGT_PERFCOUNTER1_LOW"/>
++ <reg32 offset="0x0c50" name="VGT_PERFCOUNTER2_LOW"/>
++ <reg32 offset="0x0c52" name="VGT_PERFCOUNTER3_LOW"/>
++ <reg32 offset="0x0c4d" name="VGT_PERFCOUNTER0_HI"/>
++ <reg32 offset="0x0c4f" name="VGT_PERFCOUNTER1_HI"/>
++ <reg32 offset="0x0c51" name="VGT_PERFCOUNTER2_HI"/>
++ <reg32 offset="0x0c53" name="VGT_PERFCOUNTER3_HI"/>
++ <reg32 offset="0x0e05" name="TCR_PERFCOUNTER0_SELECT"/>
++ <reg32 offset="0x0e08" name="TCR_PERFCOUNTER1_SELECT"/>
++ <reg32 offset="0x0e06" name="TCR_PERFCOUNTER0_HI"/>
++ <reg32 offset="0x0e09" name="TCR_PERFCOUNTER1_HI"/>
++ <reg32 offset="0x0e07" name="TCR_PERFCOUNTER0_LOW"/>
++ <reg32 offset="0x0e0a" name="TCR_PERFCOUNTER1_LOW"/>
++ <reg32 offset="0x0e1f" name="TP0_PERFCOUNTER0_SELECT"/>
++ <reg32 offset="0x0e20" name="TP0_PERFCOUNTER0_HI"/>
++ <reg32 offset="0x0e21" name="TP0_PERFCOUNTER0_LOW"/>
++ <reg32 offset="0x0e22" name="TP0_PERFCOUNTER1_SELECT"/>
++ <reg32 offset="0x0e23" name="TP0_PERFCOUNTER1_HI"/>
++ <reg32 offset="0x0e24" name="TP0_PERFCOUNTER1_LOW"/>
++ <reg32 offset="0x0e54" name="TCM_PERFCOUNTER0_SELECT"/>
++ <reg32 offset="0x0e57" name="TCM_PERFCOUNTER1_SELECT"/>
++ <reg32 offset="0x0e55" name="TCM_PERFCOUNTER0_HI"/>
++ <reg32 offset="0x0e58" name="TCM_PERFCOUNTER1_HI"/>
++ <reg32 offset="0x0e56" name="TCM_PERFCOUNTER0_LOW"/>
++ <reg32 offset="0x0e59" name="TCM_PERFCOUNTER1_LOW"/>
++ <reg32 offset="0x0e5a" name="TCF_PERFCOUNTER0_SELECT"/>
++ <reg32 offset="0x0e5d" name="TCF_PERFCOUNTER1_SELECT"/>
++ <reg32 offset="0x0e60" name="TCF_PERFCOUNTER2_SELECT"/>
++ <reg32 offset="0x0e63" name="TCF_PERFCOUNTER3_SELECT"/>
++ <reg32 offset="0x0e66" name="TCF_PERFCOUNTER4_SELECT"/>
++ <reg32 offset="0x0e69" name="TCF_PERFCOUNTER5_SELECT"/>
++ <reg32 offset="0x0e6c" name="TCF_PERFCOUNTER6_SELECT"/>
++ <reg32 offset="0x0e6f" name="TCF_PERFCOUNTER7_SELECT"/>
++ <reg32 offset="0x0e72" name="TCF_PERFCOUNTER8_SELECT"/>
++ <reg32 offset="0x0e75" name="TCF_PERFCOUNTER9_SELECT"/>
++ <reg32 offset="0x0e78" name="TCF_PERFCOUNTER10_SELECT"/>
++ <reg32 offset="0x0e7b" name="TCF_PERFCOUNTER11_SELECT"/>
++ <reg32 offset="0x0e5b" name="TCF_PERFCOUNTER0_HI"/>
++ <reg32 offset="0x0e5e" name="TCF_PERFCOUNTER1_HI"/>
++ <reg32 offset="0x0e61" name="TCF_PERFCOUNTER2_HI"/>
++ <reg32 offset="0x0e64" name="TCF_PERFCOUNTER3_HI"/>
++ <reg32 offset="0x0e67" name="TCF_PERFCOUNTER4_HI"/>
++ <reg32 offset="0x0e6a" name="TCF_PERFCOUNTER5_HI"/>
++ <reg32 offset="0x0e6d" name="TCF_PERFCOUNTER6_HI"/>
++ <reg32 offset="0x0e70" name="TCF_PERFCOUNTER7_HI"/>
++ <reg32 offset="0x0e73" name="TCF_PERFCOUNTER8_HI"/>
++ <reg32 offset="0x0e76" name="TCF_PERFCOUNTER9_HI"/>
++ <reg32 offset="0x0e79" name="TCF_PERFCOUNTER10_HI"/>
++ <reg32 offset="0x0e7c" name="TCF_PERFCOUNTER11_HI"/>
++ <reg32 offset="0x0e5c" name="TCF_PERFCOUNTER0_LOW"/>
++ <reg32 offset="0x0e5f" name="TCF_PERFCOUNTER1_LOW"/>
++ <reg32 offset="0x0e62" name="TCF_PERFCOUNTER2_LOW"/>
++ <reg32 offset="0x0e65" name="TCF_PERFCOUNTER3_LOW"/>
++ <reg32 offset="0x0e68" name="TCF_PERFCOUNTER4_LOW"/>
++ <reg32 offset="0x0e6b" name="TCF_PERFCOUNTER5_LOW"/>
++ <reg32 offset="0x0e6e" name="TCF_PERFCOUNTER6_LOW"/>
++ <reg32 offset="0x0e71" name="TCF_PERFCOUNTER7_LOW"/>
++ <reg32 offset="0x0e74" name="TCF_PERFCOUNTER8_LOW"/>
++ <reg32 offset="0x0e77" name="TCF_PERFCOUNTER9_LOW"/>
++ <reg32 offset="0x0e7a" name="TCF_PERFCOUNTER10_LOW"/>
++ <reg32 offset="0x0e7d" name="TCF_PERFCOUNTER11_LOW"/>
++ <reg32 offset="0x0dc8" name="SQ_PERFCOUNTER0_SELECT"/>
++ <reg32 offset="0x0dc9" name="SQ_PERFCOUNTER1_SELECT"/>
++ <reg32 offset="0x0dca" name="SQ_PERFCOUNTER2_SELECT"/>
++ <reg32 offset="0x0dcb" name="SQ_PERFCOUNTER3_SELECT"/>
++ <reg32 offset="0x0dcc" name="SQ_PERFCOUNTER0_LOW"/>
++ <reg32 offset="0x0dcd" name="SQ_PERFCOUNTER0_HI"/>
++ <reg32 offset="0x0dce" name="SQ_PERFCOUNTER1_LOW"/>
++ <reg32 offset="0x0dcf" name="SQ_PERFCOUNTER1_HI"/>
++ <reg32 offset="0x0dd0" name="SQ_PERFCOUNTER2_LOW"/>
++ <reg32 offset="0x0dd1" name="SQ_PERFCOUNTER2_HI"/>
++ <reg32 offset="0x0dd2" name="SQ_PERFCOUNTER3_LOW"/>
++ <reg32 offset="0x0dd3" name="SQ_PERFCOUNTER3_HI"/>
++ <reg32 offset="0x0dd4" name="SX_PERFCOUNTER0_SELECT"/>
++ <reg32 offset="0x0dd8" name="SX_PERFCOUNTER0_LOW"/>
++ <reg32 offset="0x0dd9" name="SX_PERFCOUNTER0_HI"/>
++ <reg32 offset="0x0a46" name="MH_PERFCOUNTER0_SELECT"/>
++ <reg32 offset="0x0a4a" name="MH_PERFCOUNTER1_SELECT"/>
++ <reg32 offset="0x0a47" name="MH_PERFCOUNTER0_CONFIG"/>
++ <reg32 offset="0x0a4b" name="MH_PERFCOUNTER1_CONFIG"/>
++ <reg32 offset="0x0a48" name="MH_PERFCOUNTER0_LOW"/>
++ <reg32 offset="0x0a4c" name="MH_PERFCOUNTER1_LOW"/>
++ <reg32 offset="0x0a49" name="MH_PERFCOUNTER0_HI"/>
++ <reg32 offset="0x0a4d" name="MH_PERFCOUNTER1_HI"/>
++ <reg32 offset="0x0f04" name="RB_PERFCOUNTER0_SELECT"/>
++ <reg32 offset="0x0f05" name="RB_PERFCOUNTER1_SELECT"/>
++ <reg32 offset="0x0f06" name="RB_PERFCOUNTER2_SELECT"/>
++ <reg32 offset="0x0f07" name="RB_PERFCOUNTER3_SELECT"/>
++ <reg32 offset="0x0f08" name="RB_PERFCOUNTER0_LOW"/>
++ <reg32 offset="0x0f09" name="RB_PERFCOUNTER0_HI"/>
++ <reg32 offset="0x0f0a" name="RB_PERFCOUNTER1_LOW"/>
++ <reg32 offset="0x0f0b" name="RB_PERFCOUNTER1_HI"/>
++ <reg32 offset="0x0f0c" name="RB_PERFCOUNTER2_LOW"/>
++ <reg32 offset="0x0f0d" name="RB_PERFCOUNTER2_HI"/>
++ <reg32 offset="0x0f0e" name="RB_PERFCOUNTER3_LOW"/>
++ <reg32 offset="0x0f0f" name="RB_PERFCOUNTER3_HI"/>
++</domain>
++
++<domain name="A2XX_SQ_TEX" width="32">
++ <doc>Texture state dwords</doc>
++ <enum name="sq_tex_clamp">
++ <value name="SQ_TEX_WRAP" value="0"/>
++ <value name="SQ_TEX_MIRROR" value="1"/>
++ <value name="SQ_TEX_CLAMP_LAST_TEXEL" value="2"/>
++ <value name="SQ_TEX_MIRROR_ONCE_LAST_TEXEL" value="3"/>
++ <value name="SQ_TEX_CLAMP_HALF_BORDER" value="4"/>
++ <value name="SQ_TEX_MIRROR_ONCE_HALF_BORDER" value="5"/>
++ <value name="SQ_TEX_CLAMP_BORDER" value="6"/>
++ <value name="SQ_TEX_MIRROR_ONCE_BORDER" value="7"/>
++ </enum>
++ <enum name="sq_tex_swiz">
++ <value name="SQ_TEX_X" value="0"/>
++ <value name="SQ_TEX_Y" value="1"/>
++ <value name="SQ_TEX_Z" value="2"/>
++ <value name="SQ_TEX_W" value="3"/>
++ <value name="SQ_TEX_ZERO" value="4"/>
++ <value name="SQ_TEX_ONE" value="5"/>
++ </enum>
++ <enum name="sq_tex_filter">
++ <value name="SQ_TEX_FILTER_POINT" value="0"/>
++ <value name="SQ_TEX_FILTER_BILINEAR" value="1"/>
++ <value name="SQ_TEX_FILTER_BASEMAP" value="2"/>
++ <value name="SQ_TEX_FILTER_USE_FETCH_CONST" value="3"/>
++ </enum>
++ <enum name="sq_tex_aniso_filter">
++ <value name="SQ_TEX_ANISO_FILTER_DISABLED" value="0"/>
++ <value name="SQ_TEX_ANISO_FILTER_MAX_1_1" value="1"/>
++ <value name="SQ_TEX_ANISO_FILTER_MAX_2_1" value="2"/>
++ <value name="SQ_TEX_ANISO_FILTER_MAX_4_1" value="3"/>
++ <value name="SQ_TEX_ANISO_FILTER_MAX_8_1" value="4"/>
++ <value name="SQ_TEX_ANISO_FILTER_MAX_16_1" value="5"/>
++ <value name="SQ_TEX_ANISO_FILTER_USE_FETCH_CONST" value="7"/>
++ </enum>
++ <enum name="sq_tex_dimension">
++ <value name="SQ_TEX_DIMENSION_1D" value="0"/>
++ <value name="SQ_TEX_DIMENSION_2D" value="1"/>
++ <value name="SQ_TEX_DIMENSION_3D" value="2"/>
++ <value name="SQ_TEX_DIMENSION_CUBE" value="3"/>
++ </enum>
++ <enum name="sq_tex_border_color">
++ <value name="SQ_TEX_BORDER_COLOR_BLACK" value="0"/>
++ <value name="SQ_TEX_BORDER_COLOR_WHITE" value="1"/>
++ <value name="SQ_TEX_BORDER_COLOR_ACBYCR_BLACK" value="2"/>
++ <value name="SQ_TEX_BORDER_COLOR_ACBCRY_BLACK" value="3"/>
++ </enum>
++ <enum name="sq_tex_sign">
++ <value name="SQ_TEX_SIGN_UNSIGNED" value="0"/>
++ <value name="SQ_TEX_SIGN_SIGNED" value="1"/>
++ <!-- biased: 2*color-1 (range -1,1 when sampling) -->
++ <value name="SQ_TEX_SIGN_UNSIGNED_BIASED" value="2"/>
++ <!-- gamma: sRGB to linear - doesn't seem to work on adreno? -->
++ <value name="SQ_TEX_SIGN_GAMMA" value="3"/>
++ </enum>
++ <enum name="sq_tex_endian">
++ <value name="SQ_TEX_ENDIAN_NONE" value="0"/>
++ <value name="SQ_TEX_ENDIAN_8IN16" value="1"/>
++ <value name="SQ_TEX_ENDIAN_8IN32" value="2"/>
++ <value name="SQ_TEX_ENDIAN_16IN32" value="3"/>
++ </enum>
++ <enum name="sq_tex_clamp_policy">
++ <value name="SQ_TEX_CLAMP_POLICY_D3D" value="0"/>
++ <value name="SQ_TEX_CLAMP_POLICY_OGL" value="1"/>
++ </enum>
++ <enum name="sq_tex_num_format">
++ <value name="SQ_TEX_NUM_FORMAT_FRAC" value="0"/>
++ <value name="SQ_TEX_NUM_FORMAT_INT" value="1"/>
++ </enum>
++ <enum name="sq_tex_type">
++ <value name="SQ_TEX_TYPE_0" value="0"/>
++ <value name="SQ_TEX_TYPE_1" value="1"/>
++ <value name="SQ_TEX_TYPE_2" value="2"/>
++ <value name="SQ_TEX_TYPE_3" value="3"/>
++ </enum>
++ <reg32 offset="0" name="0">
++ <bitfield name="TYPE" low="0" high="1" type="sq_tex_type"/>
++ <bitfield name="SIGN_X" low="2" high="3" type="sq_tex_sign"/>
++ <bitfield name="SIGN_Y" low="4" high="5" type="sq_tex_sign"/>
++ <bitfield name="SIGN_Z" low="6" high="7" type="sq_tex_sign"/>
++ <bitfield name="SIGN_W" low="8" high="9" type="sq_tex_sign"/>
++ <bitfield name="CLAMP_X" low="10" high="12" type="sq_tex_clamp"/>
++ <bitfield name="CLAMP_Y" low="13" high="15" type="sq_tex_clamp"/>
++ <bitfield name="CLAMP_Z" low="16" high="18" type="sq_tex_clamp"/>
++ <bitfield name="PITCH" low="22" high="30" shr="5" type="uint"/>
++ <bitfield name="TILED" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="FORMAT" low="0" high="5" type="a2xx_sq_surfaceformat"/>
++ <bitfield name="ENDIANNESS" low="6" high="7" type="sq_tex_endian"/>
++ <bitfield name="REQUEST_SIZE" low="8" high="9" type="uint"/>
++ <bitfield name="STACKED" pos="10" type="boolean"/>
++ <bitfield name="CLAMP_POLICY" pos="11" type="sq_tex_clamp_policy"/>
++ <bitfield name="BASE_ADDRESS" low="12" high="31" type="uint" shr="12"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="WIDTH" low="0" high="12" type="uint"/>
++ <bitfield name="HEIGHT" low="13" high="25" type="uint"/>
++ <bitfield name="DEPTH" low="26" high="31" type="uint"/>
++ <!-- 1d/3d have different bit configurations -->
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="NUM_FORMAT" pos="0" type="sq_tex_num_format"/>
++ <bitfield name="SWIZ_X" low="1" high="3" type="sq_tex_swiz"/>
++ <bitfield name="SWIZ_Y" low="4" high="6" type="sq_tex_swiz"/>
++ <bitfield name="SWIZ_Z" low="7" high="9" type="sq_tex_swiz"/>
++ <bitfield name="SWIZ_W" low="10" high="12" type="sq_tex_swiz"/>
++ <bitfield name="EXP_ADJUST" low="13" high="18" type="int"/>
++ <bitfield name="XY_MAG_FILTER" low="19" high="20" type="sq_tex_filter"/>
++ <bitfield name="XY_MIN_FILTER" low="21" high="22" type="sq_tex_filter"/>
++ <bitfield name="MIP_FILTER" low="23" high="24" type="sq_tex_filter"/>
++ <bitfield name="ANISO_FILTER" low="25" high="27" type="sq_tex_aniso_filter"/>
++ <bitfield name="BORDER_SIZE" pos="31" type="uint"/>
++ </reg32>
++ <reg32 offset="4" name="4">
++ <bitfield name="VOL_MAG_FILTER" pos="0" type="sq_tex_filter"/>
++ <bitfield name="VOL_MIN_FILTER" pos="1" type="sq_tex_filter"/>
++ <bitfield name="MIP_MIN_LEVEL" low="2" high="5" type="uint"/>
++ <bitfield name="MIP_MAX_LEVEL" low="6" high="9" type="uint"/>
++ <bitfield name="MAX_ANISO_WALK" pos="10" type="boolean"/>
++ <bitfield name="MIN_ANISO_WALK" pos="11" type="boolean"/>
++ <bitfield name="LOD_BIAS" low="12" high="21" type="fixed" radix="5"/>
++ <bitfield name="GRAD_EXP_ADJUST_H" low="22" high="26" type="uint"/>
++ <bitfield name="GRAD_EXP_ADJUST_V" low="27" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="5" name="5">
++ <bitfield name="BORDER_COLOR" low="0" high="1" type="sq_tex_border_color"/>
++ <bitfield name="FORCE_BCW_MAX" pos="2" type="boolean"/>
++ <bitfield name="TRI_CLAMP" low="3" high="4" type="uint"/>
++ <bitfield name="ANISO_BIAS" low="5" high="8" type="fixed" radix="0"/> <!-- radix unknown -->
++ <bitfield name="DIMENSION" low="9" high="10" type="sq_tex_dimension"/>
++ <bitfield name="PACKED_MIPS" pos="11" type="boolean"/>
++ <bitfield name="MIP_ADDRESS" low="12" high="31" type="uint" shr="12"/>
++ </reg32>
++</domain>
++
++</database>
+diff --git a/drivers/gpu/drm/msm/registers/adreno/a3xx.xml b/drivers/gpu/drm/msm/registers/adreno/a3xx.xml
+new file mode 100644
+index 0000000000000..6717abc0a897b
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/adreno/a3xx.xml
+@@ -0,0 +1,1751 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++<import file="adreno/adreno_common.xml"/>
++<import file="adreno/adreno_pm4.xml"/>
++
++<enum name="a3xx_tile_mode">
++ <value name="LINEAR" value="0"/>
++ <value name="TILE_4X4" value="1"/> <!-- "normal" case for textures -->
++ <value name="TILE_32X32" value="2"/> <!-- only used in GMEM -->
++ <value name="TILE_4X2" value="3"/> <!-- only used for CrCb -->
++</enum>
++
++<enum name="a3xx_state_block_id">
++ <value name="HLSQ_BLOCK_ID_TP_TEX" value="2"/>
++ <value name="HLSQ_BLOCK_ID_TP_MIPMAP" value="3"/>
++ <value name="HLSQ_BLOCK_ID_SP_VS" value="4"/>
++ <value name="HLSQ_BLOCK_ID_SP_FS" value="6"/>
++</enum>
++
++<enum name="a3xx_cache_opcode">
++ <value name="INVALIDATE" value="1"/>
++</enum>
++
++<enum name="a3xx_vtx_fmt">
++ <value name="VFMT_32_FLOAT" value="0x0"/>
++ <value name="VFMT_32_32_FLOAT" value="0x1"/>
++ <value name="VFMT_32_32_32_FLOAT" value="0x2"/>
++ <value name="VFMT_32_32_32_32_FLOAT" value="0x3"/>
++
++ <value name="VFMT_16_FLOAT" value="0x4"/>
++ <value name="VFMT_16_16_FLOAT" value="0x5"/>
++ <value name="VFMT_16_16_16_FLOAT" value="0x6"/>
++ <value name="VFMT_16_16_16_16_FLOAT" value="0x7"/>
++
++ <value name="VFMT_32_FIXED" value="0x8"/>
++ <value name="VFMT_32_32_FIXED" value="0x9"/>
++ <value name="VFMT_32_32_32_FIXED" value="0xa"/>
++ <value name="VFMT_32_32_32_32_FIXED" value="0xb"/>
++
++ <value name="VFMT_16_SINT" value="0x10"/>
++ <value name="VFMT_16_16_SINT" value="0x11"/>
++ <value name="VFMT_16_16_16_SINT" value="0x12"/>
++ <value name="VFMT_16_16_16_16_SINT" value="0x13"/>
++ <value name="VFMT_16_UINT" value="0x14"/>
++ <value name="VFMT_16_16_UINT" value="0x15"/>
++ <value name="VFMT_16_16_16_UINT" value="0x16"/>
++ <value name="VFMT_16_16_16_16_UINT" value="0x17"/>
++ <value name="VFMT_16_SNORM" value="0x18"/>
++ <value name="VFMT_16_16_SNORM" value="0x19"/>
++ <value name="VFMT_16_16_16_SNORM" value="0x1a"/>
++ <value name="VFMT_16_16_16_16_SNORM" value="0x1b"/>
++ <value name="VFMT_16_UNORM" value="0x1c"/>
++ <value name="VFMT_16_16_UNORM" value="0x1d"/>
++ <value name="VFMT_16_16_16_UNORM" value="0x1e"/>
++ <value name="VFMT_16_16_16_16_UNORM" value="0x1f"/>
++
++ <!-- seems to be no NORM variants for 32bit.. -->
++ <value name="VFMT_32_UINT" value="0x20"/>
++ <value name="VFMT_32_32_UINT" value="0x21"/>
++ <value name="VFMT_32_32_32_UINT" value="0x22"/>
++ <value name="VFMT_32_32_32_32_UINT" value="0x23"/>
++ <value name="VFMT_32_SINT" value="0x24"/>
++ <value name="VFMT_32_32_SINT" value="0x25"/>
++ <value name="VFMT_32_32_32_SINT" value="0x26"/>
++ <value name="VFMT_32_32_32_32_SINT" value="0x27"/>
++
++ <value name="VFMT_8_UINT" value="0x28"/>
++ <value name="VFMT_8_8_UINT" value="0x29"/>
++ <value name="VFMT_8_8_8_UINT" value="0x2a"/>
++ <value name="VFMT_8_8_8_8_UINT" value="0x2b"/>
++ <value name="VFMT_8_UNORM" value="0x2c"/>
++ <value name="VFMT_8_8_UNORM" value="0x2d"/>
++ <value name="VFMT_8_8_8_UNORM" value="0x2e"/>
++ <value name="VFMT_8_8_8_8_UNORM" value="0x2f"/>
++ <value name="VFMT_8_SINT" value="0x30"/>
++ <value name="VFMT_8_8_SINT" value="0x31"/>
++ <value name="VFMT_8_8_8_SINT" value="0x32"/>
++ <value name="VFMT_8_8_8_8_SINT" value="0x33"/>
++ <value name="VFMT_8_SNORM" value="0x34"/>
++ <value name="VFMT_8_8_SNORM" value="0x35"/>
++ <value name="VFMT_8_8_8_SNORM" value="0x36"/>
++ <value name="VFMT_8_8_8_8_SNORM" value="0x37"/>
++ <value name="VFMT_10_10_10_2_UINT" value="0x38"/>
++ <value name="VFMT_10_10_10_2_UNORM" value="0x39"/>
++ <value name="VFMT_10_10_10_2_SINT" value="0x3a"/>
++ <value name="VFMT_10_10_10_2_SNORM" value="0x3b"/>
++ <value name="VFMT_2_10_10_10_UINT" value="0x3c"/>
++ <value name="VFMT_2_10_10_10_UNORM" value="0x3d"/>
++ <value name="VFMT_2_10_10_10_SINT" value="0x3e"/>
++ <value name="VFMT_2_10_10_10_SNORM" value="0x3f"/>
++
++ <value name="VFMT_NONE" value="0xff"/>
++</enum>
++
++<enum name="a3xx_tex_fmt">
++ <value name="TFMT_5_6_5_UNORM" value="0x4"/>
++ <value name="TFMT_5_5_5_1_UNORM" value="0x5"/>
++ <value name="TFMT_4_4_4_4_UNORM" value="0x7"/>
++ <value name="TFMT_Z16_UNORM" value="0x9"/>
++ <value name="TFMT_X8Z24_UNORM" value="0xa"/>
++ <value name="TFMT_Z32_FLOAT" value="0xb"/>
++
++ <!--
++ The NV12 tiled/linear formats seem to require gang'd sampler
++ slots (ie. sampler state N plus N+1) for Y and UV planes.
++ They fetch yuv in single sam instruction, but still require
++ colorspace conversion in the shader.
++ -->
++ <value name="TFMT_UV_64X32" value="0x10"/>
++ <value name="TFMT_VU_64X32" value="0x11"/>
++ <value name="TFMT_Y_64X32" value="0x12"/>
++ <value name="TFMT_NV12_64X32" value="0x13"/>
++ <value name="TFMT_UV_LINEAR" value="0x14"/>
++ <value name="TFMT_VU_LINEAR" value="0x15"/>
++ <value name="TFMT_Y_LINEAR" value="0x16"/>
++ <value name="TFMT_NV12_LINEAR" value="0x17"/>
++ <value name="TFMT_I420_Y" value="0x18"/>
++ <value name="TFMT_I420_U" value="0x1a"/>
++ <value name="TFMT_I420_V" value="0x1b"/>
++
++ <value name="TFMT_ATC_RGB" value="0x20"/>
++ <value name="TFMT_ATC_RGBA_EXPLICIT" value="0x21"/>
++ <value name="TFMT_ETC1" value="0x22"/>
++ <value name="TFMT_ATC_RGBA_INTERPOLATED" value="0x23"/>
++
++ <value name="TFMT_DXT1" value="0x24"/>
++ <value name="TFMT_DXT3" value="0x25"/>
++ <value name="TFMT_DXT5" value="0x26"/>
++
++ <value name="TFMT_2_10_10_10_UNORM" value="0x28"/>
++ <value name="TFMT_10_10_10_2_UNORM" value="0x29"/>
++ <value name="TFMT_9_9_9_E5_FLOAT" value="0x2a"/>
++ <value name="TFMT_11_11_10_FLOAT" value="0x2b"/>
++ <value name="TFMT_A8_UNORM" value="0x2c"/> <!-- GL_ALPHA -->
++ <value name="TFMT_L8_UNORM" value="0x2d"/>
++ <value name="TFMT_L8_A8_UNORM" value="0x2f"/> <!-- GL_LUMINANCE_ALPHA -->
++
++ <!--
++ NOTE: GL_ALPHA and GL_LUMINANCE_ALPHA aren't handled in a similar way
++ to float16, float32.. but they seem to use non-standard swizzle too..
++ perhaps we can ditch that if the pattern follows of 0xn0, 0xn1, 0xn2,
++ 0xn3 for 1, 2, 3, 4 components respectively..
++
++ Only formats filled in below are the ones that have been observed by
++ the blob or tested.. you can guess what the missing ones are..
++ -->
++
++ <value name="TFMT_8_UNORM" value="0x30"/> <!-- GL_LUMINANCE -->
++ <value name="TFMT_8_8_UNORM" value="0x31"/>
++ <value name="TFMT_8_8_8_UNORM" value="0x32"/>
++ <value name="TFMT_8_8_8_8_UNORM" value="0x33"/>
++
++ <value name="TFMT_8_SNORM" value="0x34"/>
++ <value name="TFMT_8_8_SNORM" value="0x35"/>
++ <value name="TFMT_8_8_8_SNORM" value="0x36"/>
++ <value name="TFMT_8_8_8_8_SNORM" value="0x37"/>
++
++ <value name="TFMT_8_UINT" value="0x38"/>
++ <value name="TFMT_8_8_UINT" value="0x39"/>
++ <value name="TFMT_8_8_8_UINT" value="0x3a"/>
++ <value name="TFMT_8_8_8_8_UINT" value="0x3b"/>
++
++ <value name="TFMT_8_SINT" value="0x3c"/>
++ <value name="TFMT_8_8_SINT" value="0x3d"/>
++ <value name="TFMT_8_8_8_SINT" value="0x3e"/>
++ <value name="TFMT_8_8_8_8_SINT" value="0x3f"/>
++
++ <value name="TFMT_16_FLOAT" value="0x40"/>
++ <value name="TFMT_16_16_FLOAT" value="0x41"/>
++ <!-- TFMT_FLOAT_16_16_16 -->
++ <value name="TFMT_16_16_16_16_FLOAT" value="0x43"/>
++
++ <value name="TFMT_16_UINT" value="0x44"/>
++ <value name="TFMT_16_16_UINT" value="0x45"/>
++ <value name="TFMT_16_16_16_16_UINT" value="0x47"/>
++
++ <value name="TFMT_16_SINT" value="0x48"/>
++ <value name="TFMT_16_16_SINT" value="0x49"/>
++ <value name="TFMT_16_16_16_16_SINT" value="0x4b"/>
++
++ <value name="TFMT_16_UNORM" value="0x4c"/>
++ <value name="TFMT_16_16_UNORM" value="0x4d"/>
++ <value name="TFMT_16_16_16_16_UNORM" value="0x4f"/>
++
++ <value name="TFMT_16_SNORM" value="0x50"/>
++ <value name="TFMT_16_16_SNORM" value="0x51"/>
++ <value name="TFMT_16_16_16_16_SNORM" value="0x53"/>
++
++ <value name="TFMT_32_FLOAT" value="0x54"/>
++ <value name="TFMT_32_32_FLOAT" value="0x55"/>
++ <!-- TFMT_32_32_32_FLOAT -->
++ <value name="TFMT_32_32_32_32_FLOAT" value="0x57"/>
++
++ <value name="TFMT_32_UINT" value="0x58"/>
++ <value name="TFMT_32_32_UINT" value="0x59"/>
++ <value name="TFMT_32_32_32_32_UINT" value="0x5b"/>
++
++ <value name="TFMT_32_SINT" value="0x5c"/>
++ <value name="TFMT_32_32_SINT" value="0x5d"/>
++ <value name="TFMT_32_32_32_32_SINT" value="0x5f"/>
++
++ <value name="TFMT_2_10_10_10_UINT" value="0x60"/>
++ <value name="TFMT_10_10_10_2_UINT" value="0x61"/>
++
++ <value name="TFMT_ETC2_RG11_SNORM" value="0x70"/>
++ <value name="TFMT_ETC2_RG11_UNORM" value="0x71"/>
++ <value name="TFMT_ETC2_R11_SNORM" value="0x72"/>
++ <value name="TFMT_ETC2_R11_UNORM" value="0x73"/>
++ <value name="TFMT_ETC2_RGBA8" value="0x74"/>
++ <value name="TFMT_ETC2_RGB8A1" value="0x75"/>
++ <value name="TFMT_ETC2_RGB8" value="0x76"/>
++
++ <value name="TFMT_NONE" value="0xff"/>
++</enum>
++
++<enum name="a3xx_color_fmt">
++ <value name="RB_R5G6B5_UNORM" value="0x00"/>
++ <value name="RB_R5G5B5A1_UNORM" value="0x01"/>
++ <value name="RB_R4G4B4A4_UNORM" value="0x03"/>
++ <value name="RB_R8G8B8_UNORM" value="0x04"/>
++ <value name="RB_R8G8B8A8_UNORM" value="0x08"/>
++ <value name="RB_R8G8B8A8_SNORM" value="0x09"/>
++ <value name="RB_R8G8B8A8_UINT" value="0x0a"/>
++ <value name="RB_R8G8B8A8_SINT" value="0x0b"/>
++ <value name="RB_R8G8_UNORM" value="0x0c"/>
++ <value name="RB_R8G8_SNORM" value="0x0d"/>
++ <value name="RB_R8G8_UINT" value="0x0e"/>
++ <value name="RB_R8G8_SINT" value="0x0f"/>
++ <value name="RB_R10G10B10A2_UNORM" value="0x10"/>
++ <value name="RB_A2R10G10B10_UNORM" value="0x11"/>
++ <value name="RB_R10G10B10A2_UINT" value="0x12"/>
++ <value name="RB_A2R10G10B10_UINT" value="0x13"/>
++
++ <value name="RB_A8_UNORM" value="0x14"/>
++ <value name="RB_R8_UNORM" value="0x15"/>
++
++ <value name="RB_R16_FLOAT" value="0x18"/>
++ <value name="RB_R16G16_FLOAT" value="0x19"/>
++ <value name="RB_R16G16B16A16_FLOAT" value="0x1b"/> <!-- GL_HALF_FLOAT_OES -->
++ <value name="RB_R11G11B10_FLOAT" value="0x1c"/>
++
++ <value name="RB_R16_SNORM" value="0x20"/>
++ <value name="RB_R16G16_SNORM" value="0x21"/>
++ <value name="RB_R16G16B16A16_SNORM" value="0x23"/>
++
++ <value name="RB_R16_UNORM" value="0x24"/>
++ <value name="RB_R16G16_UNORM" value="0x25"/>
++ <value name="RB_R16G16B16A16_UNORM" value="0x27"/>
++
++ <value name="RB_R16_SINT" value="0x28"/>
++ <value name="RB_R16G16_SINT" value="0x29"/>
++ <value name="RB_R16G16B16A16_SINT" value="0x2b"/>
++
++ <value name="RB_R16_UINT" value="0x2c"/>
++ <value name="RB_R16G16_UINT" value="0x2d"/>
++ <value name="RB_R16G16B16A16_UINT" value="0x2f"/>
++
++ <value name="RB_R32_FLOAT" value="0x30"/>
++ <value name="RB_R32G32_FLOAT" value="0x31"/>
++ <value name="RB_R32G32B32A32_FLOAT" value="0x33"/> <!-- GL_FLOAT -->
++
++ <value name="RB_R32_SINT" value="0x34"/>
++ <value name="RB_R32G32_SINT" value="0x35"/>
++ <value name="RB_R32G32B32A32_SINT" value="0x37"/>
++
++ <value name="RB_R32_UINT" value="0x38"/>
++ <value name="RB_R32G32_UINT" value="0x39"/>
++ <value name="RB_R32G32B32A32_UINT" value="0x3b"/>
++
++ <value name="RB_NONE" value="0xff"/>
++</enum>
++
++<enum name="a3xx_cp_perfcounter_select">
++ <value value="0x00" name="CP_ALWAYS_COUNT"/>
++ <value value="0x03" name="CP_AHB_PFPTRANS_WAIT"/>
++ <value value="0x06" name="CP_AHB_NRTTRANS_WAIT"/>
++ <value value="0x08" name="CP_CSF_NRT_READ_WAIT"/>
++ <value value="0x09" name="CP_CSF_I1_FIFO_FULL"/>
++ <value value="0x0a" name="CP_CSF_I2_FIFO_FULL"/>
++ <value value="0x0b" name="CP_CSF_ST_FIFO_FULL"/>
++ <value value="0x0c" name="CP_RESERVED_12"/>
++ <value value="0x0d" name="CP_CSF_RING_ROQ_FULL"/>
++ <value value="0x0e" name="CP_CSF_I1_ROQ_FULL"/>
++ <value value="0x0f" name="CP_CSF_I2_ROQ_FULL"/>
++ <value value="0x10" name="CP_CSF_ST_ROQ_FULL"/>
++ <value value="0x11" name="CP_RESERVED_17"/>
++ <value value="0x12" name="CP_MIU_TAG_MEM_FULL"/>
++ <value value="0x16" name="CP_MIU_NRT_WRITE_STALLED"/>
++ <value value="0x17" name="CP_MIU_NRT_READ_STALLED"/>
++ <value value="0x1a" name="CP_ME_REGS_RB_DONE_FIFO_FULL"/>
++ <value value="0x1b" name="CP_ME_REGS_VS_EVENT_FIFO_FULL"/>
++ <value value="0x1c" name="CP_ME_REGS_PS_EVENT_FIFO_FULL"/>
++ <value value="0x1d" name="CP_ME_REGS_CF_EVENT_FIFO_FULL"/>
++ <value value="0x1e" name="CP_ME_MICRO_RB_STARVED"/>
++ <value value="0x28" name="CP_AHB_RBBM_DWORD_SENT"/>
++ <value value="0x29" name="CP_ME_BUSY_CLOCKS"/>
++ <value value="0x2a" name="CP_ME_WAIT_CONTEXT_AVAIL"/>
++ <value value="0x2b" name="CP_PFP_TYPE0_PACKET"/>
++ <value value="0x2c" name="CP_PFP_TYPE3_PACKET"/>
++ <value value="0x2d" name="CP_CSF_RB_WPTR_NEQ_RPTR"/>
++ <value value="0x2e" name="CP_CSF_I1_SIZE_NEQ_ZERO"/>
++ <value value="0x2f" name="CP_CSF_I2_SIZE_NEQ_ZERO"/>
++ <value value="0x30" name="CP_CSF_RBI1I2_FETCHING"/>
++</enum>
++
++<enum name="a3xx_gras_tse_perfcounter_select">
++ <value value="0x00" name="GRAS_TSEPERF_INPUT_PRIM"/>
++ <value value="0x01" name="GRAS_TSEPERF_INPUT_NULL_PRIM"/>
++ <value value="0x02" name="GRAS_TSEPERF_TRIVAL_REJ_PRIM"/>
++ <value value="0x03" name="GRAS_TSEPERF_CLIPPED_PRIM"/>
++ <value value="0x04" name="GRAS_TSEPERF_NEW_PRIM"/>
++ <value value="0x05" name="GRAS_TSEPERF_ZERO_AREA_PRIM"/>
++ <value value="0x06" name="GRAS_TSEPERF_FACENESS_CULLED_PRIM"/>
++ <value value="0x07" name="GRAS_TSEPERF_ZERO_PIXEL_PRIM"/>
++ <value value="0x08" name="GRAS_TSEPERF_OUTPUT_NULL_PRIM"/>
++ <value value="0x09" name="GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM"/>
++ <value value="0x0a" name="GRAS_TSEPERF_PRE_CLIP_PRIM"/>
++ <value value="0x0b" name="GRAS_TSEPERF_POST_CLIP_PRIM"/>
++ <value value="0x0c" name="GRAS_TSEPERF_WORKING_CYCLES"/>
++ <value value="0x0d" name="GRAS_TSEPERF_PC_STARVE"/>
++ <value value="0x0e" name="GRAS_TSERASPERF_STALL"/>
++</enum>
++
++<enum name="a3xx_gras_ras_perfcounter_select">
++ <value value="0x00" name="GRAS_RASPERF_16X16_TILES"/>
++ <value value="0x01" name="GRAS_RASPERF_8X8_TILES"/>
++ <value value="0x02" name="GRAS_RASPERF_4X4_TILES"/>
++ <value value="0x03" name="GRAS_RASPERF_WORKING_CYCLES"/>
++ <value value="0x04" name="GRAS_RASPERF_STALL_CYCLES_BY_RB"/>
++ <value value="0x05" name="GRAS_RASPERF_STALL_CYCLES_BY_VSC"/>
++ <value value="0x06" name="GRAS_RASPERF_STARVE_CYCLES_BY_TSE"/>
++</enum>
++
++<enum name="a3xx_hlsq_perfcounter_select">
++ <value value="0x00" name="HLSQ_PERF_SP_VS_CONSTANT"/>
++ <value value="0x01" name="HLSQ_PERF_SP_VS_INSTRUCTIONS"/>
++ <value value="0x02" name="HLSQ_PERF_SP_FS_CONSTANT"/>
++ <value value="0x03" name="HLSQ_PERF_SP_FS_INSTRUCTIONS"/>
++ <value value="0x04" name="HLSQ_PERF_TP_STATE"/>
++ <value value="0x05" name="HLSQ_PERF_QUADS"/>
++ <value value="0x06" name="HLSQ_PERF_PIXELS"/>
++ <value value="0x07" name="HLSQ_PERF_VERTICES"/>
++ <value value="0x08" name="HLSQ_PERF_FS8_THREADS"/>
++ <value value="0x09" name="HLSQ_PERF_FS16_THREADS"/>
++ <value value="0x0a" name="HLSQ_PERF_FS32_THREADS"/>
++ <value value="0x0b" name="HLSQ_PERF_VS8_THREADS"/>
++ <value value="0x0c" name="HLSQ_PERF_VS16_THREADS"/>
++ <value value="0x0d" name="HLSQ_PERF_SP_VS_DATA_BYTES"/>
++ <value value="0x0e" name="HLSQ_PERF_SP_FS_DATA_BYTES"/>
++ <value value="0x0f" name="HLSQ_PERF_ACTIVE_CYCLES"/>
++ <value value="0x10" name="HLSQ_PERF_STALL_CYCLES_SP_STATE"/>
++ <value value="0x11" name="HLSQ_PERF_STALL_CYCLES_SP_VS"/>
++ <value value="0x12" name="HLSQ_PERF_STALL_CYCLES_SP_FS"/>
++ <value value="0x13" name="HLSQ_PERF_STALL_CYCLES_UCHE"/>
++ <value value="0x14" name="HLSQ_PERF_RBBM_LOAD_CYCLES"/>
++ <value value="0x15" name="HLSQ_PERF_DI_TO_VS_START_SP0"/>
++ <value value="0x16" name="HLSQ_PERF_DI_TO_FS_START_SP0"/>
++ <value value="0x17" name="HLSQ_PERF_VS_START_TO_DONE_SP0"/>
++ <value value="0x18" name="HLSQ_PERF_FS_START_TO_DONE_SP0"/>
++ <value value="0x19" name="HLSQ_PERF_SP_STATE_COPY_CYCLES_VS"/>
++ <value value="0x1a" name="HLSQ_PERF_SP_STATE_COPY_CYCLES_FS"/>
++ <value value="0x1b" name="HLSQ_PERF_UCHE_LATENCY_CYCLES"/>
++ <value value="0x1c" name="HLSQ_PERF_UCHE_LATENCY_COUNT"/>
++</enum>
++
++<enum name="a3xx_pc_perfcounter_select">
++ <value value="0x00" name="PC_PCPERF_VISIBILITY_STREAMS"/>
++ <value value="0x01" name="PC_PCPERF_TOTAL_INSTANCES"/>
++ <value value="0x02" name="PC_PCPERF_PRIMITIVES_PC_VPC"/>
++ <value value="0x03" name="PC_PCPERF_PRIMITIVES_KILLED_BY_VS"/>
++ <value value="0x04" name="PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS"/>
++ <value value="0x05" name="PC_PCPERF_DRAWCALLS_KILLED_BY_VS"/>
++ <value value="0x06" name="PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS"/>
++ <value value="0x07" name="PC_PCPERF_VERTICES_TO_VFD"/>
++ <value value="0x08" name="PC_PCPERF_REUSED_VERTICES"/>
++ <value value="0x09" name="PC_PCPERF_CYCLES_STALLED_BY_VFD"/>
++ <value value="0x0a" name="PC_PCPERF_CYCLES_STALLED_BY_TSE"/>
++ <value value="0x0b" name="PC_PCPERF_CYCLES_STALLED_BY_VBIF"/>
++ <value value="0x0c" name="PC_PCPERF_CYCLES_IS_WORKING"/>
++</enum>
++
++<enum name="a3xx_rb_perfcounter_select">
++ <value value="0x00" name="RB_RBPERF_ACTIVE_CYCLES_ANY"/>
++ <value value="0x01" name="RB_RBPERF_ACTIVE_CYCLES_ALL"/>
++ <value value="0x02" name="RB_RBPERF_STARVE_CYCLES_BY_SP"/>
++ <value value="0x03" name="RB_RBPERF_STARVE_CYCLES_BY_RAS"/>
++ <value value="0x04" name="RB_RBPERF_STARVE_CYCLES_BY_MARB"/>
++ <value value="0x05" name="RB_RBPERF_STALL_CYCLES_BY_MARB"/>
++ <value value="0x06" name="RB_RBPERF_STALL_CYCLES_BY_HLSQ"/>
++ <value value="0x07" name="RB_RBPERF_RB_MARB_DATA"/>
++ <value value="0x08" name="RB_RBPERF_SP_RB_QUAD"/>
++ <value value="0x09" name="RB_RBPERF_RAS_EARLY_Z_QUADS"/>
++ <value value="0x0a" name="RB_RBPERF_GMEM_CH0_READ"/>
++ <value value="0x0b" name="RB_RBPERF_GMEM_CH1_READ"/>
++ <value value="0x0c" name="RB_RBPERF_GMEM_CH0_WRITE"/>
++ <value value="0x0d" name="RB_RBPERF_GMEM_CH1_WRITE"/>
++ <value value="0x0e" name="RB_RBPERF_CP_CONTEXT_DONE"/>
++ <value value="0x0f" name="RB_RBPERF_CP_CACHE_FLUSH"/>
++ <value value="0x10" name="RB_RBPERF_CP_ZPASS_DONE"/>
++</enum>
++
++<enum name="a3xx_rbbm_perfcounter_select">
++ <value value="0" name="RBBM_ALAWYS_ON"/>
++ <value value="1" name="RBBM_VBIF_BUSY"/>
++ <value value="2" name="RBBM_TSE_BUSY"/>
++ <value value="3" name="RBBM_RAS_BUSY"/>
++ <value value="4" name="RBBM_PC_DCALL_BUSY"/>
++ <value value="5" name="RBBM_PC_VSD_BUSY"/>
++ <value value="6" name="RBBM_VFD_BUSY"/>
++ <value value="7" name="RBBM_VPC_BUSY"/>
++ <value value="8" name="RBBM_UCHE_BUSY"/>
++ <value value="9" name="RBBM_VSC_BUSY"/>
++ <value value="10" name="RBBM_HLSQ_BUSY"/>
++ <value value="11" name="RBBM_ANY_RB_BUSY"/>
++ <value value="12" name="RBBM_ANY_TEX_BUSY"/>
++ <value value="13" name="RBBM_ANY_USP_BUSY"/>
++ <value value="14" name="RBBM_ANY_MARB_BUSY"/>
++ <value value="15" name="RBBM_ANY_ARB_BUSY"/>
++ <value value="16" name="RBBM_AHB_STATUS_BUSY"/>
++ <value value="17" name="RBBM_AHB_STATUS_STALLED"/>
++ <value value="18" name="RBBM_AHB_STATUS_TXFR"/>
++ <value value="19" name="RBBM_AHB_STATUS_TXFR_SPLIT"/>
++ <value value="20" name="RBBM_AHB_STATUS_TXFR_ERROR"/>
++ <value value="21" name="RBBM_AHB_STATUS_LONG_STALL"/>
++ <value value="22" name="RBBM_RBBM_STATUS_MASKED"/>
++</enum>
++
++<enum name="a3xx_sp_perfcounter_select">
++ <value value="0x00" name="SP_LM_LOAD_INSTRUCTIONS"/>
++ <value value="0x01" name="SP_LM_STORE_INSTRUCTIONS"/>
++ <value value="0x02" name="SP_LM_ATOMICS"/>
++ <value value="0x03" name="SP_UCHE_LOAD_INSTRUCTIONS"/>
++ <value value="0x04" name="SP_UCHE_STORE_INSTRUCTIONS"/>
++ <value value="0x05" name="SP_UCHE_ATOMICS"/>
++ <value value="0x06" name="SP_VS_TEX_INSTRUCTIONS"/>
++ <value value="0x07" name="SP_VS_CFLOW_INSTRUCTIONS"/>
++ <value value="0x08" name="SP_VS_EFU_INSTRUCTIONS"/>
++ <value value="0x09" name="SP_VS_FULL_ALU_INSTRUCTIONS"/>
++ <value value="0x0a" name="SP_VS_HALF_ALU_INSTRUCTIONS"/>
++ <value value="0x0b" name="SP_FS_TEX_INSTRUCTIONS"/>
++ <value value="0x0c" name="SP_FS_CFLOW_INSTRUCTIONS"/>
++ <value value="0x0d" name="SP_FS_EFU_INSTRUCTIONS"/>
++ <value value="0x0e" name="SP_FS_FULL_ALU_INSTRUCTIONS"/>
++ <value value="0x0f" name="SP_FS_HALF_ALU_INSTRUCTIONS"/>
++ <value value="0x10" name="SP_FS_BARY_INSTRUCTIONS"/>
++ <value value="0x11" name="SP_VS_INSTRUCTIONS"/>
++ <value value="0x12" name="SP_FS_INSTRUCTIONS"/>
++ <value value="0x13" name="SP_ADDR_LOCK_COUNT"/>
++ <value value="0x14" name="SP_UCHE_READ_TRANS"/>
++ <value value="0x15" name="SP_UCHE_WRITE_TRANS"/>
++ <value value="0x16" name="SP_EXPORT_VPC_TRANS"/>
++ <value value="0x17" name="SP_EXPORT_RB_TRANS"/>
++ <value value="0x18" name="SP_PIXELS_KILLED"/>
++ <value value="0x19" name="SP_ICL1_REQUESTS"/>
++ <value value="0x1a" name="SP_ICL1_MISSES"/>
++ <value value="0x1b" name="SP_ICL0_REQUESTS"/>
++ <value value="0x1c" name="SP_ICL0_MISSES"/>
++ <value value="0x1d" name="SP_ALU_ACTIVE_CYCLES"/>
++ <value value="0x1e" name="SP_EFU_ACTIVE_CYCLES"/>
++ <value value="0x1f" name="SP_STALL_CYCLES_BY_VPC"/>
++ <value value="0x20" name="SP_STALL_CYCLES_BY_TP"/>
++ <value value="0x21" name="SP_STALL_CYCLES_BY_UCHE"/>
++ <value value="0x22" name="SP_STALL_CYCLES_BY_RB"/>
++ <value value="0x23" name="SP_ACTIVE_CYCLES_ANY"/>
++ <value value="0x24" name="SP_ACTIVE_CYCLES_ALL"/>
++</enum>
++
++<enum name="a3xx_tp_perfcounter_select">
++ <value value="0x00" name="TPL1_TPPERF_L1_REQUESTS"/>
++ <value value="0x01" name="TPL1_TPPERF_TP0_L1_REQUESTS"/>
++ <value value="0x02" name="TPL1_TPPERF_TP0_L1_MISSES"/>
++ <value value="0x03" name="TPL1_TPPERF_TP1_L1_REQUESTS"/>
++ <value value="0x04" name="TPL1_TPPERF_TP1_L1_MISSES"/>
++ <value value="0x05" name="TPL1_TPPERF_TP2_L1_REQUESTS"/>
++ <value value="0x06" name="TPL1_TPPERF_TP2_L1_MISSES"/>
++ <value value="0x07" name="TPL1_TPPERF_TP3_L1_REQUESTS"/>
++ <value value="0x08" name="TPL1_TPPERF_TP3_L1_MISSES"/>
++ <value value="0x09" name="TPL1_TPPERF_OUTPUT_TEXELS_POINT"/>
++ <value value="0x0a" name="TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR"/>
++ <value value="0x0b" name="TPL1_TPPERF_OUTPUT_TEXELS_MIP"/>
++ <value value="0x0c" name="TPL1_TPPERF_OUTPUT_TEXELS_ANISO"/>
++ <value value="0x0d" name="TPL1_TPPERF_BILINEAR_OPS"/>
++ <value value="0x0e" name="TPL1_TPPERF_QUADSQUADS_OFFSET"/>
++ <value value="0x0f" name="TPL1_TPPERF_QUADQUADS_SHADOW"/>
++ <value value="0x10" name="TPL1_TPPERF_QUADS_ARRAY"/>
++ <value value="0x11" name="TPL1_TPPERF_QUADS_PROJECTION"/>
++ <value value="0x12" name="TPL1_TPPERF_QUADS_GRADIENT"/>
++ <value value="0x13" name="TPL1_TPPERF_QUADS_1D2D"/>
++ <value value="0x14" name="TPL1_TPPERF_QUADS_3DCUBE"/>
++ <value value="0x15" name="TPL1_TPPERF_ZERO_LOD"/>
++ <value value="0x16" name="TPL1_TPPERF_OUTPUT_TEXELS"/>
++ <value value="0x17" name="TPL1_TPPERF_ACTIVE_CYCLES_ANY"/>
++ <value value="0x18" name="TPL1_TPPERF_ACTIVE_CYCLES_ALL"/>
++ <value value="0x19" name="TPL1_TPPERF_STALL_CYCLES_BY_ARB"/>
++ <value value="0x1a" name="TPL1_TPPERF_LATENCY"/>
++ <value value="0x1b" name="TPL1_TPPERF_LATENCY_TRANS"/>
++</enum>
++
++<enum name="a3xx_vfd_perfcounter_select">
++ <value value="0" name="VFD_PERF_UCHE_BYTE_FETCHED"/>
++ <value value="1" name="VFD_PERF_UCHE_TRANS"/>
++ <value value="2" name="VFD_PERF_VPC_BYPASS_COMPONENTS"/>
++ <value value="3" name="VFD_PERF_FETCH_INSTRUCTIONS"/>
++ <value value="4" name="VFD_PERF_DECODE_INSTRUCTIONS"/>
++ <value value="5" name="VFD_PERF_ACTIVE_CYCLES"/>
++ <value value="6" name="VFD_PERF_STALL_CYCLES_UCHE"/>
++ <value value="7" name="VFD_PERF_STALL_CYCLES_HLSQ"/>
++ <value value="8" name="VFD_PERF_STALL_CYCLES_VPC_BYPASS"/>
++ <value value="9" name="VFD_PERF_STALL_CYCLES_VPC_ALLOC"/>
++</enum>
++
++<enum name="a3xx_vpc_perfcounter_select">
++ <value value="0" name="VPC_PERF_SP_LM_PRIMITIVES"/>
++ <value value="1" name="VPC_PERF_COMPONENTS_FROM_SP"/>
++ <value value="2" name="VPC_PERF_SP_LM_COMPONENTS"/>
++ <value value="3" name="VPC_PERF_ACTIVE_CYCLES"/>
++ <value value="4" name="VPC_PERF_STALL_CYCLES_LM"/>
++ <value value="5" name="VPC_PERF_STALL_CYCLES_RAS"/>
++</enum>
++
++<enum name="a3xx_uche_perfcounter_select">
++ <value value="0x00" name="UCHE_UCHEPERF_VBIF_READ_BEATS_TP"/>
++ <value value="0x01" name="UCHE_UCHEPERF_VBIF_READ_BEATS_VFD"/>
++ <value value="0x02" name="UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ"/>
++ <value value="0x03" name="UCHE_UCHEPERF_VBIF_READ_BEATS_MARB"/>
++ <value value="0x04" name="UCHE_UCHEPERF_VBIF_READ_BEATS_SP"/>
++ <value value="0x08" name="UCHE_UCHEPERF_READ_REQUESTS_TP"/>
++ <value value="0x09" name="UCHE_UCHEPERF_READ_REQUESTS_VFD"/>
++ <value value="0x0a" name="UCHE_UCHEPERF_READ_REQUESTS_HLSQ"/>
++ <value value="0x0b" name="UCHE_UCHEPERF_READ_REQUESTS_MARB"/>
++ <value value="0x0c" name="UCHE_UCHEPERF_READ_REQUESTS_SP"/>
++ <value value="0x0d" name="UCHE_UCHEPERF_WRITE_REQUESTS_MARB"/>
++ <value value="0x0e" name="UCHE_UCHEPERF_WRITE_REQUESTS_SP"/>
++ <value value="0x0f" name="UCHE_UCHEPERF_TAG_CHECK_FAILS"/>
++ <value value="0x10" name="UCHE_UCHEPERF_EVICTS"/>
++ <value value="0x11" name="UCHE_UCHEPERF_FLUSHES"/>
++ <value value="0x12" name="UCHE_UCHEPERF_VBIF_LATENCY_CYCLES"/>
++ <value value="0x13" name="UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES"/>
++ <value value="0x14" name="UCHE_UCHEPERF_ACTIVE_CYCLES"/>
++</enum>
++
++<enum name="a3xx_intp_mode">
++ <value name="SMOOTH" value="0"/>
++ <value name="FLAT" value="1"/>
++ <value name="ZERO" value="2"/>
++ <value name="ONE" value="3"/>
++</enum>
++
++<enum name="a3xx_repl_mode">
++ <value name="S" value="1"/>
++ <value name="T" value="2"/>
++ <value name="ONE_T" value="3"/>
++</enum>
++
++<domain name="A3XX" width="32">
++ <!-- RBBM registers -->
++ <reg32 offset="0x0000" name="RBBM_HW_VERSION"/>
++ <reg32 offset="0x0001" name="RBBM_HW_RELEASE"/>
++ <reg32 offset="0x0002" name="RBBM_HW_CONFIGURATION"/>
++ <reg32 offset="0x0010" name="RBBM_CLOCK_CTL"/>
++ <reg32 offset="0x0012" name="RBBM_SP_HYST_CNT"/>
++ <reg32 offset="0x0018" name="RBBM_SW_RESET_CMD"/>
++ <reg32 offset="0x0020" name="RBBM_AHB_CTL0"/>
++ <reg32 offset="0x0021" name="RBBM_AHB_CTL1"/>
++ <reg32 offset="0x0022" name="RBBM_AHB_CMD"/>
++ <reg32 offset="0x0027" name="RBBM_AHB_ERROR_STATUS"/>
++ <reg32 offset="0x002e" name="RBBM_GPR0_CTL"/>
++ <reg32 offset="0x0030" name="RBBM_STATUS">
++ <bitfield name="HI_BUSY" pos="0" type="boolean"/>
++ <bitfield name="CP_ME_BUSY" pos="1" type="boolean"/>
++ <bitfield name="CP_PFP_BUSY" pos="2" type="boolean"/>
++ <bitfield name="CP_NRT_BUSY" pos="14" type="boolean"/>
++ <bitfield name="VBIF_BUSY" pos="15" type="boolean"/>
++ <bitfield name="TSE_BUSY" pos="16" type="boolean"/>
++ <bitfield name="RAS_BUSY" pos="17" type="boolean"/>
++ <bitfield name="RB_BUSY" pos="18" type="boolean"/>
++ <bitfield name="PC_DCALL_BUSY" pos="19" type="boolean"/>
++ <bitfield name="PC_VSD_BUSY" pos="20" type="boolean"/>
++ <bitfield name="VFD_BUSY" pos="21" type="boolean"/>
++ <bitfield name="VPC_BUSY" pos="22" type="boolean"/>
++ <bitfield name="UCHE_BUSY" pos="23" type="boolean"/>
++ <bitfield name="SP_BUSY" pos="24" type="boolean"/>
++ <bitfield name="TPL1_BUSY" pos="25" type="boolean"/>
++ <bitfield name="MARB_BUSY" pos="26" type="boolean"/>
++ <bitfield name="VSC_BUSY" pos="27" type="boolean"/>
++ <bitfield name="ARB_BUSY" pos="28" type="boolean"/>
++ <bitfield name="HLSQ_BUSY" pos="29" type="boolean"/>
++ <bitfield name="GPU_BUSY_NOHC" pos="30" type="boolean"/>
++ <bitfield name="GPU_BUSY" pos="31" type="boolean"/>
++ </reg32>
++ <!-- used in fw CP_WAIT_FOR_IDLE, similar to NQWAIT_UNTIL on a2xx: -->
++ <reg32 offset="0x0040" name="RBBM_NQWAIT_UNTIL"/>
++ <reg32 offset="0x0033" name="RBBM_WAIT_IDLE_CLOCKS_CTL"/>
++ <reg32 offset="0x0050" name="RBBM_INTERFACE_HANG_INT_CTL"/>
++ <reg32 offset="0x0051" name="RBBM_INTERFACE_HANG_MASK_CTL0"/>
++ <reg32 offset="0x0054" name="RBBM_INTERFACE_HANG_MASK_CTL1"/>
++ <reg32 offset="0x0057" name="RBBM_INTERFACE_HANG_MASK_CTL2"/>
++ <reg32 offset="0x005a" name="RBBM_INTERFACE_HANG_MASK_CTL3"/>
++
++ <bitset name="A3XX_INT0">
++ <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
++ <bitfield name="RBBM_AHB_ERROR" pos="1" type="boolean"/>
++ <bitfield name="RBBM_REG_TIMEOUT" pos="2" type="boolean"/>
++ <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3" type="boolean"/>
++ <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4" type="boolean"/>
++ <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="5" type="boolean"/>
++ <bitfield name="VFD_ERROR" pos="6" type="boolean"/>
++ <bitfield name="CP_SW_INT" pos="7" type="boolean"/>
++ <bitfield name="CP_T0_PACKET_IN_IB" pos="8" type="boolean"/>
++ <bitfield name="CP_OPCODE_ERROR" pos="9" type="boolean"/>
++ <bitfield name="CP_RESERVED_BIT_ERROR" pos="10" type="boolean"/>
++ <bitfield name="CP_HW_FAULT" pos="11" type="boolean"/>
++ <bitfield name="CP_DMA" pos="12" type="boolean"/>
++ <bitfield name="CP_IB2_INT" pos="13" type="boolean"/>
++ <bitfield name="CP_IB1_INT" pos="14" type="boolean"/>
++ <bitfield name="CP_RB_INT" pos="15" type="boolean"/>
++ <bitfield name="CP_REG_PROTECT_FAULT" pos="16" type="boolean"/>
++ <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
++ <bitfield name="CP_VS_DONE_TS" pos="18" type="boolean"/>
++ <bitfield name="CP_PS_DONE_TS" pos="19" type="boolean"/>
++ <bitfield name="CACHE_FLUSH_TS" pos="20" type="boolean"/>
++ <bitfield name="CP_AHB_ERROR_HALT" pos="21" type="boolean"/>
++ <bitfield name="MISC_HANG_DETECT" pos="24" type="boolean"/>
++ <bitfield name="UCHE_OOB_ACCESS" pos="25" type="boolean"/>
++ </bitset>
++
++
++ <!--
++ set in pm4 fw INVALID_JUMP_TABLE_ENTRY and CP_INTERRUPT (compare
++ to CP_INT_STATUS in a2xx firmware), so this seems to be the a3xx
++ way for fw to raise and irq:
++ -->
++ <reg32 offset="0x0060" name="RBBM_INT_SET_CMD" type="A3XX_INT0"/>
++ <reg32 offset="0x0061" name="RBBM_INT_CLEAR_CMD" type="A3XX_INT0"/>
++ <reg32 offset="0x0063" name="RBBM_INT_0_MASK" type="A3XX_INT0"/>
++ <reg32 offset="0x0064" name="RBBM_INT_0_STATUS" type="A3XX_INT0"/>
++ <reg32 offset="0x0080" name="RBBM_PERFCTR_CTL">
++ <bitfield name="ENABLE" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0081" name="RBBM_PERFCTR_LOAD_CMD0"/>
++ <reg32 offset="0x0082" name="RBBM_PERFCTR_LOAD_CMD1"/>
++ <reg32 offset="0x0084" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
++ <reg32 offset="0x0085" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
++ <reg32 offset="0x0086" name="RBBM_PERFCOUNTER0_SELECT" type="a3xx_rbbm_perfcounter_select"/>
++ <reg32 offset="0x0087" name="RBBM_PERFCOUNTER1_SELECT" type="a3xx_rbbm_perfcounter_select"/>
++ <reg32 offset="0x0088" name="RBBM_GPU_BUSY_MASKED"/>
++ <reg32 offset="0x0090" name="RBBM_PERFCTR_CP_0_LO"/>
++ <reg32 offset="0x0091" name="RBBM_PERFCTR_CP_0_HI"/>
++ <reg32 offset="0x0092" name="RBBM_PERFCTR_RBBM_0_LO"/>
++ <reg32 offset="0x0093" name="RBBM_PERFCTR_RBBM_0_HI"/>
++ <reg32 offset="0x0094" name="RBBM_PERFCTR_RBBM_1_LO"/>
++ <reg32 offset="0x0095" name="RBBM_PERFCTR_RBBM_1_HI"/>
++ <reg32 offset="0x0096" name="RBBM_PERFCTR_PC_0_LO"/>
++ <reg32 offset="0x0097" name="RBBM_PERFCTR_PC_0_HI"/>
++ <reg32 offset="0x0098" name="RBBM_PERFCTR_PC_1_LO"/>
++ <reg32 offset="0x0099" name="RBBM_PERFCTR_PC_1_HI"/>
++ <reg32 offset="0x009a" name="RBBM_PERFCTR_PC_2_LO"/>
++ <reg32 offset="0x009b" name="RBBM_PERFCTR_PC_2_HI"/>
++ <reg32 offset="0x009c" name="RBBM_PERFCTR_PC_3_LO"/>
++ <reg32 offset="0x009d" name="RBBM_PERFCTR_PC_3_HI"/>
++ <reg32 offset="0x009e" name="RBBM_PERFCTR_VFD_0_LO"/>
++ <reg32 offset="0x009f" name="RBBM_PERFCTR_VFD_0_HI"/>
++ <reg32 offset="0x00a0" name="RBBM_PERFCTR_VFD_1_LO"/>
++ <reg32 offset="0x00a1" name="RBBM_PERFCTR_VFD_1_HI"/>
++ <reg32 offset="0x00a2" name="RBBM_PERFCTR_HLSQ_0_LO"/>
++ <reg32 offset="0x00a3" name="RBBM_PERFCTR_HLSQ_0_HI"/>
++ <reg32 offset="0x00a4" name="RBBM_PERFCTR_HLSQ_1_LO"/>
++ <reg32 offset="0x00a5" name="RBBM_PERFCTR_HLSQ_1_HI"/>
++ <reg32 offset="0x00a6" name="RBBM_PERFCTR_HLSQ_2_LO"/>
++ <reg32 offset="0x00a7" name="RBBM_PERFCTR_HLSQ_2_HI"/>
++ <reg32 offset="0x00a8" name="RBBM_PERFCTR_HLSQ_3_LO"/>
++ <reg32 offset="0x00a9" name="RBBM_PERFCTR_HLSQ_3_HI"/>
++ <reg32 offset="0x00aa" name="RBBM_PERFCTR_HLSQ_4_LO"/>
++ <reg32 offset="0x00ab" name="RBBM_PERFCTR_HLSQ_4_HI"/>
++ <reg32 offset="0x00ac" name="RBBM_PERFCTR_HLSQ_5_LO"/>
++ <reg32 offset="0x00ad" name="RBBM_PERFCTR_HLSQ_5_HI"/>
++ <reg32 offset="0x00ae" name="RBBM_PERFCTR_VPC_0_LO"/>
++ <reg32 offset="0x00af" name="RBBM_PERFCTR_VPC_0_HI"/>
++ <reg32 offset="0x00b0" name="RBBM_PERFCTR_VPC_1_LO"/>
++ <reg32 offset="0x00b1" name="RBBM_PERFCTR_VPC_1_HI"/>
++ <reg32 offset="0x00b2" name="RBBM_PERFCTR_TSE_0_LO"/>
++ <reg32 offset="0x00b3" name="RBBM_PERFCTR_TSE_0_HI"/>
++ <reg32 offset="0x00b4" name="RBBM_PERFCTR_TSE_1_LO"/>
++ <reg32 offset="0x00b5" name="RBBM_PERFCTR_TSE_1_HI"/>
++ <reg32 offset="0x00b6" name="RBBM_PERFCTR_RAS_0_LO"/>
++ <reg32 offset="0x00b7" name="RBBM_PERFCTR_RAS_0_HI"/>
++ <reg32 offset="0x00b8" name="RBBM_PERFCTR_RAS_1_LO"/>
++ <reg32 offset="0x00b9" name="RBBM_PERFCTR_RAS_1_HI"/>
++ <reg32 offset="0x00ba" name="RBBM_PERFCTR_UCHE_0_LO"/>
++ <reg32 offset="0x00bb" name="RBBM_PERFCTR_UCHE_0_HI"/>
++ <reg32 offset="0x00bc" name="RBBM_PERFCTR_UCHE_1_LO"/>
++ <reg32 offset="0x00bd" name="RBBM_PERFCTR_UCHE_1_HI"/>
++ <reg32 offset="0x00be" name="RBBM_PERFCTR_UCHE_2_LO"/>
++ <reg32 offset="0x00bf" name="RBBM_PERFCTR_UCHE_2_HI"/>
++ <reg32 offset="0x00c0" name="RBBM_PERFCTR_UCHE_3_LO"/>
++ <reg32 offset="0x00c1" name="RBBM_PERFCTR_UCHE_3_HI"/>
++ <reg32 offset="0x00c2" name="RBBM_PERFCTR_UCHE_4_LO"/>
++ <reg32 offset="0x00c3" name="RBBM_PERFCTR_UCHE_4_HI"/>
++ <reg32 offset="0x00c4" name="RBBM_PERFCTR_UCHE_5_LO"/>
++ <reg32 offset="0x00c5" name="RBBM_PERFCTR_UCHE_5_HI"/>
++ <reg32 offset="0x00c6" name="RBBM_PERFCTR_TP_0_LO"/>
++ <reg32 offset="0x00c7" name="RBBM_PERFCTR_TP_0_HI"/>
++ <reg32 offset="0x00c8" name="RBBM_PERFCTR_TP_1_LO"/>
++ <reg32 offset="0x00c9" name="RBBM_PERFCTR_TP_1_HI"/>
++ <reg32 offset="0x00ca" name="RBBM_PERFCTR_TP_2_LO"/>
++ <reg32 offset="0x00cb" name="RBBM_PERFCTR_TP_2_HI"/>
++ <reg32 offset="0x00cc" name="RBBM_PERFCTR_TP_3_LO"/>
++ <reg32 offset="0x00cd" name="RBBM_PERFCTR_TP_3_HI"/>
++ <reg32 offset="0x00ce" name="RBBM_PERFCTR_TP_4_LO"/>
++ <reg32 offset="0x00cf" name="RBBM_PERFCTR_TP_4_HI"/>
++ <reg32 offset="0x00d0" name="RBBM_PERFCTR_TP_5_LO"/>
++ <reg32 offset="0x00d1" name="RBBM_PERFCTR_TP_5_HI"/>
++ <reg32 offset="0x00d2" name="RBBM_PERFCTR_SP_0_LO"/>
++ <reg32 offset="0x00d3" name="RBBM_PERFCTR_SP_0_HI"/>
++ <reg32 offset="0x00d4" name="RBBM_PERFCTR_SP_1_LO"/>
++ <reg32 offset="0x00d5" name="RBBM_PERFCTR_SP_1_HI"/>
++ <reg32 offset="0x00d6" name="RBBM_PERFCTR_SP_2_LO"/>
++ <reg32 offset="0x00d7" name="RBBM_PERFCTR_SP_2_HI"/>
++ <reg32 offset="0x00d8" name="RBBM_PERFCTR_SP_3_LO"/>
++ <reg32 offset="0x00d9" name="RBBM_PERFCTR_SP_3_HI"/>
++ <reg32 offset="0x00da" name="RBBM_PERFCTR_SP_4_LO"/>
++ <reg32 offset="0x00db" name="RBBM_PERFCTR_SP_4_HI"/>
++ <reg32 offset="0x00dc" name="RBBM_PERFCTR_SP_5_LO"/>
++ <reg32 offset="0x00dd" name="RBBM_PERFCTR_SP_5_HI"/>
++ <reg32 offset="0x00de" name="RBBM_PERFCTR_SP_6_LO"/>
++ <reg32 offset="0x00df" name="RBBM_PERFCTR_SP_6_HI"/>
++ <reg32 offset="0x00e0" name="RBBM_PERFCTR_SP_7_LO"/>
++ <reg32 offset="0x00e1" name="RBBM_PERFCTR_SP_7_HI"/>
++ <reg32 offset="0x00e2" name="RBBM_PERFCTR_RB_0_LO"/>
++ <reg32 offset="0x00e3" name="RBBM_PERFCTR_RB_0_HI"/>
++ <reg32 offset="0x00e4" name="RBBM_PERFCTR_RB_1_LO"/>
++ <reg32 offset="0x00e5" name="RBBM_PERFCTR_RB_1_HI"/>
++ <reg32 offset="0x00ea" name="RBBM_PERFCTR_PWR_0_LO"/>
++ <reg32 offset="0x00eb" name="RBBM_PERFCTR_PWR_0_HI"/>
++ <reg32 offset="0x00ec" name="RBBM_PERFCTR_PWR_1_LO"/>
++ <reg32 offset="0x00ed" name="RBBM_PERFCTR_PWR_1_HI"/>
++ <reg32 offset="0x0100" name="RBBM_RBBM_CTL"/>
++ <reg32 offset="0x0111" name="RBBM_DEBUG_BUS_CTL"/>
++ <reg32 offset="0x0112" name="RBBM_DEBUG_BUS_DATA_STATUS"/>
++
++ <!-- CP registers -->
++ <reg32 offset="0x01c9" name="CP_PFP_UCODE_ADDR"/>
++ <reg32 offset="0x01ca" name="CP_PFP_UCODE_DATA"/>
++ <reg32 offset="0x01cc" name="CP_ROQ_ADDR"/>
++ <reg32 offset="0x01cd" name="CP_ROQ_DATA"/>
++ <reg32 offset="0x01d1" name="CP_MERCIU_ADDR"/>
++ <reg32 offset="0x01d2" name="CP_MERCIU_DATA"/>
++ <reg32 offset="0x01d3" name="CP_MERCIU_DATA2"/>
++ <!-- see a3xx_snapshot_cp_meq().. looks like the way to dump queue between pfp and pm4 -->
++ <reg32 offset="0x01da" name="CP_MEQ_ADDR"/>
++ <reg32 offset="0x01db" name="CP_MEQ_DATA"/>
++ <reg32 offset="0x01f5" name="CP_WFI_PEND_CTR"/>
++ <reg32 offset="0x039d" name="RBBM_PM_OVERRIDE2"/>
++
++ <reg32 offset="0x0445" name="CP_PERFCOUNTER_SELECT" type="a3xx_cp_perfcounter_select"/>
++ <reg32 offset="0x045c" name="CP_HW_FAULT"/>
++ <reg32 offset="0x045e" name="CP_PROTECT_CTRL"/>
++ <reg32 offset="0x045f" name="CP_PROTECT_STATUS"/>
++ <array offset="0x0460" name="CP_PROTECT" stride="1" length="16">
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++ <reg32 offset="0x054d" name="CP_AHB_FAULT"/>
++
++ <reg32 offset="0x0d00" name="SQ_GPR_MANAGEMENT"/>
++ <reg32 offset="0x0d02" name="SQ_INST_STORE_MANAGMENT"/>
++ <reg32 offset="0x0e1e" name="TP0_CHICKEN"/>
++
++ <!-- these I guess or either SP or HLSQ since related to shader core setup: -->
++ <reg32 offset="0x0e22" name="SP_GLOBAL_MEM_SIZE" type="uint">
++ <doc>
++ The pair of MEM_SIZE/ADDR registers get programmed
++ in sequence with the size/addr of each buffer.
++ </doc>
++ </reg32>
++ <reg32 offset="0x0e23" name="SP_GLOBAL_MEM_ADDR"/>
++
++ <!-- GRAS registers -->
++ <reg32 offset="0x2040" name="GRAS_CL_CLIP_CNTL">
++ <bitfield name="IJ_PERSP_CENTER" pos="12" type="boolean"/>
++ <bitfield name="IJ_NON_PERSP_CENTER" pos="13" type="boolean"/>
++ <bitfield name="IJ_PERSP_CENTROID" pos="14" type="boolean"/>
++ <bitfield name="IJ_NON_PERSP_CENTROID" pos="15" type="boolean"/>
++ <bitfield name="CLIP_DISABLE" pos="16" type="boolean"/>
++ <bitfield name="ZFAR_CLIP_DISABLE" pos="17" type="boolean"/>
++ <bitfield name="VP_CLIP_CODE_IGNORE" pos="19" type="boolean"/>
++ <bitfield name="VP_XFORM_DISABLE" pos="20" type="boolean"/>
++ <bitfield name="PERSP_DIVISION_DISABLE" pos="21" type="boolean"/>
++ <bitfield name="ZERO_GB_SCALE_Z" pos="22" type="boolean">
++ <doc>aka clip_halfz</doc>
++ </bitfield>
++ <!-- set when gl_FragCoord.z is enabled in frag shader: -->
++ <bitfield name="ZCOORD" pos="23" type="boolean"/>
++ <bitfield name="WCOORD" pos="24" type="boolean"/>
++ <!-- set when frag shader writes z (so early z test disabled: -->
++ <bitfield name="ZCLIP_DISABLE" pos="25" type="boolean"/>
++ <bitfield name="NUM_USER_CLIP_PLANES" low="26" high="28" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2044" name="GRAS_CL_GB_CLIP_ADJ">
++ <bitfield name="HORZ" low="0" high="9" type="uint"/>
++ <bitfield name="VERT" low="10" high="19" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2048" name="GRAS_CL_VPORT_XOFFSET" type="float"/>
++ <reg32 offset="0x2049" name="GRAS_CL_VPORT_XSCALE" type="float"/>
++ <reg32 offset="0x204a" name="GRAS_CL_VPORT_YOFFSET" type="float"/>
++ <reg32 offset="0x204b" name="GRAS_CL_VPORT_YSCALE" type="float"/>
++ <reg32 offset="0x204c" name="GRAS_CL_VPORT_ZOFFSET" type="float"/>
++ <reg32 offset="0x204d" name="GRAS_CL_VPORT_ZSCALE" type="float"/>
++ <reg32 offset="0x2068" name="GRAS_SU_POINT_MINMAX">
++ <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
++ <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
++ </reg32>
++ <reg32 offset="0x2069" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
++ <reg32 offset="0x206c" name="GRAS_SU_POLY_OFFSET_SCALE">
++ <bitfield name="VAL" low="0" high="23" type="fixed" radix="20"/>
++ <doc>range of -8.0 to 8.0</doc>
++ </reg32>
++ <reg32 offset="0x206d" name="GRAS_SU_POLY_OFFSET_OFFSET" radix="6" type="fixed">
++ <doc>range of -512.0 to 512.0</doc>
++ </reg32>
++ <reg32 offset="0x2070" name="GRAS_SU_MODE_CONTROL">
++ <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
++ <bitfield name="CULL_BACK" pos="1" type="boolean"/>
++ <bitfield name="FRONT_CW" pos="2" type="boolean"/>
++ <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
++ <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2072" name="GRAS_SC_CONTROL">
++ <!-- complete wild-ass-guess for sizes of these bitfields.. -->
++ <bitfield name="RENDER_MODE" low="4" high="7" type="a3xx_render_mode"/>
++ <bitfield name="MSAA_SAMPLES" low="8" high="11" type="a3xx_msaa_samples"/>
++ <bitfield name="RASTER_MODE" low="12" high="15"/>
++ </reg32>
++
++ <reg32 offset="0x2074" name="GRAS_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/>
++ <reg32 offset="0x2075" name="GRAS_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/>
++ <reg32 offset="0x2079" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
++ <reg32 offset="0x207a" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
++
++ <!-- RB registers -->
++ <reg32 offset="0x20c0" name="RB_MODE_CONTROL">
++ <!-- guess on the # of bits here.. -->
++ <bitfield name="GMEM_BYPASS" pos="7" type="boolean"/>
++ <doc>
++ RENDER_MODE is RB_RESOLVE_PASS for gmem->mem, otherwise RB_RENDER_PASS
++ </doc>
++ <bitfield name="RENDER_MODE" low="8" high="10" type="a3xx_render_mode"/>
++ <bitfield name="MRT" low="12" high="13" type="uint">
++ <doc>render targets - 1</doc>
++ </bitfield>
++ <bitfield name="MARB_CACHE_SPLIT_MODE" pos="15" type="boolean"/>
++ <bitfield name="PACKER_TIMER_ENABLE" pos="16" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x20c1" name="RB_RENDER_CONTROL">
++ <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
++ <bitfield name="YUV_IN_ENABLE" pos="1" type="boolean"/>
++ <bitfield name="COV_VALUE_INPUT_ENABLE" pos="2" type="boolean"/>
++ <!-- set when gl_FrontFacing is accessed in frag shader: -->
++ <bitfield name="FACENESS" pos="3" type="boolean"/>
++ <bitfield name="BIN_WIDTH" low="4" high="11" shr="5" type="uint"/>
++ <bitfield name="DISABLE_COLOR_PIPE" pos="12" type="boolean"/>
++ <!--
++ ENABLE_GMEM not set on mem2gmem.. so possibly it is actually
++ controlling blend or readback from GMEM??
++ -->
++ <bitfield name="ENABLE_GMEM" pos="13" type="boolean"/>
++ <bitfield name="COORD_MASK" low="14" high="17" type="hex"/>
++ <bitfield name="I_CLAMP_ENABLE" pos="19" type="boolean"/>
++ <bitfield name="COV_VALUE_OUTPUT_ENABLE" pos="20" type="boolean"/>
++ <bitfield name="ALPHA_TEST" pos="22" type="boolean"/>
++ <bitfield name="ALPHA_TEST_FUNC" low="24" high="26" type="adreno_compare_func"/>
++ <bitfield name="ALPHA_TO_COVERAGE" pos="30" type="boolean"/>
++ <bitfield name="ALPHA_TO_ONE" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x20c2" name="RB_MSAA_CONTROL">
++ <bitfield name="DISABLE" pos="10" type="boolean"/>
++ <bitfield name="SAMPLES" low="12" high="15" type="a3xx_msaa_samples"/>
++ <bitfield name="SAMPLE_MASK" low="16" high="31" type="hex"/>
++ </reg32>
++ <reg32 offset="0x20c3" name="RB_ALPHA_REF">
++ <bitfield name="UINT" low="8" high="15" type="hex"/>
++ <bitfield name="FLOAT" low="16" high="31" type="float"/>
++ </reg32>
++ <array offset="0x20c4" name="RB_MRT" stride="4" length="4">
++ <reg32 offset="0x0" name="CONTROL">
++ <bitfield name="READ_DEST_ENABLE" pos="3" type="boolean"/>
++ <!-- both these bits seem to get set when enabling GL_BLEND.. -->
++ <bitfield name="BLEND" pos="4" type="boolean"/>
++ <bitfield name="BLEND2" pos="5" type="boolean"/>
++ <bitfield name="ROP_CODE" low="8" high="11" type="a3xx_rop_code"/>
++ <bitfield name="DITHER_MODE" low="12" high="13" type="adreno_rb_dither_mode"/>
++ <bitfield name="COMPONENT_ENABLE" low="24" high="27" type="hex"/>
++ </reg32>
++ <reg32 offset="0x1" name="BUF_INFO">
++ <bitfield name="COLOR_FORMAT" low="0" high="5" type="a3xx_color_fmt"/>
++ <bitfield name="COLOR_TILE_MODE" low="6" high="7" type="a3xx_tile_mode"/>
++ <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
++ <bitfield name="COLOR_SRGB" pos="14" type="boolean"/>
++ <doc>
++ Pitch (actually, appears to be pitch in bytes, so really is a stride)
++ in GMEM, so pitch of the current tile.
++ </doc>
++ <bitfield name="COLOR_BUF_PITCH" low="17" high="31" shr="5" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2" name="BUF_BASE">
++ <doc>offset into GMEM (or system memory address in bypass mode)</doc>
++ <bitfield name="COLOR_BUF_BASE" low="4" high="31" shr="5" type="hex"/>
++ </reg32>
++ <reg32 offset="0x3" name="BLEND_CONTROL">
++ <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
++ <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
++ <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
++ <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
++ <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
++ <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
++ <bitfield name="CLAMP_ENABLE" pos="29" type="boolean"/>
++ </reg32>
++ </array>
++
++ <reg32 offset="0x20e4" name="RB_BLEND_RED">
++ <bitfield name="UINT" low="0" high="7" type="hex"/>
++ <bitfield name="FLOAT" low="16" high="31" type="float"/>
++ </reg32>
++ <reg32 offset="0x20e5" name="RB_BLEND_GREEN">
++ <bitfield name="UINT" low="0" high="7" type="hex"/>
++ <bitfield name="FLOAT" low="16" high="31" type="float"/>
++ </reg32>
++ <reg32 offset="0x20e6" name="RB_BLEND_BLUE">
++ <bitfield name="UINT" low="0" high="7" type="hex"/>
++ <bitfield name="FLOAT" low="16" high="31" type="float"/>
++ </reg32>
++ <reg32 offset="0x20e7" name="RB_BLEND_ALPHA">
++ <bitfield name="UINT" low="0" high="7" type="hex"/>
++ <bitfield name="FLOAT" low="16" high="31" type="float"/>
++ </reg32>
++
++ <reg32 offset="0x20e8" name="RB_CLEAR_COLOR_DW0"/>
++ <reg32 offset="0x20e9" name="RB_CLEAR_COLOR_DW1"/>
++ <reg32 offset="0x20ea" name="RB_CLEAR_COLOR_DW2"/>
++ <reg32 offset="0x20eb" name="RB_CLEAR_COLOR_DW3"/>
++ <reg32 offset="0x20ec" name="RB_COPY_CONTROL">
++ <!-- not sure # of bits -->
++ <bitfield name="MSAA_RESOLVE" low="0" high="1" type="a3xx_msaa_samples"/>
++ <bitfield name="DEPTHCLEAR" pos="3" type="boolean"/>
++ <bitfield name="MODE" low="4" high="6" type="adreno_rb_copy_control_mode"/>
++ <bitfield name="MSAA_SRGB_DOWNSAMPLE" pos="7" type="boolean"/>
++ <bitfield name="FASTCLEAR" low="8" high="11" type="hex"/>
++ <bitfield name="DEPTH32_RESOLVE" pos="12" type="boolean"/> <!-- enabled on a Z32F copy -->
++ <bitfield name="GMEM_BASE" low="14" high="31" shr="14" type="hex"/>
++ </reg32>
++ <reg32 offset="0x20ed" name="RB_COPY_DEST_BASE">
++ <bitfield name="BASE" low="4" high="31" shr="5" type="hex"/>
++ </reg32>
++ <reg32 offset="0x20ee" name="RB_COPY_DEST_PITCH">
++ <doc>actually, appears to be pitch in bytes, so really is a stride</doc>
++ <!-- not actually sure about max pitch... -->
++ <bitfield name="PITCH" low="0" high="31" shr="5" type="uint"/>
++ </reg32>
++ <reg32 offset="0x20ef" name="RB_COPY_DEST_INFO">
++ <bitfield name="TILE" low="0" high="1" type="a3xx_tile_mode"/>
++ <bitfield name="FORMAT" low="2" high="7" type="a3xx_color_fmt"/>
++ <bitfield name="SWAP" low="8" high="9" type="a3xx_color_swap"/>
++ <bitfield name="DITHER_MODE" low="10" high="11" type="adreno_rb_dither_mode"/>
++ <bitfield name="COMPONENT_ENABLE" low="14" high="17" type="hex"/>
++ <bitfield name="ENDIAN" low="18" high="20" type="adreno_rb_surface_endian"/>
++ </reg32>
++ <reg32 offset="0x2100" name="RB_DEPTH_CONTROL">
++ <!--
++ guessing that this matches a2xx with the stencil fields
++ moved out into RB_STENCIL_CONTROL?
++ -->
++ <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
++ <bitfield name="Z_TEST_ENABLE" pos="1" type="boolean"/>
++ <bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/>
++ <bitfield name="EARLY_Z_DISABLE" pos="3" type="boolean"/>
++ <bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/>
++ <bitfield name="Z_CLAMP_ENABLE" pos="7" type="boolean"/>
++ <doc>Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
++ <bitfield name="Z_READ_ENABLE" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2101" name="RB_DEPTH_CLEAR">
++ <doc>seems to be always set to 0x00000000</doc>
++ </reg32>
++ <reg32 offset="0x2102" name="RB_DEPTH_INFO">
++ <bitfield name="DEPTH_FORMAT" low="0" high="1" type="adreno_rb_depth_format"/>
++ <doc>
++ DEPTH_BASE is offset in GMEM to depth/stencil buffer, ie
++ bin_w * bin_h / 1024 (possible rounded up to multiple of
++ something?? ie. 39 becomes 40, 78 becomes 80.. 75 becomes
++ 80.. so maybe it needs to be multiple of 8??
++ </doc>
++ <bitfield name="DEPTH_BASE" low="11" high="31" shr="12" type="hex"/>
++ </reg32>
++ <reg32 offset="0x2103" name="RB_DEPTH_PITCH" shr="3" type="uint">
++ <doc>
++ Pitch of depth buffer or combined depth+stencil buffer
++ in z24s8 cases.
++ </doc>
++ </reg32>
++ <reg32 offset="0x2104" name="RB_STENCIL_CONTROL">
++ <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
++ <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
++ <!--
++ set for stencil operations that require read from stencil
++ buffer, but not for example for stencil clear (which does
++ not require read).. so guessing this is analogous to
++ READ_DEST_ENABLE for color buffer..
++ -->
++ <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
++ <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
++ <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
++ <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
++ <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
++ <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
++ <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
++ <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
++ <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
++ </reg32>
++ <reg32 offset="0x2105" name="RB_STENCIL_CLEAR">
++ <doc>seems to be always set to 0x00000000</doc>
++ </reg32>
++ <reg32 offset="0x2106" name="RB_STENCIL_INFO">
++ <doc>Base address for stencil when not using interleaved depth/stencil</doc>
++ <bitfield name="STENCIL_BASE" low="11" high="31" shr="12" type="hex"/>
++ </reg32>
++ <reg32 offset="0x2107" name="RB_STENCIL_PITCH" shr="3" type="uint">
++ <doc>pitch of stencil buffer when not using interleaved depth/stencil</doc>
++ </reg32>
++ <reg32 offset="0x2108" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
++ <reg32 offset="0x2109" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
++ <!-- VSC == visibility stream c?? -->
++ <reg32 offset="0x210c" name="RB_LRZ_VSC_CONTROL">
++ <doc>seems to be set to 0x00000002 during binning pass</doc>
++ <bitfield name="BINNING_ENABLE" pos="1" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x210e" name="RB_WINDOW_OFFSET">
++ <doc>X/Y offset of current bin</doc>
++ <bitfield name="X" low="0" high="15" type="uint"/>
++ <bitfield name="Y" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2110" name="RB_SAMPLE_COUNT_CONTROL">
++ <bitfield name="RESET" pos="0" type="boolean"/>
++ <bitfield name="COPY" pos="1" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2111" name="RB_SAMPLE_COUNT_ADDR"/>
++ <reg32 offset="0x2114" name="RB_Z_CLAMP_MIN"/>
++ <reg32 offset="0x2115" name="RB_Z_CLAMP_MAX"/>
++
++ <!-- PC registers -->
++ <reg32 offset="0x21e1" name="VGT_BIN_BASE">
++ <doc>
++ seems to be where firmware writes BIN_DATA_ADDR from
++ CP_SET_BIN_DATA packet.. probably should be called
++ PC_BIN_BASE (just using name from yamato for now)
++ </doc>
++ </reg32>
++ <reg32 offset="0x21e2" name="VGT_BIN_SIZE">
++ <doc>probably should be PC_BIN_SIZE</doc>
++ </reg32>
++ <reg32 offset="0x21e4" name="PC_VSTREAM_CONTROL">
++ <doc>SIZE is current pipe width * height (in tiles)</doc>
++ <bitfield name="SIZE" low="16" high="21" type="uint"/>
++ <doc>
++ N is some sort of slot # between 0..(SIZE-1). In case
++ multiple tiles use same pipe, each tile gets unique slot #
++ </doc>
++ <bitfield name="N" low="22" high="26" type="uint"/>
++ </reg32>
++ <reg32 offset="0x21ea" name="PC_VERTEX_REUSE_BLOCK_CNTL"/>
++ <reg32 offset="0x21ec" name="PC_PRIM_VTX_CNTL">
++ <doc>
++ STRIDE_IN_VPC: ALIGN(next_outloc - 8, 4) / 4
++ (but, in cases where you'd expect 1, the blob driver uses
++ 2, so possibly 0 (no varying) or minimum of 2)
++ </doc>
++ <bitfield name="STRIDE_IN_VPC" low="0" high="4" type="uint"/>
++ <bitfield name="POLYMODE_FRONT_PTYPE" low="5" high="7" type="adreno_pa_su_sc_draw"/>
++ <bitfield name="POLYMODE_BACK_PTYPE" low="8" high="10" type="adreno_pa_su_sc_draw"/>
++ <bitfield name="POLYMODE_ENABLE" pos="12" type="boolean"/>
++ <bitfield name="PRIMITIVE_RESTART" pos="20" type="boolean"/>
++ <bitfield name="PROVOKING_VTX_LAST" pos="25" type="boolean"/>
++ <!-- PSIZE bit set if gl_PointSize written: -->
++ <bitfield name="PSIZE" pos="26" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x21ed" name="PC_RESTART_INDEX"/>
++
++ <!-- HLSQ registers -->
++ <bitset name="a3xx_hlsq_vs_fs_control_reg" inline="yes">
++ <bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>
++ <bitfield name="CONSTSTARTOFFSET" low="12" high="20" type="uint"/>
++ <bitfield name="INSTRLENGTH" low="24" high="31" type="uint"/>
++ </bitset>
++ <bitset name="a3xx_hlsq_const_vs_fs_presv_range_reg" inline="yes">
++ <!-- are these a3xx_regid?? -->
++ <bitfield name="STARTENTRY" low="0" high="8"/>
++ <bitfield name="ENDENTRY" low="16" high="24"/>
++ </bitset>
++
++ <reg32 offset="0x2200" name="HLSQ_CONTROL_0_REG">
++ <bitfield name="FSTHREADSIZE" low="4" high="5" type="a3xx_threadsize"/>
++ <bitfield name="FSSUPERTHREADENABLE" pos="6" type="boolean"/>
++ <bitfield name="COMPUTEMODE" pos="8" type="boolean"/>
++ <bitfield name="SPSHADERRESTART" pos="9" type="boolean"/>
++ <bitfield name="RESERVED2" pos="10" type="boolean"/>
++ <bitfield name="CYCLETIMEOUTLIMITVPC" low="12" high="23" type="uint"/>
++ <bitfield name="FSONLYTEX" pos="25" type="boolean"/>
++ <bitfield name="CHUNKDISABLE" pos="26" type="boolean"/>
++ <bitfield name="CONSTMODE" pos="27" type="uint"/>
++ <bitfield name="LAZYUPDATEDISABLE" pos="28" type="boolean"/>
++ <bitfield name="SPCONSTFULLUPDATE" pos="29" type="boolean"/>
++ <bitfield name="TPFULLUPDATE" pos="30" type="boolean"/>
++ <bitfield name="SINGLECONTEXT" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2201" name="HLSQ_CONTROL_1_REG">
++ <bitfield name="VSTHREADSIZE" low="6" high="7" type="a3xx_threadsize"/>
++ <bitfield name="VSSUPERTHREADENABLE" pos="8" type="boolean"/>
++ <bitfield name="FRAGCOORDXYREGID" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="FRAGCOORDZWREGID" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0x2202" name="HLSQ_CONTROL_2_REG">
++ <bitfield name="FACENESSREGID" low="2" high="9" type="a3xx_regid"/>
++ <bitfield name="COVVALUEREGID" low="18" high="25" type="a3xx_regid"/>
++ <bitfield name="PRIMALLOCTHRESHOLD" low="26" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2203" name="HLSQ_CONTROL_3_REG">
++ <bitfield name="IJPERSPCENTERREGID" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="IJNONPERSPCENTERREGID" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="IJPERSPCENTROIDREGID" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="IJNONPERSPCENTROIDREGID" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0x2204" name="HLSQ_VS_CONTROL_REG" type="a3xx_hlsq_vs_fs_control_reg"/>
++ <reg32 offset="0x2205" name="HLSQ_FS_CONTROL_REG" type="a3xx_hlsq_vs_fs_control_reg"/>
++ <reg32 offset="0x2206" name="HLSQ_CONST_VSPRESV_RANGE_REG" type="a3xx_hlsq_const_vs_fs_presv_range_reg"/>
++ <reg32 offset="0x2207" name="HLSQ_CONST_FSPRESV_RANGE_REG" type="a3xx_hlsq_const_vs_fs_presv_range_reg"/>
++ <reg32 offset="0x220a" name="HLSQ_CL_NDRANGE_0_REG">
++ <bitfield name="WORKDIM" low="0" high="1" type="uint"/>
++ <bitfield name="LOCALSIZE0" low="2" high="11" type="uint"/>
++ <bitfield name="LOCALSIZE1" low="12" high="21" type="uint"/>
++ <bitfield name="LOCALSIZE2" low="22" high="31" type="uint"/>
++ </reg32>
++ <array offset="0x220b" name="HLSQ_CL_GLOBAL_WORK" stride="2" length="3">
++ <doc>indexed by dimension</doc>
++ <reg32 offset="0" name="SIZE" type="uint"/>
++ <reg32 offset="1" name="OFFSET" type="uint"/>
++ </array>
++ <reg32 offset="0x2211" name="HLSQ_CL_CONTROL_0_REG"/>
++ <reg32 offset="0x2212" name="HLSQ_CL_CONTROL_1_REG"/>
++ <reg32 offset="0x2214" name="HLSQ_CL_KERNEL_CONST_REG"/>
++ <array offset="0x2215" name="HLSQ_CL_KERNEL_GROUP" stride="1" length="3">
++ <doc>indexed by dimension, global_size / local_size</doc>
++ <reg32 offset="0" name="RATIO" type="uint"/>
++ </array>
++ <reg32 offset="0x2216" name="HLSQ_CL_KERNEL_GROUP_Y_REG" type="uint"/>
++ <reg32 offset="0x2217" name="HLSQ_CL_KERNEL_GROUP_Z_REG" type="uint"/>
++ <reg32 offset="0x221a" name="HLSQ_CL_WG_OFFSET_REG"/>
++
++ <!-- VFD registers -->
++ <reg32 offset="0x2240" name="VFD_CONTROL_0">
++ <doc>
++ TOTALATTRTOVS is # of attributes to vertex shader, in register
++ slots (ie. vec4+vec3 -> 7)
++ </doc>
++ <bitfield name="TOTALATTRTOVS" low="0" high="17" type="uint"/>
++ <bitfield name="PACKETSIZE" low="18" high="21" type="uint"/>
++ <doc>STRMDECINSTRCNT is # of VFD_DECODE_INSTR registers valid</doc>
++ <bitfield name="STRMDECINSTRCNT" low="22" high="26" type="uint"/>
++ <doc>STRMFETCHINSTRCNT is # of VFD_FETCH_INSTR registers valid</doc>
++ <bitfield name="STRMFETCHINSTRCNT" low="27" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2241" name="VFD_CONTROL_1">
++ <doc>MAXSTORAGE could be # of attributes/vbo's</doc>
++ <bitfield name="MAXSTORAGE" low="0" high="3" type="uint"/>
++ <bitfield name="MAXTHRESHOLD" low="4" high="7" type="uint"/>
++ <bitfield name="MINTHRESHOLD" low="8" high="11" type="uint"/>
++ <bitfield name="REGID4VTX" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="REGID4INST" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0x2242" name="VFD_INDEX_MIN" type="uint"/>
++ <reg32 offset="0x2243" name="VFD_INDEX_MAX" type="uint"/>
++ <reg32 offset="0x2244" name="VFD_INSTANCEID_OFFSET" type="uint"/>
++ <reg32 offset="0x2245" name="VFD_INDEX_OFFSET" type="uint"/>
++ <array offset="0x2246" name="VFD_FETCH" stride="2" length="16">
++ <reg32 offset="0x0" name="INSTR_0">
++ <bitfield name="FETCHSIZE" low="0" high="6" type="uint"/>
++ <bitfield name="BUFSTRIDE" low="7" high="15" type="uint"/>
++ <bitfield name="INSTANCED" pos="16" type="boolean"/>
++ <bitfield name="SWITCHNEXT" pos="17" type="boolean"/>
++ <bitfield name="INDEXCODE" low="18" high="23" type="uint"/>
++ <bitfield name="STEPRATE" low="24" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x1" name="INSTR_1"/>
++ </array>
++ <array offset="0x2266" name="VFD_DECODE" stride="1" length="16">
++ <reg32 offset="0x0" name="INSTR">
++ <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
++ <!-- not sure if this is a bit flag and another flag above it, or?? -->
++ <bitfield name="CONSTFILL" pos="4" type="boolean"/>
++ <bitfield name="FORMAT" low="6" high="11" type="a3xx_vtx_fmt"/>
++ <bitfield name="REGID" low="12" high="19" type="a3xx_regid"/>
++ <bitfield name="INT" pos="20" type="boolean"/>
++ <doc>SHIFTCNT appears to be size, ie. FLOAT_32_32_32 is 12, and BYTE_8 is 1</doc>
++ <bitfield name="SWAP" low="22" high="23" type="a3xx_color_swap"/>
++ <bitfield name="SHIFTCNT" low="24" high="28" type="uint"/>
++ <bitfield name="LASTCOMPVALID" pos="29" type="boolean"/>
++ <bitfield name="SWITCHNEXT" pos="30" type="boolean"/>
++ </reg32>
++ </array>
++ <reg32 offset="0x227e" name="VFD_VS_THREADING_THRESHOLD">
++ <bitfield name="REGID_THRESHOLD" low="0" high="3" type="uint"/>
++ <!-- <bitfield name="RESERVED6" low="4" high="7" type="uint"/> -->
++ <bitfield name="REGID_VTXCNT" low="8" high="15" type="a3xx_regid"/>
++ </reg32>
++
++ <!-- VPC registers -->
++ <reg32 offset="0x2280" name="VPC_ATTR">
++ <bitfield name="TOTALATTR" low="0" high="8" type="uint"/>
++ <!-- PSIZE bit set if gl_PointSize written: -->
++ <bitfield name="PSIZE" pos="9" type="boolean"/>
++ <bitfield name="THRDASSIGN" low="12" high="27" type="uint"/>
++ <bitfield name="LMSIZE" low="28" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2281" name="VPC_PACK">
++ <!-- these are always seem to be set to same as TOTALATTR -->
++ <bitfield name="NUMFPNONPOSVAR" low="8" high="15" type="uint"/>
++ <bitfield name="NUMNONPOSVSVAR" low="16" high="23" type="uint"/>
++ </reg32>
++ <!--
++ varying interpolate mode. One field per scalar/component
++ (since varying slots are scalar, so things don't have to
++ be aligned to vec4).
++ 4 regs * 16 scalar components each => 16 vec4
++ -->
++ <array offset="0x2282" name="VPC_VARYING_INTERP" stride="1" length="4">
++ <reg32 offset="0x0" name="MODE">
++ <bitfield name="C0" low="0" high="1" type="a3xx_intp_mode"/>
++ <bitfield name="C1" low="2" high="3" type="a3xx_intp_mode"/>
++ <bitfield name="C2" low="4" high="5" type="a3xx_intp_mode"/>
++ <bitfield name="C3" low="6" high="7" type="a3xx_intp_mode"/>
++ <bitfield name="C4" low="8" high="9" type="a3xx_intp_mode"/>
++ <bitfield name="C5" low="10" high="11" type="a3xx_intp_mode"/>
++ <bitfield name="C6" low="12" high="13" type="a3xx_intp_mode"/>
++ <bitfield name="C7" low="14" high="15" type="a3xx_intp_mode"/>
++ <bitfield name="C8" low="16" high="17" type="a3xx_intp_mode"/>
++ <bitfield name="C9" low="18" high="19" type="a3xx_intp_mode"/>
++ <bitfield name="CA" low="20" high="21" type="a3xx_intp_mode"/>
++ <bitfield name="CB" low="22" high="23" type="a3xx_intp_mode"/>
++ <bitfield name="CC" low="24" high="25" type="a3xx_intp_mode"/>
++ <bitfield name="CD" low="26" high="27" type="a3xx_intp_mode"/>
++ <bitfield name="CE" low="28" high="29" type="a3xx_intp_mode"/>
++ <bitfield name="CF" low="30" high="31" type="a3xx_intp_mode"/>
++ </reg32>
++ </array>
++ <array offset="0x2286" name="VPC_VARYING_PS_REPL" stride="1" length="4">
++ <reg32 offset="0x0" name="MODE">
++ <bitfield name="C0" low="0" high="1" type="a3xx_repl_mode"/>
++ <bitfield name="C1" low="2" high="3" type="a3xx_repl_mode"/>
++ <bitfield name="C2" low="4" high="5" type="a3xx_repl_mode"/>
++ <bitfield name="C3" low="6" high="7" type="a3xx_repl_mode"/>
++ <bitfield name="C4" low="8" high="9" type="a3xx_repl_mode"/>
++ <bitfield name="C5" low="10" high="11" type="a3xx_repl_mode"/>
++ <bitfield name="C6" low="12" high="13" type="a3xx_repl_mode"/>
++ <bitfield name="C7" low="14" high="15" type="a3xx_repl_mode"/>
++ <bitfield name="C8" low="16" high="17" type="a3xx_repl_mode"/>
++ <bitfield name="C9" low="18" high="19" type="a3xx_repl_mode"/>
++ <bitfield name="CA" low="20" high="21" type="a3xx_repl_mode"/>
++ <bitfield name="CB" low="22" high="23" type="a3xx_repl_mode"/>
++ <bitfield name="CC" low="24" high="25" type="a3xx_repl_mode"/>
++ <bitfield name="CD" low="26" high="27" type="a3xx_repl_mode"/>
++ <bitfield name="CE" low="28" high="29" type="a3xx_repl_mode"/>
++ <bitfield name="CF" low="30" high="31" type="a3xx_repl_mode"/>
++ </reg32>
++ </array>
++ <reg32 offset="0x228a" name="VPC_VARY_CYLWRAP_ENABLE_0"/>
++ <reg32 offset="0x228b" name="VPC_VARY_CYLWRAP_ENABLE_1"/>
++
++ <!-- SP registers -->
++ <bitset name="a3xx_vs_fs_length_reg" inline="yes">
++ <bitfield name="SHADERLENGTH" low="0" high="31" type="uint"/>
++ </bitset>
++
++ <bitset name="sp_vs_fs_obj_offset_reg" inline="yes">
++ <bitfield name="FIRSTEXECINSTROFFSET" low="0" high="15" type="uint"/>
++ <doc>
++ From register spec:
++ SP_FS_OBJ_OFFSET_REG.CONSTOBJECTSTARTOFFSET [16:24]: Constant object
++ start offset in on chip RAM,
++ 128bit aligned
++ </doc>
++ <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
++ <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
++ </bitset>
++
++ <reg32 offset="0x22c0" name="SP_SP_CTRL_REG">
++ <!-- this bit is set during resolve pass: -->
++ <bitfield name="RESOLVE" pos="16" type="boolean"/>
++ <bitfield name="CONSTMODE" pos="18" type="uint"/>
++ <bitfield name="BINNING" pos="19" type="boolean"/>
++ <bitfield name="SLEEPMODE" low="20" high="21" type="uint"/>
++ <!-- L0MODE==1 when oxiliForceSpL0ModeBuffer=1 -->
++ <bitfield name="L0MODE" low="22" high="23" type="uint"/>
++ </reg32>
++ <reg32 offset="0x22c4" name="SP_VS_CTRL_REG0">
++ <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
++ <bitfield name="INSTRBUFFERMODE" pos="1" type="a3xx_instrbuffermode"/>
++ <!-- maybe CACHEINVALID is two bits?? -->
++ <bitfield name="CACHEINVALID" pos="2" type="boolean"/>
++ <bitfield name="ALUSCHMODE" pos="3" type="boolean"/>
++ <doc>
++ The full/half register footprint is in units of four components,
++ so if r0.x is used, that counts as all of r0.[xyzw] as used.
++ There are separate full/half register footprint values as the
++ full and half registers are independent (not overlapping).
++ Presumably the thread scheduler hardware allocates the full/half
++ register names from the actual physical register file and
++ handles the register renaming.
++ </doc>
++ <bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>
++ <bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>
++ <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
++ <bitfield name="SUPERTHREADMODE" pos="21" type="boolean"/>
++ <doc>
++ From regspec:
++ SP_FS_CTRL_REG0.FS_LENGTH [31:24]: FS length, unit = 256bits.
++ If bit31 is 1, it means overflow
++ or any long shader.
++ </doc>
++ <bitfield name="LENGTH" low="24" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x22c5" name="SP_VS_CTRL_REG1">
++ <bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>
++ <!--
++ not sure about full vs half const.. I can't get blob generate
++ something with a mediump/lowp uniform.
++ -->
++ <bitfield name="CONSTFOOTPRINT" low="10" high="19" type="uint"/>
++ <bitfield name="INITIALOUTSTANDING" low="24" high="30" type="uint"/>
++ </reg32>
++ <reg32 offset="0x22c6" name="SP_VS_PARAM_REG">
++ <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="PSIZEREGID" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="POS2DMODE" pos="16" type="boolean"/>
++ <bitfield name="TOTALVSOUTVAR" low="20" high="24" type="uint"/>
++ </reg32>
++ <array offset="0x22c7" name="SP_VS_OUT" stride="1" length="8">
++ <reg32 offset="0x0" name="REG">
++ <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="A_HALF" pos="8" type="boolean"/>
++ <bitfield name="A_COMPMASK" low="9" high="12" type="hex"/>
++ <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="B_HALF" pos="24" type="boolean"/>
++ <bitfield name="B_COMPMASK" low="25" high="28" type="hex"/>
++ </reg32>
++ </array>
++ <array offset="0x22d0" name="SP_VS_VPC_DST" stride="1" length="4">
++ <reg32 offset="0x0" name="REG">
++ <doc>
++ These seem to be offsets for storage of the varyings.
++ Always seems to start from 8, possibly loc 0 and 4
++ are for gl_Position and gl_PointSize?
++ </doc>
++ <bitfield name="OUTLOC0" low="0" high="6" type="uint"/>
++ <bitfield name="OUTLOC1" low="8" high="14" type="uint"/>
++ <bitfield name="OUTLOC2" low="16" high="22" type="uint"/>
++ <bitfield name="OUTLOC3" low="24" high="30" type="uint"/>
++ </reg32>
++ </array>
++ <reg32 offset="0x22d4" name="SP_VS_OBJ_OFFSET_REG" type="sp_vs_fs_obj_offset_reg"/>
++ <doc>
++ SP_VS_OBJ_START_REG contains pointer to the vertex shader program,
++ immediately followed by the binning shader program (although I
++ guess that is probably just re-using the same gpu buffer)
++ </doc>
++ <reg32 offset="0x22d5" name="SP_VS_OBJ_START_REG"/>
++ <reg32 offset="0x22d6" name="SP_VS_PVT_MEM_PARAM_REG">
++ <bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="7">
++ <doc>The size of memory that ldp/stp can address, in 128 byte increments.</doc>
++ </bitfield>
++ <bitfield name="HWSTACKOFFSET" low="8" high="23" type="uint"/>
++ <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x22d7" name="SP_VS_PVT_MEM_ADDR_REG">
++ <bitfield name="BURSTLEN" low="0" high="4"/>
++ <bitfield name="SHADERSTARTADDRESS" shr="5" low="5" high="31"/>
++ </reg32>
++ <reg32 offset="0x22d8" name="SP_VS_PVT_MEM_SIZE_REG"/>
++ <reg32 offset="0x22df" name="SP_VS_LENGTH_REG" type="a3xx_vs_fs_length_reg"/>
++ <reg32 offset="0x22e0" name="SP_FS_CTRL_REG0">
++ <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
++ <bitfield name="INSTRBUFFERMODE" pos="1" type="a3xx_instrbuffermode"/>
++ <!-- maybe CACHEINVALID is two bits?? -->
++ <bitfield name="CACHEINVALID" pos="2" type="boolean"/>
++ <bitfield name="ALUSCHMODE" pos="3" type="boolean"/>
++ <doc>
++ The full/half register footprint is in units of four components,
++ so if r0.x is used, that counts as all of r0.[xyzw] as used.
++ There are separate full/half register footprint values as the
++ full and half registers are independent (not overlapping).
++ Presumably the thread scheduler hardware allocates the full/half
++ register names from the actual physical register file and
++ handles the register renaming.
++ </doc>
++ <bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>
++ <bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>
++ <bitfield name="FSBYPASSENABLE" pos="17" type="boolean"/>
++ <bitfield name="INOUTREGOVERLAP" pos="18" type="boolean"/>
++ <bitfield name="OUTORDERED" pos="19" type="boolean"/>
++ <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
++ <bitfield name="SUPERTHREADMODE" pos="21" type="boolean"/>
++ <bitfield name="PIXLODENABLE" pos="22" type="boolean"/>
++ <bitfield name="COMPUTEMODE" pos="23" type="boolean"/>
++ <doc>
++ From regspec:
++ SP_FS_CTRL_REG0.FS_LENGTH [31:24]: FS length, unit = 256bits.
++ If bit31 is 1, it means overflow
++ or any long shader.
++ </doc>
++ <bitfield name="LENGTH" low="24" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x22e1" name="SP_FS_CTRL_REG1">
++ <bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>
++ <bitfield name="CONSTFOOTPRINT" low="10" high="19" type="uint"/>
++ <bitfield name="INITIALOUTSTANDING" low="20" high="23" type="uint"/>
++ <bitfield name="HALFPRECVAROFFSET" low="24" high="30" type="uint"/>
++ </reg32>
++ <reg32 offset="0x22e2" name="SP_FS_OBJ_OFFSET_REG" type="sp_vs_fs_obj_offset_reg"/>
++ <doc>SP_FS_OBJ_START_REG contains pointer to fragment shader program</doc>
++ <reg32 offset="0x22e3" name="SP_FS_OBJ_START_REG"/>
++ <reg32 offset="0x22e4" name="SP_FS_PVT_MEM_PARAM_REG">
++ <bitfield name="MEMSIZEPERITEM" low="0" high="7" type="uint"/>
++ <bitfield name="HWSTACKOFFSET" low="8" high="23" type="uint"/>
++ <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x22e5" name="SP_FS_PVT_MEM_ADDR_REG">
++ <bitfield name="BURSTLEN" low="0" high="4"/>
++ <bitfield name="SHADERSTARTADDRESS" shr="5" low="5" high="31"/>
++ </reg32>
++ <reg32 offset="0x22e6" name="SP_FS_PVT_MEM_SIZE_REG"/>
++ <reg32 offset="0x22e8" name="SP_FS_FLAT_SHAD_MODE_REG_0">
++ <doc>seems to be one bit per scalar, '1' for flat, '0' for smooth</doc>
++ </reg32>
++ <reg32 offset="0x22e9" name="SP_FS_FLAT_SHAD_MODE_REG_1">
++ <doc>seems to be one bit per scalar, '1' for flat, '0' for smooth</doc>
++ </reg32>
++ <reg32 offset="0x22ec" name="SP_FS_OUTPUT_REG">
++ <bitfield name="MRT" low="0" high="1" type="uint">
++ <doc>render targets - 1</doc>
++ </bitfield>
++ <bitfield name="DEPTH_ENABLE" pos="7" type="boolean"/>
++ <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
++ </reg32>
++ <array offset="0x22f0" name="SP_FS_MRT" stride="1" length="4">
++ <reg32 offset="0x0" name="REG">
++ <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
++ <bitfield name="SINT" pos="10" type="boolean"/>
++ <bitfield name="UINT" pos="11" type="boolean"/>
++ </reg32>
++ </array>
++ <array offset="0x22f4" name="SP_FS_IMAGE_OUTPUT" stride="1" length="4">
++ <reg32 offset="0x0" name="REG">
++ <bitfield name="MRTFORMAT" low="0" high="5" type="a3xx_color_fmt"/>
++ </reg32>
++ </array>
++ <reg32 offset="0x22ff" name="SP_FS_LENGTH_REG" type="a3xx_vs_fs_length_reg"/>
++
++ <reg32 offset="0x2301" name="PA_SC_AA_CONFIG"/>
++ <!-- TPL1 registers -->
++ <!-- assume VS/FS_TEX_OFFSET is same -->
++ <bitset name="a3xx_tpl1_tp_vs_fs_tex_offset" inline="yes">
++ <bitfield name="SAMPLEROFFSET" low="0" high="7" type="uint"/>
++ <bitfield name="MEMOBJOFFSET" low="8" high="15" type="uint"/>
++ <!-- not sure the size of this: -->
++ <bitfield name="BASETABLEPTR" low="16" high="31" type="uint"/>
++ </bitset>
++ <reg32 offset="0x2340" name="TPL1_TP_VS_TEX_OFFSET" type="a3xx_tpl1_tp_vs_fs_tex_offset"/>
++ <reg32 offset="0x2341" name="TPL1_TP_VS_BORDER_COLOR_BASE_ADDR"/>
++ <reg32 offset="0x2342" name="TPL1_TP_FS_TEX_OFFSET" type="a3xx_tpl1_tp_vs_fs_tex_offset"/>
++ <reg32 offset="0x2343" name="TPL1_TP_FS_BORDER_COLOR_BASE_ADDR"/>
++
++ <!-- VBIF registers -->
++ <reg32 offset="0x3001" name="VBIF_CLKON"/>
++ <reg32 offset="0x300c" name="VBIF_FIXED_SORT_EN"/>
++ <reg32 offset="0x300d" name="VBIF_FIXED_SORT_SEL0"/>
++ <reg32 offset="0x300e" name="VBIF_FIXED_SORT_SEL1"/>
++ <reg32 offset="0x301c" name="VBIF_ABIT_SORT"/>
++ <reg32 offset="0x301d" name="VBIF_ABIT_SORT_CONF"/>
++ <reg32 offset="0x302a" name="VBIF_GATE_OFF_WRREQ_EN"/>
++ <reg32 offset="0x302c" name="VBIF_IN_RD_LIM_CONF0"/>
++ <reg32 offset="0x302d" name="VBIF_IN_RD_LIM_CONF1"/>
++ <reg32 offset="0x3030" name="VBIF_IN_WR_LIM_CONF0"/>
++ <reg32 offset="0x3031" name="VBIF_IN_WR_LIM_CONF1"/>
++ <reg32 offset="0x3034" name="VBIF_OUT_RD_LIM_CONF0"/>
++ <reg32 offset="0x3035" name="VBIF_OUT_WR_LIM_CONF0"/>
++ <reg32 offset="0x3036" name="VBIF_DDR_OUT_MAX_BURST"/>
++ <reg32 offset="0x303c" name="VBIF_ARB_CTL"/>
++ <reg32 offset="0x3049" name="VBIF_ROUND_ROBIN_QOS_ARB"/>
++ <reg32 offset="0x3058" name="VBIF_OUT_AXI_AMEMTYPE_CONF0"/>
++ <reg32 offset="0x305e" name="VBIF_OUT_AXI_AOOO_EN"/>
++ <reg32 offset="0x305f" name="VBIF_OUT_AXI_AOOO"/>
++
++ <bitset name="a3xx_vbif_perf_cnt" inline="yes">
++ <bitfield name="CNT0" pos="0" type="boolean"/>
++ <bitfield name="CNT1" pos="1" type="boolean"/>
++ <bitfield name="PWRCNT0" pos="2" type="boolean"/>
++ <bitfield name="PWRCNT1" pos="3" type="boolean"/>
++ <bitfield name="PWRCNT2" pos="4" type="boolean"/>
++ </bitset>
++
++ <reg32 offset="0x3070" name="VBIF_PERF_CNT_EN" type="a3xx_vbif_perf_cnt"/>
++ <reg32 offset="0x3071" name="VBIF_PERF_CNT_CLR" type="a3xx_vbif_perf_cnt"/>
++ <reg32 offset="0x3072" name="VBIF_PERF_CNT_SEL"/>
++ <reg32 offset="0x3073" name="VBIF_PERF_CNT0_LO"/>
++ <reg32 offset="0x3074" name="VBIF_PERF_CNT0_HI"/>
++ <reg32 offset="0x3075" name="VBIF_PERF_CNT1_LO"/>
++ <reg32 offset="0x3076" name="VBIF_PERF_CNT1_HI"/>
++ <reg32 offset="0x3077" name="VBIF_PERF_PWR_CNT0_LO"/>
++ <reg32 offset="0x3078" name="VBIF_PERF_PWR_CNT0_HI"/>
++ <reg32 offset="0x3079" name="VBIF_PERF_PWR_CNT1_LO"/>
++ <reg32 offset="0x307a" name="VBIF_PERF_PWR_CNT1_HI"/>
++ <reg32 offset="0x307b" name="VBIF_PERF_PWR_CNT2_LO"/>
++ <reg32 offset="0x307c" name="VBIF_PERF_PWR_CNT2_HI"/>
++
++
++ <reg32 offset="0x0c01" name="VSC_BIN_SIZE">
++ <bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/>
++ <bitfield name="HEIGHT" low="5" high="9" shr="5" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x0c02" name="VSC_SIZE_ADDRESS"/>
++ <array offset="0x0c06" name="VSC_PIPE" stride="3" length="8">
++ <reg32 offset="0x0" name="CONFIG">
++ <doc>
++ Configures the mapping between VSC_PIPE buffer and
++ bin, X/Y specify the bin index in the horiz/vert
++ direction (0,0 is upper left, 0,1 is leftmost bin
++ on second row, and so on). W/H specify the number
++ of bins assigned to this VSC_PIPE in the horiz/vert
++ dimension.
++ </doc>
++ <bitfield name="X" low="0" high="9" type="uint"/>
++ <bitfield name="Y" low="10" high="19" type="uint"/>
++ <bitfield name="W" low="20" high="23" type="uint"/>
++ <bitfield name="H" low="24" high="27" type="uint"/>
++ </reg32>
++ <reg32 offset="0x1" name="DATA_ADDRESS"/>
++ <reg32 offset="0x2" name="DATA_LENGTH"/>
++ </array>
++ <reg32 offset="0x0c3c" name="VSC_BIN_CONTROL">
++ <doc>seems to be set to 0x00000001 during binning pass</doc>
++ <bitfield name="BINNING_ENABLE" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0c3d" name="UNKNOWN_0C3D">
++ <doc>seems to be always set to 0x00000001</doc>
++ </reg32>
++ <reg32 offset="0x0c48" name="PC_PERFCOUNTER0_SELECT" type="a3xx_pc_perfcounter_select"/>
++ <reg32 offset="0x0c49" name="PC_PERFCOUNTER1_SELECT" type="a3xx_pc_perfcounter_select"/>
++ <reg32 offset="0x0c4a" name="PC_PERFCOUNTER2_SELECT" type="a3xx_pc_perfcounter_select"/>
++ <reg32 offset="0x0c4b" name="PC_PERFCOUNTER3_SELECT" type="a3xx_pc_perfcounter_select"/>
++ <reg32 offset="0x0c81" name="GRAS_TSE_DEBUG_ECO">
++ <doc>seems to be always set to 0x00000001</doc>
++ </reg32>
++
++ <reg32 offset="0x0c88" name="GRAS_PERFCOUNTER0_SELECT" type="a3xx_gras_tse_perfcounter_select"/>
++ <reg32 offset="0x0c89" name="GRAS_PERFCOUNTER1_SELECT" type="a3xx_gras_tse_perfcounter_select"/>
++ <reg32 offset="0x0c8a" name="GRAS_PERFCOUNTER2_SELECT" type="a3xx_gras_ras_perfcounter_select"/>
++ <reg32 offset="0x0c8b" name="GRAS_PERFCOUNTER3_SELECT" type="a3xx_gras_ras_perfcounter_select"/>
++ <array offset="0x0ca0" name="GRAS_CL_USER_PLANE" stride="4" length="6">
++ <reg32 offset="0x0" name="X"/>
++ <reg32 offset="0x1" name="Y"/>
++ <reg32 offset="0x2" name="Z"/>
++ <reg32 offset="0x3" name="W"/>
++ </array>
++ <reg32 offset="0x0cc0" name="RB_GMEM_BASE_ADDR"/>
++ <reg32 offset="0x0cc1" name="RB_DEBUG_ECO_CONTROLS_ADDR"/>
++ <reg32 offset="0x0cc6" name="RB_PERFCOUNTER0_SELECT" type="a3xx_rb_perfcounter_select"/>
++ <reg32 offset="0x0cc7" name="RB_PERFCOUNTER1_SELECT" type="a3xx_rb_perfcounter_select"/>
++ <reg32 offset="0x0ce0" name="RB_FRAME_BUFFER_DIMENSION">
++ <bitfield name="WIDTH" low="0" high="13" type="uint"/>
++ <bitfield name="HEIGHT" low="14" high="27" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0e00" name="HLSQ_PERFCOUNTER0_SELECT" type="a3xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e01" name="HLSQ_PERFCOUNTER1_SELECT" type="a3xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e02" name="HLSQ_PERFCOUNTER2_SELECT" type="a3xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e03" name="HLSQ_PERFCOUNTER3_SELECT" type="a3xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e04" name="HLSQ_PERFCOUNTER4_SELECT" type="a3xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e05" name="HLSQ_PERFCOUNTER5_SELECT" type="a3xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e43" name="UNKNOWN_0E43">
++ <doc>seems to be always set to 0x00000001</doc>
++ </reg32>
++ <reg32 offset="0x0e44" name="VFD_PERFCOUNTER0_SELECT" type="a3xx_vfd_perfcounter_select"/>
++ <reg32 offset="0x0e45" name="VFD_PERFCOUNTER1_SELECT" type="a3xx_vfd_perfcounter_select"/>
++ <reg32 offset="0x0e61" name="VPC_VPC_DEBUG_RAM_SEL"/>
++ <reg32 offset="0x0e62" name="VPC_VPC_DEBUG_RAM_READ"/>
++ <reg32 offset="0x0e64" name="VPC_PERFCOUNTER0_SELECT" type="a3xx_vpc_perfcounter_select"/>
++ <reg32 offset="0x0e65" name="VPC_PERFCOUNTER1_SELECT" type="a3xx_vpc_perfcounter_select"/>
++ <reg32 offset="0x0e82" name="UCHE_CACHE_MODE_CONTROL_REG"/>
++ <reg32 offset="0x0e84" name="UCHE_PERFCOUNTER0_SELECT" type="a3xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0e85" name="UCHE_PERFCOUNTER1_SELECT" type="a3xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0e86" name="UCHE_PERFCOUNTER2_SELECT" type="a3xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0e87" name="UCHE_PERFCOUNTER3_SELECT" type="a3xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0e88" name="UCHE_PERFCOUNTER4_SELECT" type="a3xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0e89" name="UCHE_PERFCOUNTER5_SELECT" type="a3xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0ea0" name="UCHE_CACHE_INVALIDATE0_REG">
++ <!-- might be shifted right by 5, assuming 32byte cache line size.. -->
++ <bitfield name="ADDR" low="0" high="27" type="hex"/>
++ </reg32>
++ <reg32 offset="0x0ea1" name="UCHE_CACHE_INVALIDATE1_REG">
++ <!-- might be shifted right by 5, assuming 32byte cache line size.. -->
++ <bitfield name="ADDR" low="0" high="27" type="hex"/>
++ <!-- I'd assume 2 bits, for FLUSH/INVALIDATE/CLEAN? -->
++ <bitfield name="OPCODE" low="28" high="29" type="a3xx_cache_opcode"/>
++ <bitfield name="ENTIRE_CACHE" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0ea6" name="UNKNOWN_0EA6"/>
++ <reg32 offset="0x0ec4" name="SP_PERFCOUNTER0_SELECT" type="a3xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ec5" name="SP_PERFCOUNTER1_SELECT" type="a3xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ec6" name="SP_PERFCOUNTER2_SELECT" type="a3xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ec7" name="SP_PERFCOUNTER3_SELECT" type="a3xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ec8" name="SP_PERFCOUNTER4_SELECT" type="a3xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ec9" name="SP_PERFCOUNTER5_SELECT" type="a3xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0eca" name="SP_PERFCOUNTER6_SELECT" type="a3xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ecb" name="SP_PERFCOUNTER7_SELECT" type="a3xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ee0" name="UNKNOWN_0EE0">
++ <doc>seems to be always set to 0x00000003</doc>
++ </reg32>
++ <reg32 offset="0x0f03" name="UNKNOWN_0F03">
++ <doc>seems to be always set to 0x00000001</doc>
++ </reg32>
++ <reg32 offset="0x0f04" name="TP_PERFCOUNTER0_SELECT" type="a3xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f05" name="TP_PERFCOUNTER1_SELECT" type="a3xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f06" name="TP_PERFCOUNTER2_SELECT" type="a3xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f07" name="TP_PERFCOUNTER3_SELECT" type="a3xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f08" name="TP_PERFCOUNTER4_SELECT" type="a3xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f09" name="TP_PERFCOUNTER5_SELECT" type="a3xx_tp_perfcounter_select"/>
++
++ <!-- this seems to be the register that CP_RUN_OPENCL writes: -->
++ <reg32 offset="0x21f0" name="VGT_CL_INITIATOR"/>
++
++ <!-- seems to be same as a2xx according to fwdump.. -->
++ <reg32 offset="0x21f9" name="VGT_EVENT_INITIATOR"/>
++ <reg32 offset="0x21fc" name="VGT_DRAW_INITIATOR" type="vgt_draw_initiator"/>
++ <reg32 offset="0x21fd" name="VGT_IMMED_DATA"/>
++</domain>
++
++<domain name="A3XX_TEX_SAMP" width="32">
++ <doc>Texture sampler dwords</doc>
++ <enum name="a3xx_tex_filter">
++ <value name="A3XX_TEX_NEAREST" value="0"/>
++ <value name="A3XX_TEX_LINEAR" value="1"/>
++ <value name="A3XX_TEX_ANISO" value="2"/>
++ </enum>
++ <enum name="a3xx_tex_clamp">
++ <value name="A3XX_TEX_REPEAT" value="0"/>
++ <value name="A3XX_TEX_CLAMP_TO_EDGE" value="1"/>
++ <value name="A3XX_TEX_MIRROR_REPEAT" value="2"/>
++ <value name="A3XX_TEX_CLAMP_TO_BORDER" value="3"/>
++ <value name="A3XX_TEX_MIRROR_CLAMP" value="4"/>
++ </enum>
++ <enum name="a3xx_tex_aniso">
++ <value name="A3XX_TEX_ANISO_1" value="0"/>
++ <value name="A3XX_TEX_ANISO_2" value="1"/>
++ <value name="A3XX_TEX_ANISO_4" value="2"/>
++ <value name="A3XX_TEX_ANISO_8" value="3"/>
++ <value name="A3XX_TEX_ANISO_16" value="4"/>
++ </enum>
++ <reg32 offset="0" name="0">
++ <bitfield name="CLAMPENABLE" pos="0" type="boolean"/>
++ <bitfield name="MIPFILTER_LINEAR" pos="1" type="boolean"/>
++ <bitfield name="XY_MAG" low="2" high="3" type="a3xx_tex_filter"/>
++ <bitfield name="XY_MIN" low="4" high="5" type="a3xx_tex_filter"/>
++ <bitfield name="WRAP_S" low="6" high="8" type="a3xx_tex_clamp"/>
++ <bitfield name="WRAP_T" low="9" high="11" type="a3xx_tex_clamp"/>
++ <bitfield name="WRAP_R" low="12" high="14" type="a3xx_tex_clamp"/>
++ <bitfield name="ANISO" low="15" high="17" type="a3xx_tex_aniso"/>
++ <bitfield name="COMPARE_FUNC" low="20" high="22" type="adreno_compare_func"/>
++ <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="24" type="boolean"/>
++ <!-- UNNORM_COORDS == CLK_NORMALIZED_COORDS_FALSE -->
++ <bitfield name="UNNORM_COORDS" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="LOD_BIAS" low="0" high="10" type="fixed" radix="6"/>
++ <bitfield name="MAX_LOD" low="12" high="21" type="ufixed" radix="6"/>
++ <bitfield name="MIN_LOD" low="22" high="31" type="ufixed" radix="6"/>
++ </reg32>
++</domain>
++
++<domain name="A3XX_TEX_CONST" width="32">
++ <doc>Texture constant dwords</doc>
++ <enum name="a3xx_tex_swiz">
++ <!-- same as a2xx? -->
++ <value name="A3XX_TEX_X" value="0"/>
++ <value name="A3XX_TEX_Y" value="1"/>
++ <value name="A3XX_TEX_Z" value="2"/>
++ <value name="A3XX_TEX_W" value="3"/>
++ <value name="A3XX_TEX_ZERO" value="4"/>
++ <value name="A3XX_TEX_ONE" value="5"/>
++ </enum>
++ <enum name="a3xx_tex_type">
++ <value name="A3XX_TEX_1D" value="0"/>
++ <value name="A3XX_TEX_2D" value="1"/>
++ <value name="A3XX_TEX_CUBE" value="2"/>
++ <value name="A3XX_TEX_3D" value="3"/>
++ </enum>
++ <enum name="a3xx_tex_msaa">
++ <value name="A3XX_TPL1_MSAA1X" value="0"/>
++ <value name="A3XX_TPL1_MSAA2X" value="1"/>
++ <value name="A3XX_TPL1_MSAA4X" value="2"/>
++ <value name="A3XX_TPL1_MSAA8X" value="3"/>
++ </enum>
++ <reg32 offset="0" name="0">
++ <bitfield name="TILE_MODE" low="0" high="1" type="a3xx_tile_mode"/>
++ <bitfield name="SRGB" pos="2" type="boolean"/>
++ <bitfield name="SWIZ_X" low="4" high="6" type="a3xx_tex_swiz"/>
++ <bitfield name="SWIZ_Y" low="7" high="9" type="a3xx_tex_swiz"/>
++ <bitfield name="SWIZ_Z" low="10" high="12" type="a3xx_tex_swiz"/>
++ <bitfield name="SWIZ_W" low="13" high="15" type="a3xx_tex_swiz"/>
++ <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
++ <bitfield name="MSAATEX" low="20" high="21" type="a3xx_tex_msaa"/>
++ <bitfield name="FMT" low="22" high="28" type="a3xx_tex_fmt"/>
++ <bitfield name="NOCONVERT" pos="29" type="boolean"/>
++ <bitfield name="TYPE" low="30" high="31" type="a3xx_tex_type"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="HEIGHT" low="0" high="13" type="uint"/>
++ <bitfield name="WIDTH" low="14" high="27" type="uint"/>
++ <!-- minimum pitch (for mipmap levels): log2(pitchalign / 16) -->
++ <bitfield name="PITCHALIGN" low="28" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <doc>INDX is index of texture address(es) in MIPMAP state block</doc>
++ <bitfield name="INDX" low="0" high="8" type="uint"/>
++ <doc>Pitch in bytes (so actually stride)</doc>
++ <bitfield name="PITCH" low="12" high="29" type="uint"/>
++ <doc>SWAP bit is set for BGRA instead of RGBA</doc>
++ <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <!--
++ Update: the two LAYERSZn seem not to be the same thing.
++ According to Ilia's experimentation the first one goes up
++ to at *least* bit 14..
++ -->
++ <bitfield name="LAYERSZ1" low="0" high="16" shr="12" type="uint"/>
++ <bitfield name="DEPTH" low="17" high="27" type="uint"/>
++ <bitfield name="LAYERSZ2" low="28" high="31" shr="12" type="uint"/>
++ </reg32>
++</domain>
++
++</database>
+diff --git a/drivers/gpu/drm/msm/registers/adreno/a4xx.xml b/drivers/gpu/drm/msm/registers/adreno/a4xx.xml
+new file mode 100644
+index 0000000000000..69a9f9b02bc95
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/adreno/a4xx.xml
+@@ -0,0 +1,2409 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++<import file="adreno/adreno_common.xml"/>
++<import file="adreno/adreno_pm4.xml"/>
++
++<enum name="a4xx_color_fmt">
++ <value name="RB4_A8_UNORM" value="0x01"/>
++ <value name="RB4_R8_UNORM" value="0x02"/>
++ <value name="RB4_R8_SNORM" value="0x03"/>
++ <value name="RB4_R8_UINT" value="0x04"/>
++ <value name="RB4_R8_SINT" value="0x05"/>
++
++ <value name="RB4_R4G4B4A4_UNORM" value="0x08"/>
++ <value name="RB4_R5G5B5A1_UNORM" value="0x0a"/>
++ <value name="RB4_R5G6B5_UNORM" value="0x0e"/>
++ <value name="RB4_R8G8_UNORM" value="0x0f"/>
++ <value name="RB4_R8G8_SNORM" value="0x10"/>
++ <value name="RB4_R8G8_UINT" value="0x11"/>
++ <value name="RB4_R8G8_SINT" value="0x12"/>
++ <value name="RB4_R16_UNORM" value="0x13"/>
++ <value name="RB4_R16_SNORM" value="0x14"/>
++ <value name="RB4_R16_FLOAT" value="0x15"/>
++ <value name="RB4_R16_UINT" value="0x16"/>
++ <value name="RB4_R16_SINT" value="0x17"/>
++
++ <value name="RB4_R8G8B8_UNORM" value="0x19"/>
++
++ <value name="RB4_R8G8B8A8_UNORM" value="0x1a"/>
++ <value name="RB4_R8G8B8A8_SNORM" value="0x1c"/>
++ <value name="RB4_R8G8B8A8_UINT" value="0x1d"/>
++ <value name="RB4_R8G8B8A8_SINT" value="0x1e"/>
++ <value name="RB4_R10G10B10A2_UNORM" value="0x1f"/>
++ <value name="RB4_R10G10B10A2_UINT" value="0x22"/>
++ <value name="RB4_R11G11B10_FLOAT" value="0x27"/>
++ <value name="RB4_R16G16_UNORM" value="0x28"/>
++ <value name="RB4_R16G16_SNORM" value="0x29"/>
++ <value name="RB4_R16G16_FLOAT" value="0x2a"/>
++ <value name="RB4_R16G16_UINT" value="0x2b"/>
++ <value name="RB4_R16G16_SINT" value="0x2c"/>
++ <value name="RB4_R32_FLOAT" value="0x2d"/>
++ <value name="RB4_R32_UINT" value="0x2e"/>
++ <value name="RB4_R32_SINT" value="0x2f"/>
++
++ <value name="RB4_R16G16B16A16_UNORM" value="0x34"/>
++ <value name="RB4_R16G16B16A16_SNORM" value="0x35"/>
++ <value name="RB4_R16G16B16A16_FLOAT" value="0x36"/>
++ <value name="RB4_R16G16B16A16_UINT" value="0x37"/>
++ <value name="RB4_R16G16B16A16_SINT" value="0x38"/>
++ <value name="RB4_R32G32_FLOAT" value="0x39"/>
++ <value name="RB4_R32G32_UINT" value="0x3a"/>
++ <value name="RB4_R32G32_SINT" value="0x3b"/>
++
++ <value name="RB4_R32G32B32A32_FLOAT" value="0x3c"/>
++ <value name="RB4_R32G32B32A32_UINT" value="0x3d"/>
++ <value name="RB4_R32G32B32A32_SINT" value="0x3e"/>
++
++ <value name="RB4_NONE" value="0xff"/>
++</enum>
++
++<enum name="a4xx_tile_mode">
++ <value name="TILE4_LINEAR" value="0"/>
++ <value name="TILE4_2" value="2"/>
++ <value name="TILE4_3" value="3"/>
++</enum>
++
++<enum name="a4xx_vtx_fmt" prefix="chipset">
++ <!-- hmm, shifted one compared to a3xx?!? -->
++ <value name="VFMT4_32_FLOAT" value="0x1"/>
++ <value name="VFMT4_32_32_FLOAT" value="0x2"/>
++ <value name="VFMT4_32_32_32_FLOAT" value="0x3"/>
++ <value name="VFMT4_32_32_32_32_FLOAT" value="0x4"/>
++
++ <value name="VFMT4_16_FLOAT" value="0x5"/>
++ <value name="VFMT4_16_16_FLOAT" value="0x6"/>
++ <value name="VFMT4_16_16_16_FLOAT" value="0x7"/>
++ <value name="VFMT4_16_16_16_16_FLOAT" value="0x8"/>
++
++ <value name="VFMT4_32_FIXED" value="0x9"/>
++ <value name="VFMT4_32_32_FIXED" value="0xa"/>
++ <value name="VFMT4_32_32_32_FIXED" value="0xb"/>
++ <value name="VFMT4_32_32_32_32_FIXED" value="0xc"/>
++
++ <value name="VFMT4_11_11_10_FLOAT" value="0xd"/>
++
++ <!-- beyond here it does not appear to be shifted -->
++ <value name="VFMT4_16_SINT" value="0x10"/>
++ <value name="VFMT4_16_16_SINT" value="0x11"/>
++ <value name="VFMT4_16_16_16_SINT" value="0x12"/>
++ <value name="VFMT4_16_16_16_16_SINT" value="0x13"/>
++ <value name="VFMT4_16_UINT" value="0x14"/>
++ <value name="VFMT4_16_16_UINT" value="0x15"/>
++ <value name="VFMT4_16_16_16_UINT" value="0x16"/>
++ <value name="VFMT4_16_16_16_16_UINT" value="0x17"/>
++ <value name="VFMT4_16_SNORM" value="0x18"/>
++ <value name="VFMT4_16_16_SNORM" value="0x19"/>
++ <value name="VFMT4_16_16_16_SNORM" value="0x1a"/>
++ <value name="VFMT4_16_16_16_16_SNORM" value="0x1b"/>
++ <value name="VFMT4_16_UNORM" value="0x1c"/>
++ <value name="VFMT4_16_16_UNORM" value="0x1d"/>
++ <value name="VFMT4_16_16_16_UNORM" value="0x1e"/>
++ <value name="VFMT4_16_16_16_16_UNORM" value="0x1f"/>
++
++ <value name="VFMT4_32_UINT" value="0x20"/>
++ <value name="VFMT4_32_32_UINT" value="0x21"/>
++ <value name="VFMT4_32_32_32_UINT" value="0x22"/>
++ <value name="VFMT4_32_32_32_32_UINT" value="0x23"/>
++ <value name="VFMT4_32_SINT" value="0x24"/>
++ <value name="VFMT4_32_32_SINT" value="0x25"/>
++ <value name="VFMT4_32_32_32_SINT" value="0x26"/>
++ <value name="VFMT4_32_32_32_32_SINT" value="0x27"/>
++
++ <value name="VFMT4_8_UINT" value="0x28"/>
++ <value name="VFMT4_8_8_UINT" value="0x29"/>
++ <value name="VFMT4_8_8_8_UINT" value="0x2a"/>
++ <value name="VFMT4_8_8_8_8_UINT" value="0x2b"/>
++ <value name="VFMT4_8_UNORM" value="0x2c"/>
++ <value name="VFMT4_8_8_UNORM" value="0x2d"/>
++ <value name="VFMT4_8_8_8_UNORM" value="0x2e"/>
++ <value name="VFMT4_8_8_8_8_UNORM" value="0x2f"/>
++ <value name="VFMT4_8_SINT" value="0x30"/>
++ <value name="VFMT4_8_8_SINT" value="0x31"/>
++ <value name="VFMT4_8_8_8_SINT" value="0x32"/>
++ <value name="VFMT4_8_8_8_8_SINT" value="0x33"/>
++ <value name="VFMT4_8_SNORM" value="0x34"/>
++ <value name="VFMT4_8_8_SNORM" value="0x35"/>
++ <value name="VFMT4_8_8_8_SNORM" value="0x36"/>
++ <value name="VFMT4_8_8_8_8_SNORM" value="0x37"/>
++
++ <value name="VFMT4_10_10_10_2_UINT" value="0x38"/>
++ <value name="VFMT4_10_10_10_2_UNORM" value="0x39"/>
++ <value name="VFMT4_10_10_10_2_SINT" value="0x3a"/>
++ <value name="VFMT4_10_10_10_2_SNORM" value="0x3b"/>
++ <value name="VFMT4_2_10_10_10_UINT" value="0x3c"/>
++ <value name="VFMT4_2_10_10_10_UNORM" value="0x3d"/>
++ <value name="VFMT4_2_10_10_10_SINT" value="0x3e"/>
++ <value name="VFMT4_2_10_10_10_SNORM" value="0x3f"/>
++
++ <value name="VFMT4_NONE" value="0xff"/>
++</enum>
++
++<enum name="a4xx_tex_fmt">
++ <!-- 0x00 .. 0x02 -->
++
++ <!-- 8-bit formats -->
++ <value name="TFMT4_A8_UNORM" value="0x03"/>
++ <value name="TFMT4_8_UNORM" value="0x04"/>
++ <value name="TFMT4_8_SNORM" value="0x05"/>
++ <value name="TFMT4_8_UINT" value="0x06"/>
++ <value name="TFMT4_8_SINT" value="0x07"/>
++
++ <!-- 16-bit formats -->
++ <value name="TFMT4_4_4_4_4_UNORM" value="0x08"/>
++ <value name="TFMT4_5_5_5_1_UNORM" value="0x09"/>
++ <!-- 0x0a -->
++ <value name="TFMT4_5_6_5_UNORM" value="0x0b"/>
++
++ <!-- 0x0c -->
++
++ <value name="TFMT4_L8_A8_UNORM" value="0x0d"/>
++ <value name="TFMT4_8_8_UNORM" value="0x0e"/>
++ <value name="TFMT4_8_8_SNORM" value="0x0f"/>
++ <value name="TFMT4_8_8_UINT" value="0x10"/>
++ <value name="TFMT4_8_8_SINT" value="0x11"/>
++
++ <value name="TFMT4_16_UNORM" value="0x12"/>
++ <value name="TFMT4_16_SNORM" value="0x13"/>
++ <value name="TFMT4_16_FLOAT" value="0x14"/>
++ <value name="TFMT4_16_UINT" value="0x15"/>
++ <value name="TFMT4_16_SINT" value="0x16"/>
++
++ <!-- 0x17 .. 0x1b -->
++
++ <!-- 32-bit formats -->
++ <value name="TFMT4_8_8_8_8_UNORM" value="0x1c"/>
++ <value name="TFMT4_8_8_8_8_SNORM" value="0x1d"/>
++ <value name="TFMT4_8_8_8_8_UINT" value="0x1e"/>
++ <value name="TFMT4_8_8_8_8_SINT" value="0x1f"/>
++
++ <value name="TFMT4_9_9_9_E5_FLOAT" value="0x20"/>
++ <value name="TFMT4_10_10_10_2_UNORM" value="0x21"/>
++ <value name="TFMT4_10_10_10_2_UINT" value="0x22"/>
++ <!-- 0x23 .. 0x24 -->
++ <value name="TFMT4_11_11_10_FLOAT" value="0x25"/>
++
++ <value name="TFMT4_16_16_UNORM" value="0x26"/>
++ <value name="TFMT4_16_16_SNORM" value="0x27"/>
++ <value name="TFMT4_16_16_FLOAT" value="0x28"/>
++ <value name="TFMT4_16_16_UINT" value="0x29"/>
++ <value name="TFMT4_16_16_SINT" value="0x2a"/>
++
++ <value name="TFMT4_32_FLOAT" value="0x2b"/>
++ <value name="TFMT4_32_UINT" value="0x2c"/>
++ <value name="TFMT4_32_SINT" value="0x2d"/>
++
++ <!-- 0x2e .. 0x32 -->
++
++ <!-- 64-bit formats -->
++ <value name="TFMT4_16_16_16_16_UNORM" value="0x33"/>
++ <value name="TFMT4_16_16_16_16_SNORM" value="0x34"/>
++ <value name="TFMT4_16_16_16_16_FLOAT" value="0x35"/>
++ <value name="TFMT4_16_16_16_16_UINT" value="0x36"/>
++ <value name="TFMT4_16_16_16_16_SINT" value="0x37"/>
++
++ <value name="TFMT4_32_32_FLOAT" value="0x38"/>
++ <value name="TFMT4_32_32_UINT" value="0x39"/>
++ <value name="TFMT4_32_32_SINT" value="0x3a"/>
++
++ <!-- 96-bit formats -->
++ <value name="TFMT4_32_32_32_FLOAT" value="0x3b"/>
++ <value name="TFMT4_32_32_32_UINT" value="0x3c"/>
++ <value name="TFMT4_32_32_32_SINT" value="0x3d"/>
++
++ <!-- 0x3e -->
++
++ <!-- 128-bit formats -->
++ <value name="TFMT4_32_32_32_32_FLOAT" value="0x3f"/>
++ <value name="TFMT4_32_32_32_32_UINT" value="0x40"/>
++ <value name="TFMT4_32_32_32_32_SINT" value="0x41"/>
++
++ <!-- 0x42 .. 0x46 -->
++ <value name="TFMT4_X8Z24_UNORM" value="0x47"/>
++ <!-- 0x48 .. 0x55 -->
++
++ <!-- compressed formats -->
++ <value name="TFMT4_DXT1" value="0x56"/>
++ <value name="TFMT4_DXT3" value="0x57"/>
++ <value name="TFMT4_DXT5" value="0x58"/>
++ <!-- 0x59 -->
++ <value name="TFMT4_RGTC1_UNORM" value="0x5a"/>
++ <value name="TFMT4_RGTC1_SNORM" value="0x5b"/>
++ <!-- 0x5c .. 0x5d -->
++ <value name="TFMT4_RGTC2_UNORM" value="0x5e"/>
++ <value name="TFMT4_RGTC2_SNORM" value="0x5f"/>
++ <!-- 0x60 -->
++ <value name="TFMT4_BPTC_UFLOAT" value="0x61"/>
++ <value name="TFMT4_BPTC_FLOAT" value="0x62"/>
++ <value name="TFMT4_BPTC" value="0x63"/>
++ <value name="TFMT4_ATC_RGB" value="0x64"/>
++ <value name="TFMT4_ATC_RGBA_EXPLICIT" value="0x65"/>
++ <value name="TFMT4_ATC_RGBA_INTERPOLATED" value="0x66"/>
++ <value name="TFMT4_ETC2_RG11_UNORM" value="0x67"/>
++ <value name="TFMT4_ETC2_RG11_SNORM" value="0x68"/>
++ <value name="TFMT4_ETC2_R11_UNORM" value="0x69"/>
++ <value name="TFMT4_ETC2_R11_SNORM" value="0x6a"/>
++ <value name="TFMT4_ETC1" value="0x6b"/>
++ <value name="TFMT4_ETC2_RGB8" value="0x6c"/>
++ <value name="TFMT4_ETC2_RGBA8" value="0x6d"/>
++ <value name="TFMT4_ETC2_RGB8A1" value="0x6e"/>
++ <value name="TFMT4_ASTC_4x4" value="0x6f"/>
++ <value name="TFMT4_ASTC_5x4" value="0x70"/>
++ <value name="TFMT4_ASTC_5x5" value="0x71"/>
++ <value name="TFMT4_ASTC_6x5" value="0x72"/>
++ <value name="TFMT4_ASTC_6x6" value="0x73"/>
++ <value name="TFMT4_ASTC_8x5" value="0x74"/>
++ <value name="TFMT4_ASTC_8x6" value="0x75"/>
++ <value name="TFMT4_ASTC_8x8" value="0x76"/>
++ <value name="TFMT4_ASTC_10x5" value="0x77"/>
++ <value name="TFMT4_ASTC_10x6" value="0x78"/>
++ <value name="TFMT4_ASTC_10x8" value="0x79"/>
++ <value name="TFMT4_ASTC_10x10" value="0x7a"/>
++ <value name="TFMT4_ASTC_12x10" value="0x7b"/>
++ <value name="TFMT4_ASTC_12x12" value="0x7c"/>
++ <!-- 0x7d .. 0x7f -->
++
++ <value name="TFMT4_NONE" value="0xff"/>
++</enum>
++
++<enum name="a4xx_depth_format">
++ <value name="DEPTH4_NONE" value="0"/>
++ <value name="DEPTH4_16" value="1"/>
++ <value name="DEPTH4_24_8" value="2"/>
++ <value name="DEPTH4_32" value="3"/>
++</enum>
++
++<!--
++NOTE counters extracted from test-perf log with the following awful
++script:
++##################
++#!/bin/bash
++
++log=$1
++
++grep -F "counter
++countable
++group" $log | grep -v gl > shortlist.txt
++
++countable=""
++IFS=$'\n'; for line in $(cat shortlist.txt); do
++ # parse ######### group[$n]: $name
++ l=${line########### group}
++ if [ $l != $line ]; then
++ group=`echo $line | awk '{print $3}'`
++ echo "Group: $group"
++ continue
++ fi
++ # parse ######### counter[$n]: $name
++ l=${line########### counter}
++ if [ $l != $line ]; then
++ countable=`echo $line | awk '{print $3}'`
++ #echo " Countable: $countable"
++ continue
++ fi
++ # parse countable:
++ l=${line## countable:}
++ if [ $l != $line ]; then
++ val=`echo $line | awk '{print $2}'`
++ echo "<value value=\"$val\" name=\"$countable\"/>"
++ fi
++
++done
++##################
++ -->
++<enum name="a4xx_ccu_perfcounter_select">
++ <value value="0" name="CCU_BUSY_CYCLES"/>
++ <value value="2" name="CCU_RB_DEPTH_RETURN_STALL"/>
++ <value value="3" name="CCU_RB_COLOR_RETURN_STALL"/>
++ <value value="6" name="CCU_DEPTH_BLOCKS"/>
++ <value value="7" name="CCU_COLOR_BLOCKS"/>
++ <value value="8" name="CCU_DEPTH_BLOCK_HIT"/>
++ <value value="9" name="CCU_COLOR_BLOCK_HIT"/>
++ <value value="10" name="CCU_DEPTH_FLAG1_COUNT"/>
++ <value value="11" name="CCU_DEPTH_FLAG2_COUNT"/>
++ <value value="12" name="CCU_DEPTH_FLAG3_COUNT"/>
++ <value value="13" name="CCU_DEPTH_FLAG4_COUNT"/>
++ <value value="14" name="CCU_COLOR_FLAG1_COUNT"/>
++ <value value="15" name="CCU_COLOR_FLAG2_COUNT"/>
++ <value value="16" name="CCU_COLOR_FLAG3_COUNT"/>
++ <value value="17" name="CCU_COLOR_FLAG4_COUNT"/>
++ <value value="18" name="CCU_PARTIAL_BLOCK_READ"/>
++</enum>
++
++<!--
++NOTE other than CP_ALWAYS_COUNT (which is the only one we use so far),
++on a3xx the countable #'s from AMD_performance_monitor disagreed with
++TRM. All these #'s for a4xx come from AMD_performance_monitor, so
++perhaps they should be taken with a grain of salt
++-->
++<enum name="a4xx_cp_perfcounter_select">
++ <!-- first ctr at least seems same as a3xx, so we can measure freq -->
++ <value value="0" name="CP_ALWAYS_COUNT"/>
++ <value value="1" name="CP_BUSY"/>
++ <value value="2" name="CP_PFP_IDLE"/>
++ <value value="3" name="CP_PFP_BUSY_WORKING"/>
++ <value value="4" name="CP_PFP_STALL_CYCLES_ANY"/>
++ <value value="5" name="CP_PFP_STARVE_CYCLES_ANY"/>
++ <value value="6" name="CP_PFP_STARVED_PER_LOAD_ADDR"/>
++ <value value="7" name="CP_PFP_STALLED_PER_STORE_ADDR"/>
++ <value value="8" name="CP_PFP_PC_PROFILE"/>
++ <value value="9" name="CP_PFP_MATCH_PM4_PKT_PROFILE"/>
++ <value value="10" name="CP_PFP_COND_INDIRECT_DISCARDED"/>
++ <value value="11" name="CP_LONG_RESUMPTIONS"/>
++ <value value="12" name="CP_RESUME_CYCLES"/>
++ <value value="13" name="CP_RESUME_TO_BOUNDARY_CYCLES"/>
++ <value value="14" name="CP_LONG_PREEMPTIONS"/>
++ <value value="15" name="CP_PREEMPT_CYCLES"/>
++ <value value="16" name="CP_PREEMPT_TO_BOUNDARY_CYCLES"/>
++ <value value="17" name="CP_ME_FIFO_EMPTY_PFP_IDLE"/>
++ <value value="18" name="CP_ME_FIFO_EMPTY_PFP_BUSY"/>
++ <value value="19" name="CP_ME_FIFO_NOT_EMPTY_NOT_FULL"/>
++ <value value="20" name="CP_ME_FIFO_FULL_ME_BUSY"/>
++ <value value="21" name="CP_ME_FIFO_FULL_ME_NON_WORKING"/>
++ <value value="22" name="CP_ME_WAITING_FOR_PACKETS"/>
++ <value value="23" name="CP_ME_BUSY_WORKING"/>
++ <value value="24" name="CP_ME_STARVE_CYCLES_ANY"/>
++ <value value="25" name="CP_ME_STARVE_CYCLES_PER_PROFILE"/>
++ <value value="26" name="CP_ME_STALL_CYCLES_PER_PROFILE"/>
++ <value value="27" name="CP_ME_PC_PROFILE"/>
++ <value value="28" name="CP_RCIU_FIFO_EMPTY"/>
++ <value value="29" name="CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL"/>
++ <value value="30" name="CP_RCIU_FIFO_FULL"/>
++ <value value="31" name="CP_RCIU_FIFO_FULL_NO_CONTEXT"/>
++ <value value="32" name="CP_RCIU_FIFO_FULL_AHB_MASTER"/>
++ <value value="33" name="CP_RCIU_FIFO_FULL_OTHER"/>
++ <value value="34" name="CP_AHB_IDLE"/>
++ <value value="35" name="CP_AHB_STALL_ON_GRANT_NO_SPLIT"/>
++ <value value="36" name="CP_AHB_STALL_ON_GRANT_SPLIT"/>
++ <value value="37" name="CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE"/>
++ <value value="38" name="CP_AHB_BUSY_WORKING"/>
++ <value value="39" name="CP_AHB_BUSY_STALL_ON_HRDY"/>
++ <value value="40" name="CP_AHB_BUSY_STALL_ON_HRDY_PROFILE"/>
++</enum>
++
++<enum name="a4xx_gras_ras_perfcounter_select">
++ <value value="0" name="RAS_SUPER_TILES"/>
++ <value value="1" name="RAS_8X8_TILES"/>
++ <value value="2" name="RAS_4X4_TILES"/>
++ <value value="3" name="RAS_BUSY_CYCLES"/>
++ <value value="4" name="RAS_STALL_CYCLES_BY_RB"/>
++ <value value="5" name="RAS_STALL_CYCLES_BY_VSC"/>
++ <value value="6" name="RAS_STARVE_CYCLES_BY_TSE"/>
++ <value value="7" name="RAS_SUPERTILE_CYCLES"/>
++ <value value="8" name="RAS_TILE_CYCLES"/>
++ <value value="9" name="RAS_FULLY_COVERED_SUPER_TILES"/>
++ <value value="10" name="RAS_FULLY_COVERED_8X8_TILES"/>
++ <value value="11" name="RAS_4X4_PRIM"/>
++ <value value="12" name="RAS_8X4_4X8_PRIM"/>
++ <value value="13" name="RAS_8X8_PRIM"/>
++</enum>
++
++<enum name="a4xx_gras_tse_perfcounter_select">
++ <value value="0" name="TSE_INPUT_PRIM"/>
++ <value value="1" name="TSE_INPUT_NULL_PRIM"/>
++ <value value="2" name="TSE_TRIVAL_REJ_PRIM"/>
++ <value value="3" name="TSE_CLIPPED_PRIM"/>
++ <value value="4" name="TSE_NEW_PRIM"/>
++ <value value="5" name="TSE_ZERO_AREA_PRIM"/>
++ <value value="6" name="TSE_FACENESS_CULLED_PRIM"/>
++ <value value="7" name="TSE_ZERO_PIXEL_PRIM"/>
++ <value value="8" name="TSE_OUTPUT_NULL_PRIM"/>
++ <value value="9" name="TSE_OUTPUT_VISIBLE_PRIM"/>
++ <value value="10" name="TSE_PRE_CLIP_PRIM"/>
++ <value value="11" name="TSE_POST_CLIP_PRIM"/>
++ <value value="12" name="TSE_BUSY_CYCLES"/>
++ <value value="13" name="TSE_PC_STARVE"/>
++ <value value="14" name="TSE_RAS_STALL"/>
++ <value value="15" name="TSE_STALL_BARYPLANE_FIFO_FULL"/>
++ <value value="16" name="TSE_STALL_ZPLANE_FIFO_FULL"/>
++</enum>
++
++<enum name="a4xx_hlsq_perfcounter_select">
++ <value value="0" name="HLSQ_SP_VS_STAGE_CONSTANT"/>
++ <value value="1" name="HLSQ_SP_VS_STAGE_INSTRUCTIONS"/>
++ <value value="2" name="HLSQ_SP_FS_STAGE_CONSTANT"/>
++ <value value="3" name="HLSQ_SP_FS_STAGE_INSTRUCTIONS"/>
++ <value value="4" name="HLSQ_TP_STATE"/>
++ <value value="5" name="HLSQ_QUADS"/>
++ <value value="6" name="HLSQ_PIXELS"/>
++ <value value="7" name="HLSQ_VERTICES"/>
++ <value value="13" name="HLSQ_SP_VS_STAGE_DATA_BYTES"/>
++ <value value="14" name="HLSQ_SP_FS_STAGE_DATA_BYTES"/>
++ <value value="15" name="HLSQ_BUSY_CYCLES"/>
++ <value value="16" name="HLSQ_STALL_CYCLES_SP_STATE"/>
++ <value value="17" name="HLSQ_STALL_CYCLES_SP_VS_STAGE"/>
++ <value value="18" name="HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
++ <value value="19" name="HLSQ_STALL_CYCLES_UCHE"/>
++ <value value="20" name="HLSQ_RBBM_LOAD_CYCLES"/>
++ <value value="21" name="HLSQ_DI_TO_VS_START_SP"/>
++ <value value="22" name="HLSQ_DI_TO_FS_START_SP"/>
++ <value value="23" name="HLSQ_VS_STAGE_START_TO_DONE_SP"/>
++ <value value="24" name="HLSQ_FS_STAGE_START_TO_DONE_SP"/>
++ <value value="25" name="HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE"/>
++ <value value="26" name="HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE"/>
++ <value value="27" name="HLSQ_UCHE_LATENCY_CYCLES"/>
++ <value value="28" name="HLSQ_UCHE_LATENCY_COUNT"/>
++ <value value="29" name="HLSQ_STARVE_CYCLES_VFD"/>
++</enum>
++
++<enum name="a4xx_pc_perfcounter_select">
++ <value value="0" name="PC_VIS_STREAMS_LOADED"/>
++ <value value="2" name="PC_VPC_PRIMITIVES"/>
++ <value value="3" name="PC_DEAD_PRIM"/>
++ <value value="4" name="PC_LIVE_PRIM"/>
++ <value value="5" name="PC_DEAD_DRAWCALLS"/>
++ <value value="6" name="PC_LIVE_DRAWCALLS"/>
++ <value value="7" name="PC_VERTEX_MISSES"/>
++ <value value="9" name="PC_STALL_CYCLES_VFD"/>
++ <value value="10" name="PC_STALL_CYCLES_TSE"/>
++ <value value="11" name="PC_STALL_CYCLES_UCHE"/>
++ <value value="12" name="PC_WORKING_CYCLES"/>
++ <value value="13" name="PC_IA_VERTICES"/>
++ <value value="14" name="PC_GS_PRIMITIVES"/>
++ <value value="15" name="PC_HS_INVOCATIONS"/>
++ <value value="16" name="PC_DS_INVOCATIONS"/>
++ <value value="17" name="PC_DS_PRIMITIVES"/>
++ <value value="20" name="PC_STARVE_CYCLES_FOR_INDEX"/>
++ <value value="21" name="PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
++ <value value="22" name="PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
++ <value value="23" name="PC_STALL_CYCLES_TESS"/>
++ <value value="24" name="PC_STARVE_CYCLES_FOR_POSITION"/>
++ <value value="25" name="PC_MODE0_DRAWCALL"/>
++ <value value="26" name="PC_MODE1_DRAWCALL"/>
++ <value value="27" name="PC_MODE2_DRAWCALL"/>
++ <value value="28" name="PC_MODE3_DRAWCALL"/>
++ <value value="29" name="PC_MODE4_DRAWCALL"/>
++ <value value="30" name="PC_PREDICATED_DEAD_DRAWCALL"/>
++ <value value="31" name="PC_STALL_CYCLES_BY_TSE_ONLY"/>
++ <value value="32" name="PC_STALL_CYCLES_BY_VPC_ONLY"/>
++ <value value="33" name="PC_VPC_POS_DATA_TRANSACTION"/>
++ <value value="34" name="PC_BUSY_CYCLES"/>
++ <value value="35" name="PC_STARVE_CYCLES_DI"/>
++ <value value="36" name="PC_STALL_CYCLES_VPC"/>
++ <value value="37" name="TESS_WORKING_CYCLES"/>
++ <value value="38" name="TESS_NUM_CYCLES_SETUP_WORKING"/>
++ <value value="39" name="TESS_NUM_CYCLES_PTGEN_WORKING"/>
++ <value value="40" name="TESS_NUM_CYCLES_CONNGEN_WORKING"/>
++ <value value="41" name="TESS_BUSY_CYCLES"/>
++ <value value="42" name="TESS_STARVE_CYCLES_PC"/>
++ <value value="43" name="TESS_STALL_CYCLES_PC"/>
++</enum>
++
++<enum name="a4xx_pwr_perfcounter_select">
++ <!-- NOTE not actually used.. see RBBM_RBBM_CTL.RESET_PWR_CTR0/1 -->
++ <value value="0" name="PWR_CORE_CLOCK_CYCLES"/>
++ <value value="1" name="PWR_BUSY_CLOCK_CYCLES"/>
++</enum>
++
++<enum name="a4xx_rb_perfcounter_select">
++ <value value="0" name="RB_BUSY_CYCLES"/>
++ <value value="1" name="RB_BUSY_CYCLES_BINNING"/>
++ <value value="2" name="RB_BUSY_CYCLES_RENDERING"/>
++ <value value="3" name="RB_BUSY_CYCLES_RESOLVE"/>
++ <value value="4" name="RB_STARVE_CYCLES_BY_SP"/>
++ <value value="5" name="RB_STARVE_CYCLES_BY_RAS"/>
++ <value value="6" name="RB_STARVE_CYCLES_BY_MARB"/>
++ <value value="7" name="RB_STALL_CYCLES_BY_MARB"/>
++ <value value="8" name="RB_STALL_CYCLES_BY_HLSQ"/>
++ <value value="9" name="RB_RB_RB_MARB_DATA"/>
++ <value value="10" name="RB_SP_RB_QUAD"/>
++ <value value="11" name="RB_RAS_RB_Z_QUADS"/>
++ <value value="12" name="RB_GMEM_CH0_READ"/>
++ <value value="13" name="RB_GMEM_CH1_READ"/>
++ <value value="14" name="RB_GMEM_CH0_WRITE"/>
++ <value value="15" name="RB_GMEM_CH1_WRITE"/>
++ <value value="16" name="RB_CP_CONTEXT_DONE"/>
++ <value value="17" name="RB_CP_CACHE_FLUSH"/>
++ <value value="18" name="RB_CP_ZPASS_DONE"/>
++ <value value="19" name="RB_STALL_FIFO0_FULL"/>
++ <value value="20" name="RB_STALL_FIFO1_FULL"/>
++ <value value="21" name="RB_STALL_FIFO2_FULL"/>
++ <value value="22" name="RB_STALL_FIFO3_FULL"/>
++ <value value="23" name="RB_RB_HLSQ_TRANSACTIONS"/>
++ <value value="24" name="RB_Z_READ"/>
++ <value value="25" name="RB_Z_WRITE"/>
++ <value value="26" name="RB_C_READ"/>
++ <value value="27" name="RB_C_WRITE"/>
++ <value value="28" name="RB_C_READ_LATENCY"/>
++ <value value="29" name="RB_Z_READ_LATENCY"/>
++ <value value="30" name="RB_STALL_BY_UCHE"/>
++ <value value="31" name="RB_MARB_UCHE_TRANSACTIONS"/>
++ <value value="32" name="RB_CACHE_STALL_MISS"/>
++ <value value="33" name="RB_CACHE_STALL_FIFO_FULL"/>
++ <value value="34" name="RB_8BIT_BLENDER_UNITS_ACTIVE"/>
++ <value value="35" name="RB_16BIT_BLENDER_UNITS_ACTIVE"/>
++ <value value="36" name="RB_SAMPLER_UNITS_ACTIVE"/>
++ <value value="38" name="RB_TOTAL_PASS"/>
++ <value value="39" name="RB_Z_PASS"/>
++ <value value="40" name="RB_Z_FAIL"/>
++ <value value="41" name="RB_S_FAIL"/>
++ <value value="42" name="RB_POWER0"/>
++ <value value="43" name="RB_POWER1"/>
++ <value value="44" name="RB_POWER2"/>
++ <value value="45" name="RB_POWER3"/>
++ <value value="46" name="RB_POWER4"/>
++ <value value="47" name="RB_POWER5"/>
++ <value value="48" name="RB_POWER6"/>
++ <value value="49" name="RB_POWER7"/>
++</enum>
++
++<enum name="a4xx_rbbm_perfcounter_select">
++ <value value="0" name="RBBM_ALWAYS_ON"/>
++ <value value="1" name="RBBM_VBIF_BUSY"/>
++ <value value="2" name="RBBM_TSE_BUSY"/>
++ <value value="3" name="RBBM_RAS_BUSY"/>
++ <value value="4" name="RBBM_PC_DCALL_BUSY"/>
++ <value value="5" name="RBBM_PC_VSD_BUSY"/>
++ <value value="6" name="RBBM_VFD_BUSY"/>
++ <value value="7" name="RBBM_VPC_BUSY"/>
++ <value value="8" name="RBBM_UCHE_BUSY"/>
++ <value value="9" name="RBBM_VSC_BUSY"/>
++ <value value="10" name="RBBM_HLSQ_BUSY"/>
++ <value value="11" name="RBBM_ANY_RB_BUSY"/>
++ <value value="12" name="RBBM_ANY_TPL1_BUSY"/>
++ <value value="13" name="RBBM_ANY_SP_BUSY"/>
++ <value value="14" name="RBBM_ANY_MARB_BUSY"/>
++ <value value="15" name="RBBM_ANY_ARB_BUSY"/>
++ <value value="16" name="RBBM_AHB_STATUS_BUSY"/>
++ <value value="17" name="RBBM_AHB_STATUS_STALLED"/>
++ <value value="18" name="RBBM_AHB_STATUS_TXFR"/>
++ <value value="19" name="RBBM_AHB_STATUS_TXFR_SPLIT"/>
++ <value value="20" name="RBBM_AHB_STATUS_TXFR_ERROR"/>
++ <value value="21" name="RBBM_AHB_STATUS_LONG_STALL"/>
++ <value value="22" name="RBBM_STATUS_MASKED"/>
++ <value value="23" name="RBBM_CP_BUSY_GFX_CORE_IDLE"/>
++ <value value="24" name="RBBM_TESS_BUSY"/>
++ <value value="25" name="RBBM_COM_BUSY"/>
++ <value value="32" name="RBBM_DCOM_BUSY"/>
++ <value value="33" name="RBBM_ANY_CCU_BUSY"/>
++ <value value="34" name="RBBM_DPM_BUSY"/>
++</enum>
++
++<enum name="a4xx_sp_perfcounter_select">
++ <value value="0" name="SP_LM_LOAD_INSTRUCTIONS"/>
++ <value value="1" name="SP_LM_STORE_INSTRUCTIONS"/>
++ <value value="2" name="SP_LM_ATOMICS"/>
++ <value value="3" name="SP_GM_LOAD_INSTRUCTIONS"/>
++ <value value="4" name="SP_GM_STORE_INSTRUCTIONS"/>
++ <value value="5" name="SP_GM_ATOMICS"/>
++ <value value="6" name="SP_VS_STAGE_TEX_INSTRUCTIONS"/>
++ <value value="7" name="SP_VS_STAGE_CFLOW_INSTRUCTIONS"/>
++ <value value="8" name="SP_VS_STAGE_EFU_INSTRUCTIONS"/>
++ <value value="9" name="SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
++ <value value="10" name="SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
++ <value value="11" name="SP_FS_STAGE_TEX_INSTRUCTIONS"/>
++ <value value="12" name="SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
++ <value value="13" name="SP_FS_STAGE_EFU_INSTRUCTIONS"/>
++ <value value="14" name="SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
++ <value value="15" name="SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
++ <value value="17" name="SP_VS_INSTRUCTIONS"/>
++ <value value="18" name="SP_FS_INSTRUCTIONS"/>
++ <value value="19" name="SP_ADDR_LOCK_COUNT"/>
++ <value value="20" name="SP_UCHE_READ_TRANS"/>
++ <value value="21" name="SP_UCHE_WRITE_TRANS"/>
++ <value value="22" name="SP_EXPORT_VPC_TRANS"/>
++ <value value="23" name="SP_EXPORT_RB_TRANS"/>
++ <value value="24" name="SP_PIXELS_KILLED"/>
++ <value value="25" name="SP_ICL1_REQUESTS"/>
++ <value value="26" name="SP_ICL1_MISSES"/>
++ <value value="27" name="SP_ICL0_REQUESTS"/>
++ <value value="28" name="SP_ICL0_MISSES"/>
++ <value value="29" name="SP_ALU_WORKING_CYCLES"/>
++ <value value="30" name="SP_EFU_WORKING_CYCLES"/>
++ <value value="31" name="SP_STALL_CYCLES_BY_VPC"/>
++ <value value="32" name="SP_STALL_CYCLES_BY_TP"/>
++ <value value="33" name="SP_STALL_CYCLES_BY_UCHE"/>
++ <value value="34" name="SP_STALL_CYCLES_BY_RB"/>
++ <value value="35" name="SP_BUSY_CYCLES"/>
++ <value value="36" name="SP_HS_INSTRUCTIONS"/>
++ <value value="37" name="SP_DS_INSTRUCTIONS"/>
++ <value value="38" name="SP_GS_INSTRUCTIONS"/>
++ <value value="39" name="SP_CS_INSTRUCTIONS"/>
++ <value value="40" name="SP_SCHEDULER_NON_WORKING"/>
++ <value value="41" name="SP_WAVE_CONTEXTS"/>
++ <value value="42" name="SP_WAVE_CONTEXT_CYCLES"/>
++ <value value="43" name="SP_POWER0"/>
++ <value value="44" name="SP_POWER1"/>
++ <value value="45" name="SP_POWER2"/>
++ <value value="46" name="SP_POWER3"/>
++ <value value="47" name="SP_POWER4"/>
++ <value value="48" name="SP_POWER5"/>
++ <value value="49" name="SP_POWER6"/>
++ <value value="50" name="SP_POWER7"/>
++ <value value="51" name="SP_POWER8"/>
++ <value value="52" name="SP_POWER9"/>
++ <value value="53" name="SP_POWER10"/>
++ <value value="54" name="SP_POWER11"/>
++ <value value="55" name="SP_POWER12"/>
++ <value value="56" name="SP_POWER13"/>
++ <value value="57" name="SP_POWER14"/>
++ <value value="58" name="SP_POWER15"/>
++</enum>
++
++<enum name="a4xx_tp_perfcounter_select">
++ <value value="0" name="TP_L1_REQUESTS"/>
++ <value value="1" name="TP_L1_MISSES"/>
++ <value value="8" name="TP_QUADS_OFFSET"/>
++ <value value="9" name="TP_QUAD_SHADOW"/>
++ <value value="10" name="TP_QUADS_ARRAY"/>
++ <value value="11" name="TP_QUADS_GRADIENT"/>
++ <value value="12" name="TP_QUADS_1D2D"/>
++ <value value="13" name="TP_QUADS_3DCUBE"/>
++ <value value="16" name="TP_BUSY_CYCLES"/>
++ <value value="17" name="TP_STALL_CYCLES_BY_ARB"/>
++ <value value="20" name="TP_STATE_CACHE_REQUESTS"/>
++ <value value="21" name="TP_STATE_CACHE_MISSES"/>
++ <value value="22" name="TP_POWER0"/>
++ <value value="23" name="TP_POWER1"/>
++ <value value="24" name="TP_POWER2"/>
++ <value value="25" name="TP_POWER3"/>
++ <value value="26" name="TP_POWER4"/>
++ <value value="27" name="TP_POWER5"/>
++ <value value="28" name="TP_POWER6"/>
++ <value value="29" name="TP_POWER7"/>
++</enum>
++
++<enum name="a4xx_uche_perfcounter_select">
++ <value value="0" name="UCHE_VBIF_READ_BEATS_TP"/>
++ <value value="1" name="UCHE_VBIF_READ_BEATS_VFD"/>
++ <value value="2" name="UCHE_VBIF_READ_BEATS_HLSQ"/>
++ <value value="3" name="UCHE_VBIF_READ_BEATS_MARB"/>
++ <value value="4" name="UCHE_VBIF_READ_BEATS_SP"/>
++ <value value="5" name="UCHE_READ_REQUESTS_TP"/>
++ <value value="6" name="UCHE_READ_REQUESTS_VFD"/>
++ <value value="7" name="UCHE_READ_REQUESTS_HLSQ"/>
++ <value value="8" name="UCHE_READ_REQUESTS_MARB"/>
++ <value value="9" name="UCHE_READ_REQUESTS_SP"/>
++ <value value="10" name="UCHE_WRITE_REQUESTS_MARB"/>
++ <value value="11" name="UCHE_WRITE_REQUESTS_SP"/>
++ <value value="12" name="UCHE_TAG_CHECK_FAILS"/>
++ <value value="13" name="UCHE_EVICTS"/>
++ <value value="14" name="UCHE_FLUSHES"/>
++ <value value="15" name="UCHE_VBIF_LATENCY_CYCLES"/>
++ <value value="16" name="UCHE_VBIF_LATENCY_SAMPLES"/>
++ <value value="17" name="UCHE_BUSY_CYCLES"/>
++ <value value="18" name="UCHE_VBIF_READ_BEATS_PC"/>
++ <value value="19" name="UCHE_READ_REQUESTS_PC"/>
++ <value value="20" name="UCHE_WRITE_REQUESTS_VPC"/>
++ <value value="21" name="UCHE_STALL_BY_VBIF"/>
++ <value value="22" name="UCHE_WRITE_REQUESTS_VSC"/>
++ <value value="23" name="UCHE_POWER0"/>
++ <value value="24" name="UCHE_POWER1"/>
++ <value value="25" name="UCHE_POWER2"/>
++ <value value="26" name="UCHE_POWER3"/>
++ <value value="27" name="UCHE_POWER4"/>
++ <value value="28" name="UCHE_POWER5"/>
++ <value value="29" name="UCHE_POWER6"/>
++ <value value="30" name="UCHE_POWER7"/>
++</enum>
++
++<enum name="a4xx_vbif_perfcounter_select">
++ <value value="0" name="AXI_READ_REQUESTS_ID_0"/>
++ <value value="1" name="AXI_READ_REQUESTS_ID_1"/>
++ <value value="2" name="AXI_READ_REQUESTS_ID_2"/>
++ <value value="3" name="AXI_READ_REQUESTS_ID_3"/>
++ <value value="4" name="AXI_READ_REQUESTS_ID_4"/>
++ <value value="5" name="AXI_READ_REQUESTS_ID_5"/>
++ <value value="6" name="AXI_READ_REQUESTS_ID_6"/>
++ <value value="7" name="AXI_READ_REQUESTS_ID_7"/>
++ <value value="8" name="AXI_READ_REQUESTS_ID_8"/>
++ <value value="9" name="AXI_READ_REQUESTS_ID_9"/>
++ <value value="10" name="AXI_READ_REQUESTS_ID_10"/>
++ <value value="11" name="AXI_READ_REQUESTS_ID_11"/>
++ <value value="12" name="AXI_READ_REQUESTS_ID_12"/>
++ <value value="13" name="AXI_READ_REQUESTS_ID_13"/>
++ <value value="14" name="AXI_READ_REQUESTS_ID_14"/>
++ <value value="15" name="AXI_READ_REQUESTS_ID_15"/>
++ <value value="16" name="AXI0_READ_REQUESTS_TOTAL"/>
++ <value value="17" name="AXI1_READ_REQUESTS_TOTAL"/>
++ <value value="18" name="AXI2_READ_REQUESTS_TOTAL"/>
++ <value value="19" name="AXI3_READ_REQUESTS_TOTAL"/>
++ <value value="20" name="AXI_READ_REQUESTS_TOTAL"/>
++ <value value="21" name="AXI_WRITE_REQUESTS_ID_0"/>
++ <value value="22" name="AXI_WRITE_REQUESTS_ID_1"/>
++ <value value="23" name="AXI_WRITE_REQUESTS_ID_2"/>
++ <value value="24" name="AXI_WRITE_REQUESTS_ID_3"/>
++ <value value="25" name="AXI_WRITE_REQUESTS_ID_4"/>
++ <value value="26" name="AXI_WRITE_REQUESTS_ID_5"/>
++ <value value="27" name="AXI_WRITE_REQUESTS_ID_6"/>
++ <value value="28" name="AXI_WRITE_REQUESTS_ID_7"/>
++ <value value="29" name="AXI_WRITE_REQUESTS_ID_8"/>
++ <value value="30" name="AXI_WRITE_REQUESTS_ID_9"/>
++ <value value="31" name="AXI_WRITE_REQUESTS_ID_10"/>
++ <value value="32" name="AXI_WRITE_REQUESTS_ID_11"/>
++ <value value="33" name="AXI_WRITE_REQUESTS_ID_12"/>
++ <value value="34" name="AXI_WRITE_REQUESTS_ID_13"/>
++ <value value="35" name="AXI_WRITE_REQUESTS_ID_14"/>
++ <value value="36" name="AXI_WRITE_REQUESTS_ID_15"/>
++ <value value="37" name="AXI0_WRITE_REQUESTS_TOTAL"/>
++ <value value="38" name="AXI1_WRITE_REQUESTS_TOTAL"/>
++ <value value="39" name="AXI2_WRITE_REQUESTS_TOTAL"/>
++ <value value="40" name="AXI3_WRITE_REQUESTS_TOTAL"/>
++ <value value="41" name="AXI_WRITE_REQUESTS_TOTAL"/>
++ <value value="42" name="AXI_TOTAL_REQUESTS"/>
++ <value value="43" name="AXI_READ_DATA_BEATS_ID_0"/>
++ <value value="44" name="AXI_READ_DATA_BEATS_ID_1"/>
++ <value value="45" name="AXI_READ_DATA_BEATS_ID_2"/>
++ <value value="46" name="AXI_READ_DATA_BEATS_ID_3"/>
++ <value value="47" name="AXI_READ_DATA_BEATS_ID_4"/>
++ <value value="48" name="AXI_READ_DATA_BEATS_ID_5"/>
++ <value value="49" name="AXI_READ_DATA_BEATS_ID_6"/>
++ <value value="50" name="AXI_READ_DATA_BEATS_ID_7"/>
++ <value value="51" name="AXI_READ_DATA_BEATS_ID_8"/>
++ <value value="52" name="AXI_READ_DATA_BEATS_ID_9"/>
++ <value value="53" name="AXI_READ_DATA_BEATS_ID_10"/>
++ <value value="54" name="AXI_READ_DATA_BEATS_ID_11"/>
++ <value value="55" name="AXI_READ_DATA_BEATS_ID_12"/>
++ <value value="56" name="AXI_READ_DATA_BEATS_ID_13"/>
++ <value value="57" name="AXI_READ_DATA_BEATS_ID_14"/>
++ <value value="58" name="AXI_READ_DATA_BEATS_ID_15"/>
++ <value value="59" name="AXI0_READ_DATA_BEATS_TOTAL"/>
++ <value value="60" name="AXI1_READ_DATA_BEATS_TOTAL"/>
++ <value value="61" name="AXI2_READ_DATA_BEATS_TOTAL"/>
++ <value value="62" name="AXI3_READ_DATA_BEATS_TOTAL"/>
++ <value value="63" name="AXI_READ_DATA_BEATS_TOTAL"/>
++ <value value="64" name="AXI_WRITE_DATA_BEATS_ID_0"/>
++ <value value="65" name="AXI_WRITE_DATA_BEATS_ID_1"/>
++ <value value="66" name="AXI_WRITE_DATA_BEATS_ID_2"/>
++ <value value="67" name="AXI_WRITE_DATA_BEATS_ID_3"/>
++ <value value="68" name="AXI_WRITE_DATA_BEATS_ID_4"/>
++ <value value="69" name="AXI_WRITE_DATA_BEATS_ID_5"/>
++ <value value="70" name="AXI_WRITE_DATA_BEATS_ID_6"/>
++ <value value="71" name="AXI_WRITE_DATA_BEATS_ID_7"/>
++ <value value="72" name="AXI_WRITE_DATA_BEATS_ID_8"/>
++ <value value="73" name="AXI_WRITE_DATA_BEATS_ID_9"/>
++ <value value="74" name="AXI_WRITE_DATA_BEATS_ID_10"/>
++ <value value="75" name="AXI_WRITE_DATA_BEATS_ID_11"/>
++ <value value="76" name="AXI_WRITE_DATA_BEATS_ID_12"/>
++ <value value="77" name="AXI_WRITE_DATA_BEATS_ID_13"/>
++ <value value="78" name="AXI_WRITE_DATA_BEATS_ID_14"/>
++ <value value="79" name="AXI_WRITE_DATA_BEATS_ID_15"/>
++ <value value="80" name="AXI0_WRITE_DATA_BEATS_TOTAL"/>
++ <value value="81" name="AXI1_WRITE_DATA_BEATS_TOTAL"/>
++ <value value="82" name="AXI2_WRITE_DATA_BEATS_TOTAL"/>
++ <value value="83" name="AXI3_WRITE_DATA_BEATS_TOTAL"/>
++ <value value="84" name="AXI_WRITE_DATA_BEATS_TOTAL"/>
++ <value value="85" name="AXI_DATA_BEATS_TOTAL"/>
++ <value value="86" name="CYCLES_HELD_OFF_ID_0"/>
++ <value value="87" name="CYCLES_HELD_OFF_ID_1"/>
++ <value value="88" name="CYCLES_HELD_OFF_ID_2"/>
++ <value value="89" name="CYCLES_HELD_OFF_ID_3"/>
++ <value value="90" name="CYCLES_HELD_OFF_ID_4"/>
++ <value value="91" name="CYCLES_HELD_OFF_ID_5"/>
++ <value value="92" name="CYCLES_HELD_OFF_ID_6"/>
++ <value value="93" name="CYCLES_HELD_OFF_ID_7"/>
++ <value value="94" name="CYCLES_HELD_OFF_ID_8"/>
++ <value value="95" name="CYCLES_HELD_OFF_ID_9"/>
++ <value value="96" name="CYCLES_HELD_OFF_ID_10"/>
++ <value value="97" name="CYCLES_HELD_OFF_ID_11"/>
++ <value value="98" name="CYCLES_HELD_OFF_ID_12"/>
++ <value value="99" name="CYCLES_HELD_OFF_ID_13"/>
++ <value value="100" name="CYCLES_HELD_OFF_ID_14"/>
++ <value value="101" name="CYCLES_HELD_OFF_ID_15"/>
++ <value value="102" name="AXI_READ_REQUEST_HELD_OFF"/>
++ <value value="103" name="AXI_WRITE_REQUEST_HELD_OFF"/>
++ <value value="104" name="AXI_REQUEST_HELD_OFF"/>
++ <value value="105" name="AXI_WRITE_DATA_HELD_OFF"/>
++ <value value="106" name="OCMEM_AXI_READ_REQUEST_HELD_OFF"/>
++ <value value="107" name="OCMEM_AXI_WRITE_REQUEST_HELD_OFF"/>
++ <value value="108" name="OCMEM_AXI_REQUEST_HELD_OFF"/>
++ <value value="109" name="OCMEM_AXI_WRITE_DATA_HELD_OFF"/>
++ <value value="110" name="ELAPSED_CYCLES_DDR"/>
++ <value value="111" name="ELAPSED_CYCLES_OCMEM"/>
++</enum>
++
++<enum name="a4xx_vfd_perfcounter_select">
++ <value value="0" name="VFD_UCHE_BYTE_FETCHED"/>
++ <value value="1" name="VFD_UCHE_TRANS"/>
++ <value value="3" name="VFD_FETCH_INSTRUCTIONS"/>
++ <value value="5" name="VFD_BUSY_CYCLES"/>
++ <value value="6" name="VFD_STALL_CYCLES_UCHE"/>
++ <value value="7" name="VFD_STALL_CYCLES_HLSQ"/>
++ <value value="8" name="VFD_STALL_CYCLES_VPC_BYPASS"/>
++ <value value="9" name="VFD_STALL_CYCLES_VPC_ALLOC"/>
++ <value value="13" name="VFD_MODE_0_FIBERS"/>
++ <value value="14" name="VFD_MODE_1_FIBERS"/>
++ <value value="15" name="VFD_MODE_2_FIBERS"/>
++ <value value="16" name="VFD_MODE_3_FIBERS"/>
++ <value value="17" name="VFD_MODE_4_FIBERS"/>
++ <value value="18" name="VFD_BFIFO_STALL"/>
++ <value value="19" name="VFD_NUM_VERTICES_TOTAL"/>
++ <value value="20" name="VFD_PACKER_FULL"/>
++ <value value="21" name="VFD_UCHE_REQUEST_FIFO_FULL"/>
++ <value value="22" name="VFD_STARVE_CYCLES_PC"/>
++ <value value="23" name="VFD_STARVE_CYCLES_UCHE"/>
++</enum>
++
++<enum name="a4xx_vpc_perfcounter_select">
++ <value value="2" name="VPC_SP_LM_COMPONENTS"/>
++ <value value="3" name="VPC_SP0_LM_BYTES"/>
++ <value value="4" name="VPC_SP1_LM_BYTES"/>
++ <value value="5" name="VPC_SP2_LM_BYTES"/>
++ <value value="6" name="VPC_SP3_LM_BYTES"/>
++ <value value="7" name="VPC_WORKING_CYCLES"/>
++ <value value="8" name="VPC_STALL_CYCLES_LM"/>
++ <value value="9" name="VPC_STARVE_CYCLES_RAS"/>
++ <value value="10" name="VPC_STREAMOUT_CYCLES"/>
++ <value value="12" name="VPC_UCHE_TRANSACTIONS"/>
++ <value value="13" name="VPC_STALL_CYCLES_UCHE"/>
++ <value value="14" name="VPC_BUSY_CYCLES"/>
++ <value value="15" name="VPC_STARVE_CYCLES_SP"/>
++</enum>
++
++<enum name="a4xx_vsc_perfcounter_select">
++ <value value="0" name="VSC_BUSY_CYCLES"/>
++ <value value="1" name="VSC_WORKING_CYCLES"/>
++ <value value="2" name="VSC_STALL_CYCLES_UCHE"/>
++ <value value="3" name="VSC_STARVE_CYCLES_RAS"/>
++ <value value="4" name="VSC_EOT_NUM"/>
++</enum>
++
++<domain name="A4XX" width="32">
++ <!-- RB registers -->
++ <reg32 offset="0x0cc0" name="RB_GMEM_BASE_ADDR"/>
++ <reg32 offset="0x0cc7" name="RB_PERFCTR_RB_SEL_0" type="a4xx_rb_perfcounter_select"/>
++ <reg32 offset="0x0cc8" name="RB_PERFCTR_RB_SEL_1" type="a4xx_rb_perfcounter_select"/>
++ <reg32 offset="0x0cc9" name="RB_PERFCTR_RB_SEL_2" type="a4xx_rb_perfcounter_select"/>
++ <reg32 offset="0x0cca" name="RB_PERFCTR_RB_SEL_3" type="a4xx_rb_perfcounter_select"/>
++ <reg32 offset="0x0ccb" name="RB_PERFCTR_RB_SEL_4" type="a4xx_rb_perfcounter_select"/>
++ <reg32 offset="0x0ccc" name="RB_PERFCTR_RB_SEL_5" type="a4xx_rb_perfcounter_select"/>
++ <reg32 offset="0x0ccd" name="RB_PERFCTR_RB_SEL_6" type="a4xx_rb_perfcounter_select"/>
++ <reg32 offset="0x0cce" name="RB_PERFCTR_RB_SEL_7" type="a4xx_rb_perfcounter_select"/>
++ <reg32 offset="0x0ccf" name="RB_PERFCTR_CCU_SEL_0" type="a4xx_ccu_perfcounter_select"/>
++ <reg32 offset="0x0cd0" name="RB_PERFCTR_CCU_SEL_1" type="a4xx_ccu_perfcounter_select"/>
++ <reg32 offset="0x0cd1" name="RB_PERFCTR_CCU_SEL_2" type="a4xx_ccu_perfcounter_select"/>
++ <reg32 offset="0x0cd2" name="RB_PERFCTR_CCU_SEL_3" type="a4xx_ccu_perfcounter_select"/>
++ <reg32 offset="0x0ce0" name="RB_FRAME_BUFFER_DIMENSION">
++ <bitfield name="WIDTH" low="0" high="13" type="uint"/>
++ <bitfield name="HEIGHT" low="16" high="29" type="uint"/>
++ </reg32>
++ <reg32 offset="0x20cc" name="RB_CLEAR_COLOR_DW0"/>
++ <reg32 offset="0x20cd" name="RB_CLEAR_COLOR_DW1"/>
++ <reg32 offset="0x20ce" name="RB_CLEAR_COLOR_DW2"/>
++ <reg32 offset="0x20cf" name="RB_CLEAR_COLOR_DW3"/>
++ <reg32 offset="0x20a0" name="RB_MODE_CONTROL">
++ <!--
++ for non-bypass mode, these are bin width/height.. although
++ possibly bigger bitfields to hold entire width/height for
++ gmem-bypass?? Either way, it appears to need to be multiple
++ of 32..
++ -->
++ <bitfield name="WIDTH" low="0" high="5" shr="5" type="uint"/>
++ <bitfield name="HEIGHT" low="8" high="13" shr="5" type="uint"/>
++ <bitfield name="ENABLE_GMEM" pos="16" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x20a1" name="RB_RENDER_CONTROL">
++ <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
++ <!-- nearly everything has bit3 set.. -->
++ <!-- bit5 set on resolve and tiling pass -->
++ <bitfield name="DISABLE_COLOR_PIPE" pos="5" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x20a2" name="RB_MSAA_CONTROL">
++ <bitfield name="DISABLE" pos="12" type="boolean"/>
++ <bitfield name="SAMPLES" low="13" high="15" type="uint"/>
++ </reg32>
++ <reg32 offset="0x20a3" name="RB_RENDER_CONTROL2">
++ <bitfield name="COORD_MASK" low="0" high="3" type="hex"/>
++ <bitfield name="SAMPLEMASK" pos="4" type="boolean"/>
++ <bitfield name="FACENESS" pos="5" type="boolean"/>
++ <bitfield name="SAMPLEID" pos="6" type="boolean"/>
++ <bitfield name="MSAA_SAMPLES" low="7" high="9" type="uint"/>
++ <bitfield name="SAMPLEID_HR" pos="11" type="boolean"/>
++ <bitfield name="IJ_PERSP_PIXEL" pos="12" type="boolean"/>
++ <!-- the 2 below are just educated guesses -->
++ <bitfield name="IJ_PERSP_CENTROID" pos="13" type="boolean"/>
++ <bitfield name="IJ_PERSP_SAMPLE" pos="14" type="boolean"/>
++ <!-- needs to be enabled to get nopersp values,
++ perhaps other cases too? -->
++ <bitfield name="SIZE" pos="15" type="boolean"/>
++ </reg32>
++ <array offset="0x20a4" name="RB_MRT" stride="5" length="8">
++ <reg32 offset="0x0" name="CONTROL">
++ <bitfield name="READ_DEST_ENABLE" pos="3" type="boolean"/>
++ <!-- both these bits seem to get set when enabling GL_BLEND.. -->
++ <bitfield name="BLEND" pos="4" type="boolean"/>
++ <bitfield name="BLEND2" pos="5" type="boolean"/>
++ <bitfield name="ROP_ENABLE" pos="6" type="boolean"/>
++ <bitfield name="ROP_CODE" low="8" high="11" type="a3xx_rop_code"/>
++ <bitfield name="COMPONENT_ENABLE" low="24" high="27" type="hex"/>
++ </reg32>
++ <reg32 offset="0x1" name="BUF_INFO">
++ <bitfield name="COLOR_FORMAT" low="0" high="5" type="a4xx_color_fmt"/>
++ <!--
++ guestimate position of COLOR_TILE_MODE.. this works out if
++ common value is 2, like on a3xx..
++ -->
++ <bitfield name="COLOR_TILE_MODE" low="6" high="7" type="a4xx_tile_mode"/>
++ <bitfield name="DITHER_MODE" low="9" high="10" type="adreno_rb_dither_mode"/>
++ <bitfield name="COLOR_SWAP" low="11" high="12" type="a3xx_color_swap"/>
++ <bitfield name="COLOR_SRGB" pos="13" type="boolean"/>
++ <!-- note: possibly some # of lsb's aren't there: -->
++ <doc>
++ Pitch (actually, appears to be pitch in bytes, so really is a stride)
++ in GMEM, so pitch of the current tile.
++ </doc>
++ <bitfield name="COLOR_BUF_PITCH" low="14" high="31" shr="4" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2" name="BASE"/>
++ <reg32 offset="0x3" name="CONTROL3">
++ <!-- probably missing some lsb's.. and guessing upper size -->
++ <!-- pitch * cpp * msaa: -->
++ <bitfield name="STRIDE" low="3" high="25" type="uint"/>
++ </reg32>
++ <reg32 offset="0x4" name="BLEND_CONTROL">
++ <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
++ <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
++ <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
++ <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
++ <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
++ <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
++ </reg32>
++ </array>
++
++ <reg32 offset="0x20f0" name="RB_BLEND_RED">
++ <bitfield name="UINT" low="0" high="7" type="hex"/>
++ <bitfield name="SINT" low="8" high="15" type="hex"/>
++ <bitfield name="FLOAT" low="16" high="31" type="float"/>
++ </reg32>
++ <reg32 offset="0x20f1" name="RB_BLEND_RED_F32" type="float"/>
++
++ <reg32 offset="0x20f2" name="RB_BLEND_GREEN">
++ <bitfield name="UINT" low="0" high="7" type="hex"/>
++ <bitfield name="SINT" low="8" high="15" type="hex"/>
++ <bitfield name="FLOAT" low="16" high="31" type="float"/>
++ </reg32>
++ <reg32 offset="0x20f3" name="RB_BLEND_GREEN_F32" type="float"/>
++
++ <reg32 offset="0x20f4" name="RB_BLEND_BLUE">
++ <bitfield name="UINT" low="0" high="7" type="hex"/>
++ <bitfield name="SINT" low="8" high="15" type="hex"/>
++ <bitfield name="FLOAT" low="16" high="31" type="float"/>
++ </reg32>
++ <reg32 offset="0x20f5" name="RB_BLEND_BLUE_F32" type="float"/>
++
++ <reg32 offset="0x20f6" name="RB_BLEND_ALPHA">
++ <bitfield name="UINT" low="0" high="7" type="hex"/>
++ <bitfield name="SINT" low="8" high="15" type="hex"/>
++ <bitfield name="FLOAT" low="16" high="31" type="float"/>
++ </reg32>
++ <reg32 offset="0x20f7" name="RB_BLEND_ALPHA_F32" type="float"/>
++
++ <reg32 offset="0x20f8" name="RB_ALPHA_CONTROL">
++ <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
++ <bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
++ <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
++ </reg32>
++ <reg32 offset="0x20f9" name="RB_FS_OUTPUT">
++ <!-- per-mrt enable bit -->
++ <bitfield name="ENABLE_BLEND" low="0" high="7"/>
++ <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
++ <!-- a guess? -->
++ <bitfield name="SAMPLE_MASK" low="16" high="31"/>
++ </reg32>
++ <reg32 offset="0x20fa" name="RB_SAMPLE_COUNT_CONTROL">
++ <bitfield name="COPY" pos="1" type="boolean"/>
++ <bitfield name="ADDR" low="2" high="31" shr="2"/>
++ </reg32>
++ <!-- always 00000000 for binning pass, else 0000000f: -->
++ <reg32 offset="0x20fb" name="RB_RENDER_COMPONENTS">
++ <bitfield name="RT0" low="0" high="3"/>
++ <bitfield name="RT1" low="4" high="7"/>
++ <bitfield name="RT2" low="8" high="11"/>
++ <bitfield name="RT3" low="12" high="15"/>
++ <bitfield name="RT4" low="16" high="19"/>
++ <bitfield name="RT5" low="20" high="23"/>
++ <bitfield name="RT6" low="24" high="27"/>
++ <bitfield name="RT7" low="28" high="31"/>
++ </reg32>
++
++ <reg32 offset="0x20fc" name="RB_COPY_CONTROL">
++ <!-- not sure # of bits -->
++ <bitfield name="MSAA_RESOLVE" low="0" high="1" type="a3xx_msaa_samples"/>
++ <bitfield name="MODE" low="4" high="6" type="adreno_rb_copy_control_mode"/>
++ <bitfield name="FASTCLEAR" low="8" high="11" type="hex"/>
++ <bitfield name="GMEM_BASE" low="14" high="31" shr="14" type="hex"/>
++ </reg32>
++ <reg32 offset="0x20fd" name="RB_COPY_DEST_BASE">
++ <bitfield name="BASE" low="5" high="31" shr="5" type="hex"/>
++ </reg32>
++ <reg32 offset="0x20fe" name="RB_COPY_DEST_PITCH">
++ <doc>actually, appears to be pitch in bytes, so really is a stride</doc>
++ <!-- not actually sure about max pitch... -->
++ <bitfield name="PITCH" low="0" high="31" shr="5" type="uint"/>
++ </reg32>
++ <reg32 offset="0x20ff" name="RB_COPY_DEST_INFO">
++ <bitfield name="FORMAT" low="2" high="7" type="a4xx_color_fmt"/>
++ <bitfield name="SWAP" low="8" high="9" type="a3xx_color_swap"/>
++ <bitfield name="DITHER_MODE" low="10" high="11" type="adreno_rb_dither_mode"/>
++ <bitfield name="COMPONENT_ENABLE" low="14" high="17" type="hex"/>
++ <bitfield name="ENDIAN" low="18" high="20" type="adreno_rb_surface_endian"/>
++ <bitfield name="TILE" low="24" high="25" type="a4xx_tile_mode"/>
++ </reg32>
++ <reg32 offset="0x2100" name="RB_FS_OUTPUT_REG">
++ <!-- bit0 set except for binning pass.. -->
++ <bitfield name="MRT" low="0" high="3" type="uint"/>
++ <bitfield name="FRAG_WRITES_Z" pos="5" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2101" name="RB_DEPTH_CONTROL">
++ <!--
++ guessing that this matches a2xx with the stencil fields
++ moved out into RB_STENCIL_CONTROL?
++ -->
++ <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
++ <bitfield name="Z_TEST_ENABLE" pos="1" type="boolean"/>
++ <bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/>
++ <bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/>
++ <bitfield name="Z_CLAMP_ENABLE" pos="7" type="boolean"/>
++ <bitfield name="EARLY_Z_DISABLE" pos="16" type="boolean"/>
++ <bitfield name="FORCE_FRAGZ_TO_FS" pos="17" type="boolean"/>
++ <doc>Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
++ <bitfield name="Z_READ_ENABLE" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2102" name="RB_DEPTH_CLEAR"/>
++ <reg32 offset="0x2103" name="RB_DEPTH_INFO">
++ <bitfield name="DEPTH_FORMAT" low="0" high="1" type="a4xx_depth_format"/>
++ <doc>
++ DEPTH_BASE is offset in GMEM to depth/stencil buffer, ie
++ bin_w * bin_h / 1024 (possible rounded up to multiple of
++ something?? ie. 39 becomes 40, 78 becomes 80.. 75 becomes
++ 80.. so maybe it needs to be multiple of 8??
++ </doc>
++ <bitfield name="DEPTH_BASE" low="12" high="31" shr="12" type="hex"/>
++ </reg32>
++ <reg32 offset="0x2104" name="RB_DEPTH_PITCH" shr="5" type="uint">
++ <doc>stride of depth/stencil buffer</doc>
++ </reg32>
++ <reg32 offset="0x2105" name="RB_DEPTH_PITCH2" shr="5" type="uint">
++ <doc>???</doc>
++ </reg32>
++ <reg32 offset="0x2106" name="RB_STENCIL_CONTROL">
++ <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
++ <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
++ <!--
++ set for stencil operations that require read from stencil
++ buffer, but not for example for stencil clear (which does
++ not require read).. so guessing this is analogous to
++ READ_DEST_ENABLE for color buffer..
++ -->
++ <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
++ <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
++ <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
++ <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
++ <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
++ <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
++ <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
++ <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
++ <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
++ </reg32>
++ <reg32 offset="0x2107" name="RB_STENCIL_CONTROL2">
++ <!--
++ This seems to be set by blob if there is a stencil buffer
++ at all in GMEM, regardless of whether it is enabled for
++ a particular draw (ie. RB_STENCIL_CONTROL). Not really
++ sure if that is required or just a quirk of the blob
++ -->
++ <bitfield name="STENCIL_BUFFER" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2108" name="RB_STENCIL_INFO">
++ <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
++ <doc>Base address for stencil when not using interleaved depth/stencil</doc>
++ <bitfield name="STENCIL_BASE" low="12" high="31" shr="12" type="hex"/>
++ </reg32>
++ <reg32 offset="0x2109" name="RB_STENCIL_PITCH" shr="5" type="uint">
++ <doc>pitch of stencil buffer when not using interleaved depth/stencil</doc>
++ </reg32>
++
++ <reg32 offset="0x210b" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
++ <reg32 offset="0x210c" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
++ <reg32 offset="0x210d" name="RB_BIN_OFFSET" type="adreno_reg_xy"/>
++ <array offset="0x2120" name="RB_VPORT_Z_CLAMP" stride="2" length="16">
++ <reg32 offset="0x0" name="MIN"/>
++ <reg32 offset="0x1" name="MAX"/>
++ </array>
++
++ <!-- RBBM registers -->
++ <reg32 offset="0x0000" name="RBBM_HW_VERSION"/>
++ <reg32 offset="0x0002" name="RBBM_HW_CONFIGURATION"/>
++ <array offset="0x4" name="RBBM_CLOCK_CTL_TP" stride="1" length="4">
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++ <array offset="0x8" name="RBBM_CLOCK_CTL2_TP" stride="1" length="4">
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++ <array offset="0xc" name="RBBM_CLOCK_HYST_TP" stride="1" length="4">
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++ <array offset="0x10" name="RBBM_CLOCK_DELAY_TP" stride="1" length="4">
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++ <reg32 offset="0x0014" name="RBBM_CLOCK_CTL_UCHE "/>
++ <reg32 offset="0x0015" name="RBBM_CLOCK_CTL2_UCHE"/>
++ <reg32 offset="0x0016" name="RBBM_CLOCK_CTL3_UCHE"/>
++ <reg32 offset="0x0017" name="RBBM_CLOCK_CTL4_UCHE"/>
++ <reg32 offset="0x0018" name="RBBM_CLOCK_HYST_UCHE"/>
++ <reg32 offset="0x0019" name="RBBM_CLOCK_DELAY_UCHE"/>
++ <reg32 offset="0x001a" name="RBBM_CLOCK_MODE_GPC"/>
++ <reg32 offset="0x001b" name="RBBM_CLOCK_DELAY_GPC"/>
++ <reg32 offset="0x001c" name="RBBM_CLOCK_HYST_GPC"/>
++ <reg32 offset="0x001d" name="RBBM_CLOCK_CTL_TSE_RAS_RBBM"/>
++ <reg32 offset="0x001e" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
++ <reg32 offset="0x001f" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
++ <reg32 offset="0x0020" name="RBBM_CLOCK_CTL"/>
++ <reg32 offset="0x0021" name="RBBM_SP_HYST_CNT"/>
++ <reg32 offset="0x0022" name="RBBM_SW_RESET_CMD"/>
++ <reg32 offset="0x0023" name="RBBM_AHB_CTL0"/>
++ <reg32 offset="0x0024" name="RBBM_AHB_CTL1"/>
++ <reg32 offset="0x0025" name="RBBM_AHB_CMD"/>
++ <reg32 offset="0x0026" name="RBBM_RB_SUB_BLOCK_SEL_CTL"/>
++ <reg32 offset="0x0028" name="RBBM_RAM_ACC_63_32"/>
++ <reg32 offset="0x002b" name="RBBM_WAIT_IDLE_CLOCKS_CTL"/>
++ <reg32 offset="0x002f" name="RBBM_INTERFACE_HANG_INT_CTL"/>
++ <reg32 offset="0x0034" name="RBBM_INTERFACE_HANG_MASK_CTL4"/>
++ <reg32 offset="0x0036" name="RBBM_INT_CLEAR_CMD"/>
++ <reg32 offset="0x0037" name="RBBM_INT_0_MASK"/>
++ <reg32 offset="0x003e" name="RBBM_RBBM_CTL"/>
++ <reg32 offset="0x003f" name="RBBM_AHB_DEBUG_CTL"/>
++ <reg32 offset="0x0041" name="RBBM_VBIF_DEBUG_CTL"/>
++ <reg32 offset="0x0042" name="RBBM_CLOCK_CTL2"/>
++ <reg32 offset="0x0045" name="RBBM_BLOCK_SW_RESET_CMD"/>
++ <reg32 offset="0x0047" name="RBBM_RESET_CYCLES"/>
++ <reg32 offset="0x0049" name="RBBM_EXT_TRACE_BUS_CTL"/>
++ <reg32 offset="0x004a" name="RBBM_CFG_DEBBUS_SEL_A"/>
++ <reg32 offset="0x004b" name="RBBM_CFG_DEBBUS_SEL_B"/>
++ <reg32 offset="0x004c" name="RBBM_CFG_DEBBUS_SEL_C"/>
++ <reg32 offset="0x004d" name="RBBM_CFG_DEBBUS_SEL_D"/>
++ <reg32 offset="0x0098" name="RBBM_POWER_CNTL_IP">
++ <bitfield name="SW_COLLAPSE" pos="0" type="boolean"/>
++ <bitfield name="SP_TP_PWR_ON" pos="20" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x009c" name="RBBM_PERFCTR_CP_0_LO"/>
++ <reg32 offset="0x009d" name="RBBM_PERFCTR_CP_0_HI"/>
++ <reg32 offset="0x009e" name="RBBM_PERFCTR_CP_1_LO"/>
++ <reg32 offset="0x009f" name="RBBM_PERFCTR_CP_1_HI"/>
++ <reg32 offset="0x00a0" name="RBBM_PERFCTR_CP_2_LO"/>
++ <reg32 offset="0x00a1" name="RBBM_PERFCTR_CP_2_HI"/>
++ <reg32 offset="0x00a2" name="RBBM_PERFCTR_CP_3_LO"/>
++ <reg32 offset="0x00a3" name="RBBM_PERFCTR_CP_3_HI"/>
++ <reg32 offset="0x00a4" name="RBBM_PERFCTR_CP_4_LO"/>
++ <reg32 offset="0x00a5" name="RBBM_PERFCTR_CP_4_HI"/>
++ <reg32 offset="0x00a6" name="RBBM_PERFCTR_CP_5_LO"/>
++ <reg32 offset="0x00a7" name="RBBM_PERFCTR_CP_5_HI"/>
++ <reg32 offset="0x00a8" name="RBBM_PERFCTR_CP_6_LO"/>
++ <reg32 offset="0x00a9" name="RBBM_PERFCTR_CP_6_HI"/>
++ <reg32 offset="0x00aa" name="RBBM_PERFCTR_CP_7_LO"/>
++ <reg32 offset="0x00ab" name="RBBM_PERFCTR_CP_7_HI"/>
++ <reg32 offset="0x00ac" name="RBBM_PERFCTR_RBBM_0_LO"/>
++ <reg32 offset="0x00ad" name="RBBM_PERFCTR_RBBM_0_HI"/>
++ <reg32 offset="0x00ae" name="RBBM_PERFCTR_RBBM_1_LO"/>
++ <reg32 offset="0x00af" name="RBBM_PERFCTR_RBBM_1_HI"/>
++ <reg32 offset="0x00b0" name="RBBM_PERFCTR_RBBM_2_LO"/>
++ <reg32 offset="0x00b1" name="RBBM_PERFCTR_RBBM_2_HI"/>
++ <reg32 offset="0x00b2" name="RBBM_PERFCTR_RBBM_3_LO"/>
++ <reg32 offset="0x00b3" name="RBBM_PERFCTR_RBBM_3_HI"/>
++ <reg32 offset="0x00b4" name="RBBM_PERFCTR_PC_0_LO"/>
++ <reg32 offset="0x00b5" name="RBBM_PERFCTR_PC_0_HI"/>
++ <reg32 offset="0x00b6" name="RBBM_PERFCTR_PC_1_LO"/>
++ <reg32 offset="0x00b7" name="RBBM_PERFCTR_PC_1_HI"/>
++ <reg32 offset="0x00b8" name="RBBM_PERFCTR_PC_2_LO"/>
++ <reg32 offset="0x00b9" name="RBBM_PERFCTR_PC_2_HI"/>
++ <reg32 offset="0x00ba" name="RBBM_PERFCTR_PC_3_LO"/>
++ <reg32 offset="0x00bb" name="RBBM_PERFCTR_PC_3_HI"/>
++ <reg32 offset="0x00bc" name="RBBM_PERFCTR_PC_4_LO"/>
++ <reg32 offset="0x00bd" name="RBBM_PERFCTR_PC_4_HI"/>
++ <reg32 offset="0x00be" name="RBBM_PERFCTR_PC_5_LO"/>
++ <reg32 offset="0x00bf" name="RBBM_PERFCTR_PC_5_HI"/>
++ <reg32 offset="0x00c0" name="RBBM_PERFCTR_PC_6_LO"/>
++ <reg32 offset="0x00c1" name="RBBM_PERFCTR_PC_6_HI"/>
++ <reg32 offset="0x00c2" name="RBBM_PERFCTR_PC_7_LO"/>
++ <reg32 offset="0x00c3" name="RBBM_PERFCTR_PC_7_HI"/>
++ <reg32 offset="0x00c4" name="RBBM_PERFCTR_VFD_0_LO"/>
++ <reg32 offset="0x00c5" name="RBBM_PERFCTR_VFD_0_HI"/>
++ <reg32 offset="0x00c6" name="RBBM_PERFCTR_VFD_1_LO"/>
++ <reg32 offset="0x00c7" name="RBBM_PERFCTR_VFD_1_HI"/>
++ <reg32 offset="0x00c8" name="RBBM_PERFCTR_VFD_2_LO"/>
++ <reg32 offset="0x00c9" name="RBBM_PERFCTR_VFD_2_HI"/>
++ <reg32 offset="0x00ca" name="RBBM_PERFCTR_VFD_3_LO"/>
++ <reg32 offset="0x00cb" name="RBBM_PERFCTR_VFD_3_HI"/>
++ <reg32 offset="0x00cc" name="RBBM_PERFCTR_VFD_4_LO"/>
++ <reg32 offset="0x00cd" name="RBBM_PERFCTR_VFD_4_HI"/>
++ <reg32 offset="0x00ce" name="RBBM_PERFCTR_VFD_5_LO"/>
++ <reg32 offset="0x00cf" name="RBBM_PERFCTR_VFD_5_HI"/>
++ <reg32 offset="0x00d0" name="RBBM_PERFCTR_VFD_6_LO"/>
++ <reg32 offset="0x00d1" name="RBBM_PERFCTR_VFD_6_HI"/>
++ <reg32 offset="0x00d2" name="RBBM_PERFCTR_VFD_7_LO"/>
++ <reg32 offset="0x00d3" name="RBBM_PERFCTR_VFD_7_HI"/>
++ <reg32 offset="0x00d4" name="RBBM_PERFCTR_HLSQ_0_LO"/>
++ <reg32 offset="0x00d5" name="RBBM_PERFCTR_HLSQ_0_HI"/>
++ <reg32 offset="0x00d6" name="RBBM_PERFCTR_HLSQ_1_LO"/>
++ <reg32 offset="0x00d7" name="RBBM_PERFCTR_HLSQ_1_HI"/>
++ <reg32 offset="0x00d8" name="RBBM_PERFCTR_HLSQ_2_LO"/>
++ <reg32 offset="0x00d9" name="RBBM_PERFCTR_HLSQ_2_HI"/>
++ <reg32 offset="0x00da" name="RBBM_PERFCTR_HLSQ_3_LO"/>
++ <reg32 offset="0x00db" name="RBBM_PERFCTR_HLSQ_3_HI"/>
++ <reg32 offset="0x00dc" name="RBBM_PERFCTR_HLSQ_4_LO"/>
++ <reg32 offset="0x00dd" name="RBBM_PERFCTR_HLSQ_4_HI"/>
++ <reg32 offset="0x00de" name="RBBM_PERFCTR_HLSQ_5_LO"/>
++ <reg32 offset="0x00df" name="RBBM_PERFCTR_HLSQ_5_HI"/>
++ <reg32 offset="0x00e0" name="RBBM_PERFCTR_HLSQ_6_LO"/>
++ <reg32 offset="0x00e1" name="RBBM_PERFCTR_HLSQ_6_HI"/>
++ <reg32 offset="0x00e2" name="RBBM_PERFCTR_HLSQ_7_LO"/>
++ <reg32 offset="0x00e3" name="RBBM_PERFCTR_HLSQ_7_HI"/>
++ <reg32 offset="0x00e4" name="RBBM_PERFCTR_VPC_0_LO"/>
++ <reg32 offset="0x00e5" name="RBBM_PERFCTR_VPC_0_HI"/>
++ <reg32 offset="0x00e6" name="RBBM_PERFCTR_VPC_1_LO"/>
++ <reg32 offset="0x00e7" name="RBBM_PERFCTR_VPC_1_HI"/>
++ <reg32 offset="0x00e8" name="RBBM_PERFCTR_VPC_2_LO"/>
++ <reg32 offset="0x00e9" name="RBBM_PERFCTR_VPC_2_HI"/>
++ <reg32 offset="0x00ea" name="RBBM_PERFCTR_VPC_3_LO"/>
++ <reg32 offset="0x00eb" name="RBBM_PERFCTR_VPC_3_HI"/>
++ <reg32 offset="0x00ec" name="RBBM_PERFCTR_CCU_0_LO"/>
++ <reg32 offset="0x00ed" name="RBBM_PERFCTR_CCU_0_HI"/>
++ <reg32 offset="0x00ee" name="RBBM_PERFCTR_CCU_1_LO"/>
++ <reg32 offset="0x00ef" name="RBBM_PERFCTR_CCU_1_HI"/>
++ <reg32 offset="0x00f0" name="RBBM_PERFCTR_CCU_2_LO"/>
++ <reg32 offset="0x00f1" name="RBBM_PERFCTR_CCU_2_HI"/>
++ <reg32 offset="0x00f2" name="RBBM_PERFCTR_CCU_3_LO"/>
++ <reg32 offset="0x00f3" name="RBBM_PERFCTR_CCU_3_HI"/>
++ <reg32 offset="0x00f4" name="RBBM_PERFCTR_TSE_0_LO"/>
++ <reg32 offset="0x00f5" name="RBBM_PERFCTR_TSE_0_HI"/>
++ <reg32 offset="0x00f6" name="RBBM_PERFCTR_TSE_1_LO"/>
++ <reg32 offset="0x00f7" name="RBBM_PERFCTR_TSE_1_HI"/>
++ <reg32 offset="0x00f8" name="RBBM_PERFCTR_TSE_2_LO"/>
++ <reg32 offset="0x00f9" name="RBBM_PERFCTR_TSE_2_HI"/>
++ <reg32 offset="0x00fa" name="RBBM_PERFCTR_TSE_3_LO"/>
++ <reg32 offset="0x00fb" name="RBBM_PERFCTR_TSE_3_HI"/>
++ <reg32 offset="0x00fc" name="RBBM_PERFCTR_RAS_0_LO"/>
++ <reg32 offset="0x00fd" name="RBBM_PERFCTR_RAS_0_HI"/>
++ <reg32 offset="0x00fe" name="RBBM_PERFCTR_RAS_1_LO"/>
++ <reg32 offset="0x00ff" name="RBBM_PERFCTR_RAS_1_HI"/>
++ <reg32 offset="0x0100" name="RBBM_PERFCTR_RAS_2_LO"/>
++ <reg32 offset="0x0101" name="RBBM_PERFCTR_RAS_2_HI"/>
++ <reg32 offset="0x0102" name="RBBM_PERFCTR_RAS_3_LO"/>
++ <reg32 offset="0x0103" name="RBBM_PERFCTR_RAS_3_HI"/>
++ <reg32 offset="0x0104" name="RBBM_PERFCTR_UCHE_0_LO"/>
++ <reg32 offset="0x0105" name="RBBM_PERFCTR_UCHE_0_HI"/>
++ <reg32 offset="0x0106" name="RBBM_PERFCTR_UCHE_1_LO"/>
++ <reg32 offset="0x0107" name="RBBM_PERFCTR_UCHE_1_HI"/>
++ <reg32 offset="0x0108" name="RBBM_PERFCTR_UCHE_2_LO"/>
++ <reg32 offset="0x0109" name="RBBM_PERFCTR_UCHE_2_HI"/>
++ <reg32 offset="0x010a" name="RBBM_PERFCTR_UCHE_3_LO"/>
++ <reg32 offset="0x010b" name="RBBM_PERFCTR_UCHE_3_HI"/>
++ <reg32 offset="0x010c" name="RBBM_PERFCTR_UCHE_4_LO"/>
++ <reg32 offset="0x010d" name="RBBM_PERFCTR_UCHE_4_HI"/>
++ <reg32 offset="0x010e" name="RBBM_PERFCTR_UCHE_5_LO"/>
++ <reg32 offset="0x010f" name="RBBM_PERFCTR_UCHE_5_HI"/>
++ <reg32 offset="0x0110" name="RBBM_PERFCTR_UCHE_6_LO"/>
++ <reg32 offset="0x0111" name="RBBM_PERFCTR_UCHE_6_HI"/>
++ <reg32 offset="0x0112" name="RBBM_PERFCTR_UCHE_7_LO"/>
++ <reg32 offset="0x0113" name="RBBM_PERFCTR_UCHE_7_HI"/>
++ <reg32 offset="0x0114" name="RBBM_PERFCTR_TP_0_LO"/>
++ <reg32 offset="0x0115" name="RBBM_PERFCTR_TP_0_HI"/>
++ <reg32 offset="0x0116" name="RBBM_PERFCTR_TP_1_LO"/>
++ <reg32 offset="0x0117" name="RBBM_PERFCTR_TP_1_HI"/>
++ <reg32 offset="0x0118" name="RBBM_PERFCTR_TP_2_LO"/>
++ <reg32 offset="0x0119" name="RBBM_PERFCTR_TP_2_HI"/>
++ <reg32 offset="0x011a" name="RBBM_PERFCTR_TP_3_LO"/>
++ <reg32 offset="0x011b" name="RBBM_PERFCTR_TP_3_HI"/>
++ <reg32 offset="0x011c" name="RBBM_PERFCTR_TP_4_LO"/>
++ <reg32 offset="0x011d" name="RBBM_PERFCTR_TP_4_HI"/>
++ <reg32 offset="0x011e" name="RBBM_PERFCTR_TP_5_LO"/>
++ <reg32 offset="0x011f" name="RBBM_PERFCTR_TP_5_HI"/>
++ <reg32 offset="0x0120" name="RBBM_PERFCTR_TP_6_LO"/>
++ <reg32 offset="0x0121" name="RBBM_PERFCTR_TP_6_HI"/>
++ <reg32 offset="0x0122" name="RBBM_PERFCTR_TP_7_LO"/>
++ <reg32 offset="0x0123" name="RBBM_PERFCTR_TP_7_HI"/>
++ <reg32 offset="0x0124" name="RBBM_PERFCTR_SP_0_LO"/>
++ <reg32 offset="0x0125" name="RBBM_PERFCTR_SP_0_HI"/>
++ <reg32 offset="0x0126" name="RBBM_PERFCTR_SP_1_LO"/>
++ <reg32 offset="0x0127" name="RBBM_PERFCTR_SP_1_HI"/>
++ <reg32 offset="0x0128" name="RBBM_PERFCTR_SP_2_LO"/>
++ <reg32 offset="0x0129" name="RBBM_PERFCTR_SP_2_HI"/>
++ <reg32 offset="0x012a" name="RBBM_PERFCTR_SP_3_LO"/>
++ <reg32 offset="0x012b" name="RBBM_PERFCTR_SP_3_HI"/>
++ <reg32 offset="0x012c" name="RBBM_PERFCTR_SP_4_LO"/>
++ <reg32 offset="0x012d" name="RBBM_PERFCTR_SP_4_HI"/>
++ <reg32 offset="0x012e" name="RBBM_PERFCTR_SP_5_LO"/>
++ <reg32 offset="0x012f" name="RBBM_PERFCTR_SP_5_HI"/>
++ <reg32 offset="0x0130" name="RBBM_PERFCTR_SP_6_LO"/>
++ <reg32 offset="0x0131" name="RBBM_PERFCTR_SP_6_HI"/>
++ <reg32 offset="0x0132" name="RBBM_PERFCTR_SP_7_LO"/>
++ <reg32 offset="0x0133" name="RBBM_PERFCTR_SP_7_HI"/>
++ <reg32 offset="0x0134" name="RBBM_PERFCTR_SP_8_LO"/>
++ <reg32 offset="0x0135" name="RBBM_PERFCTR_SP_8_HI"/>
++ <reg32 offset="0x0136" name="RBBM_PERFCTR_SP_9_LO"/>
++ <reg32 offset="0x0137" name="RBBM_PERFCTR_SP_9_HI"/>
++ <reg32 offset="0x0138" name="RBBM_PERFCTR_SP_10_LO"/>
++ <reg32 offset="0x0139" name="RBBM_PERFCTR_SP_10_HI"/>
++ <reg32 offset="0x013a" name="RBBM_PERFCTR_SP_11_LO"/>
++ <reg32 offset="0x013b" name="RBBM_PERFCTR_SP_11_HI"/>
++ <reg32 offset="0x013c" name="RBBM_PERFCTR_RB_0_LO"/>
++ <reg32 offset="0x013d" name="RBBM_PERFCTR_RB_0_HI"/>
++ <reg32 offset="0x013e" name="RBBM_PERFCTR_RB_1_LO"/>
++ <reg32 offset="0x013f" name="RBBM_PERFCTR_RB_1_HI"/>
++ <reg32 offset="0x0140" name="RBBM_PERFCTR_RB_2_LO"/>
++ <reg32 offset="0x0141" name="RBBM_PERFCTR_RB_2_HI"/>
++ <reg32 offset="0x0142" name="RBBM_PERFCTR_RB_3_LO"/>
++ <reg32 offset="0x0143" name="RBBM_PERFCTR_RB_3_HI"/>
++ <reg32 offset="0x0144" name="RBBM_PERFCTR_RB_4_LO"/>
++ <reg32 offset="0x0145" name="RBBM_PERFCTR_RB_4_HI"/>
++ <reg32 offset="0x0146" name="RBBM_PERFCTR_RB_5_LO"/>
++ <reg32 offset="0x0147" name="RBBM_PERFCTR_RB_5_HI"/>
++ <reg32 offset="0x0148" name="RBBM_PERFCTR_RB_6_LO"/>
++ <reg32 offset="0x0149" name="RBBM_PERFCTR_RB_6_HI"/>
++ <reg32 offset="0x014a" name="RBBM_PERFCTR_RB_7_LO"/>
++ <reg32 offset="0x014b" name="RBBM_PERFCTR_RB_7_HI"/>
++ <reg32 offset="0x014c" name="RBBM_PERFCTR_VSC_0_LO"/>
++ <reg32 offset="0x014d" name="RBBM_PERFCTR_VSC_0_HI"/>
++ <reg32 offset="0x014e" name="RBBM_PERFCTR_VSC_1_LO"/>
++ <reg32 offset="0x014f" name="RBBM_PERFCTR_VSC_1_HI"/>
++ <reg32 offset="0x0166" name="RBBM_PERFCTR_PWR_0_LO"/>
++ <reg32 offset="0x0167" name="RBBM_PERFCTR_PWR_0_HI"/>
++ <reg32 offset="0x0168" name="RBBM_PERFCTR_PWR_1_LO"/>
++ <reg32 offset="0x0169" name="RBBM_PERFCTR_PWR_1_HI"/>
++ <reg32 offset="0x016e" name="RBBM_ALWAYSON_COUNTER_LO"/>
++ <reg32 offset="0x016f" name="RBBM_ALWAYSON_COUNTER_HI"/>
++ <array offset="0x0068" name="RBBM_CLOCK_CTL_SP" stride="1" length="4">
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++ <array offset="0x006c" name="RBBM_CLOCK_CTL2_SP" stride="1" length="4">
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++ <array offset="0x0070" name="RBBM_CLOCK_HYST_SP" stride="1" length="4">
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++ <array offset="0x0074" name="RBBM_CLOCK_DELAY_SP" stride="1" length="4">
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++ <array offset="0x0078" name="RBBM_CLOCK_CTL_RB" stride="1" length="4">
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++ <array offset="0x007c" name="RBBM_CLOCK_CTL2_RB" stride="1" length="4">
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++ <array offset="0x0082" name="RBBM_CLOCK_CTL_MARB_CCU" stride="1" length="4">
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++ <array offset="0x0086" name="RBBM_CLOCK_HYST_RB_MARB_CCU" stride="1" length="4">
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++ <reg32 offset="0x0080" name="RBBM_CLOCK_HYST_COM_DCOM"/>
++ <reg32 offset="0x0081" name="RBBM_CLOCK_CTL_COM_DCOM"/>
++ <reg32 offset="0x008a" name="RBBM_CLOCK_CTL_HLSQ"/>
++ <reg32 offset="0x008b" name="RBBM_CLOCK_HYST_HLSQ"/>
++ <reg32 offset="0x008c" name="RBBM_CLOCK_DELAY_HLSQ"/>
++ <bitset name="A4XX_CGC_HLSQ">
++ <bitfield name="EARLY_CYC" low="20" high="22" type="uint"/>
++ </bitset>
++ <reg32 offset="0x008d" name="RBBM_CLOCK_DELAY_COM_DCOM"/>
++ <array offset="0x008e" name="RBBM_CLOCK_DELAY_RB_MARB_CCU_L1" stride="1" length="4">
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++ <bitset name="A4XX_INT0">
++ <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
++ <bitfield name="RBBM_AHB_ERROR" pos="1" type="boolean"/>
++ <bitfield name="RBBM_REG_TIMEOUT" pos="2" type="boolean"/>
++ <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3" type="boolean"/>
++ <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4" type="boolean"/>
++ <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="5" type="boolean"/>
++ <bitfield name="VFD_ERROR" pos="6" type="boolean"/>
++ <bitfield name="CP_SW_INT" pos="7" type="boolean"/>
++ <bitfield name="CP_T0_PACKET_IN_IB" pos="8" type="boolean"/>
++ <bitfield name="CP_OPCODE_ERROR" pos="9" type="boolean"/>
++ <bitfield name="CP_RESERVED_BIT_ERROR" pos="10" type="boolean"/>
++ <bitfield name="CP_HW_FAULT" pos="11" type="boolean"/>
++ <bitfield name="CP_DMA" pos="12" type="boolean"/>
++ <bitfield name="CP_IB2_INT" pos="13" type="boolean"/>
++ <bitfield name="CP_IB1_INT" pos="14" type="boolean"/>
++ <bitfield name="CP_RB_INT" pos="15" type="boolean"/>
++ <bitfield name="CP_REG_PROTECT_FAULT" pos="16" type="boolean"/>
++ <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
++ <bitfield name="CP_VS_DONE_TS" pos="18" type="boolean"/>
++ <bitfield name="CP_PS_DONE_TS" pos="19" type="boolean"/>
++ <bitfield name="CACHE_FLUSH_TS" pos="20" type="boolean"/>
++ <bitfield name="CP_AHB_ERROR_HALT" pos="21" type="boolean"/>
++ <bitfield name="MISC_HANG_DETECT" pos="24" type="boolean"/>
++ <bitfield name="UCHE_OOB_ACCESS" pos="25" type="boolean"/>
++ </bitset>
++
++ <reg32 offset="0x0099" name="RBBM_SP_REGFILE_SLEEP_CNTL_0"/>
++ <reg32 offset="0x009a" name="RBBM_SP_REGFILE_SLEEP_CNTL_1"/>
++ <reg32 offset="0x0170" name="RBBM_PERFCTR_CTL"/>
++ <reg32 offset="0x0171" name="RBBM_PERFCTR_LOAD_CMD0"/>
++ <reg32 offset="0x0172" name="RBBM_PERFCTR_LOAD_CMD1"/>
++ <reg32 offset="0x0173" name="RBBM_PERFCTR_LOAD_CMD2"/>
++ <reg32 offset="0x0174" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
++ <reg32 offset="0x0175" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
++ <reg32 offset="0x0176" name="RBBM_PERFCTR_RBBM_SEL_0" type="a4xx_rbbm_perfcounter_select"/>
++ <reg32 offset="0x0177" name="RBBM_PERFCTR_RBBM_SEL_1" type="a4xx_rbbm_perfcounter_select"/>
++ <reg32 offset="0x0178" name="RBBM_PERFCTR_RBBM_SEL_2" type="a4xx_rbbm_perfcounter_select"/>
++ <reg32 offset="0x0179" name="RBBM_PERFCTR_RBBM_SEL_3" type="a4xx_rbbm_perfcounter_select"/>
++ <reg32 offset="0x017a" name="RBBM_GPU_BUSY_MASKED"/>
++ <reg32 offset="0x017d" name="RBBM_INT_0_STATUS"/>
++ <reg32 offset="0x0182" name="RBBM_CLOCK_STATUS"/>
++ <reg32 offset="0x0189" name="RBBM_AHB_STATUS"/>
++ <reg32 offset="0x018c" name="RBBM_AHB_ME_SPLIT_STATUS"/>
++ <reg32 offset="0x018d" name="RBBM_AHB_PFP_SPLIT_STATUS"/>
++ <reg32 offset="0x018f" name="RBBM_AHB_ERROR_STATUS"/>
++ <reg32 offset="0x0191" name="RBBM_STATUS">
++ <bitfield name="HI_BUSY" pos="0" type="boolean"/>
++ <bitfield name="CP_ME_BUSY" pos="1" type="boolean"/>
++ <bitfield name="CP_PFP_BUSY" pos="2" type="boolean"/>
++ <bitfield name="CP_NRT_BUSY" pos="14" type="boolean"/>
++ <bitfield name="VBIF_BUSY" pos="15" type="boolean"/>
++ <bitfield name="TSE_BUSY" pos="16" type="boolean"/>
++ <bitfield name="RAS_BUSY" pos="17" type="boolean"/>
++ <bitfield name="RB_BUSY" pos="18" type="boolean"/>
++ <bitfield name="PC_DCALL_BUSY" pos="19" type="boolean"/>
++ <bitfield name="PC_VSD_BUSY" pos="20" type="boolean"/>
++ <bitfield name="VFD_BUSY" pos="21" type="boolean"/>
++ <bitfield name="VPC_BUSY" pos="22" type="boolean"/>
++ <bitfield name="UCHE_BUSY" pos="23" type="boolean"/>
++ <bitfield name="SP_BUSY" pos="24" type="boolean"/>
++ <bitfield name="TPL1_BUSY" pos="25" type="boolean"/>
++ <bitfield name="MARB_BUSY" pos="26" type="boolean"/>
++ <bitfield name="VSC_BUSY" pos="27" type="boolean"/>
++ <bitfield name="ARB_BUSY" pos="28" type="boolean"/>
++ <bitfield name="HLSQ_BUSY" pos="29" type="boolean"/>
++ <bitfield name="GPU_BUSY_NOHC" pos="30" type="boolean"/>
++ <bitfield name="GPU_BUSY" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x019f" name="RBBM_INTERFACE_RRDY_STATUS5"/>
++ <reg32 offset="0x01b0" name="RBBM_POWER_STATUS">
++ <bitfield name="SP_TP_PWR_ON" pos="20" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x01b8" name="RBBM_WAIT_IDLE_CLOCKS_CTL2"/>
++
++ <!-- CP registers -->
++ <reg32 offset="0x0228" name="CP_SCRATCH_UMASK"/>
++ <reg32 offset="0x0229" name="CP_SCRATCH_ADDR"/>
++ <reg32 offset="0x0200" name="CP_RB_BASE"/>
++ <reg32 offset="0x0201" name="CP_RB_CNTL"/>
++ <reg32 offset="0x0205" name="CP_RB_WPTR"/>
++ <reg32 offset="0x0203" name="CP_RB_RPTR_ADDR"/>
++ <reg32 offset="0x0204" name="CP_RB_RPTR"/>
++ <reg32 offset="0x0206" name="CP_IB1_BASE"/>
++ <reg32 offset="0x0207" name="CP_IB1_BUFSZ"/>
++ <reg32 offset="0x0208" name="CP_IB2_BASE"/>
++ <reg32 offset="0x0209" name="CP_IB2_BUFSZ"/>
++ <reg32 offset="0x020c" name="CP_ME_NRT_ADDR"/>
++ <reg32 offset="0x020d" name="CP_ME_NRT_DATA"/>
++ <reg32 offset="0x0217" name="CP_ME_RB_DONE_DATA"/>
++ <reg32 offset="0x0219" name="CP_QUEUE_THRESH2"/>
++ <reg32 offset="0x021b" name="CP_MERCIU_SIZE"/>
++ <reg32 offset="0x021c" name="CP_ROQ_ADDR"/>
++ <reg32 offset="0x021d" name="CP_ROQ_DATA"/>
++ <reg32 offset="0x021e" name="CP_MEQ_ADDR"/>
++ <reg32 offset="0x021f" name="CP_MEQ_DATA"/>
++ <reg32 offset="0x0220" name="CP_MERCIU_ADDR"/>
++ <reg32 offset="0x0221" name="CP_MERCIU_DATA"/>
++ <reg32 offset="0x0222" name="CP_MERCIU_DATA2"/>
++ <reg32 offset="0x0223" name="CP_PFP_UCODE_ADDR"/>
++ <reg32 offset="0x0224" name="CP_PFP_UCODE_DATA"/>
++ <reg32 offset="0x0225" name="CP_ME_RAM_WADDR"/>
++ <reg32 offset="0x0226" name="CP_ME_RAM_RADDR"/>
++ <reg32 offset="0x0227" name="CP_ME_RAM_DATA"/>
++ <reg32 offset="0x022a" name="CP_PREEMPT"/>
++ <reg32 offset="0x022c" name="CP_CNTL"/>
++ <reg32 offset="0x022d" name="CP_ME_CNTL"/>
++ <reg32 offset="0x022e" name="CP_DEBUG"/>
++ <reg32 offset="0x0231" name="CP_DEBUG_ECO_CONTROL"/>
++ <reg32 offset="0x0232" name="CP_DRAW_STATE_ADDR"/>
++ <array offset="0x0240" name="CP_PROTECT" stride="1" length="16">
++ <reg32 offset="0x0" name="REG" type="adreno_cp_protect"/>
++ </array>
++ <reg32 offset="0x0250" name="CP_PROTECT_CTRL"/>
++ <reg32 offset="0x04c0" name="CP_ST_BASE"/>
++ <reg32 offset="0x04ce" name="CP_STQ_AVAIL"/>
++ <reg32 offset="0x04d0" name="CP_MERCIU_STAT"/>
++ <reg32 offset="0x04d2" name="CP_WFI_PEND_CTR"/>
++ <reg32 offset="0x04d8" name="CP_HW_FAULT"/>
++ <reg32 offset="0x04da" name="CP_PROTECT_STATUS"/>
++ <reg32 offset="0x04dd" name="CP_EVENTS_IN_FLIGHT"/>
++ <reg32 offset="0x0500" name="CP_PERFCTR_CP_SEL_0" type="a4xx_cp_perfcounter_select"/>
++ <reg32 offset="0x0501" name="CP_PERFCTR_CP_SEL_1" type="a4xx_cp_perfcounter_select"/>
++ <reg32 offset="0x0502" name="CP_PERFCTR_CP_SEL_2" type="a4xx_cp_perfcounter_select"/>
++ <reg32 offset="0x0503" name="CP_PERFCTR_CP_SEL_3" type="a4xx_cp_perfcounter_select"/>
++ <reg32 offset="0x0504" name="CP_PERFCTR_CP_SEL_4" type="a4xx_cp_perfcounter_select"/>
++ <reg32 offset="0x0505" name="CP_PERFCTR_CP_SEL_5" type="a4xx_cp_perfcounter_select"/>
++ <reg32 offset="0x0506" name="CP_PERFCTR_CP_SEL_6" type="a4xx_cp_perfcounter_select"/>
++ <reg32 offset="0x0507" name="CP_PERFCTR_CP_SEL_7" type="a4xx_cp_perfcounter_select"/>
++ <reg32 offset="0x050b" name="CP_PERFCOMBINER_SELECT"/>
++ <array offset="0x0578" name="CP_SCRATCH" stride="1" length="23">
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++
++
++ <!-- SP registers -->
++ <reg32 offset="0x0ec0" name="SP_VS_STATUS"/>
++ <reg32 offset="0x0ec3" name="SP_MODE_CONTROL"/>
++
++ <reg32 offset="0x0ec4" name="SP_PERFCTR_SP_SEL_0" type="a4xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ec5" name="SP_PERFCTR_SP_SEL_1" type="a4xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ec6" name="SP_PERFCTR_SP_SEL_2" type="a4xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ec7" name="SP_PERFCTR_SP_SEL_3" type="a4xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ec8" name="SP_PERFCTR_SP_SEL_4" type="a4xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ec9" name="SP_PERFCTR_SP_SEL_5" type="a4xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0eca" name="SP_PERFCTR_SP_SEL_6" type="a4xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ecb" name="SP_PERFCTR_SP_SEL_7" type="a4xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ecc" name="SP_PERFCTR_SP_SEL_8" type="a4xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ecd" name="SP_PERFCTR_SP_SEL_9" type="a4xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ece" name="SP_PERFCTR_SP_SEL_10" type="a4xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ecf" name="SP_PERFCTR_SP_SEL_11" type="a4xx_sp_perfcounter_select"/>
++
++ <reg32 offset="0x22c0" name="SP_SP_CTRL_REG">
++ <bitfield name="BINNING_PASS" pos="19" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x22c1" name="SP_INSTR_CACHE_CTRL">
++ <!-- set when VS in buffer mode: -->
++ <bitfield name="VS_BUFFER" pos="7" type="boolean"/>
++ <!-- set when FS in buffer mode: -->
++ <bitfield name="FS_BUFFER" pos="8" type="boolean"/>
++ <!-- set when both VS or FS in buffer mode: -->
++ <bitfield name="INSTR_BUFFER" pos="10" type="boolean"/>
++ <!-- TODO other bits probably matter when other stages active? -->
++ </reg32>
++
++ <bitset name="a4xx_sp_vs_fs_ctrl_reg0" inline="yes">
++ <!--
++ NOTE that SP_{VS,FS}_CTRL_REG1 are different, but so far REG0
++ appears to be the same..
++ -->
++ <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
++ <!-- VARYING bit only for FS.. think it controls emitting (ei) flag? -->
++ <bitfield name="VARYING" pos="1" type="boolean"/>
++ <!-- maybe CACHEINVALID is two bits?? -->
++ <bitfield name="CACHEINVALID" pos="2" type="boolean"/>
++ <doc>
++ The full/half register footprint is in units of four components,
++ so if r0.x is used, that counts as all of r0.[xyzw] as used.
++ There are separate full/half register footprint values as the
++ full and half registers are independent (not overlapping).
++ Presumably the thread scheduler hardware allocates the full/half
++ register names from the actual physical register file and
++ handles the register renaming.
++ </doc>
++ <bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>
++ <bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>
++ <!-- maybe INOUTREGOVERLAP is a bitflag? -->
++ <bitfield name="INOUTREGOVERLAP" low="18" high="19" type="uint"/>
++ <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
++ <bitfield name="SUPERTHREADMODE" pos="21" type="boolean"/>
++ <bitfield name="PIXLODENABLE" pos="22" type="boolean"/>
++ </bitset>
++
++ <reg32 offset="0x22c4" name="SP_VS_CTRL_REG0" type="a4xx_sp_vs_fs_ctrl_reg0"/>
++ <reg32 offset="0x22c5" name="SP_VS_CTRL_REG1">
++ <bitfield name="CONSTLENGTH" low="0" high="7" type="uint"/>
++ <bitfield name="INITIALOUTSTANDING" low="24" high="30" type="uint"/>
++ </reg32>
++ <reg32 offset="0x22c6" name="SP_VS_PARAM_REG">
++ <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="PSIZEREGID" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="TOTALVSOUTVAR" low="20" high="31" type="uint"/>
++ </reg32>
++ <array offset="0x22c7" name="SP_VS_OUT" stride="1" length="16">
++ <reg32 offset="0x0" name="REG">
++ <bitfield name="A_REGID" low="0" high="8" type="a3xx_regid"/>
++ <bitfield name="A_COMPMASK" low="9" high="12" type="hex"/>
++ <bitfield name="B_REGID" low="16" high="24" type="a3xx_regid"/>
++ <bitfield name="B_COMPMASK" low="25" high="28" type="hex"/>
++ </reg32>
++ </array>
++ <array offset="0x22d8" name="SP_VS_VPC_DST" stride="1" length="8">
++ <reg32 offset="0x0" name="REG">
++ <doc>
++ These seem to be offsets for storage of the varyings.
++ Always seems to start from 8, possibly loc 0 and 4
++ are for gl_Position and gl_PointSize?
++ </doc>
++ <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
++ <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
++ <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
++ <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
++ </reg32>
++ </array>
++
++ <reg32 offset="0x22e0" name="SP_VS_OBJ_OFFSET_REG">
++ <!-- always 00000000: -->
++ <doc>
++ From register spec:
++ SP_FS_OBJ_OFFSET_REG.CONSTOBJECTSTARTOFFSET [16:24]: Constant object
++ start offset in on chip RAM,
++ 128bit aligned
++ </doc>
++ <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
++ <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x22e1" name="SP_VS_OBJ_START"/>
++ <reg32 offset="0x22e2" name="SP_VS_PVT_MEM_PARAM"/>
++ <reg32 offset="0x22e3" name="SP_VS_PVT_MEM_ADDR"/>
++ <reg32 offset="0x22e5" name="SP_VS_LENGTH_REG" type="uint"/>
++ <reg32 offset="0x22e8" name="SP_FS_CTRL_REG0" type="a4xx_sp_vs_fs_ctrl_reg0"/>
++ <reg32 offset="0x22e9" name="SP_FS_CTRL_REG1">
++ <bitfield name="CONSTLENGTH" low="0" high="7" type="uint"/>
++ <bitfield name="FACENESS" pos="19" type="boolean"/>
++ <bitfield name="VARYING" pos="20" type="boolean"/>
++ <bitfield name="FRAGCOORD" pos="21" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x22ea" name="SP_FS_OBJ_OFFSET_REG">
++ <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
++ <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x22eb" name="SP_FS_OBJ_START"/>
++ <reg32 offset="0x22ec" name="SP_FS_PVT_MEM_PARAM"/>
++ <reg32 offset="0x22ed" name="SP_FS_PVT_MEM_ADDR"/>
++ <reg32 offset="0x22ef" name="SP_FS_LENGTH_REG" type="uint"/>
++ <reg32 offset="0x22f0" name="SP_FS_OUTPUT_REG">
++ <bitfield name="MRT" low="0" high="3" type="uint"/>
++ <bitfield name="DEPTH_ENABLE" pos="7" type="boolean"/>
++ <!-- TODO double check.. for now assume same as a3xx -->
++ <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="SAMPLEMASK_REGID" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <array offset="0x22f1" name="SP_FS_MRT" stride="1" length="8">
++ <reg32 offset="0x0" name="REG">
++ <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
++ <bitfield name="COLOR_SINT" pos="10" type="boolean"/>
++ <bitfield name="COLOR_UINT" pos="11" type="boolean"/>
++ <bitfield name="MRTFORMAT" low="12" high="17" type="a4xx_color_fmt"/>
++ <bitfield name="COLOR_SRGB" pos="18" type="boolean"/>
++ </reg32>
++ </array>
++ <reg32 offset="0x2300" name="SP_CS_CTRL_REG0" type="a4xx_sp_vs_fs_ctrl_reg0"/>
++ <reg32 offset="0x2301" name="SP_CS_OBJ_OFFSET_REG"/>
++ <reg32 offset="0x2302" name="SP_CS_OBJ_START"/>
++ <reg32 offset="0x2303" name="SP_CS_PVT_MEM_PARAM"/>
++ <reg32 offset="0x2304" name="SP_CS_PVT_MEM_ADDR"/>
++ <reg32 offset="0x2305" name="SP_CS_PVT_MEM_SIZE"/>
++ <reg32 offset="0x2306" name="SP_CS_LENGTH_REG" type="uint"/>
++ <reg32 offset="0x230d" name="SP_HS_OBJ_OFFSET_REG">
++ <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
++ <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x230e" name="SP_HS_OBJ_START"/>
++ <reg32 offset="0x230f" name="SP_HS_PVT_MEM_PARAM"/>
++ <reg32 offset="0x2310" name="SP_HS_PVT_MEM_ADDR"/>
++ <reg32 offset="0x2312" name="SP_HS_LENGTH_REG" type="uint"/>
++
++ <reg32 offset="0x231a" name="SP_DS_PARAM_REG">
++ <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="TOTALGSOUTVAR" low="20" high="31" type="uint"/>
++ </reg32>
++ <array offset="0x231b" name="SP_DS_OUT" stride="1" length="16">
++ <reg32 offset="0x0" name="REG">
++ <bitfield name="A_REGID" low="0" high="8" type="a3xx_regid"/>
++ <bitfield name="A_COMPMASK" low="9" high="12" type="hex"/>
++ <bitfield name="B_REGID" low="16" high="24" type="a3xx_regid"/>
++ <bitfield name="B_COMPMASK" low="25" high="28" type="hex"/>
++ </reg32>
++ </array>
++ <array offset="0x232c" name="SP_DS_VPC_DST" stride="1" length="8">
++ <reg32 offset="0x0" name="REG">
++ <doc>
++ These seem to be offsets for storage of the varyings.
++ Always seems to start from 8, possibly loc 0 and 4
++ are for gl_Position and gl_PointSize?
++ </doc>
++ <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
++ <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
++ <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
++ <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
++ </reg32>
++ </array>
++ <reg32 offset="0x2334" name="SP_DS_OBJ_OFFSET_REG">
++ <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
++ <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2335" name="SP_DS_OBJ_START"/>
++ <reg32 offset="0x2336" name="SP_DS_PVT_MEM_PARAM"/>
++ <reg32 offset="0x2337" name="SP_DS_PVT_MEM_ADDR"/>
++ <reg32 offset="0x2339" name="SP_DS_LENGTH_REG" type="uint"/>
++
++ <reg32 offset="0x2341" name="SP_GS_PARAM_REG">
++ <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="PRIMREGID" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="TOTALGSOUTVAR" low="20" high="31" type="uint"/>
++ </reg32>
++ <array offset="0x2342" name="SP_GS_OUT" stride="1" length="16">
++ <reg32 offset="0x0" name="REG">
++ <bitfield name="A_REGID" low="0" high="8" type="a3xx_regid"/>
++ <bitfield name="A_COMPMASK" low="9" high="12" type="hex"/>
++ <bitfield name="B_REGID" low="16" high="24" type="a3xx_regid"/>
++ <bitfield name="B_COMPMASK" low="25" high="28" type="hex"/>
++ </reg32>
++ </array>
++ <array offset="0x2353" name="SP_GS_VPC_DST" stride="1" length="8">
++ <reg32 offset="0x0" name="REG">
++ <doc>
++ These seem to be offsets for storage of the varyings.
++ Always seems to start from 8, possibly loc 0 and 4
++ are for gl_Position and gl_PointSize?
++ </doc>
++ <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
++ <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
++ <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
++ <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
++ </reg32>
++ </array>
++ <reg32 offset="0x235b" name="SP_GS_OBJ_OFFSET_REG">
++ <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
++ <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x235c" name="SP_GS_OBJ_START"/>
++ <reg32 offset="0x235d" name="SP_GS_PVT_MEM_PARAM"/>
++ <reg32 offset="0x235e" name="SP_GS_PVT_MEM_ADDR"/>
++ <reg32 offset="0x2360" name="SP_GS_LENGTH_REG" type="uint"/>
++
++ <!-- VPC registers -->
++ <reg32 offset="0x0e60" name="VPC_DEBUG_RAM_SEL"/>
++ <reg32 offset="0x0e61" name="VPC_DEBUG_RAM_READ"/>
++ <reg32 offset="0x0e64" name="VPC_DEBUG_ECO_CONTROL"/>
++ <reg32 offset="0x0e65" name="VPC_PERFCTR_VPC_SEL_0" type="a4xx_vpc_perfcounter_select"/>
++ <reg32 offset="0x0e66" name="VPC_PERFCTR_VPC_SEL_1" type="a4xx_vpc_perfcounter_select"/>
++ <reg32 offset="0x0e67" name="VPC_PERFCTR_VPC_SEL_2" type="a4xx_vpc_perfcounter_select"/>
++ <reg32 offset="0x0e68" name="VPC_PERFCTR_VPC_SEL_3" type="a4xx_vpc_perfcounter_select"/>
++ <reg32 offset="0x2140" name="VPC_ATTR">
++ <bitfield name="TOTALATTR" low="0" high="8" type="uint"/>
++ <!-- PSIZE bit set if gl_PointSize written: -->
++ <bitfield name="PSIZE" pos="9" type="boolean"/>
++ <bitfield name="THRDASSIGN" low="12" high="13" type="uint"/>
++ <bitfield name="ENABLE" pos="25" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2141" name="VPC_PACK">
++ <bitfield name="NUMBYPASSVAR" low="0" high="7" type="uint"/>
++ <bitfield name="NUMFPNONPOSVAR" low="8" high="15" type="uint"/>
++ <bitfield name="NUMNONPOSVSVAR" low="16" high="23" type="uint"/>
++ </reg32>
++ <array offset="0x2142" name="VPC_VARYING_INTERP" stride="1" length="8">
++ <reg32 offset="0x0" name="MODE"/>
++ </array>
++ <array offset="0x214a" name="VPC_VARYING_PS_REPL" stride="1" length="8">
++ <reg32 offset="0x0" name="MODE"/>
++ </array>
++
++ <reg32 offset="0x216e" name="VPC_SO_FLUSH_WADDR_3"/>
++
++ <!-- VSC registers -->
++ <reg32 offset="0x0c00" name="VSC_BIN_SIZE">
++ <bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/>
++ <bitfield name="HEIGHT" low="5" high="9" shr="5" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0c01" name="VSC_SIZE_ADDRESS"/>
++ <reg32 offset="0x0c02" name="VSC_SIZE_ADDRESS2"/>
++ <reg32 offset="0x0c03" name="VSC_DEBUG_ECO_CONTROL"/>
++ <array offset="0x0c08" name="VSC_PIPE_CONFIG" stride="1" length="8">
++ <reg32 offset="0x0" name="REG">
++ <doc>
++ Configures the mapping between VSC_PIPE buffer and
++ bin, X/Y specify the bin index in the horiz/vert
++ direction (0,0 is upper left, 0,1 is leftmost bin
++ on second row, and so on). W/H specify the number
++ of bins assigned to this VSC_PIPE in the horiz/vert
++ dimension.
++ </doc>
++ <bitfield name="X" low="0" high="9" type="uint"/>
++ <bitfield name="Y" low="10" high="19" type="uint"/>
++ <bitfield name="W" low="20" high="23" type="uint"/>
++ <bitfield name="H" low="24" high="27" type="uint"/>
++ </reg32>
++ </array>
++ <array offset="0x0c10" name="VSC_PIPE_DATA_ADDRESS" stride="1" length="8">
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++ <array offset="0x0c18" name="VSC_PIPE_DATA_LENGTH" stride="1" length="8">
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++ <reg32 offset="0x0c41" name="VSC_PIPE_PARTIAL_POSN_1"/>
++ <reg32 offset="0x0c50" name="VSC_PERFCTR_VSC_SEL_0" type="a4xx_vsc_perfcounter_select"/>
++ <reg32 offset="0x0c51" name="VSC_PERFCTR_VSC_SEL_1" type="a4xx_vsc_perfcounter_select"/>
++
++ <!-- VFD registers -->
++ <reg32 offset="0x0e40" name="VFD_DEBUG_CONTROL"/>
++ <reg32 offset="0x0e43" name="VFD_PERFCTR_VFD_SEL_0" type="a4xx_vfd_perfcounter_select"/>
++ <reg32 offset="0x0e44" name="VFD_PERFCTR_VFD_SEL_1" type="a4xx_vfd_perfcounter_select"/>
++ <reg32 offset="0x0e45" name="VFD_PERFCTR_VFD_SEL_2" type="a4xx_vfd_perfcounter_select"/>
++ <reg32 offset="0x0e46" name="VFD_PERFCTR_VFD_SEL_3" type="a4xx_vfd_perfcounter_select"/>
++ <reg32 offset="0x0e47" name="VFD_PERFCTR_VFD_SEL_4" type="a4xx_vfd_perfcounter_select"/>
++ <reg32 offset="0x0e48" name="VFD_PERFCTR_VFD_SEL_5" type="a4xx_vfd_perfcounter_select"/>
++ <reg32 offset="0x0e49" name="VFD_PERFCTR_VFD_SEL_6" type="a4xx_vfd_perfcounter_select"/>
++ <reg32 offset="0x0e4a" name="VFD_PERFCTR_VFD_SEL_7" type="a4xx_vfd_perfcounter_select"/>
++ <reg32 offset="0x21d0" name="VGT_CL_INITIATOR"/>
++ <reg32 offset="0x21d9" name="VGT_EVENT_INITIATOR"/>
++ <reg32 offset="0x2200" name="VFD_CONTROL_0">
++ <doc>
++ TOTALATTRTOVS is # of attributes to vertex shader, in register
++ slots (ie. vec4+vec3 -> 7)
++ </doc>
++ <bitfield name="TOTALATTRTOVS" low="0" high="7" type="uint"/>
++ <doc>
++ BYPASSATTROVS seems to count varyings that are just directly
++ assigned from attributes (ie, "vFoo = aFoo;")
++ </doc>
++ <bitfield name="BYPASSATTROVS" low="9" high="16" type="uint"/>
++ <doc>STRMDECINSTRCNT is # of VFD_DECODE_INSTR registers valid</doc>
++ <bitfield name="STRMDECINSTRCNT" low="20" high="25" type="uint"/>
++ <doc>STRMFETCHINSTRCNT is # of VFD_FETCH_INSTR registers valid</doc>
++ <bitfield name="STRMFETCHINSTRCNT" low="26" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2201" name="VFD_CONTROL_1">
++ <doc>MAXSTORAGE could be # of attributes/vbo's</doc>
++ <bitfield name="MAXSTORAGE" low="0" high="15" type="uint"/>
++ <bitfield name="REGID4VTX" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="REGID4INST" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0x2202" name="VFD_CONTROL_2"/>
++ <reg32 offset="0x2203" name="VFD_CONTROL_3">
++ <bitfield name="REGID_VTXCNT" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0x2204" name="VFD_CONTROL_4"/>
++ <reg32 offset="0x2208" name="VFD_INDEX_OFFSET"/>
++ <array offset="0x220a" name="VFD_FETCH" stride="4" length="32">
++ <reg32 offset="0x0" name="INSTR_0">
++ <bitfield name="FETCHSIZE" low="0" high="6" type="uint"/>
++ <bitfield name="BUFSTRIDE" low="7" high="16" type="uint"/>
++ <bitfield name="SWITCHNEXT" pos="19" type="boolean"/>
++ <bitfield name="INSTANCED" pos="20" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x1" name="INSTR_1"/>
++ <reg32 offset="0x2" name="INSTR_2">
++ <bitfield name="SIZE" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="0x3" name="INSTR_3">
++ <!-- might well be bigger.. -->
++ <bitfield name="STEPRATE" low="0" high="8" type="uint"/>
++ </reg32>
++ </array>
++ <array offset="0x228a" name="VFD_DECODE" stride="1" length="32">
++ <reg32 offset="0x0" name="INSTR">
++ <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
++ <!-- not sure if this is a bit flag and another flag above it, or?? -->
++ <bitfield name="CONSTFILL" pos="4" type="boolean"/>
++ <bitfield name="FORMAT" low="6" high="11" type="a4xx_vtx_fmt"/>
++ <bitfield name="REGID" low="12" high="19" type="a3xx_regid"/>
++ <bitfield name="INT" pos="20" type="boolean"/>
++ <doc>SHIFTCNT appears to be size, ie. FLOAT_32_32_32 is 12, and BYTE_8 is 1</doc>
++ <bitfield name="SWAP" low="22" high="23" type="a3xx_color_swap"/>
++ <bitfield name="SHIFTCNT" low="24" high="28" type="uint"/>
++ <bitfield name="LASTCOMPVALID" pos="29" type="boolean"/>
++ <bitfield name="SWITCHNEXT" pos="30" type="boolean"/>
++ </reg32>
++ </array>
++
++ <!-- TPL1 registers -->
++ <reg32 offset="0x0f00" name="TPL1_DEBUG_ECO_CONTROL"/>
++ <!-- always 0000003a: -->
++ <reg32 offset="0x0f03" name="TPL1_TP_MODE_CONTROL"/>
++ <reg32 offset="0x0f04" name="TPL1_PERFCTR_TP_SEL_0" type="a4xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f05" name="TPL1_PERFCTR_TP_SEL_1" type="a4xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f06" name="TPL1_PERFCTR_TP_SEL_2" type="a4xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f07" name="TPL1_PERFCTR_TP_SEL_3" type="a4xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f08" name="TPL1_PERFCTR_TP_SEL_4" type="a4xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f09" name="TPL1_PERFCTR_TP_SEL_5" type="a4xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f0a" name="TPL1_PERFCTR_TP_SEL_6" type="a4xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f0b" name="TPL1_PERFCTR_TP_SEL_7" type="a4xx_tp_perfcounter_select"/>
++ <reg32 offset="0x2380" name="TPL1_TP_TEX_OFFSET"/>
++ <reg32 offset="0x2381" name="TPL1_TP_TEX_COUNT">
++ <bitfield name="VS" low="0" high="7" type="uint"/>
++ <bitfield name="HS" low="8" high="15" type="uint"/>
++ <bitfield name="DS" low="16" high="23" type="uint"/>
++ <bitfield name="GS" low="24" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2384" name="TPL1_TP_VS_BORDER_COLOR_BASE_ADDR"/>
++ <reg32 offset="0x2387" name="TPL1_TP_HS_BORDER_COLOR_BASE_ADDR"/>
++ <reg32 offset="0x238a" name="TPL1_TP_DS_BORDER_COLOR_BASE_ADDR"/>
++ <reg32 offset="0x238d" name="TPL1_TP_GS_BORDER_COLOR_BASE_ADDR"/>
++ <reg32 offset="0x23a0" name="TPL1_TP_FS_TEX_COUNT">
++ <bitfield name="FS" low="0" high="7" type="uint"/>
++ <bitfield name="CS" low="8" high="15" type="uint"/>
++ </reg32>
++ <reg32 offset="0x23a1" name="TPL1_TP_FS_BORDER_COLOR_BASE_ADDR"/>
++ <reg32 offset="0x23a4" name="TPL1_TP_CS_BORDER_COLOR_BASE_ADDR"/>
++ <reg32 offset="0x23a5" name="TPL1_TP_CS_SAMPLER_BASE_ADDR"/>
++ <reg32 offset="0x23a6" name="TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR"/>
++
++ <!-- GRAS registers -->
++ <reg32 offset="0x0c80" name="GRAS_TSE_STATUS"/>
++ <reg32 offset="0x0c81" name="GRAS_DEBUG_ECO_CONTROL"/>
++ <reg32 offset="0x0c88" name="GRAS_PERFCTR_TSE_SEL_0" type="a4xx_gras_tse_perfcounter_select"/>
++ <reg32 offset="0x0c89" name="GRAS_PERFCTR_TSE_SEL_1" type="a4xx_gras_tse_perfcounter_select"/>
++ <reg32 offset="0x0c8a" name="GRAS_PERFCTR_TSE_SEL_2" type="a4xx_gras_tse_perfcounter_select"/>
++ <reg32 offset="0x0c8b" name="GRAS_PERFCTR_TSE_SEL_3" type="a4xx_gras_tse_perfcounter_select"/>
++ <reg32 offset="0x0c8c" name="GRAS_PERFCTR_RAS_SEL_0" type="a4xx_gras_ras_perfcounter_select"/>
++ <reg32 offset="0x0c8d" name="GRAS_PERFCTR_RAS_SEL_1" type="a4xx_gras_ras_perfcounter_select"/>
++ <reg32 offset="0x0c8e" name="GRAS_PERFCTR_RAS_SEL_2" type="a4xx_gras_ras_perfcounter_select"/>
++ <reg32 offset="0x0c8f" name="GRAS_PERFCTR_RAS_SEL_3" type="a4xx_gras_ras_perfcounter_select"/>
++ <reg32 offset="0x2000" name="GRAS_CL_CLIP_CNTL">
++ <bitfield name="CLIP_DISABLE" pos="15" type="boolean"/>
++ <bitfield name="ZNEAR_CLIP_DISABLE" pos="16" type="boolean"/>
++ <bitfield name="ZFAR_CLIP_DISABLE" pos="17" type="boolean"/>
++ <bitfield name="ZERO_GB_SCALE_Z" pos="22" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2003" name="GRAS_CNTL">
++ <bitfield name="IJ_PERSP" pos="0" type="boolean"/>
++ <bitfield name="IJ_LINEAR" pos="1" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2004" name="GRAS_CL_GB_CLIP_ADJ">
++ <bitfield name="HORZ" low="0" high="9" type="uint"/>
++ <bitfield name="VERT" low="10" high="19" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2008" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/>
++ <reg32 offset="0x2009" name="GRAS_CL_VPORT_XSCALE_0" type="float"/>
++ <reg32 offset="0x200a" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/>
++ <reg32 offset="0x200b" name="GRAS_CL_VPORT_YSCALE_0" type="float"/>
++ <reg32 offset="0x200c" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
++ <reg32 offset="0x200d" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
++ <reg32 offset="0x2070" name="GRAS_SU_POINT_MINMAX">
++ <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
++ <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
++ </reg32>
++ <reg32 offset="0x2071" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
++ <reg32 offset="0x2073" name="GRAS_ALPHA_CONTROL">
++ <bitfield name="ALPHA_TEST_ENABLE" pos="2" type="boolean"/>
++ <bitfield name="FORCE_FRAGZ_TO_FS" pos="3" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2074" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
++ <reg32 offset="0x2075" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
++ <reg32 offset="0x2076" name="GRAS_SU_POLY_OFFSET_CLAMP" type="float"/>
++ <reg32 offset="0x2077" name="GRAS_DEPTH_CONTROL">
++ <!-- guestimating that this is GRAS based on addr -->
++ <bitfield name="FORMAT" low="0" high="1" type="a4xx_depth_format"/>
++ </reg32>
++ <reg32 offset="0x2078" name="GRAS_SU_MODE_CONTROL">
++ <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
++ <bitfield name="CULL_BACK" pos="1" type="boolean"/>
++ <bitfield name="FRONT_CW" pos="2" type="boolean"/>
++ <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
++ <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
++ <bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
++ <!-- bit20 set whenever RENDER_MODE = RB_RENDERING_PASS -->
++ <bitfield name="RENDERING_PASS" pos="20" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x207b" name="GRAS_SC_CONTROL">
++ <!-- complete wild-ass-guess for sizes of these bitfields.. -->
++ <bitfield name="RENDER_MODE" low="2" high="3" type="a3xx_render_mode"/>
++ <bitfield name="MSAA_SAMPLES" low="7" high="9" type="uint"/>
++ <bitfield name="MSAA_DISABLE" pos="11" type="boolean"/>
++ <bitfield name="RASTER_MODE" low="12" high="15"/>
++ </reg32>
++ <reg32 offset="0x207c" name="GRAS_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/>
++ <reg32 offset="0x207d" name="GRAS_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/>
++ <reg32 offset="0x209c" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
++ <reg32 offset="0x209d" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
++ <reg32 offset="0x209e" name="GRAS_SC_EXTENT_WINDOW_BR" type="adreno_reg_xy"/>
++ <reg32 offset="0x209f" name="GRAS_SC_EXTENT_WINDOW_TL" type="adreno_reg_xy"/>
++
++ <!-- UCHE registers -->
++ <reg32 offset="0x0e80" name="UCHE_CACHE_MODE_CONTROL"/>
++ <reg32 offset="0x0e83" name="UCHE_TRAP_BASE_LO"/>
++ <reg32 offset="0x0e84" name="UCHE_TRAP_BASE_HI"/>
++ <reg32 offset="0x0e88" name="UCHE_CACHE_STATUS"/>
++ <reg32 offset="0x0e8a" name="UCHE_INVALIDATE0"/>
++ <reg32 offset="0x0e8b" name="UCHE_INVALIDATE1"/>
++ <reg32 offset="0x0e8c" name="UCHE_CACHE_WAYS_VFD"/>
++ <reg32 offset="0x0e8e" name="UCHE_PERFCTR_UCHE_SEL_0" type="a4xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0e8f" name="UCHE_PERFCTR_UCHE_SEL_1" type="a4xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0e90" name="UCHE_PERFCTR_UCHE_SEL_2" type="a4xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0e91" name="UCHE_PERFCTR_UCHE_SEL_3" type="a4xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0e92" name="UCHE_PERFCTR_UCHE_SEL_4" type="a4xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0e93" name="UCHE_PERFCTR_UCHE_SEL_5" type="a4xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0e94" name="UCHE_PERFCTR_UCHE_SEL_6" type="a4xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0e95" name="UCHE_PERFCTR_UCHE_SEL_7" type="a4xx_uche_perfcounter_select"/>
++
++ <!-- HLSQ registers -->
++ <reg32 offset="0x0e00" name="HLSQ_TIMEOUT_THRESHOLD"/>
++ <reg32 offset="0x0e04" name="HLSQ_DEBUG_ECO_CONTROL"/>
++ <!-- always 00000000: -->
++ <reg32 offset="0x0e05" name="HLSQ_MODE_CONTROL"/>
++ <reg32 offset="0x0e0e" name="HLSQ_PERF_PIPE_MASK"/>
++ <reg32 offset="0x0e06" name="HLSQ_PERFCTR_HLSQ_SEL_0" type="a4xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e07" name="HLSQ_PERFCTR_HLSQ_SEL_1" type="a4xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e08" name="HLSQ_PERFCTR_HLSQ_SEL_2" type="a4xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e09" name="HLSQ_PERFCTR_HLSQ_SEL_3" type="a4xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e0a" name="HLSQ_PERFCTR_HLSQ_SEL_4" type="a4xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e0b" name="HLSQ_PERFCTR_HLSQ_SEL_5" type="a4xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e0c" name="HLSQ_PERFCTR_HLSQ_SEL_6" type="a4xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e0d" name="HLSQ_PERFCTR_HLSQ_SEL_7" type="a4xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x23c0" name="HLSQ_CONTROL_0_REG">
++ <!-- I guess same as a3xx, but so far only seen 08000050 -->
++ <bitfield name="FSTHREADSIZE" pos="4" type="a3xx_threadsize"/>
++ <bitfield name="FSSUPERTHREADENABLE" pos="6" type="boolean"/>
++ <bitfield name="SPSHADERRESTART" pos="9" type="boolean"/>
++ <bitfield name="RESERVED2" pos="10" type="boolean"/>
++ <bitfield name="CHUNKDISABLE" pos="26" type="boolean"/>
++ <bitfield name="CONSTMODE" pos="27" type="uint"/>
++ <bitfield name="LAZYUPDATEDISABLE" pos="28" type="boolean"/>
++ <bitfield name="SPCONSTFULLUPDATE" pos="29" type="boolean"/>
++ <bitfield name="TPFULLUPDATE" pos="30" type="boolean"/>
++ <bitfield name="SINGLECONTEXT" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x23c1" name="HLSQ_CONTROL_1_REG">
++ <bitfield name="VSTHREADSIZE" pos="6" type="a3xx_threadsize"/>
++ <bitfield name="VSSUPERTHREADENABLE" pos="8" type="boolean"/>
++ <bitfield name="RESERVED1" pos="9" type="boolean"/>
++ <bitfield name="COORDREGID" low="16" high="23" type="a3xx_regid"/>
++ <!-- set if gl_FragCoord.[zw] used in frag shader: -->
++ <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0x23c2" name="HLSQ_CONTROL_2_REG">
++ <bitfield name="PRIMALLOCTHRESHOLD" low="26" high="31" type="uint"/>
++ <bitfield name="FACEREGID" low="2" high="9" type="a3xx_regid"/>
++ <bitfield name="SAMPLEID_REGID" low="10" high="17" type="a3xx_regid"/>
++ <bitfield name="SAMPLEMASK_REGID" low="18" high="25" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0x23c3" name="HLSQ_CONTROL_3_REG">
++ <!-- register loaded with position (bary.f) -->
++ <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <!-- 0x23c4 3 regids, lowest one goes to 0 when *not* per-sample shading -->
++ <reg32 offset="0x23c4" name="HLSQ_CONTROL_4_REG">
++ <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
++ </reg32>
++
++ <bitset name="a4xx_xs_control_reg" inline="yes">
++ <bitfield name="CONSTLENGTH" low="0" high="7" type="uint"/>
++ <bitfield name="CONSTOBJECTOFFSET" low="8" high="14" type="uint"/>
++ <bitfield name="SSBO_ENABLE" pos="15" type="boolean"/>
++ <bitfield name="ENABLED" pos="16" type="boolean"/>
++ <bitfield name="SHADEROBJOFFSET" low="17" high="23" type="uint"/>
++ <bitfield name="INSTRLENGTH" low="24" high="31" type="uint"/>
++ </bitset>
++ <reg32 offset="0x23c5" name="HLSQ_VS_CONTROL_REG" type="a4xx_xs_control_reg"/>
++ <reg32 offset="0x23c6" name="HLSQ_FS_CONTROL_REG" type="a4xx_xs_control_reg"/>
++ <reg32 offset="0x23c7" name="HLSQ_HS_CONTROL_REG" type="a4xx_xs_control_reg"/>
++ <reg32 offset="0x23c8" name="HLSQ_DS_CONTROL_REG" type="a4xx_xs_control_reg"/>
++ <reg32 offset="0x23c9" name="HLSQ_GS_CONTROL_REG" type="a4xx_xs_control_reg"/>
++ <reg32 offset="0x23ca" name="HLSQ_CS_CONTROL_REG" type="a4xx_xs_control_reg"/>
++ <reg32 offset="0x23cd" name="HLSQ_CL_NDRANGE_0">
++ <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
++ <!-- localsize is value minus one: -->
++ <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
++ <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
++ <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x23ce" name="HLSQ_CL_NDRANGE_1">
++ <bitfield name="SIZE_X" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x23cf" name="HLSQ_CL_NDRANGE_2"/>
++ <reg32 offset="0x23d0" name="HLSQ_CL_NDRANGE_3">
++ <bitfield name="SIZE_Y" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x23d1" name="HLSQ_CL_NDRANGE_4"/>
++ <reg32 offset="0x23d2" name="HLSQ_CL_NDRANGE_5">
++ <bitfield name="SIZE_Z" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x23d3" name="HLSQ_CL_NDRANGE_6"/>
++ <reg32 offset="0x23d4" name="HLSQ_CL_CONTROL_0">
++ <bitfield name="WGIDCONSTID" low="0" high="11" type="a3xx_regid"/>
++ <bitfield name="KERNELDIMCONSTID" low="12" high="23" type="a3xx_regid"/>
++ <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0x23d5" name="HLSQ_CL_CONTROL_1">
++ <!-- GLOBALSIZECONSTID? "kernel size" -->
++ <bitfield name="UNK0CONSTID" low="0" high="11" type="a3xx_regid"/>
++ <bitfield name="WORKGROUPSIZECONSTID" low="12" high="23" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0x23d6" name="HLSQ_CL_KERNEL_CONST">
++ <!-- GLOBALOFFSETCONSTID -->
++ <bitfield name="UNK0CONSTID" low="0" high="11" type="a3xx_regid"/>
++ <bitfield name="NUMWGCONSTID" low="12" high="23" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0x23d7" name="HLSQ_CL_KERNEL_GROUP_X"/>
++ <reg32 offset="0x23d8" name="HLSQ_CL_KERNEL_GROUP_Y"/>
++ <reg32 offset="0x23d9" name="HLSQ_CL_KERNEL_GROUP_Z"/>
++ <reg32 offset="0x23da" name="HLSQ_CL_WG_OFFSET">
++ <!-- WGOFFSETCONSTID -->
++ <bitfield name="UNK0CONSTID" low="0" high="11" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0x23db" name="HLSQ_UPDATE_CONTROL"/>
++
++ <!-- PC registers -->
++ <reg32 offset="0x0d00" name="PC_BINNING_COMMAND">
++ <bitfield name="BINNING_ENABLE" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0d08" name="PC_TESSFACTOR_ADDR"/>
++ <reg32 offset="0x0d0c" name="PC_DRAWCALL_SETUP_OVERRIDE"/>
++ <reg32 offset="0x0d10" name="PC_PERFCTR_PC_SEL_0" type="a4xx_pc_perfcounter_select"/>
++ <reg32 offset="0x0d11" name="PC_PERFCTR_PC_SEL_1" type="a4xx_pc_perfcounter_select"/>
++ <reg32 offset="0x0d12" name="PC_PERFCTR_PC_SEL_2" type="a4xx_pc_perfcounter_select"/>
++ <reg32 offset="0x0d13" name="PC_PERFCTR_PC_SEL_3" type="a4xx_pc_perfcounter_select"/>
++ <reg32 offset="0x0d14" name="PC_PERFCTR_PC_SEL_4" type="a4xx_pc_perfcounter_select"/>
++ <reg32 offset="0x0d15" name="PC_PERFCTR_PC_SEL_5" type="a4xx_pc_perfcounter_select"/>
++ <reg32 offset="0x0d16" name="PC_PERFCTR_PC_SEL_6" type="a4xx_pc_perfcounter_select"/>
++ <reg32 offset="0x0d17" name="PC_PERFCTR_PC_SEL_7" type="a4xx_pc_perfcounter_select"/>
++ <reg32 offset="0x21c0" name="PC_BIN_BASE"/>
++ <reg32 offset="0x21c2" name="PC_VSTREAM_CONTROL">
++ <doc>SIZE is current pipe width * height (in tiles)</doc>
++ <bitfield name="SIZE" low="16" high="21" type="uint"/>
++ <doc>
++ N is some sort of slot # between 0..(SIZE-1). In case
++ multiple tiles use same pipe, each tile gets unique slot #
++ </doc>
++ <bitfield name="N" low="22" high="26" type="uint"/>
++ </reg32>
++ <reg32 offset="0x21c4" name="PC_PRIM_VTX_CNTL">
++ <!-- bit0 set if there is >= 1 varying (actually used by FS) -->
++ <bitfield name="VAROUT" low="0" high="3" type="uint">
++ <doc>in groups of 4x vec4, blob only uses values
++ 0, 1, 2, 4, 6, 8</doc>
++ </bitfield>
++ <bitfield name="PRIMITIVE_RESTART" pos="20" type="boolean"/>
++ <bitfield name="PROVOKING_VTX_LAST" pos="25" type="boolean"/>
++ <!-- PSIZE bit set if gl_PointSize written: -->
++ <bitfield name="PSIZE" pos="26" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x21c5" name="PC_PRIM_VTX_CNTL2">
++ <bitfield name="POLYMODE_FRONT_PTYPE" low="0" high="2" type="adreno_pa_su_sc_draw"/>
++ <bitfield name="POLYMODE_BACK_PTYPE" low="3" high="5" type="adreno_pa_su_sc_draw"/>
++ <bitfield name="POLYMODE_ENABLE" pos="6" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x21c6" name="PC_RESTART_INDEX"/>
++ <reg32 offset="0x21e5" name="PC_GS_PARAM">
++ <bitfield name="MAX_VERTICES" low="0" high="9" type="uint"/><!-- +1, i.e. max is 1024 -->
++ <bitfield name="INVOCATIONS" low="11" high="15" type="uint"/><!-- +1, i.e. max is 32 -->
++ <bitfield name="PRIMTYPE" low="23" high="24" type="adreno_pa_su_sc_draw"/>
++ <bitfield name="LAYER" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x21e7" name="PC_HS_PARAM">
++ <bitfield name="VERTICES_OUT" low="0" high="5" type="uint"/>
++ <bitfield name="SPACING" low="21" high="22" type="a4xx_tess_spacing"/>
++ <bitfield name="CW" pos="23" type="boolean"/>
++ <bitfield name="CONNECTED" pos="24" type="boolean"/>
++ </reg32>
++
++ <!-- VBIF registers -->
++ <reg32 offset="0x3000" name="VBIF_VERSION"/>
++ <reg32 offset="0x3001" name="VBIF_CLKON">
++ <bitfield name="FORCE_ON_TESTBUS" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x301c" name="VBIF_ABIT_SORT"/>
++ <reg32 offset="0x301d" name="VBIF_ABIT_SORT_CONF"/>
++ <reg32 offset="0x302a" name="VBIF_GATE_OFF_WRREQ_EN"/>
++ <reg32 offset="0x302c" name="VBIF_IN_RD_LIM_CONF0"/>
++ <reg32 offset="0x302d" name="VBIF_IN_RD_LIM_CONF1"/>
++ <reg32 offset="0x3030" name="VBIF_IN_WR_LIM_CONF0"/>
++ <reg32 offset="0x3031" name="VBIF_IN_WR_LIM_CONF1"/>
++ <reg32 offset="0x3049" name="VBIF_ROUND_ROBIN_QOS_ARB"/>
++ <reg32 offset="0x30c0" name="VBIF_PERF_CNT_EN0"/>
++ <reg32 offset="0x30c1" name="VBIF_PERF_CNT_EN1"/>
++ <reg32 offset="0x30c2" name="VBIF_PERF_CNT_EN2"/>
++ <reg32 offset="0x30c3" name="VBIF_PERF_CNT_EN3"/>
++ <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0" type="a4xx_vbif_perfcounter_select"/>
++ <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1" type="a4xx_vbif_perfcounter_select"/>
++ <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2" type="a4xx_vbif_perfcounter_select"/>
++ <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3" type="a4xx_vbif_perfcounter_select"/>
++ <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
++ <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
++ <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
++ <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
++ <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
++ <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
++ <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
++ <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
++ <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
++ <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
++ <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
++
++ <!--
++ Unknown registers:
++ (mostly related to DX11 features not used yet, I guess?)
++ -->
++
++ <!-- always 00000006: -->
++ <reg32 offset="0x0cc5" name="UNKNOWN_0CC5"/>
++
++ <!-- always 00000000: -->
++ <reg32 offset="0x0cc6" name="UNKNOWN_0CC6"/>
++
++ <!-- always 00000001: -->
++ <reg32 offset="0x0d01" name="UNKNOWN_0D01"/>
++
++ <!-- always 00000000: -->
++ <reg32 offset="0x0e42" name="UNKNOWN_0E42"/>
++
++ <!-- always 00040000: -->
++ <reg32 offset="0x0ec2" name="UNKNOWN_0EC2"/>
++
++ <!-- always 00000000: -->
++ <reg32 offset="0x2001" name="UNKNOWN_2001"/>
++
++ <!-- always 00000000: -->
++ <reg32 offset="0x209b" name="UNKNOWN_209B"/>
++
++ <!-- always 00000000: -->
++ <reg32 offset="0x20ef" name="UNKNOWN_20EF"/>
++
++ <!-- always 00000000: -->
++ <reg32 offset="0x2152" name="UNKNOWN_2152"/>
++
++ <!-- always 00000000: -->
++ <reg32 offset="0x2153" name="UNKNOWN_2153"/>
++
++ <!-- always 00000000: -->
++ <reg32 offset="0x2154" name="UNKNOWN_2154"/>
++
++ <!-- always 00000000: -->
++ <reg32 offset="0x2155" name="UNKNOWN_2155"/>
++
++ <!-- always 00000000: -->
++ <reg32 offset="0x2156" name="UNKNOWN_2156"/>
++
++ <!-- always 00000000: -->
++ <reg32 offset="0x2157" name="UNKNOWN_2157"/>
++
++ <!-- always 0000000b: -->
++ <reg32 offset="0x21c3" name="UNKNOWN_21C3"/>
++
++ <!-- always 00000001: -->
++ <reg32 offset="0x21e6" name="UNKNOWN_21E6"/>
++
++ <!-- always 00000000: -->
++ <reg32 offset="0x2209" name="UNKNOWN_2209"/>
++
++ <!-- always 00000000: -->
++ <reg32 offset="0x22d7" name="UNKNOWN_22D7"/>
++
++ <!-- always 00fcfc00: -->
++ <reg32 offset="0x2352" name="UNKNOWN_2352"/>
++
++</domain>
++
++
++<domain name="A4XX_TEX_SAMP" width="32">
++ <doc>Texture sampler dwords</doc>
++ <enum name="a4xx_tex_filter">
++ <value name="A4XX_TEX_NEAREST" value="0"/>
++ <value name="A4XX_TEX_LINEAR" value="1"/>
++ <value name="A4XX_TEX_ANISO" value="2"/>
++ </enum>
++ <enum name="a4xx_tex_clamp">
++ <value name="A4XX_TEX_REPEAT" value="0"/>
++ <value name="A4XX_TEX_CLAMP_TO_EDGE" value="1"/>
++ <value name="A4XX_TEX_MIRROR_REPEAT" value="2"/>
++ <value name="A4XX_TEX_CLAMP_TO_BORDER" value="3"/>
++ <value name="A4XX_TEX_MIRROR_CLAMP" value="4"/>
++ </enum>
++ <enum name="a4xx_tex_aniso">
++ <value name="A4XX_TEX_ANISO_1" value="0"/>
++ <value name="A4XX_TEX_ANISO_2" value="1"/>
++ <value name="A4XX_TEX_ANISO_4" value="2"/>
++ <value name="A4XX_TEX_ANISO_8" value="3"/>
++ <value name="A4XX_TEX_ANISO_16" value="4"/>
++ </enum>
++ <reg32 offset="0" name="0">
++ <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
++ <bitfield name="XY_MAG" low="1" high="2" type="a4xx_tex_filter"/>
++ <bitfield name="XY_MIN" low="3" high="4" type="a4xx_tex_filter"/>
++ <bitfield name="WRAP_S" low="5" high="7" type="a4xx_tex_clamp"/>
++ <bitfield name="WRAP_T" low="8" high="10" type="a4xx_tex_clamp"/>
++ <bitfield name="WRAP_R" low="11" high="13" type="a4xx_tex_clamp"/>
++ <bitfield name="ANISO" low="14" high="16" type="a4xx_tex_aniso"/>
++ <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
++ <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
++ <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
++ <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
++ <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
++ <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
++ </reg32>
++</domain>
++
++<domain name="A4XX_TEX_CONST" width="32">
++ <doc>Texture constant dwords</doc>
++ <enum name="a4xx_tex_swiz">
++ <!-- same as a2xx? -->
++ <value name="A4XX_TEX_X" value="0"/>
++ <value name="A4XX_TEX_Y" value="1"/>
++ <value name="A4XX_TEX_Z" value="2"/>
++ <value name="A4XX_TEX_W" value="3"/>
++ <value name="A4XX_TEX_ZERO" value="4"/>
++ <value name="A4XX_TEX_ONE" value="5"/>
++ </enum>
++ <enum name="a4xx_tex_type">
++ <value name="A4XX_TEX_1D" value="0"/>
++ <value name="A4XX_TEX_2D" value="1"/>
++ <value name="A4XX_TEX_CUBE" value="2"/>
++ <value name="A4XX_TEX_3D" value="3"/>
++ <value name="A4XX_TEX_BUFFER" value="4"/>
++ </enum>
++ <reg32 offset="0" name="0">
++ <bitfield name="TILED" pos="0" type="boolean"/>
++ <bitfield name="SRGB" pos="2" type="boolean"/>
++ <bitfield name="SWIZ_X" low="4" high="6" type="a4xx_tex_swiz"/>
++ <bitfield name="SWIZ_Y" low="7" high="9" type="a4xx_tex_swiz"/>
++ <bitfield name="SWIZ_Z" low="10" high="12" type="a4xx_tex_swiz"/>
++ <bitfield name="SWIZ_W" low="13" high="15" type="a4xx_tex_swiz"/>
++ <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
++ <bitfield name="FMT" low="22" high="28" type="a4xx_tex_fmt"/>
++ <bitfield name="TYPE" low="29" high="31" type="a4xx_tex_type"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="HEIGHT" low="0" high="14" type="uint"/>
++ <bitfield name="WIDTH" low="15" high="29" type="uint"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <!-- minimum pitch (for mipmap levels): log2(pitchalign / 32) -->
++ <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
++ <bitfield name="BUFFER" pos="6" type="boolean"/>
++ <doc>Pitch in bytes (so actually stride)</doc>
++ <bitfield name="PITCH" low="9" high="29" type="uint"/>
++ <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="LAYERSZ" low="0" high="13" shr="12" type="uint"/>
++ <bitfield name="DEPTH" low="18" high="30" type="uint"/>
++ </reg32>
++ <reg32 offset="4" name="4">
++ <!--
++ like a3xx we seem to have two LAYERSZ's.. although this one
++ seems too small to be useful, and when it overflows blob just
++ sets it to zero..
++ -->
++ <bitfield name="LAYERSZ" low="0" high="3" shr="12" type="uint"/>
++ <bitfield name="BASE" low="5" high="31" shr="5"/>
++ </reg32>
++ <reg32 offset="5" name="5"/>
++ <reg32 offset="6" name="6"/>
++ <reg32 offset="7" name="7"/>
++</domain>
++
++<domain name="A4XX_SSBO_0" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="BASE" low="5" high="31" shr="5"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <doc>Pitch in bytes (so actually stride)</doc>
++ <bitfield name="PITCH" low="0" high="21" type="uint"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="ARRAY_PITCH" low="12" high="25" shr="12" type="uint"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <!-- bytes per pixel: -->
++ <bitfield name="CPP" low="0" high="5" type="uint"/>
++ </reg32>
++</domain>
++
++<domain name="A4XX_SSBO_1" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="CPP" low="0" high="4" type="uint"/>
++ <bitfield name="FMT" low="8" high="15" type="a4xx_color_fmt"/>
++ <bitfield name="WIDTH" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="HEIGHT" low="0" high="15" type="uint"/>
++ <bitfield name="DEPTH" low="16" high="31" type="uint"/>
++ </reg32>
++</domain>
++
++</database>
+diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml b/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml
+new file mode 100644
+index 0000000000000..218ec8bb966e3
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml
+@@ -0,0 +1,400 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++
++<enum name="chip" bare="yes">
++ <value name="A2XX" value="2"/>
++ <value name="A3XX" value="3"/>
++ <value name="A4XX" value="4"/>
++ <value name="A5XX" value="5"/>
++ <value name="A6XX" value="6"/>
++ <value name="A7XX" value="7"/>
++</enum>
++
++<enum name="adreno_pa_su_sc_draw">
++ <value name="PC_DRAW_POINTS" value="0"/>
++ <value name="PC_DRAW_LINES" value="1"/>
++ <value name="PC_DRAW_TRIANGLES" value="2"/>
++</enum>
++
++<enum name="adreno_compare_func">
++ <value name="FUNC_NEVER" value="0"/>
++ <value name="FUNC_LESS" value="1"/>
++ <value name="FUNC_EQUAL" value="2"/>
++ <value name="FUNC_LEQUAL" value="3"/>
++ <value name="FUNC_GREATER" value="4"/>
++ <value name="FUNC_NOTEQUAL" value="5"/>
++ <value name="FUNC_GEQUAL" value="6"/>
++ <value name="FUNC_ALWAYS" value="7"/>
++</enum>
++
++<enum name="adreno_stencil_op">
++ <value name="STENCIL_KEEP" value="0"/>
++ <value name="STENCIL_ZERO" value="1"/>
++ <value name="STENCIL_REPLACE" value="2"/>
++ <value name="STENCIL_INCR_CLAMP" value="3"/>
++ <value name="STENCIL_DECR_CLAMP" value="4"/>
++ <value name="STENCIL_INVERT" value="5"/>
++ <value name="STENCIL_INCR_WRAP" value="6"/>
++ <value name="STENCIL_DECR_WRAP" value="7"/>
++</enum>
++
++<enum name="adreno_rb_blend_factor">
++ <value name="FACTOR_ZERO" value="0"/>
++ <value name="FACTOR_ONE" value="1"/>
++ <value name="FACTOR_SRC_COLOR" value="4"/>
++ <value name="FACTOR_ONE_MINUS_SRC_COLOR" value="5"/>
++ <value name="FACTOR_SRC_ALPHA" value="6"/>
++ <value name="FACTOR_ONE_MINUS_SRC_ALPHA" value="7"/>
++ <value name="FACTOR_DST_COLOR" value="8"/>
++ <value name="FACTOR_ONE_MINUS_DST_COLOR" value="9"/>
++ <value name="FACTOR_DST_ALPHA" value="10"/>
++ <value name="FACTOR_ONE_MINUS_DST_ALPHA" value="11"/>
++ <value name="FACTOR_CONSTANT_COLOR" value="12"/>
++ <value name="FACTOR_ONE_MINUS_CONSTANT_COLOR" value="13"/>
++ <value name="FACTOR_CONSTANT_ALPHA" value="14"/>
++ <value name="FACTOR_ONE_MINUS_CONSTANT_ALPHA" value="15"/>
++ <value name="FACTOR_SRC_ALPHA_SATURATE" value="16"/>
++ <value name="FACTOR_SRC1_COLOR" value="20"/>
++ <value name="FACTOR_ONE_MINUS_SRC1_COLOR" value="21"/>
++ <value name="FACTOR_SRC1_ALPHA" value="22"/>
++ <value name="FACTOR_ONE_MINUS_SRC1_ALPHA" value="23"/>
++</enum>
++
++<bitset name="adreno_rb_stencilrefmask" inline="yes">
++ <bitfield name="STENCILREF" low="0" high="7" type="hex"/>
++ <bitfield name="STENCILMASK" low="8" high="15" type="hex"/>
++ <bitfield name="STENCILWRITEMASK" low="16" high="23" type="hex"/>
++</bitset>
++
++<enum name="adreno_rb_surface_endian">
++ <value name="ENDIAN_NONE" value="0"/>
++ <value name="ENDIAN_8IN16" value="1"/>
++ <value name="ENDIAN_8IN32" value="2"/>
++ <value name="ENDIAN_16IN32" value="3"/>
++ <value name="ENDIAN_8IN64" value="4"/>
++ <value name="ENDIAN_8IN128" value="5"/>
++</enum>
++
++<enum name="adreno_rb_dither_mode">
++ <value name="DITHER_DISABLE" value="0"/>
++ <value name="DITHER_ALWAYS" value="1"/>
++ <value name="DITHER_IF_ALPHA_OFF" value="2"/>
++</enum>
++
++<enum name="adreno_rb_depth_format">
++ <value name="DEPTHX_16" value="0"/>
++ <value name="DEPTHX_24_8" value="1"/>
++ <value name="DEPTHX_32" value="2"/>
++</enum>
++
++<enum name="adreno_rb_copy_control_mode">
++ <value name="RB_COPY_RESOLVE" value="1"/>
++ <value name="RB_COPY_CLEAR" value="2"/>
++ <value name="RB_COPY_DEPTH_STENCIL" value="5"/> <!-- not sure if this is part of MODE or another bitfield?? -->
++</enum>
++
++<bitset name="adreno_reg_xy" inline="yes">
++ <bitfield name="WINDOW_OFFSET_DISABLE" pos="31" type="boolean"/>
++ <bitfield name="X" low="0" high="14" type="uint"/>
++ <bitfield name="Y" low="16" high="30" type="uint"/>
++</bitset>
++
++<bitset name="adreno_cp_protect" inline="yes">
++ <bitfield name="BASE_ADDR" low="0" high="16"/>
++ <bitfield name="MASK_LEN" low="24" high="28"/>
++ <bitfield name="TRAP_WRITE" pos="29"/>
++ <bitfield name="TRAP_READ" pos="30"/>
++</bitset>
++
++<domain name="AXXX" width="32">
++ <brief>Registers in common between a2xx and a3xx</brief>
++
++ <reg32 offset="0x01c0" name="CP_RB_BASE"/>
++ <reg32 offset="0x01c1" name="CP_RB_CNTL">
++ <bitfield name="BUFSZ" low="0" high="5"/>
++ <bitfield name="BLKSZ" low="8" high="13"/>
++ <bitfield name="BUF_SWAP" low="16" high="17"/>
++ <bitfield name="POLL_EN" pos="20" type="boolean"/>
++ <bitfield name="NO_UPDATE" pos="27" type="boolean"/>
++ <bitfield name="RPTR_WR_EN" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x01c3" name="CP_RB_RPTR_ADDR">
++ <bitfield name="SWAP" low="0" high="1" type="uint"/>
++ <bitfield name="ADDR" low="2" high="31" shr="2"/>
++ </reg32>
++ <reg32 offset="0x01c4" name="CP_RB_RPTR" type="uint"/>
++ <reg32 offset="0x01c5" name="CP_RB_WPTR" type="uint"/>
++ <reg32 offset="0x01c6" name="CP_RB_WPTR_DELAY"/>
++ <reg32 offset="0x01c7" name="CP_RB_RPTR_WR"/>
++ <reg32 offset="0x01c8" name="CP_RB_WPTR_BASE"/>
++ <reg32 offset="0x01d5" name="CP_QUEUE_THRESHOLDS">
++ <bitfield name="CSQ_IB1_START" low="0" high="3" type="uint"/>
++ <bitfield name="CSQ_IB2_START" low="8" high="11" type="uint"/>
++ <bitfield name="CSQ_ST_START" low="16" high="19" type="uint"/>
++ </reg32>
++ <reg32 offset="0x01d6" name="CP_MEQ_THRESHOLDS">
++ <bitfield name="MEQ_END" low="16" high="20" type="uint"/>
++ <bitfield name="ROQ_END" low="24" high="28" type="uint"/>
++ </reg32>
++ <reg32 offset="0x01d7" name="CP_CSQ_AVAIL">
++ <bitfield name="RING" low="0" high="6" type="uint"/>
++ <bitfield name="IB1" low="8" high="14" type="uint"/>
++ <bitfield name="IB2" low="16" high="22" type="uint"/>
++ </reg32>
++ <reg32 offset="0x01d8" name="CP_STQ_AVAIL">
++ <bitfield name="ST" low="0" high="6" type="uint"/>
++ </reg32>
++ <reg32 offset="0x01d9" name="CP_MEQ_AVAIL">
++ <bitfield name="MEQ" low="0" high="4" type="uint"/>
++ </reg32>
++ <reg32 offset="0x01dc" name="SCRATCH_UMSK">
++ <bitfield name="UMSK" low="0" high="7" type="uint"/>
++ <bitfield name="SWAP" low="16" high="17" type="uint"/>
++ </reg32>
++ <reg32 offset="0x01dd" name="SCRATCH_ADDR"/>
++ <reg32 offset="0x01ea" name="CP_ME_RDADDR"/>
++
++ <reg32 offset="0x01ec" name="CP_STATE_DEBUG_INDEX"/>
++ <reg32 offset="0x01ed" name="CP_STATE_DEBUG_DATA"/>
++ <reg32 offset="0x01f2" name="CP_INT_CNTL">
++ <bitfield name="SW_INT_MASK" pos="19" type="boolean"/>
++ <bitfield name="T0_PACKET_IN_IB_MASK" pos="23" type="boolean"/>
++ <bitfield name="OPCODE_ERROR_MASK" pos="24" type="boolean"/>
++ <bitfield name="PROTECTED_MODE_ERROR_MASK" pos="25" type="boolean"/>
++ <bitfield name="RESERVED_BIT_ERROR_MASK" pos="26" type="boolean"/>
++ <bitfield name="IB_ERROR_MASK" pos="27" type="boolean"/>
++ <bitfield name="IB2_INT_MASK" pos="29" type="boolean"/>
++ <bitfield name="IB1_INT_MASK" pos="30" type="boolean"/>
++ <bitfield name="RB_INT_MASK" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x01f3" name="CP_INT_STATUS"/>
++ <reg32 offset="0x01f4" name="CP_INT_ACK"/>
++ <reg32 offset="0x01f6" name="CP_ME_CNTL">
++ <bitfield name="BUSY" pos="29" type="boolean"/>
++ <bitfield name="HALT" pos="28" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x01f7" name="CP_ME_STATUS"/>
++ <reg32 offset="0x01f8" name="CP_ME_RAM_WADDR"/>
++ <reg32 offset="0x01f9" name="CP_ME_RAM_RADDR"/>
++ <reg32 offset="0x01fa" name="CP_ME_RAM_DATA"/>
++ <reg32 offset="0x01fc" name="CP_DEBUG">
++ <bitfield name="PREDICATE_DISABLE" pos="23" type="boolean"/>
++ <bitfield name="PROG_END_PTR_ENABLE" pos="24" type="boolean"/>
++ <bitfield name="MIU_128BIT_WRITE_ENABLE" pos="25" type="boolean"/>
++ <bitfield name="PREFETCH_PASS_NOPS" pos="26" type="boolean"/>
++ <bitfield name="DYNAMIC_CLK_DISABLE" pos="27" type="boolean"/>
++ <bitfield name="PREFETCH_MATCH_DISABLE" pos="28" type="boolean"/>
++ <bitfield name="SIMPLE_ME_FLOW_CONTROL" pos="30" type="boolean"/>
++ <bitfield name="MIU_WRITE_PACK_DISABLE" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x01fd" name="CP_CSQ_RB_STAT">
++ <bitfield name="RPTR" low="0" high="6" type="uint"/>
++ <bitfield name="WPTR" low="16" high="22" type="uint"/>
++ </reg32>
++ <reg32 offset="0x01fe" name="CP_CSQ_IB1_STAT">
++ <bitfield name="RPTR" low="0" high="6" type="uint"/>
++ <bitfield name="WPTR" low="16" high="22" type="uint"/>
++ </reg32>
++ <reg32 offset="0x01ff" name="CP_CSQ_IB2_STAT">
++ <bitfield name="RPTR" low="0" high="6" type="uint"/>
++ <bitfield name="WPTR" low="16" high="22" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x0440" name="CP_NON_PREFETCH_CNTRS"/>
++ <reg32 offset="0x0443" name="CP_STQ_ST_STAT"/>
++ <reg32 offset="0x044d" name="CP_ST_BASE"/>
++ <reg32 offset="0x044e" name="CP_ST_BUFSZ"/>
++ <reg32 offset="0x044f" name="CP_MEQ_STAT"/>
++ <reg32 offset="0x0452" name="CP_MIU_TAG_STAT"/>
++ <reg32 offset="0x0454" name="CP_BIN_MASK_LO"/>
++ <reg32 offset="0x0455" name="CP_BIN_MASK_HI"/>
++ <reg32 offset="0x0456" name="CP_BIN_SELECT_LO"/>
++ <reg32 offset="0x0457" name="CP_BIN_SELECT_HI"/>
++ <reg32 offset="0x0458" name="CP_IB1_BASE"/>
++ <reg32 offset="0x0459" name="CP_IB1_BUFSZ"/>
++ <reg32 offset="0x045a" name="CP_IB2_BASE"/>
++ <reg32 offset="0x045b" name="CP_IB2_BUFSZ"/>
++ <reg32 offset="0x047f" name="CP_STAT">
++ <bitfield pos="31" name="CP_BUSY"/>
++ <bitfield pos="30" name="VS_EVENT_FIFO_BUSY"/>
++ <bitfield pos="29" name="PS_EVENT_FIFO_BUSY"/>
++ <bitfield pos="28" name="CF_EVENT_FIFO_BUSY"/>
++ <bitfield pos="27" name="RB_EVENT_FIFO_BUSY"/>
++ <bitfield pos="26" name="ME_BUSY"/>
++ <bitfield pos="25" name="MIU_WR_C_BUSY"/>
++ <bitfield pos="23" name="CP_3D_BUSY"/>
++ <bitfield pos="22" name="CP_NRT_BUSY"/>
++ <bitfield pos="21" name="RBIU_SCRATCH_BUSY"/>
++ <bitfield pos="20" name="RCIU_ME_BUSY"/>
++ <bitfield pos="19" name="RCIU_PFP_BUSY"/>
++ <bitfield pos="18" name="MEQ_RING_BUSY"/>
++ <bitfield pos="17" name="PFP_BUSY"/>
++ <bitfield pos="16" name="ST_QUEUE_BUSY"/>
++ <bitfield pos="13" name="INDIRECT2_QUEUE_BUSY"/>
++ <bitfield pos="12" name="INDIRECTS_QUEUE_BUSY"/>
++ <bitfield pos="11" name="RING_QUEUE_BUSY"/>
++ <bitfield pos="10" name="CSF_BUSY"/>
++ <bitfield pos="9" name="CSF_ST_BUSY"/>
++ <bitfield pos="8" name="EVENT_BUSY"/>
++ <bitfield pos="7" name="CSF_INDIRECT2_BUSY"/>
++ <bitfield pos="6" name="CSF_INDIRECTS_BUSY"/>
++ <bitfield pos="5" name="CSF_RING_BUSY"/>
++ <bitfield pos="4" name="RCIU_BUSY"/>
++ <bitfield pos="3" name="RBIU_BUSY"/>
++ <bitfield pos="2" name="MIU_RD_RETURN_BUSY"/>
++ <bitfield pos="1" name="MIU_RD_REQ_BUSY"/>
++ <bitfield pos="0" name="MIU_WR_BUSY"/>
++ </reg32>
++ <reg32 offset="0x0578" name="CP_SCRATCH_REG0" type="uint"/>
++ <reg32 offset="0x0579" name="CP_SCRATCH_REG1" type="uint"/>
++ <reg32 offset="0x057a" name="CP_SCRATCH_REG2" type="uint"/>
++ <reg32 offset="0x057b" name="CP_SCRATCH_REG3" type="uint"/>
++ <reg32 offset="0x057c" name="CP_SCRATCH_REG4" type="uint"/>
++ <reg32 offset="0x057d" name="CP_SCRATCH_REG5" type="uint"/>
++ <reg32 offset="0x057e" name="CP_SCRATCH_REG6" type="uint"/>
++ <reg32 offset="0x057f" name="CP_SCRATCH_REG7" type="uint"/>
++
++ <reg32 offset="0x0600" name="CP_ME_VS_EVENT_SRC"/>
++ <reg32 offset="0x0601" name="CP_ME_VS_EVENT_ADDR"/>
++ <reg32 offset="0x0602" name="CP_ME_VS_EVENT_DATA"/>
++ <reg32 offset="0x0603" name="CP_ME_VS_EVENT_ADDR_SWM"/>
++ <reg32 offset="0x0604" name="CP_ME_VS_EVENT_DATA_SWM"/>
++ <reg32 offset="0x0605" name="CP_ME_PS_EVENT_SRC"/>
++ <reg32 offset="0x0606" name="CP_ME_PS_EVENT_ADDR"/>
++ <reg32 offset="0x0607" name="CP_ME_PS_EVENT_DATA"/>
++ <reg32 offset="0x0608" name="CP_ME_PS_EVENT_ADDR_SWM"/>
++ <reg32 offset="0x0609" name="CP_ME_PS_EVENT_DATA_SWM"/>
++ <reg32 offset="0x060a" name="CP_ME_CF_EVENT_SRC"/>
++ <reg32 offset="0x060b" name="CP_ME_CF_EVENT_ADDR"/>
++ <reg32 offset="0x060c" name="CP_ME_CF_EVENT_DATA" type="uint"/>
++ <reg32 offset="0x060d" name="CP_ME_NRT_ADDR"/>
++ <reg32 offset="0x060e" name="CP_ME_NRT_DATA"/>
++ <reg32 offset="0x0612" name="CP_ME_VS_FETCH_DONE_SRC"/>
++ <reg32 offset="0x0613" name="CP_ME_VS_FETCH_DONE_ADDR"/>
++ <reg32 offset="0x0614" name="CP_ME_VS_FETCH_DONE_DATA"/>
++
++</domain>
++
++<!--
++ Common between A3xx and A4xx:
++ -->
++
++<enum name="a3xx_rop_code">
++ <value name="ROP_CLEAR" value="0"/>
++ <value name="ROP_NOR" value="1"/>
++ <value name="ROP_AND_INVERTED" value="2"/>
++ <value name="ROP_COPY_INVERTED" value="3"/>
++ <value name="ROP_AND_REVERSE" value="4"/>
++ <value name="ROP_INVERT" value="5"/>
++ <value name="ROP_XOR" value="6"/>
++ <value name="ROP_NAND" value="7"/>
++ <value name="ROP_AND" value="8"/>
++ <value name="ROP_EQUIV" value="9"/>
++ <value name="ROP_NOOP" value="10"/>
++ <value name="ROP_OR_INVERTED" value="11"/>
++ <value name="ROP_COPY" value="12"/>
++ <value name="ROP_OR_REVERSE" value="13"/>
++ <value name="ROP_OR" value="14"/>
++ <value name="ROP_SET" value="15"/>
++</enum>
++
++<enum name="a3xx_render_mode">
++ <value name="RB_RENDERING_PASS" value="0"/>
++ <value name="RB_TILING_PASS" value="1"/>
++ <value name="RB_RESOLVE_PASS" value="2"/>
++ <value name="RB_COMPUTE_PASS" value="3"/>
++</enum>
++
++<enum name="a3xx_msaa_samples">
++ <value name="MSAA_ONE" value="0"/>
++ <value name="MSAA_TWO" value="1"/>
++ <value name="MSAA_FOUR" value="2"/>
++ <value name="MSAA_EIGHT" value="3"/>
++</enum>
++
++<enum name="a3xx_threadmode">
++ <value value="0" name="MULTI"/>
++ <value value="1" name="SINGLE"/>
++</enum>
++
++<enum name="a3xx_instrbuffermode">
++ <!--
++ When shader size goes above ~128 or so, blob switches to '0'
++ and doesn't emit shader in cmdstream. When either is '0' it
++ doesn't get emitted via CP_LOAD_STATE. When only one is
++ '0' the other gets size 256-others_size. So I think that:
++ BUFFER => execute out of state memory
++ CACHE => use available state memory as local cache
++ NOTE that when CACHE mode, also set CACHEINVALID flag!
++
++ TODO check if that 256 size is same for all a3xx
++ -->
++ <value value="0" name="CACHE"/>
++ <value value="1" name="BUFFER"/>
++</enum>
++
++<enum name="a3xx_threadsize">
++ <value value="0" name="TWO_QUADS"/>
++ <value value="1" name="FOUR_QUADS"/>
++</enum>
++
++<enum name="a3xx_color_swap">
++ <value name="WZYX" value="0"/>
++ <value name="WXYZ" value="1"/>
++ <value name="ZYXW" value="2"/>
++ <value name="XYZW" value="3"/>
++</enum>
++
++<enum name="a3xx_rb_blend_opcode">
++ <value name="BLEND_DST_PLUS_SRC" value="0"/>
++ <value name="BLEND_SRC_MINUS_DST" value="1"/>
++ <value name="BLEND_DST_MINUS_SRC" value="2"/>
++ <value name="BLEND_MIN_DST_SRC" value="3"/>
++ <value name="BLEND_MAX_DST_SRC" value="4"/>
++</enum>
++
++<enum name="a4xx_tess_spacing">
++ <value name="EQUAL_SPACING" value="0"/>
++ <value name="ODD_SPACING" value="2"/>
++ <value name="EVEN_SPACING" value="3"/>
++</enum>
++
++<doc>Address mode for a5xx+</doc>
++<enum name="a5xx_address_mode">
++ <value name="ADDR_32B" value="0"/>
++ <value name="ADDR_64B" value="1"/>
++</enum>
++
++<doc>
++ Line mode for a5xx+
++ Note that Bresenham lines are only supported with MSAA disabled.
++</doc>
++<enum name="a5xx_line_mode">
++ <value value="0x0" name="BRESENHAM"/>
++ <value value="0x1" name="RECTANGULAR"/>
++</enum>
++
++<doc>
++ Blob (v615) seem to only use SAM and I wasn't able to coerce
++ it to produce any other command.
++ Probably valid for a4xx+ but not enabled or tested on anything
++ but a6xx.
++</doc>
++<enum name="a6xx_tex_prefetch_cmd">
++ <doc> Produces garbage </doc>
++ <value value="0x0" name="TEX_PREFETCH_UNK0"/>
++ <value value="0x1" name="TEX_PREFETCH_SAM"/>
++ <value value="0x2" name="TEX_PREFETCH_GATHER4R"/>
++ <value value="0x3" name="TEX_PREFETCH_GATHER4G"/>
++ <value value="0x4" name="TEX_PREFETCH_GATHER4B"/>
++ <value value="0x5" name="TEX_PREFETCH_GATHER4A"/>
++ <doc> Causes reads from an invalid address </doc>
++ <value value="0x6" name="TEX_PREFETCH_UNK6"/>
++ <doc> Results in color being zero </doc>
++ <value value="0x7" name="TEX_PREFETCH_UNK7"/>
++</enum>
++
++</database>
+diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml
+new file mode 100644
+index 0000000000000..cab01af55d222
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml
+@@ -0,0 +1,2268 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++<import file="adreno/adreno_common.xml"/>
++
++<enum name="vgt_event_type" varset="chip">
++ <value name="VS_DEALLOC" value="0"/>
++ <value name="PS_DEALLOC" value="1" variants="A2XX-A6XX"/>
++ <value name="VS_DONE_TS" value="2"/>
++ <value name="PS_DONE_TS" value="3"/>
++ <doc>
++ Flushes dirty data from UCHE, and also writes a GPU timestamp to
++ the address if one is provided.
++ </doc>
++ <value name="CACHE_FLUSH_TS" value="4"/>
++ <value name="CONTEXT_DONE" value="5"/>
++ <value name="CACHE_FLUSH" value="6" variants="A2XX-A4XX"/>
++ <value name="VIZQUERY_START" value="7" variants="A2XX"/>
++ <value name="HLSQ_FLUSH" value="7" variants="A3XX-A4XX"/>
++ <value name="VIZQUERY_END" value="8" variants="A2XX"/>
++ <value name="SC_WAIT_WC" value="9" variants="A2XX"/>
++ <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/>
++ <value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX"/>
++ <value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX"/>
++ <!-- Not sure that these 4 events don't have the same meaning as on A5XX+ -->
++ <value name="RST_PIX_CNT" value="13" variants="A2XX-A4XX"/>
++ <value name="RST_VTX_CNT" value="14" variants="A2XX-A4XX"/>
++ <value name="TILE_FLUSH" value="15" variants="A2XX-A4XX"/>
++ <value name="STAT_EVENT" value="16" variants="A2XX-A4XX"/>
++ <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX-A4XX"/>
++ <doc>
++ If A6XX_RB_SAMPLE_COUNT_CONTROL.copy is true, writes OQ Z passed
++ sample counts to RB_SAMPLE_COUNT_ADDR. This writes to main
++ memory, skipping UCHE.
++ </doc>
++ <value name="ZPASS_DONE" value="21"/>
++ <value name="CACHE_FLUSH_AND_INV_EVENT" value="22" variants="A2XX"/>
++
++ <doc>
++ Writes the GPU timestamp to the address that follows, once RB
++ access and flushes are complete.
++ </doc>
++ <value name="RB_DONE_TS" value="22" variants="A3XX-"/>
++
++ <value name="PERFCOUNTER_START" value="23" variants="A2XX-A4XX"/>
++ <value name="PERFCOUNTER_STOP" value="24" variants="A2XX-A4XX"/>
++ <value name="VS_FETCH_DONE" value="27"/>
++ <value name="FACENESS_FLUSH" value="28" variants="A2XX-A4XX"/>
++
++ <!-- a5xx events -->
++ <value name="WT_DONE_TS" value="8" variants="A5XX-"/>
++ <value name="START_FRAGMENT_CTRS" value="13" variants="A5XX-"/>
++ <value name="STOP_FRAGMENT_CTRS" value="14" variants="A5XX-"/>
++ <value name="START_COMPUTE_CTRS" value="15" variants="A5XX-"/>
++ <value name="STOP_COMPUTE_CTRS" value="16" variants="A5XX-"/>
++ <value name="FLUSH_SO_0" value="17" variants="A5XX-"/>
++ <value name="FLUSH_SO_1" value="18" variants="A5XX-"/>
++ <value name="FLUSH_SO_2" value="19" variants="A5XX-"/>
++ <value name="FLUSH_SO_3" value="20" variants="A5XX-"/>
++
++ <doc>
++ Invalidates depth attachment data from the CCU. We assume this
++ happens in the last stage.
++ </doc>
++ <value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX-"/>
++
++ <doc>
++ Invalidates color attachment data from the CCU. We assume this
++ happens in the last stage.
++ </doc>
++ <value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX-"/>
++
++ <doc>
++ Flushes the small cache used by CP_EVENT_WRITE::BLIT (which,
++ along with its registers, would be better named RESOLVE).
++ </doc>
++ <value name="PC_CCU_RESOLVE_TS" value="26" variants="A6XX"/>
++
++ <doc>
++ Flushes depth attachment data from the CCU. We assume this
++ happens in the last stage.
++ </doc>
++ <value name="PC_CCU_FLUSH_DEPTH_TS" value="28" variants="A5XX-"/>
++
++ <doc>
++ Flushes color attachment data from the CCU. We assume this
++ happens in the last stage.
++ </doc>
++ <value name="PC_CCU_FLUSH_COLOR_TS" value="29" variants="A5XX-"/>
++
++ <doc>
++ 2D blit to resolve GMEM to system memory (skipping CCU) at the
++ end of a render pass. Compare to CP_BLIT's BLIT_OP_SCALE for
++ more general blitting.
++ </doc>
++ <value name="BLIT" value="30" variants="A5XX-"/>
++
++ <doc>
++ Clears based on GRAS_LRZ_CNTL configuration, could clear
++ fast-clear buffer or LRZ direction.
++ LRZ direction is stored at lrz_fc_offset + 0x200, has 1 byte which
++ could be expressed by enum:
++ CUR_DIR_DISABLED = 0x0
++ CUR_DIR_GE = 0x1
++ CUR_DIR_LE = 0x2
++ CUR_DIR_UNSET = 0x3
++ Clear of direction means setting the direction to CUR_DIR_UNSET.
++ </doc>
++ <value name="LRZ_CLEAR" value="37" variants="A5XX-"/>
++
++ <value name="LRZ_FLUSH" value="38" variants="A5XX-"/>
++ <value name="BLIT_OP_FILL_2D" value="39" variants="A5XX-"/>
++ <value name="BLIT_OP_COPY_2D" value="40" variants="A5XX-A6XX"/>
++ <value name="UNK_40" value="40" variants="A7XX"/>
++ <value name="BLIT_OP_SCALE_2D" value="42" variants="A5XX-"/>
++ <value name="CONTEXT_DONE_2D" value="43" variants="A5XX-"/>
++ <value name="UNK_2C" value="44" variants="A5XX-"/>
++ <value name="UNK_2D" value="45" variants="A5XX-"/>
++
++ <!-- a6xx events -->
++ <doc>
++ Invalidates UCHE.
++ </doc>
++ <value name="CACHE_INVALIDATE" value="49" variants="A6XX"/>
++
++ <value name="LABEL" value="63" variants="A6XX-"/>
++
++ <!-- note, some of these are the same as a6xx, just named differently -->
++
++ <doc> Doesn't seem to do anything </doc>
++ <value name="DUMMY_EVENT" value="1" variants="A7XX"/>
++ <value name="CCU_INVALIDATE_DEPTH" value="24" variants="A7XX"/>
++ <value name="CCU_INVALIDATE_COLOR" value="25" variants="A7XX"/>
++ <value name="CCU_RESOLVE_CLEAN" value="26" variants="A7XX"/>
++ <value name="CCU_FLUSH_DEPTH" value="28" variants="A7XX"/>
++ <value name="CCU_FLUSH_COLOR" value="29" variants="A7XX"/>
++ <value name="CCU_RESOLVE" value="30" variants="A7XX"/>
++ <value name="CCU_END_RESOLVE_GROUP" value="31" variants="A7XX"/>
++ <value name="CCU_CLEAN_DEPTH" value="32" variants="A7XX"/>
++ <value name="CCU_CLEAN_COLOR" value="33" variants="A7XX"/>
++ <value name="CACHE_RESET" value="48" variants="A7XX"/>
++ <value name="CACHE_CLEAN" value="49" variants="A7XX"/>
++ <!-- TODO: deal with name conflicts with other gens -->
++ <value name="CACHE_FLUSH7" value="50" variants="A7XX"/>
++ <value name="CACHE_INVALIDATE7" value="51" variants="A7XX"/>
++</enum>
++
++<enum name="pc_di_primtype">
++ <value name="DI_PT_NONE" value="0"/>
++ <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: -->
++ <value name="DI_PT_POINTLIST_PSIZE" value="1"/>
++ <value name="DI_PT_LINELIST" value="2"/>
++ <value name="DI_PT_LINESTRIP" value="3"/>
++ <value name="DI_PT_TRILIST" value="4"/>
++ <value name="DI_PT_TRIFAN" value="5"/>
++ <value name="DI_PT_TRISTRIP" value="6"/>
++ <value name="DI_PT_LINELOOP" value="7"/> <!-- a22x, a3xx -->
++ <value name="DI_PT_RECTLIST" value="8"/>
++ <value name="DI_PT_POINTLIST" value="9"/>
++ <value name="DI_PT_LINE_ADJ" value="0xa"/>
++ <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/>
++ <value name="DI_PT_TRI_ADJ" value="0xc"/>
++ <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/>
++
++ <value name="DI_PT_PATCHES0" value="0x1f"/>
++ <value name="DI_PT_PATCHES1" value="0x20"/>
++ <value name="DI_PT_PATCHES2" value="0x21"/>
++ <value name="DI_PT_PATCHES3" value="0x22"/>
++ <value name="DI_PT_PATCHES4" value="0x23"/>
++ <value name="DI_PT_PATCHES5" value="0x24"/>
++ <value name="DI_PT_PATCHES6" value="0x25"/>
++ <value name="DI_PT_PATCHES7" value="0x26"/>
++ <value name="DI_PT_PATCHES8" value="0x27"/>
++ <value name="DI_PT_PATCHES9" value="0x28"/>
++ <value name="DI_PT_PATCHES10" value="0x29"/>
++ <value name="DI_PT_PATCHES11" value="0x2a"/>
++ <value name="DI_PT_PATCHES12" value="0x2b"/>
++ <value name="DI_PT_PATCHES13" value="0x2c"/>
++ <value name="DI_PT_PATCHES14" value="0x2d"/>
++ <value name="DI_PT_PATCHES15" value="0x2e"/>
++ <value name="DI_PT_PATCHES16" value="0x2f"/>
++ <value name="DI_PT_PATCHES17" value="0x30"/>
++ <value name="DI_PT_PATCHES18" value="0x31"/>
++ <value name="DI_PT_PATCHES19" value="0x32"/>
++ <value name="DI_PT_PATCHES20" value="0x33"/>
++ <value name="DI_PT_PATCHES21" value="0x34"/>
++ <value name="DI_PT_PATCHES22" value="0x35"/>
++ <value name="DI_PT_PATCHES23" value="0x36"/>
++ <value name="DI_PT_PATCHES24" value="0x37"/>
++ <value name="DI_PT_PATCHES25" value="0x38"/>
++ <value name="DI_PT_PATCHES26" value="0x39"/>
++ <value name="DI_PT_PATCHES27" value="0x3a"/>
++ <value name="DI_PT_PATCHES28" value="0x3b"/>
++ <value name="DI_PT_PATCHES29" value="0x3c"/>
++ <value name="DI_PT_PATCHES30" value="0x3d"/>
++ <value name="DI_PT_PATCHES31" value="0x3e"/>
++</enum>
++
++<enum name="pc_di_src_sel">
++ <value name="DI_SRC_SEL_DMA" value="0"/>
++ <value name="DI_SRC_SEL_IMMEDIATE" value="1"/>
++ <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/>
++ <value name="DI_SRC_SEL_AUTO_XFB" value="3"/>
++</enum>
++
++<enum name="pc_di_face_cull_sel">
++ <value name="DI_FACE_CULL_NONE" value="0"/>
++ <value name="DI_FACE_CULL_FETCH" value="1"/>
++ <value name="DI_FACE_BACKFACE_CULL" value="2"/>
++ <value name="DI_FACE_FRONTFACE_CULL" value="3"/>
++</enum>
++
++<enum name="pc_di_index_size">
++ <value name="INDEX_SIZE_IGN" value="0"/>
++ <value name="INDEX_SIZE_16_BIT" value="0"/>
++ <value name="INDEX_SIZE_32_BIT" value="1"/>
++ <value name="INDEX_SIZE_8_BIT" value="2"/>
++ <value name="INDEX_SIZE_INVALID"/>
++</enum>
++
++<enum name="pc_di_vis_cull_mode">
++ <value name="IGNORE_VISIBILITY" value="0"/>
++ <value name="USE_VISIBILITY" value="1"/>
++</enum>
++
++<enum name="adreno_pm4_packet_type">
++ <value name="CP_TYPE0_PKT" value="0x00000000"/>
++ <value name="CP_TYPE1_PKT" value="0x40000000"/>
++ <value name="CP_TYPE2_PKT" value="0x80000000"/>
++ <value name="CP_TYPE3_PKT" value="0xc0000000"/>
++ <value name="CP_TYPE4_PKT" value="0x40000000"/>
++ <value name="CP_TYPE7_PKT" value="0x70000000"/>
++</enum>
++
++<!--
++ Note that in some cases, the same packet id is recycled on a later
++ generation, so variants attribute is used to distinguish. They
++ may not be completely accurate, we would probably have to analyze
++ the pfp and me/pm4 firmware to verify the packet is actually
++ handled on a particular generation. But it is at least enough to
++ disambiguate the packet-id's that were re-used for different
++ packets starting with a5xx.
++ -->
++<enum name="adreno_pm4_type3_packets" varset="chip">
++ <doc>initialize CP's micro-engine</doc>
++ <value name="CP_ME_INIT" value="0x48"/>
++ <doc>skip N 32-bit words to get to the next packet</doc>
++ <value name="CP_NOP" value="0x10"/>
++ <doc>
++ indirect buffer dispatch. prefetch parser uses this packet
++ type to determine whether to pre-fetch the IB
++ </doc>
++ <value name="CP_PREEMPT_ENABLE" value="0x1c" variants="A5XX"/>
++ <value name="CP_PREEMPT_TOKEN" value="0x1e" variants="A5XX"/>
++ <value name="CP_INDIRECT_BUFFER" value="0x3f"/>
++ <doc>
++ Takes the same arguments as CP_INDIRECT_BUFFER, but jumps to
++ another buffer at the same level. Must be at the end of IB, and
++ doesn't work with draw state IB's.
++ </doc>
++ <value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" variants="A5XX-"/>
++ <doc>indirect buffer dispatch. same as IB, but init is pipelined</doc>
++ <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/>
++ <doc>
++ Waits for the IDLE state of the engine before further drawing.
++ This is pipelined, so the CP may continue.
++ </doc>
++ <value name="CP_WAIT_FOR_IDLE" value="0x26"/>
++ <doc>wait until a register or memory location is a specific value</doc>
++ <value name="CP_WAIT_REG_MEM" value="0x3c"/>
++ <doc>wait until a register location is equal to a specific value</doc>
++ <value name="CP_WAIT_REG_EQ" value="0x52"/>
++ <doc>wait until a register location is >= a specific value</doc>
++ <value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX-A4XX"/>
++ <doc>wait until a read completes</doc>
++ <value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX-A4XX"/>
++ <doc>wait until all base/size writes from an IB_PFD packet have completed</doc>
++ <!--
++ NOTE: CP_WAIT_IB_PFD_COMPLETE unimplemented at least since a5xx fw, and
++ recycled for something new on a7xx
++ -->
++ <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d" varset="chip" variants="A2XX-A4XX"/>
++ <doc>register read/modify/write</doc>
++ <value name="CP_REG_RMW" value="0x21"/>
++ <doc>Set binning configuration registers</doc>
++ <value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX-A4XX"/>
++ <value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX-"/>
++ <doc>reads register in chip and writes to memory</doc>
++ <value name="CP_REG_TO_MEM" value="0x3e"/>
++ <doc>write N 32-bit words to memory</doc>
++ <value name="CP_MEM_WRITE" value="0x3d"/>
++ <doc>write CP_PROG_COUNTER value to memory</doc>
++ <value name="CP_MEM_WRITE_CNTR" value="0x4f"/>
++ <doc>conditional execution of a sequence of packets</doc>
++ <value name="CP_COND_EXEC" value="0x44"/>
++ <doc>conditional write to memory or register</doc>
++ <value name="CP_COND_WRITE" value="0x45" variants="A2XX-A4XX"/>
++ <value name="CP_COND_WRITE5" value="0x45" variants="A5XX-"/>
++ <doc>generate an event that creates a write to memory when completed</doc>
++ <value name="CP_EVENT_WRITE" value="0x46" variants="A2XX-A6XX"/>
++ <value name="CP_EVENT_WRITE7" value="0x46" variants="A7XX-"/>
++ <doc>generate a VS|PS_done event</doc>
++ <value name="CP_EVENT_WRITE_SHD" value="0x58"/>
++ <doc>generate a cache flush done event</doc>
++ <value name="CP_EVENT_WRITE_CFL" value="0x59"/>
++ <doc>generate a z_pass done event</doc>
++ <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
++ <doc>
++ not sure the real name, but this seems to be what is used for
++ opencl, instead of CP_DRAW_INDX..
++ </doc>
++ <value name="CP_RUN_OPENCL" value="0x31"/>
++ <doc>initiate fetch of index buffer and draw</doc>
++ <value name="CP_DRAW_INDX" value="0x22"/>
++ <doc>draw using supplied indices in packet</doc>
++ <value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX-A4XX"/> <!-- this is something different on a6xx and unused on a5xx -->
++ <doc>initiate fetch of index buffer and binIDs and draw</doc>
++ <value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX-A4XX"/>
++ <doc>initiate fetch of bin IDs and draw using supplied indices</doc>
++ <value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX-A4XX"/>
++ <doc>begin/end initiator for viz query extent processing</doc>
++ <value name="CP_VIZ_QUERY" value="0x23" variants="A2XX-A4XX"/>
++ <doc>fetch state sub-blocks and initiate shader code DMAs</doc>
++ <value name="CP_SET_STATE" value="0x25"/>
++ <doc>load constant into chip and to memory</doc>
++ <value name="CP_SET_CONSTANT" value="0x2d" variants="A2XX"/>
++ <doc>load sequencer instruction memory (pointer-based)</doc>
++ <value name="CP_IM_LOAD" value="0x27"/>
++ <doc>load sequencer instruction memory (code embedded in packet)</doc>
++ <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
++ <doc>load constants from a location in memory</doc>
++ <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/>
++ <doc>selective invalidation of state pointers</doc>
++ <value name="CP_INVALIDATE_STATE" value="0x3b"/>
++ <doc>dynamically changes shader instruction memory partition</doc>
++ <value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX-A4XX"/>
++ <doc>sets the 64-bit BIN_MASK register in the PFP</doc>
++ <value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX-A4XX"/>
++ <doc>sets the 64-bit BIN_SELECT register in the PFP</doc>
++ <value name="CP_SET_BIN_SELECT" value="0x51" variants="A2XX-A4XX"/>
++ <doc>updates the current context, if needed</doc>
++ <value name="CP_CONTEXT_UPDATE" value="0x5e"/>
++ <doc>generate interrupt from the command stream</doc>
++ <value name="CP_INTERRUPT" value="0x40"/>
++ <doc>copy sequencer instruction memory to system memory</doc>
++ <value name="CP_IM_STORE" value="0x2c" variants="A2XX"/>
++
++ <!-- For a20x -->
++<!-- TODO handle variants..
++ <doc>
++ Program an offset that will added to the BIN_BASE value of
++ the 3D_DRAW_INDX_BIN packet
++ </doc>
++ <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/>
++ -->
++
++ <!-- for a22x -->
++ <doc>
++ sets draw initiator flags register in PFP, gets bitwise-ORed into
++ every draw initiator
++ </doc>
++ <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/>
++ <doc>sets the register protection mode</doc>
++ <value name="CP_SET_PROTECTED_MODE" value="0x5f"/>
++
++ <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/>
++
++ <!-- for a3xx -->
++ <doc>load high level sequencer command</doc>
++ <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/>
++ <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX-A5XX"/>
++ <doc>Conditionally load a IB based on a flag, prefetch enabled</doc>
++ <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/>
++ <doc>Conditionally load a IB based on a flag, prefetch disabled</doc>
++ <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/>
++ <doc>Load a buffer with pre-fetch enabled</doc>
++ <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/>
++ <doc>Set bin (?)</doc>
++ <value name="CP_SET_BIN" value="0x4c" variants="A2XX"/>
++
++ <doc>test 2 memory locations to dword values specified</doc>
++ <value name="CP_TEST_TWO_MEMS" value="0x71"/>
++
++ <doc>Write register, ignoring context state for context sensitive registers</doc>
++ <value name="CP_REG_WR_NO_CTXT" value="0x78"/>
++
++ <doc>Record the real-time when this packet is processed by PFP</doc>
++ <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/>
++
++ <!-- Used to switch GPU between secure and non-secure modes -->
++ <value name="CP_SET_SECURE_MODE" value="0x66"/>
++
++ <doc>PFP waits until the FIFO between the PFP and the ME is empty</doc>
++ <value name="CP_WAIT_FOR_ME" value="0x13"/>
++
++ <!-- for a4xx -->
++ <doc>
++ Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple
++ groups of registers. Looks like it can be used to create state
++ objects in GPU memory, and on state change only emit pointer
++ (via CP_SET_DRAW_STATE), which should be nice for reducing CPU
++ overhead:
++
++ (A4x) save PM4 stream pointers to execute upon a visible draw
++ </doc>
++ <value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX-"/>
++ <value name="CP_DRAW_INDX_OFFSET" value="0x38"/>
++ <value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX-"/>
++ <value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX-"/>
++ <value name="CP_DRAW_INDIRECT_MULTI" value="0x2a" variants="A6XX-"/>
++ <value name="CP_DRAW_AUTO" value="0x24"/>
++
++ <doc>
++ Enable or disable predication globally. Also resets the
++ predicate to "passing" and the local bit to enabled when
++ enabling global predication.
++ </doc>
++ <value name="CP_DRAW_PRED_ENABLE_GLOBAL" value="0x19"/>
++
++ <doc>
++ Enable or disable predication locally. Unlike globally enabling
++ predication, this packet doesn't touch any other state.
++ Predication only happens when enabled globally and locally and a
++ predicate has been set. This should be used for internal draws
++ which aren't supposed to use the predication state:
++
++ CP_DRAW_PRED_ENABLE_LOCAL(0)
++ ... do draw...
++ CP_DRAW_PRED_ENABLE_LOCAL(1)
++ </doc>
++ <value name="CP_DRAW_PRED_ENABLE_LOCAL" value="0x1a"/>
++
++ <doc>
++ Latch a draw predicate into the internal register.
++ </doc>
++ <value name="CP_DRAW_PRED_SET" value="0x4e"/>
++
++ <doc>
++ for A4xx
++ Write to register with address that does not fit into type-0 pkt
++ </doc>
++ <value name="CP_WIDE_REG_WRITE" value="0x74" variants="A4XX"/>
++
++ <doc>copy from ME scratch RAM to a register</doc>
++ <value name="CP_SCRATCH_TO_REG" value="0x4d"/>
++
++ <doc>Copy from REG to ME scratch RAM</doc>
++ <value name="CP_REG_TO_SCRATCH" value="0x4a"/>
++
++ <doc>Wait for memory writes to complete</doc>
++ <value name="CP_WAIT_MEM_WRITES" value="0x12"/>
++
++ <doc>Conditional execution based on register comparison</doc>
++ <value name="CP_COND_REG_EXEC" value="0x47"/>
++
++ <doc>Memory to REG copy</doc>
++ <value name="CP_MEM_TO_REG" value="0x42"/>
++
++ <value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX-"/>
++ <value name="CP_EXEC_CS" value="0x33"/>
++
++ <doc>
++ for a5xx
++ </doc>
++ <value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/>
++ <!-- switches SMMU pagetable, used on a5xx+ only -->
++ <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX-"/>
++ <!-- for a6xx -->
++ <doc>Tells CP the current mode of GPU operation</doc>
++ <value name="CP_SET_MARKER" value="0x65" variants="A6XX-"/>
++ <doc>Instruct CP to set a few internal CP registers</doc>
++ <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX-"/>
++ <!--
++ pairs of regid and value.. seems to be used to program some TF
++ related regs:
++ -->
++ <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX-"/>
++ <!-- A5XX Enable yield in RB only -->
++ <value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/>
++ <doc>
++ Enables IB2 skipping. If both GLOBAL and LOCAL are 1 and
++ nothing is left in the visibility stream, then
++ CP_INDIRECT_BUFFER will be skipped, and draws will early return
++ from their IB.
++ </doc>
++ <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX-"/>
++ <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX-"/>
++ <value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX-"/>
++ <value name="CP_WHERE_AM_I" value="0x62" variants="A5XX-"/>
++ <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX-"/>
++ <!-- Enable/Disable/Defer A5x global preemption model -->
++ <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/>
++ <!-- Enable/Disable A5x local preemption model -->
++ <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/>
++ <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx -->
++ <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX-"/>
++ <!-- Inform CP about current render mode (needed for a5xx preemption) -->
++ <value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/>
++ <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/>
++ <!-- check if this works on earlier.. -->
++ <value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX-"/>
++
++ <doc>
++ General purpose 2D blit engine for image transfers and mipmap
++ generation. Reads through UCHE, writes through the CCU cache in
++ the PS stage.
++ </doc>
++ <value name="CP_BLIT" value="0x2c" variants="A5XX-"/>
++
++ <!-- Test specified bit in specified register and set predicate -->
++ <value name="CP_REG_TEST" value="0x39" variants="A5XX-"/>
++
++ <!--
++ Seems to set the mode flags which control which CP_SET_DRAW_STATE
++ packets are executed, based on their ENABLE_MASK values
++
++ CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE
++ packets w/ ENABLE_MASK & 0x6 to execute immediately
++ -->
++ <value name="CP_SET_MODE" value="0x63" variants="A6XX-"/>
++
++ <!--
++ Seems like there are now separate blocks of state for VS vs FS/CS
++ (probably these amounts to geometry vs fragments so that geometry
++ stage of the pipeline for next draw can start while fragment stage
++ of current draw is still running. The format of the payload of the
++ packets is the same, the only difference is the offsets of the regs
++ the firmware code that handles the packet writes.
++
++ Note that for CL, starting with a6xx, the preferred # of local
++ threads is no longer the same as the max, implying that the shader
++ core can now run warps from unrelated shaders (ie.
++ CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs
++ CL_KERNEL_WORK_GROUP_SIZE)
++ -->
++ <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX-"/>
++ <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX-"/>
++ <!--
++ Note: For IBO state (Image/SSBOs) which have shared state across
++ shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for
++ compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are
++ interchangable.
++ -->
++ <value name="CP_LOAD_STATE6" value="0x36" variants="A6XX-"/>
++
++ <!-- internal packets: -->
++ <value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/>
++ <value name="IN_SUBBLK_PREFETCH" value="0x1f" variants="A2XX"/>
++ <value name="IN_INSTR_PREFETCH" value="0x20" variants="A2XX"/>
++ <value name="IN_INSTR_MATCH" value="0x47" variants="A2XX"/>
++ <value name="IN_CONST_PREFETCH" value="0x49" variants="A2XX"/>
++ <value name="IN_INCR_UPDT_STATE" value="0x55" variants="A2XX"/>
++ <value name="IN_INCR_UPDT_CONST" value="0x56" variants="A2XX"/>
++ <value name="IN_INCR_UPDT_INSTR" value="0x57" variants="A2XX"/>
++
++ <!-- internal jumptable entries on a6xx+, possibly a5xx: -->
++
++ <!-- jmptable entry used to handle type4 packet on a5xx+: -->
++ <value name="PKT4" value="0x04" variants="A5XX-"/>
++ <!-- called when ROQ is empty, "returns" from an IB or merged sequence of IBs -->
++ <value name="IN_IB_END" value="0x0a" variants="A6XX-"/>
++ <!-- handles IFPC save/restore -->
++ <value name="IN_GMU_INTERRUPT" value="0x0b" variants="A6XX-"/>
++ <!-- preemption/context-swtich routine -->
++ <value name="IN_PREEMPT" value="0x0f" variants="A6XX-"/>
++
++ <!-- TODO do these exist on A5xx? -->
++ <value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX"/>
++ <value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX-"/>
++ <value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX-"/>
++ <value name="CP_WAIT_MEM_GTE" value="0x14" variants="A6XX"/>
++ <value name="CP_WAIT_TWO_REGS" value="0x70" variants="A6XX"/>
++ <value name="CP_MEMCPY" value="0x75" variants="A6XX-"/>
++ <value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" variants="A6XX-"/>
++ <!-- A750+, set in place of CP_SET_BIN_DATA5_OFFSET but has different values -->
++ <value name="CP_SET_UNK_BIN_DATA" value="0x2d" variants="A7XX-"/>
++ <doc>
++ Write CP_CONTEXT_SWITCH_*_INFO from CP to the following dwords,
++ and forcibly switch to the indicated context.
++ </doc>
++ <value name="CP_CONTEXT_SWITCH" value="0x54" variants="A6XX"/>
++ <!-- Note, kgsl calls this CP_SET_AMBLE: -->
++ <value name="CP_SET_CTXSWITCH_IB" value="0x55" variants="A6XX-"/>
++
++ <!--
++ Seems to always have the payload:
++ 00000002 00008801 00004010
++ or:
++ 00000002 00008801 00004090
++ or:
++ 00000002 00008801 00000010
++ 00000002 00008801 00010010
++ 00000002 00008801 00d64010
++ ...
++ Note set for compute shaders..
++ Is 0x8801 a register offset?
++ This appears to be a special sort of register write packet
++ more or less, but the firmware has some special handling..
++ Seems like it intercepts/modifies certain register offsets,
++ but others are treated like a normal PKT4 reg write. I
++ guess there are some registers that the fw controls certain
++ bits.
++ -->
++ <value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/>
++
++ <doc>
++ These first appear in a650_sqe.bin. They can in theory be used
++ to loop any sequence of IB1 commands, but in practice they are
++ used to loop over bins. There is a fixed-size per-iteration
++ prefix, used to set per-bin state, and then the following IB1
++ commands are executed until CP_END_BIN which are always the same
++ for each iteration and usually contain a list of
++ CP_INDIRECT_BUFFER calls to IB2 commands which setup state and
++ execute restore/draw/save commands. This replaces the previous
++ technique of just repeating the CP_INDIRECT_BUFFER calls and
++ "unrolling" the loop.
++ </doc>
++ <value name="CP_START_BIN" value="0x50" variants="A6XX-"/>
++ <value name="CP_END_BIN" value="0x51" variants="A6XX-"/>
++
++ <doc> Make next dword 1 to disable preemption, 0 to re-enable it. </doc>
++ <value name="CP_PREEMPT_DISABLE" value="0x6c" variants="A6XX"/>
++
++ <value name="CP_WAIT_TIMESTAMP" value="0x14" variants="A7XX-"/>
++ <value name="CP_GLOBAL_TIMESTAMP" value="0x15" variants="A7XX-"/> <!-- payload 1 dword -->
++ <value name="CP_LOCAL_TIMESTAMP" value="0x16" variants="A7XX-"/> <!-- payload 1 dword, follows 0x15 -->
++ <value name="CP_THREAD_CONTROL" value="0x17" variants="A7XX-"/>
++ <!-- payload 4 dwords, last two could be render target addr (one pkt per MRT), possibly used for GMEM save/restore?-->
++ <value name="CP_RESOURCE_LIST" value="0x18" variants="A7XX-"/>
++ <doc> Can clear BV/BR counters, or wait until one catches up to another </doc>
++ <value name="CP_BV_BR_COUNT_OPS" value="0x1b" variants="A7XX-"/>
++ <doc> Clears, adds to local, or adds to global timestamp </doc>
++ <value name="CP_MODIFY_TIMESTAMP" value="0x1c" variants="A7XX-"/>
++ <!-- similar to CP_CONTEXT_REG_BUNCH, but discards first two dwords?? -->
++ <value name="CP_CONTEXT_REG_BUNCH2" value="0x5d" variants="A7XX-"/>
++ <doc>
++ Write to a scratch memory that is read by CP_REG_TEST with
++ SOURCE_SCRATCH_MEM set. It's not the same scratch as scratch registers.
++ However it uses the same memory space.
++ </doc>
++ <value name="CP_MEM_TO_SCRATCH_MEM" value="0x49" variants="A7XX-"/>
++
++ <doc>
++ Executes an array of fixed-size command buffers where each
++ buffer is assumed to have one draw call, skipping buffers with
++ non-visible draw calls.
++ </doc>
++ <value name="CP_FIXED_STRIDE_DRAW_TABLE" value="0x7f" variants="A7XX-"/>
++
++ <doc>Reset various on-chip state used for synchronization</doc>
++ <value name="CP_RESET_CONTEXT_STATE" value="0x1f" variants="A7XX-"/>
++</enum>
++
++
++<domain name="CP_LOAD_STATE" width="32">
++ <doc>Load state, a3xx (and later?)</doc>
++ <enum name="adreno_state_block">
++ <value name="SB_VERT_TEX" value="0"/>
++ <value name="SB_VERT_MIPADDR" value="1"/>
++ <value name="SB_FRAG_TEX" value="2"/>
++ <value name="SB_FRAG_MIPADDR" value="3"/>
++ <value name="SB_VERT_SHADER" value="4"/>
++ <value name="SB_GEOM_SHADER" value="5"/>
++ <value name="SB_FRAG_SHADER" value="6"/>
++ <value name="SB_COMPUTE_SHADER" value="7"/>
++ </enum>
++ <enum name="adreno_state_type">
++ <value name="ST_SHADER" value="0"/>
++ <value name="ST_CONSTANTS" value="1"/>
++ </enum>
++ <enum name="adreno_state_src">
++ <value name="SS_DIRECT" value="0">
++ <doc>inline with the CP_LOAD_STATE packet</doc>
++ </value>
++ <value name="SS_INVALID_ALL_IC" value="2"/>
++ <value name="SS_INVALID_PART_IC" value="3"/>
++ <value name="SS_INDIRECT" value="4">
++ <doc>in buffer pointed to by EXT_SRC_ADDR</doc>
++ </value>
++ <value name="SS_INDIRECT_TCM" value="5"/>
++ <value name="SS_INDIRECT_STM" value="6"/>
++ </enum>
++ <reg32 offset="0" name="0">
++ <bitfield name="DST_OFF" low="0" high="15" type="uint"/>
++ <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/>
++ <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/>
++ <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/>
++ <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
++ </reg32>
++</domain>
++
++<domain name="CP_LOAD_STATE4" width="32" varset="chip">
++ <doc>Load state, a4xx+</doc>
++ <enum name="a4xx_state_block">
++ <!--
++ unknown: 0x7 and 0xf <- seen in compute shader
++
++ STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption?
++ Seen in some GL shaders. Payload is NUM_UNIT dwords, and it contains
++ the gpuaddr of the following shader constants block. DST_OFF seems
++ to specify which shader stage:
++
++ 16 -> vert
++ 36 -> tcs
++ 56 -> tes
++ 76 -> geom
++ 96 -> frag
++
++ Example:
++
++opcode: CP_LOAD_STATE4 (30) (12 dwords)
++ { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 }
++ { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 }
++ { EXT_SRC_ADDR_HI = 0 }
++ 0000: c0264100 00000000 00000000 00000000
++ 0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000
++
++opcode: CP_LOAD_STATE4 (30) (4 dwords)
++ { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
++ { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 }
++ { EXT_SRC_ADDR_HI = 0 }
++ 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
++ 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
++ 0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000
++
++ STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader. NUM_UNITS * 2 dwords.
++
++ -->
++ <value name="SB4_VS_TEX" value="0x0"/>
++ <value name="SB4_HS_TEX" value="0x1"/> <!-- aka. TCS -->
++ <value name="SB4_DS_TEX" value="0x2"/> <!-- aka. TES -->
++ <value name="SB4_GS_TEX" value="0x3"/>
++ <value name="SB4_FS_TEX" value="0x4"/>
++ <value name="SB4_CS_TEX" value="0x5"/>
++ <value name="SB4_VS_SHADER" value="0x8"/>
++ <value name="SB4_HS_SHADER" value="0x9"/>
++ <value name="SB4_DS_SHADER" value="0xa"/>
++ <value name="SB4_GS_SHADER" value="0xb"/>
++ <value name="SB4_FS_SHADER" value="0xc"/>
++ <value name="SB4_CS_SHADER" value="0xd"/>
++ <!--
++ for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each),
++ STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each)
++
++ Compute has it's own dedicated SSBO state, it seems, but the rest
++ of the stages share state
++ -->
++ <value name="SB4_SSBO" value="0xe"/>
++ <value name="SB4_CS_SSBO" value="0xf"/>
++ </enum>
++ <enum name="a4xx_state_type">
++ <value name="ST4_SHADER" value="0"/>
++ <value name="ST4_CONSTANTS" value="1"/>
++ <value name="ST4_UBO" value="2"/>
++ </enum>
++ <enum name="a4xx_state_src">
++ <value name="SS4_DIRECT" value="0"/>
++ <value name="SS4_INDIRECT" value="2"/>
++ </enum>
++ <reg32 offset="0" name="0">
++ <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
++ <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/>
++ <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/>
++ <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/>
++ <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
++ </reg32>
++ <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
++ <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
++ </reg32>
++</domain>
++
++<!-- looks basically same CP_LOAD_STATE4 -->
++<domain name="CP_LOAD_STATE6" width="32" varset="chip">
++ <doc>Load state, a6xx+</doc>
++ <enum name="a6xx_state_block">
++ <value name="SB6_VS_TEX" value="0x0"/>
++ <value name="SB6_HS_TEX" value="0x1"/> <!-- aka. TCS -->
++ <value name="SB6_DS_TEX" value="0x2"/> <!-- aka. TES -->
++ <value name="SB6_GS_TEX" value="0x3"/>
++ <value name="SB6_FS_TEX" value="0x4"/>
++ <value name="SB6_CS_TEX" value="0x5"/>
++ <value name="SB6_VS_SHADER" value="0x8"/>
++ <value name="SB6_HS_SHADER" value="0x9"/>
++ <value name="SB6_DS_SHADER" value="0xa"/>
++ <value name="SB6_GS_SHADER" value="0xb"/>
++ <value name="SB6_FS_SHADER" value="0xc"/>
++ <value name="SB6_CS_SHADER" value="0xd"/>
++ <value name="SB6_IBO" value="0xe"/>
++ <value name="SB6_CS_IBO" value="0xf"/>
++ </enum>
++ <enum name="a6xx_state_type">
++ <value name="ST6_SHADER" value="0"/>
++ <value name="ST6_CONSTANTS" value="1"/>
++ <value name="ST6_UBO" value="2"/>
++ <value name="ST6_IBO" value="3"/>
++ </enum>
++ <enum name="a6xx_state_src">
++ <value name="SS6_DIRECT" value="0"/>
++ <value name="SS6_BINDLESS" value="1"/> <!-- TODO does this exist on a4xx/a5xx? -->
++ <value name="SS6_INDIRECT" value="2"/>
++ <doc>
++ SS6_UBO used by the a6xx vulkan blob with tesselation constants
++ in this case, EXT_SRC_ADDR is (ubo_id shl 16 | offset)
++ to load constants from a UBO loaded with DST_OFF = 14 and offset 0,
++ EXT_SRC_ADDR = 0xe0000
++ (offset is a guess, should be in bytes given that maxUniformBufferRange=64k)
++ </doc>
++ <value name="SS6_UBO" value="3"/>
++ </enum>
++ <reg32 offset="0" name="0">
++ <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
++ <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/>
++ <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/>
++ <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/>
++ <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
++ </reg32>
++ <reg64 offset="1" name="EXT_SRC_ADDR" type="address"/>
++</domain>
++
++<bitset name="vgt_draw_initiator" inline="yes">
++ <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
++ <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
++ <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/>
++ <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/>
++ <bitfield name="NOT_EOP" pos="12" type="boolean"/>
++ <bitfield name="SMALL_INDEX" pos="13" type="boolean"/>
++ <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/>
++ <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/>
++</bitset>
++
++<!-- changed on a4xx: -->
++<enum name="a4xx_index_size">
++ <value name="INDEX4_SIZE_8_BIT" value="0"/>
++ <value name="INDEX4_SIZE_16_BIT" value="1"/>
++ <value name="INDEX4_SIZE_32_BIT" value="2"/>
++</enum>
++
++<enum name="a6xx_patch_type">
++ <value name="TESS_QUADS" value="0"/>
++ <value name="TESS_TRIANGLES" value="1"/>
++ <value name="TESS_ISOLINES" value="2"/>
++</enum>
++
++<bitset name="vgt_draw_initiator_a4xx" inline="yes">
++ <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 -->
++ <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
++ <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
++ <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/>
++ <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/>
++ <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/>
++ <bitfield name="GS_ENABLE" pos="16" type="boolean"/>
++ <bitfield name="TESS_ENABLE" pos="17" type="boolean"/>
++</bitset>
++
++<domain name="CP_DRAW_INDX" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="VIZ_QUERY" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
++ <reg32 offset="2" name="2">
++ <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="INDX_BASE" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="4" name="4">
++ <bitfield name="INDX_SIZE" low="0" high="31"/>
++ </reg32>
++</domain>
++
++<domain name="CP_DRAW_INDX_2" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="VIZ_QUERY" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
++ <reg32 offset="2" name="2">
++ <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
++ </reg32>
++ <!-- followed by NUM_INDICES indices.. -->
++</domain>
++
++<domain name="CP_DRAW_INDX_OFFSET" width="32">
++ <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
++ <reg32 offset="1" name="1">
++ <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="FIRST_INDX" low="0" high="31"/>
++ </reg32>
++
++ <stripe varset="chip" variants="A5XX-">
++ <reg32 offset="4" name="4">
++ <bitfield name="INDX_BASE_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="5" name="5">
++ <bitfield name="INDX_BASE_HI" low="0" high="31"/>
++ </reg32>
++ <reg64 offset="4" name="INDX_BASE" type="address"/>
++ <reg32 offset="6" name="6">
++ <!-- max # of elements in index buffer -->
++ <bitfield name="MAX_INDICES" low="0" high="31"/>
++ </reg32>
++ </stripe>
++
++ <reg32 offset="4" name="4">
++ <bitfield name="INDX_BASE" low="0" high="31" type="address"/>
++ </reg32>
++
++ <reg32 offset="5" name="5">
++ <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
++ </reg32>
++</domain>
++
++<domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
++ <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
++ <stripe varset="chip" variants="A4XX">
++ <reg32 offset="1" name="1">
++ <bitfield name="INDIRECT" low="0" high="31"/>
++ </reg32>
++ </stripe>
++ <stripe varset="chip" variants="A5XX-">
++ <reg32 offset="1" name="1">
++ <bitfield name="INDIRECT_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="INDIRECT_HI" low="0" high="31"/>
++ </reg32>
++ <reg64 offset="1" name="INDIRECT" type="address"/>
++ </stripe>
++</domain>
++
++<domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
++ <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
++ <stripe varset="chip" variants="A4XX">
++ <reg32 offset="1" name="1">
++ <bitfield name="INDX_BASE" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <!-- max # of bytes in index buffer -->
++ <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="INDIRECT" low="0" high="31"/>
++ </reg32>
++ </stripe>
++ <stripe varset="chip" variants="A5XX-">
++ <reg32 offset="1" name="1">
++ <bitfield name="INDX_BASE_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="INDX_BASE_HI" low="0" high="31"/>
++ </reg32>
++ <reg64 offset="1" name="INDX_BASE" type="address"/>
++ <reg32 offset="3" name="3">
++ <!-- max # of elements in index buffer -->
++ <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="4" name="4">
++ <bitfield name="INDIRECT_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="5" name="5">
++ <bitfield name="INDIRECT_HI" low="0" high="31"/>
++ </reg32>
++ <reg64 offset="4" name="INDIRECT" type="address"/>
++ </stripe>
++</domain>
++
++<domain name="CP_DRAW_INDIRECT_MULTI" width="32" varset="chip" prefix="chip" variants="A6XX-">
++ <enum name="a6xx_draw_indirect_opcode">
++ <value name="INDIRECT_OP_NORMAL" value="0x2"/>
++ <value name="INDIRECT_OP_INDEXED" value="0x4"/>
++ <value name="INDIRECT_OP_INDIRECT_COUNT" value="0x6"/>
++ <value name="INDIRECT_OP_INDIRECT_COUNT_INDEXED" value="0x7"/>
++ </enum>
++ <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
++ <reg32 offset="1" name="1">
++ <bitfield name="OPCODE" low="0" high="3" type="a6xx_draw_indirect_opcode" addvariant="yes"/>
++ <doc>
++ DST_OFF same as in CP_LOAD_STATE6 - vec4 VS const at this offset will
++ be updated for each draw to {draw_id, first_vertex, first_instance, 0}
++ value of 0 disables it
++ </doc>
++ <bitfield name="DST_OFF" low="8" high="21" type="hex"/>
++ </reg32>
++ <reg32 offset="2" name="DRAW_COUNT" type="uint"/>
++ <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_NORMAL">
++ <reg64 offset="3" name="INDIRECT" type="address"/>
++ <reg32 offset="5" name="STRIDE" type="uint"/>
++ </stripe>
++ <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDEXED" prefix="INDEXED">
++ <reg64 offset="3" name="INDEX" type="address"/>
++ <reg32 offset="5" name="MAX_INDICES" type="uint"/>
++ <reg64 offset="6" name="INDIRECT" type="address"/>
++ <reg32 offset="8" name="STRIDE" type="uint"/>
++ </stripe>
++ <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT" prefix="INDIRECT">
++ <reg64 offset="3" name="INDIRECT" type="address"/>
++ <reg64 offset="5" name="INDIRECT_COUNT" type="address"/>
++ <reg32 offset="7" name="STRIDE" type="uint"/>
++ </stripe>
++ <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT_INDEXED" prefix="INDIRECT_INDEXED">
++ <reg64 offset="3" name="INDEX" type="address"/>
++ <reg32 offset="5" name="MAX_INDICES" type="uint"/>
++ <reg64 offset="6" name="INDIRECT" type="address"/>
++ <reg64 offset="8" name="INDIRECT_COUNT" type="address"/>
++ <reg32 offset="10" name="STRIDE" type="uint"/>
++ </stripe>
++</domain>
++
++<domain name="CP_DRAW_AUTO" width="32">
++ <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
++ <reg32 offset="1" name="1">
++ <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg64 offset="2" name="NUM_VERTICES_BASE" type="address"/>
++ <reg32 offset="4" name="4">
++ <bitfield name="NUM_VERTICES_OFFSET" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="5" name="5">
++ <bitfield name="STRIDE" low="0" high="31" type="uint"/>
++ </reg32>
++</domain>
++
++<domain name="CP_DRAW_PRED_ENABLE_GLOBAL" width="32" varset="chip">
++ <reg32 offset="0" name="0">
++ <bitfield name="ENABLE" pos="0" type="boolean"/>
++ </reg32>
++</domain>
++
++<domain name="CP_DRAW_PRED_ENABLE_LOCAL" width="32" varset="chip">
++ <reg32 offset="0" name="0">
++ <bitfield name="ENABLE" pos="0" type="boolean"/>
++ </reg32>
++</domain>
++
++<domain name="CP_DRAW_PRED_SET" width="32" varset="chip">
++ <enum name="cp_draw_pred_src">
++ <!--
++ Sources 1-4 seem to be about combining reading
++ SO/primitive queries and setting the predicate, which is
++ a DX11-specific optimization (since in DX11 you can only
++ predicate on the result of queries).
++ -->
++ <value name="PRED_SRC_MEM" value="5">
++ <doc>
++ Read a 64-bit value at the given address and
++ test if it equals/doesn't equal 0.
++ </doc>
++ </value>
++ </enum>
++ <enum name="cp_draw_pred_test">
++ <value name="NE_0_PASS" value="0"/>
++ <value name="EQ_0_PASS" value="1"/>
++ </enum>
++ <reg32 offset="0" name="0">
++ <bitfield name="SRC" low="4" high="7" type="cp_draw_pred_src"/>
++ <bitfield name="TEST" pos="8" type="cp_draw_pred_test"/>
++ </reg32>
++ <reg64 offset="1" name="MEM_ADDR" type="address"/>
++</domain>
++
++<domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-">
++ <array offset="0" stride="3" length="100">
++ <reg32 offset="0" name="0">
++ <bitfield name="COUNT" low="0" high="15" type="uint"/>
++ <bitfield name="DIRTY" pos="16" type="boolean"/>
++ <bitfield name="DISABLE" pos="17" type="boolean"/>
++ <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/>
++ <bitfield name="LOAD_IMMED" pos="19" type="boolean"/>
++ <bitfield name="BINNING" pos="20" varset="chip" variants="A6XX-" type="boolean"/>
++ <bitfield name="GMEM" pos="21" varset="chip" variants="A6XX-" type="boolean"/>
++ <bitfield name="SYSMEM" pos="22" varset="chip" variants="A6XX-" type="boolean"/>
++ <bitfield name="GROUP_ID" low="24" high="28" type="uint"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="ADDR_LO" low="0" high="31" type="hex"/>
++ </reg32>
++ <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
++ <bitfield name="ADDR_HI" low="0" high="31" type="hex"/>
++ </reg32>
++ </array>
++</domain>
++
++<domain name="CP_SET_BIN" width="32">
++ <doc>value at offset 0 always seems to be 0x00000000..</doc>
++ <reg32 offset="0" name="0"/>
++ <reg32 offset="1" name="1">
++ <bitfield name="X1" low="0" high="15" type="uint"/>
++ <bitfield name="Y1" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="X2" low="0" high="15" type="uint"/>
++ <bitfield name="Y2" low="16" high="31" type="uint"/>
++ </reg32>
++</domain>
++
++<domain name="CP_SET_BIN_DATA" width="32">
++ <reg32 offset="0" name="0">
++ <!-- corresponds to VSC_PIPE[n].DATA_ADDR -->
++ <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <!-- seesm to correspond to VSC_SIZE_ADDRESS -->
++ <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/>
++ </reg32>
++</domain>
++
++<domain name="CP_SET_BIN_DATA5" width="32">
++ <reg32 offset="0" name="0">
++ <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
++ <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
++ <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
++ <bitfield name="VSC_N" low="22" high="26" type="uint"/>
++ </reg32>
++ <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
++ <reg32 offset="1" name="1">
++ <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
++ </reg32>
++ <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
++ <reg32 offset="3" name="3">
++ <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="4" name="4">
++ <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
++ </reg32>
++ <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: -->
++ <reg32 offset="5" name="5">
++ <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="6" name="6">
++ <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/>
++ </reg32>
++ <!--
++ a7xx adds a few more addresses to the end of the pkt
++ -->
++ <reg64 offset="7" name="7"/>
++ <reg64 offset="9" name="9"/>
++</domain>
++
++<domain name="CP_SET_BIN_DATA5_OFFSET" width="32">
++ <doc>
++ Like CP_SET_BIN_DATA5, but set the pointers as offsets from the
++ pointers stored in VSC_PIPE_{DATA,DATA2,SIZE}_ADDRESS. Useful
++ for Vulkan where these values aren't known when the command
++ stream is recorded.
++ </doc>
++ <reg32 offset="0" name="0">
++ <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
++ <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
++ <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
++ <bitfield name="VSC_N" low="22" high="26" type="uint"/>
++ </reg32>
++ <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
++ <reg32 offset="1" name="1">
++ <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/>
++ </reg32>
++ <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
++ <reg32 offset="2" name="2">
++ <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/>
++ </reg32>
++ <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS -->
++ <reg32 offset="3" name="3">
++ <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/>
++ </reg32>
++</domain>
++
++<domain name="CP_REG_RMW" width="32">
++ <doc>
++ Modifies DST_REG using two sources that can either be registers
++ or immediates. If SRC1_ADD is set, then do the following:
++
++ $dst = (($dst & $src0) rot $rotate) + $src1
++
++ Otherwise:
++
++ $dst = (($dst & $src0) rot $rotate) | $src1
++
++ Here "rot" means rotate left.
++ </doc>
++ <reg32 offset="0" name="0">
++ <bitfield name="DST_REG" low="0" high="17" type="hex"/>
++ <bitfield name="ROTATE" low="24" high="28" type="uint"/>
++ <bitfield name="SRC1_ADD" pos="29" type="boolean"/>
++ <bitfield name="SRC1_IS_REG" pos="30" type="boolean"/>
++ <bitfield name="SRC0_IS_REG" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="SRC0" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="SRC1" low="0" high="31" type="uint"/>
++ </reg32>
++</domain>
++
++<domain name="CP_REG_TO_MEM" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="REG" low="0" high="17" type="hex"/>
++ <!-- number of registers/dwords copied is max(CNT, 1). -->
++ <bitfield name="CNT" low="18" high="29" type="uint"/>
++ <bitfield name="64B" pos="30" type="boolean"/>
++ <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="DEST" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
++ <bitfield name="DEST_HI" low="0" high="31"/>
++ </reg32>
++</domain>
++
++<domain name="CP_REG_TO_MEM_OFFSET_REG" width="32">
++ <doc>
++ Like CP_REG_TO_MEM, but the memory address to write to can be
++ offsetted using either one or two registers or scratch
++ registers.
++ </doc>
++ <reg32 offset="0" name="0">
++ <bitfield name="REG" low="0" high="17" type="hex"/>
++ <!-- number of registers/dwords copied is max(CNT, 1). -->
++ <bitfield name="CNT" low="18" high="29" type="uint"/>
++ <bitfield name="64B" pos="30" type="boolean"/>
++ <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="DEST" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
++ <bitfield name="DEST_HI" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="OFFSET0" low="0" high="17" type="hex"/>
++ <bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/>
++ </reg32>
++ <!-- followed by an optional identical OFFSET1 dword -->
++</domain>
++
++<domain name="CP_REG_TO_MEM_OFFSET_MEM" width="32">
++ <doc>
++ Like CP_REG_TO_MEM, but the memory address to write to can be
++ offsetted using a DWORD in memory.
++ </doc>
++ <reg32 offset="0" name="0">
++ <bitfield name="REG" low="0" high="17" type="hex"/>
++ <!-- number of registers/dwords copied is max(CNT, 1). -->
++ <bitfield name="CNT" low="18" high="29" type="uint"/>
++ <bitfield name="64B" pos="30" type="boolean"/>
++ <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="DEST" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
++ <bitfield name="DEST_HI" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="OFFSET_LO" low="0" high="31" type="hex"/>
++ </reg32>
++ <reg32 offset="4" name="4">
++ <bitfield name="OFFSET_HI" low="0" high="31" type="hex"/>
++ </reg32>
++</domain>
++
++<domain name="CP_MEM_TO_REG" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="REG" low="0" high="17" type="hex"/>
++ <!-- number of registers/dwords copied is max(CNT, 1). -->
++ <bitfield name="CNT" low="19" high="29" type="uint"/>
++ <!-- shift each DWORD left by 2 while copying -->
++ <bitfield name="SHIFT_BY_2" pos="30" type="boolean"/>
++ <!-- does the same thing as CP_MEM_TO_MEM::UNK31 -->
++ <bitfield name="UNK31" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="SRC" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
++ <bitfield name="SRC_HI" low="0" high="31"/>
++ </reg32>
++</domain>
++
++<domain name="CP_MEM_TO_MEM" width="32">
++ <reg32 offset="0" name="0">
++ <!--
++ not sure how many src operands we have, but the low
++ bits negate the n'th src argument.
++ -->
++ <bitfield name="NEG_A" pos="0" type="boolean"/>
++ <bitfield name="NEG_B" pos="1" type="boolean"/>
++ <bitfield name="NEG_C" pos="2" type="boolean"/>
++
++ <!-- if set treat src/dst as 64bit values -->
++ <bitfield name="DOUBLE" pos="29" type="boolean"/>
++ <!-- execute CP_WAIT_FOR_MEM_WRITES beforehand -->
++ <bitfield name="WAIT_FOR_MEM_WRITES" pos="30" type="boolean"/>
++ <!-- some other kind of wait -->
++ <bitfield name="UNK31" pos="31" type="boolean"/>
++ </reg32>
++ <!--
++ followed by sequence of addresses.. the first is the
++ destination and the rest are N src addresses which are
++ summed (after being negated if NEG_x bit set) allowing
++ to do things like 'result += end - start' (which turns
++ out to be useful for queries and accumulating results
++ across multiple tiles)
++ -->
++</domain>
++
++<domain name="CP_MEMCPY" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="DWORDS" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="SRC_LO" low="0" high="31" type="hex"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="SRC_HI" low="0" high="31" type="hex"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="DST_LO" low="0" high="31" type="hex"/>
++ </reg32>
++ <reg32 offset="4" name="4">
++ <bitfield name="DST_HI" low="0" high="31" type="hex"/>
++ </reg32>
++</domain>
++
++<domain name="CP_REG_TO_SCRATCH" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="REG" low="0" high="17" type="hex"/>
++ <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
++ <!-- number of registers/dwords copied is CNT + 1. -->
++ <bitfield name="CNT" low="24" high="26" type="uint"/>
++ </reg32>
++</domain>
++
++<domain name="CP_SCRATCH_TO_REG" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="REG" low="0" high="17" type="hex"/>
++ <!-- note: CP_MEM_TO_REG always sets this when writing to the register -->
++ <bitfield name="UNK18" pos="18" type="boolean"/>
++ <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
++ <!-- number of registers/dwords copied is CNT + 1. -->
++ <bitfield name="CNT" low="24" high="26" type="uint"/>
++ </reg32>
++</domain>
++
++<domain name="CP_SCRATCH_WRITE" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
++ </reg32>
++ <!-- followed by one or more DWORDs to write to scratch registers -->
++</domain>
++
++<domain name="CP_MEM_WRITE" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="ADDR_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="ADDR_HI" low="0" high="31"/>
++ </reg32>
++ <!-- followed by the DWORDs to write -->
++</domain>
++
++<enum name="cp_cond_function">
++ <value value="0" name="WRITE_ALWAYS"/>
++ <value value="1" name="WRITE_LT"/>
++ <value value="2" name="WRITE_LE"/>
++ <value value="3" name="WRITE_EQ"/>
++ <value value="4" name="WRITE_NE"/>
++ <value value="5" name="WRITE_GE"/>
++ <value value="6" name="WRITE_GT"/>
++</enum>
++
++<domain name="CP_COND_WRITE" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
++ <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
++ <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="REF" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="MASK" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="4" name="4">
++ <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/>
++ </reg32>
++ <reg32 offset="5" name="5">
++ <bitfield name="WRITE_DATA" low="0" high="31"/>
++ </reg32>
++</domain>
++
++<enum name="poll_memory_type">
++ <value value="0" name="POLL_REGISTER"/>
++ <value value="1" name="POLL_MEMORY"/>
++ <value value="2" name="POLL_SCRATCH"/>
++ <value value="3" name="POLL_ON_CHIP" varset="chip" variants="A7XX-"/>
++</enum>
++
++<domain name="CP_COND_WRITE5" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
++ <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
++ <!-- POLL_REGISTER polls a register at POLL_ADDR_LO. -->
++ <bitfield name="POLL" low="4" high="5" type="poll_memory_type"/>
++ <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="REF" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="4" name="4">
++ <bitfield name="MASK" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="5" name="5">
++ <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/>
++ </reg32>
++ <reg32 offset="6" name="6">
++ <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/>
++ </reg32>
++ <reg32 offset="7" name="7">
++ <bitfield name="WRITE_DATA" low="0" high="31"/>
++ </reg32>
++</domain>
++
++<domain name="CP_WAIT_MEM_GTE" width="32">
++ <doc>
++ Wait until a memory value is greater than or equal to the
++ reference, using signed comparison.
++ </doc>
++ <reg32 offset="0" name="0">
++ <!-- Reserved for flags, presumably? Unused in FW -->
++ <bitfield name="RESERVED" low="0" high="31" type="hex"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="REF" low="0" high="31"/>
++ </reg32>
++</domain>
++
++<domain name="CP_WAIT_REG_MEM" width="32">
++ <doc>
++ This uses the same internal comparison as CP_COND_WRITE,
++ but waits until the comparison is true instead. It busy-loops in
++ the CP for the given number of cycles before trying again.
++ </doc>
++ <reg32 offset="0" name="0">
++ <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
++ <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
++ <bitfield name="POLL" low="4" high="5" type="poll_memory_type"/>
++ <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="REF" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="4" name="4">
++ <bitfield name="MASK" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="5" name="5">
++ <bitfield name="DELAY_LOOP_CYCLES" low="0" high="31"/>
++ </reg32>
++</domain>
++
++<domain name="CP_WAIT_TWO_REGS" width="32">
++ <doc>
++ Waits for REG0 to not be 0 or REG1 to not equal REF
++ </doc>
++ <reg32 offset="0" name="0">
++ <bitfield name="REG0" low="0" high="17" type="hex"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="REG1" low="0" high="17" type="hex"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="REF" low="0" high="31" type="uint"/>
++ </reg32>
++</domain>
++
++<domain name="CP_DISPATCH_COMPUTE" width="32">
++ <reg32 offset="0" name="0"/>
++ <reg32 offset="1" name="1">
++ <bitfield name="X" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="Y" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="Z" low="0" high="31"/>
++ </reg32>
++</domain>
++
++<domain name="CP_SET_RENDER_MODE" width="32">
++ <enum name="render_mode_cmd">
++ <value value="1" name="BYPASS"/>
++ <value value="2" name="BINNING"/>
++ <value value="3" name="GMEM"/>
++ <value value="5" name="BLIT2D"/>
++ <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? -->
++ <value value="7" name="BLIT2DSCALE"/>
++ <!-- 8 set before going back to BYPASS exiting 2D -->
++ <value value="8" name="END2D"/>
++ </enum>
++ <reg32 offset="0" name="0">
++ <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/>
++ <!--
++ normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in
++ 0x21xx range.. possibly (at least some) a5xx variants have a
++ 2d core?
++ -->
++ </reg32>
++ <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
++ <reg32 offset="1" name="1">
++ <bitfield name="ADDR_0_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="ADDR_0_HI" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <!--
++ set when in GMEM.. maybe indicates GMEM contents need to be
++ preserved on ctx switch?
++ -->
++ <bitfield name="VSC_ENABLE" pos="3" type="boolean"/>
++ <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/>
++ </reg32>
++ <reg32 offset="4" name="4"/>
++ <!-- second buffer looks like some cmdstream.. length in dwords: -->
++ <reg32 offset="5" name="5">
++ <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="6" name="6">
++ <bitfield name="ADDR_1_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="7" name="7">
++ <bitfield name="ADDR_1_HI" low="0" high="31"/>
++ </reg32>
++</domain>
++
++<!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword -->
++<domain name="CP_COMPUTE_CHECKPOINT" width="32">
++ <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
++ <reg32 offset="0" name="0">
++ <bitfield name="ADDR_0_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="ADDR_0_HI" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ </reg32>
++ <reg32 offset="3" name="3"/>
++ <!-- second buffer looks like some cmdstream.. length in dwords: -->
++ <reg32 offset="4" name="4">
++ <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="5" name="5">
++ <bitfield name="ADDR_1_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="6" name="6">
++ <bitfield name="ADDR_1_HI" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="7" name="7"/>
++</domain>
++
++<domain name="CP_PERFCOUNTER_ACTION" width="32">
++ <reg32 offset="0" name="0">
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="ADDR_0_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="ADDR_0_HI" low="0" high="31"/>
++ </reg32>
++</domain>
++
++<domain varset="chip" name="CP_EVENT_WRITE" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
++ <!-- when set, write back timestamp instead of value from packet: -->
++ <bitfield name="TIMESTAMP" pos="30" type="boolean"/>
++ <bitfield name="IRQ" pos="31" type="boolean"/>
++ </reg32>
++ <!--
++ TODO what is gpuaddr for, seems to be all 0's.. maybe needed for
++ context switch?
++ -->
++ <reg32 offset="1" name="1">
++ <bitfield name="ADDR_0_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="ADDR_0_HI" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <!-- ??? -->
++ </reg32>
++</domain>
++
++<domain varset="chip" name="CP_EVENT_WRITE7" width="32">
++ <enum name="event_write_src">
++ <!-- Write payload[0] -->
++ <value value="0" name="EV_WRITE_USER_32B"/>
++ <!-- Write payload[0] payload[1] -->
++ <value value="1" name="EV_WRITE_USER_64B"/>
++ <!-- Write (TIMESTAMP_GLOBAL + TIMESTAMP_LOCAL) -->
++ <value value="2" name="EV_WRITE_TIMESTAMP_SUM"/>
++ <value value="3" name="EV_WRITE_ALWAYSON"/>
++ <!-- Write payload[1] regs starting at payload[0] offset -->
++ <value value="4" name="EV_WRITE_REGS_CONTENT"/>
++ </enum>
++
++ <enum name="event_write_dst">
++ <value value="0" name="EV_DST_RAM"/>
++ <value value="1" name="EV_DST_ONCHIP"/>
++ </enum>
++
++ <reg32 offset="0" name="0">
++ <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
++ <bitfield name="WRITE_SAMPLE_COUNT" pos="12" type="boolean"/>
++ <!-- Write sample count at (iova + 16) -->
++ <bitfield name="SAMPLE_COUNT_END_OFFSET" pos="13" type="boolean"/>
++ <!-- *(iova + 8) = *(iova + 16) - *iova -->
++ <bitfield name="WRITE_SAMPLE_COUNT_DIFF" pos="14" type="boolean"/>
++
++ <!-- Next 4 flags are valid to set only when concurrent binning is enabled -->
++ <!-- Increment 16b BV counter. Valid only in BV pipe -->
++ <bitfield name="INC_BV_COUNT" pos="16" type="boolean"/>
++ <!-- Increment 16b BR counter. Valid only in BR pipe -->
++ <bitfield name="INC_BR_COUNT" pos="17" type="boolean"/>
++ <bitfield name="CLEAR_RENDER_RESOURCE" pos="18" type="boolean"/>
++ <bitfield name="CLEAR_LRZ_RESOURCE" pos="19" type="boolean"/>
++
++ <bitfield name="WRITE_SRC" low="20" high="22" type="event_write_src"/>
++ <bitfield name="WRITE_DST" pos="24" type="event_write_dst" addvariant="yes"/>
++ <!-- Writes into WRITE_DST from WRITE_SRC. RB_DONE_TS requires WRITE_ENABLED. -->
++ <bitfield name="WRITE_ENABLED" pos="27" type="boolean"/>
++ </reg32>
++
++ <stripe varset="event_write_dst" variants="EV_DST_RAM">
++ <reg32 offset="1" name="1">
++ <bitfield name="ADDR_0_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="ADDR_0_HI" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="PAYLOAD_0" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="4" name="4">
++ <bitfield name="PAYLOAD_1" low="0" high="31"/>
++ </reg32>
++ </stripe>
++
++ <stripe varset="event_write_dst" variants="EV_DST_ONCHIP">
++ <reg32 offset="1" name="1">
++ <bitfield name="ONCHIP_ADDR_0" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="PAYLOAD_0" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="4" name="4">
++ <bitfield name="PAYLOAD_1" low="0" high="31"/>
++ </reg32>
++ </stripe>
++</domain>
++
++<domain name="CP_BLIT" width="32">
++ <enum name="cp_blit_cmd">
++ <value value="0" name="BLIT_OP_FILL"/>
++ <value value="1" name="BLIT_OP_COPY"/>
++ <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation -->
++ </enum>
++ <reg32 offset="0" name="0">
++ <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="SRC_X1" low="0" high="13" type="uint"/>
++ <bitfield name="SRC_Y1" low="16" high="29" type="uint"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="SRC_X2" low="0" high="13" type="uint"/>
++ <bitfield name="SRC_Y2" low="16" high="29" type="uint"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="DST_X1" low="0" high="13" type="uint"/>
++ <bitfield name="DST_Y1" low="16" high="29" type="uint"/>
++ </reg32>
++ <reg32 offset="4" name="4">
++ <bitfield name="DST_X2" low="0" high="13" type="uint"/>
++ <bitfield name="DST_Y2" low="16" high="29" type="uint"/>
++ </reg32>
++</domain>
++
++<domain name="CP_EXEC_CS" width="32">
++ <reg32 offset="0" name="0">
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/>
++ </reg32>
++</domain>
++
++<domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
++ <reg32 offset="0" name="0">
++ </reg32>
++ <stripe varset="chip" variants="A4XX">
++ <reg32 offset="1" name="1">
++ <bitfield name="ADDR" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <!-- localsize is value minus one: -->
++ <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
++ <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
++ <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
++ </reg32>
++ </stripe>
++ <stripe varset="chip" variants="A5XX-">
++ <reg32 offset="1" name="1">
++ <bitfield name="ADDR_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="ADDR_HI" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <!-- localsize is value minus one: -->
++ <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
++ <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
++ <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
++ </reg32>
++ </stripe>
++</domain>
++
++<domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
++ <doc>Tell CP the current operation mode, indicates save and restore procedure</doc>
++ <enum name="a6xx_marker">
++ <value value="1" name="RM6_BYPASS"/>
++ <value value="2" name="RM6_BINNING"/>
++ <value value="4" name="RM6_GMEM"/>
++ <value value="5" name="RM6_ENDVIS"/>
++ <value value="6" name="RM6_RESOLVE"/>
++ <value value="7" name="RM6_YIELD"/>
++ <value value="8" name="RM6_COMPUTE"/>
++ <value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) -->
++
++ <!--
++ These values come from a6xx_set_marker() in the
++ downstream kernel, and they can only be set by the kernel
++ -->
++ <value value="0xd" name="RM6_IB1LIST_START"/>
++ <value value="0xe" name="RM6_IB1LIST_END"/>
++ <!-- IFPC - inter-frame power collapse -->
++ <value value="0x100" name="RM6_IFPC_ENABLE"/>
++ <value value="0x101" name="RM6_IFPC_DISABLE"/>
++ </enum>
++ <reg32 offset="0" name="0">
++ <!--
++ NOTE: blob driver and some versions of freedreno/turnip set
++ b4, which is unused (at least by current sqe fw), but interferes
++ with parsing if we extend the size of the bitfield to include
++ b8 (only sent by kernel mode driver). Really, the way the
++ parsing works in the firmware, only b0-b3 are considered, but
++ if b8 is set, the low bits are interpreted differently. To
++ model this, without getting confused by spurious b4, this is
++ described as two overlapping bitfields:
++ -->
++ <bitfield name="MODE" low="0" high="8" type="a6xx_marker"/>
++ <bitfield name="MARKER" low="0" high="3" type="a6xx_marker"/>
++ </reg32>
++</domain>
++
++<domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
++ <doc>Set internal CP registers, used to indicate context save data addresses</doc>
++ <enum name="pseudo_reg">
++ <value value="0" name="SMMU_INFO"/>
++ <value value="1" name="NON_SECURE_SAVE_ADDR"/>
++ <value value="2" name="SECURE_SAVE_ADDR"/>
++ <value value="3" name="NON_PRIV_SAVE_ADDR"/>
++ <value value="4" name="COUNTER"/>
++
++ <!--
++ On a6xx the registers are set directly and CP_SET_BIN_DATA5_OFFSET reads them,
++ but that doesn't work with concurrent binning because BR will be reading from
++ a different set of streams than BV is writing, so on a7xx we have these
++ pseudo-regs instead, which do the right thing.
++
++ The corresponding VSC registers exist, and they're written by BV when it
++ encounters CP_SET_PSEUDO_REG. When BR later encounters the same CP_SET_PSEUDO_REG
++ it will only write some private scratch registers which are read by
++ CP_SET_BIN_DATA5_OFFSET.
++
++ If concurrent binning is disabled then BR also does binning so it will also
++ write the "real" registers in BR.
++ -->
++ <value value="8" name="DRAW_STRM_ADDRESS"/>
++ <value value="9" name="DRAW_STRM_SIZE_ADDRESS"/>
++ <value value="10" name="PRIM_STRM_ADDRESS"/>
++ <value value="11" name="UNK_STRM_ADDRESS"/>
++ <value value="12" name="UNK_STRM_SIZE_ADDRESS"/>
++
++ <value value="16" name="BINDLESS_BASE_0_ADDR"/>
++ <value value="17" name="BINDLESS_BASE_1_ADDR"/>
++ <value value="18" name="BINDLESS_BASE_2_ADDR"/>
++ <value value="19" name="BINDLESS_BASE_3_ADDR"/>
++ <value value="20" name="BINDLESS_BASE_4_ADDR"/>
++ <value value="21" name="BINDLESS_BASE_5_ADDR"/>
++ <value value="22" name="BINDLESS_BASE_6_ADDR"/>
++ </enum>
++ <array offset="0" stride="3" length="100">
++ <reg32 offset="0" name="0">
++ <bitfield name="PSEUDO_REG" low="0" high="10" type="pseudo_reg"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="HI" low="0" high="31"/>
++ </reg32>
++ </array>
++</domain>
++
++<domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-">
++ <doc>
++ Tests bit in specified register and sets predicate for CP_COND_REG_EXEC.
++ So:
++
++ opcode: CP_REG_TEST (39) (2 dwords)
++ { REG = 0xc10 | BIT = 0 }
++ 0000: 70b90001 00000c10
++ opcode: CP_COND_REG_EXEC (47) (3 dwords)
++ 0000: 70c70002 10000000 00000004
++ opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
++
++ Will execute the CP_INDIRECT_BUFFER only if b0 in the register at
++ offset 0x0c10 is 1
++ </doc>
++ <enum name="source_type">
++ <value value="0" name="SOURCE_REG"/>
++ <!-- Don't confuse with scratch registers, this is a separate memory
++ written into by CP_MEM_TO_SCRATCH_MEM. -->
++ <value value="1" name="SOURCE_SCRATCH_MEM" varset="chip" variants="A7XX-"/>
++ </enum>
++ <reg32 offset="0" name="0">
++ <!-- the register to test -->
++ <bitfield name="REG" low="0" high="17" varset="source_type" variants="SOURCE_REG"/>
++ <bitfield name="SCRATCH_MEM_OFFSET" low="0" high="17" varset="source_type" variants="SOURCE_SCRATCH_MEM"/>
++ <bitfield name="SOURCE" pos="18" type="source_type" addvariant="yes"/>
++ <!-- the bit to test -->
++ <bitfield name="BIT" low="20" high="24" type="uint"/>
++ <!-- skip implied CP_WAIT_FOR_ME -->
++ <bitfield name="SKIP_WAIT_FOR_ME" pos="25" type="boolean"/>
++ <!-- the predicate bit to set (new in gen3+) -->
++ <bitfield name="PRED_BIT" low="26" high="30" type="uint"/>
++ <!-- update the predicate reg directly (new in gen3+) -->
++ <bitfield name="PRED_UPDATE" pos="31" type="boolean"/>
++ </reg32>
++
++ <!--
++ In PRED_UPDATE mode, the predicate reg is updated directly using two
++ more dwords, ignoring other bits:
++
++ PRED_REG = (PRED_REG & ~PRED_MASK) | (PRED_VAL & PRED_MASK);
++ -->
++ <reg32 offset="1" name="PRED_MASK" type="hex"/>
++ <reg32 offset="2" name="PRED_VAL" type="hex"/>
++</domain>
++
++<!-- I *think* this existed at least as far back as a4xx -->
++<domain name="CP_COND_REG_EXEC" width="32">
++ <enum name="compare_mode">
++ <!-- use the predicate bit set by CP_REG_TEST -->
++ <value value="1" name="PRED_TEST"/>
++ <!-- compare two registers directly for equality -->
++ <value value="2" name="REG_COMPARE"/>
++ <!-- test if certain render modes are set via CP_SET_MARKER -->
++ <value value="3" name="RENDER_MODE" varset="chip" variants="A6XX-"/>
++ <!-- compare REG0 for equality with immediate -->
++ <value value="4" name="REG_COMPARE_IMM" varset="chip" variants="A7XX-"/>
++ <!-- test which of BR/BV are enabled -->
++ <value value="5" name="THREAD_MODE" varset="chip" variants="A7XX-"/>
++ </enum>
++ <reg32 offset="0" name="0" varset="compare_mode">
++ <bitfield name="REG0" low="0" high="17" variants="REG_COMPARE" type="hex"/>
++
++ <!-- the predicate bit to test (new in gen3+) -->
++ <bitfield name="PRED_BIT" low="18" high="22" variants="PRED_TEST" type="uint"/>
++ <bitfield name="SKIP_WAIT_FOR_ME" pos="23" varset="chip" variants="A7XX-" type="boolean"/>
++ <!-- With REG_COMPARE instead of register read from ONCHIP memory -->
++ <bitfield name="ONCHIP_MEM" pos="24" varset="chip" variants="A7XX-" type="boolean"/>
++
++ <!--
++ Note: these bits have the same meaning, and use the same
++ internal mechanism as the bits in CP_SET_DRAW_STATE.
++ When RENDER_MODE is selected, they're used as
++ a bitmask of which modes pass the test.
++ -->
++
++ <!-- RM6_BINNING -->
++ <bitfield name="BINNING" pos="25" variants="RENDER_MODE" type="boolean"/>
++ <!-- all others -->
++ <bitfield name="GMEM" pos="26" variants="RENDER_MODE" type="boolean"/>
++ <!-- RM6_BYPASS -->
++ <bitfield name="SYSMEM" pos="27" variants="RENDER_MODE" type="boolean"/>
++
++ <bitfield name="BV" pos="25" variants="THREAD_MODE" type="boolean"/>
++ <bitfield name="BR" pos="26" variants="THREAD_MODE" type="boolean"/>
++ <bitfield name="LPAC" pos="27" variants="THREAD_MODE" type="boolean"/>
++
++ <bitfield name="MODE" low="28" high="31" type="compare_mode" addvariant="yes"/>
++ </reg32>
++
++ <stripe varset="compare_mode" variants="PRED_TEST">
++ <reg32 offset="1" name="1">
++ <bitfield name="DWORDS" low="0" high="23" type="uint"/>
++ </reg32>
++ </stripe>
++
++ <stripe varset="compare_mode" variants="REG_COMPARE">
++ <reg32 offset="1" name="1">
++ <bitfield name="REG1" low="0" high="17" type="hex"/>
++ <!-- Instead of register read from ONCHIP memory -->
++ <bitfield name="ONCHIP_MEM" pos="24" varset="chip" variants="A7XX-" type="boolean"/>
++ </reg32>
++ </stripe>
++
++ <stripe varset="compare_mode" variants="RENDER_MODE">
++ <reg32 offset="1" name="1">
++ <bitfield name="DWORDS" low="0" high="23" type="uint"/>
++ </reg32>
++ </stripe>
++
++ <stripe varset="compare_mode" variants="REG_COMPARE_IMM">
++ <reg32 offset="1" name="1">
++ <bitfield name="IMM" low="0" high="31"/>
++ </reg32>
++ </stripe>
++
++ <stripe varset="compare_mode" variants="THREAD_MODE">
++ <reg32 offset="1" name="1">
++ <bitfield name="DWORDS" low="0" high="23" type="uint"/>
++ </reg32>
++ </stripe>
++
++ <reg32 offset="2" name="2">
++ <bitfield name="DWORDS" low="0" high="23" type="uint"/>
++ </reg32>
++</domain>
++
++<domain name="CP_COND_EXEC" width="32">
++ <doc>
++ Executes the following DWORDs of commands if the dword at ADDR0
++ is not equal to 0 and the dword at ADDR1 is less than REF
++ (signed comparison).
++ </doc>
++ <reg32 offset="0" name="0">
++ <bitfield name="ADDR0_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="ADDR0_HI" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="ADDR1_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="ADDR1_HI" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="4" name="4">
++ <bitfield name="REF" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="5" name="5">
++ <bitfield name="DWORDS" low="0" high="31" type="uint"/>
++ </reg32>
++</domain>
++
++<domain name="CP_SET_CTXSWITCH_IB" width="32">
++ <doc>
++ Used by the userspace driver to set various IB's which are
++ executed during context save/restore for handling
++ state that isn't restored by the
++ context switch routine itself.
++ </doc>
++ <enum name="ctxswitch_ib">
++ <value name="RESTORE_IB" value="0">
++ <doc>Executed unconditionally when switching back to the context.</doc>
++ </value>
++ <value name="YIELD_RESTORE_IB" value="1">
++ <doc>
++ Executed when switching back after switching
++ away during execution of
++ a CP_SET_MARKER packet with RM6_YIELD as the
++ payload *and* the normal save routine was
++ bypassed for a shorter one. I think this is
++ connected to the "skipsaverestore" bit set by
++ the kernel when preempting.
++ </doc>
++ </value>
++ <value name="SAVE_IB" value="2">
++ <doc>
++ Executed when switching away from the context,
++ except for context switches initiated via
++ CP_YIELD.
++ </doc>
++ </value>
++ <value name="RB_SAVE_IB" value="3">
++ <doc>
++ This can only be set by the RB (i.e. the kernel)
++ and executes with protected mode off, but
++ is otherwise similar to SAVE_IB.
++
++ Note, kgsl calls this CP_KMD_AMBLE_TYPE
++ </doc>
++ </value>
++ </enum>
++ <reg32 offset="0" name="0">
++ <bitfield name="ADDR_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="ADDR_HI" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="DWORDS" low="0" high="19" type="uint"/>
++ <bitfield name="TYPE" low="20" high="21" type="ctxswitch_ib"/>
++ </reg32>
++</domain>
++
++<domain name="CP_REG_WRITE" width="32">
++ <enum name="reg_tracker">
++ <doc>
++ Keep shadow copies of these registers and only set them
++ when drawing, avoiding redundant writes:
++ - VPC_CNTL_0
++ - HLSQ_CONTROL_1_REG
++ - HLSQ_UNKNOWN_B980
++ </doc>
++ <value name="TRACK_CNTL_REG" value="0x1"/>
++ <doc>
++ Track RB_RENDER_CNTL, and insert a WFI in the following
++ situation:
++ - There is a write that disables binning
++ - There was a draw with binning left enabled, but in
++ BYPASS mode
++ Presumably this is a hang workaround?
++ </doc>
++ <value name="TRACK_RENDER_CNTL" value="0x2"/>
++ <doc>
++ Do a mysterious CP_EVENT_WRITE 0x3f when the low bit of
++ the data to write is 0. Used by the Vulkan blob with
++ PC_MULTIVIEW_CNTL, but this isn't predicated on particular
++ register(s) like the others.
++ </doc>
++ <value name="UNK_EVENT_WRITE" value="0x4"/>
++ <doc>
++ Tracks GRAS_LRZ_CNTL::GREATER, GRAS_LRZ_CNTL::DIR, and
++ GRAS_LRZ_DEPTH_VIEW with previous values, and if one of
++ the following is true:
++ - GRAS_LRZ_CNTL::GREATER has changed
++ - GRAS_LRZ_CNTL::DIR has changed, the old value is not
++ CUR_DIR_GE, and the new value is not CUR_DIR_DISABLED
++ - GRAS_LRZ_DEPTH_VIEW has changed
++ then it does a LRZ_FLUSH with GRAS_LRZ_CNTL::ENABLE
++ forced to 1.
++ Only exists in a650_sqe.fw.
++ </doc>
++ <value name="TRACK_LRZ" value="0x8"/>
++ </enum>
++ <reg32 offset="0" name="0">
++ <bitfield name="TRACKER" low="0" high="3" type="reg_tracker"/>
++ </reg32>
++ <reg32 offset="1" name="1"/>
++ <reg32 offset="2" name="2"/>
++</domain>
++
++<domain name="CP_SMMU_TABLE_UPDATE" width="32">
++ <doc>
++ Note that the SMMU's definition of TTBRn can take different forms
++ depending on the pgtable format. But a5xx+ only uses aarch64
++ format.
++ </doc>
++ <reg32 offset="0" name="0">
++ <bitfield name="TTBR0_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="TTBR0_HI" low="0" high="15"/>
++ <bitfield name="ASID" low="16" high="31"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <doc>Unused, does not apply to aarch64 pgtable format</doc>
++ <bitfield name="CONTEXTIDR" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="CONTEXTBANK" low="0" high="31"/>
++ </reg32>
++</domain>
++
++<domain name="CP_START_BIN" width="32">
++ <reg32 offset="0" name="BIN_COUNT" type="uint"/>
++ <reg64 offset="1" name="PREFIX_ADDR" type="address"/>
++ <reg32 offset="3" name="PREFIX_DWORDS">
++ <doc>
++ Size of prefix for each bin. For each bin index i, the
++ prefix commands at PREFIX_ADDR + i * PREFIX_DWORDS are
++ executed in an IB2 before the IB1 commands following
++ this packet.
++ </doc>
++ </reg32>
++ <reg32 offset="4" name="BODY_DWORDS">
++ <doc>Number of dwords after this packet until CP_END_BIN</doc>
++ </reg32>
++</domain>
++
++<domain name="CP_WAIT_TIMESTAMP" width="32">
++ <enum name="ts_wait_value_src">
++ <!-- Wait for value at memory address to be >= SRC_0 (signed comparison) -->
++ <value value="0" name="TS_WAIT_GE_32B"/>
++ <!-- Wait for value at memory address to be >= SRC_0 (unsigned) -->
++ <value value="1" name="TS_WAIT_GE_64B"/>
++ <!-- Write (TIMESTAMP_GLOBAL + TIMESTAMP_LOCAL) -->
++ <value value="2" name="TS_WAIT_GE_TIMESTAMP_SUM"/>
++ </enum>
++
++ <enum name="ts_wait_type">
++ <value value="0" name="TS_WAIT_RAM"/>
++ <value value="1" name="TS_WAIT_ONCHIP"/>
++ </enum>
++
++ <reg32 offset="0" name="0">
++ <bitfield name="WAIT_VALUE_SRC" low="0" high="1" type="ts_wait_value_src"/>
++ <bitfield name="WAIT_DST" pos="4" type="ts_wait_type" addvariant="yes"/>
++ </reg32>
++
++ <stripe varset="ts_wait_type" variants="TS_WAIT_RAM">
++ <reg64 offset="1" name="ADDR" type="address"/>
++ </stripe>
++
++ <stripe varset="ts_wait_type" variants="TS_WAIT_ONCHIP">
++ <reg32 offset="1" name="ONCHIP_ADDR_0" low="0" high="31"/>
++ </stripe>
++
++ <reg32 offset="3" name="SRC_0"/>
++ <reg32 offset="4" name="SRC_1"/>
++</domain>
++
++<domain name="CP_BV_BR_COUNT_OPS" width="32">
++ <enum name="pipe_count_op">
++ <value name="PIPE_CLEAR_BV_BR" value="0x1"/>
++ <value name="PIPE_SET_BR_OFFSET" value="0x2"/>
++ <!-- Wait until for BV_counter > BR_counter -->
++ <value name="PIPE_BR_WAIT_FOR_BV" value="0x3"/>
++ <!-- Wait until (BR_counter + BR_OFFSET) > BV_counter -->
++ <value name="PIPE_BV_WAIT_FOR_BR" value="0x4"/>
++ </enum>
++ <reg32 offset="0" name="0">
++ <bitfield name="OP" low="0" high="3" type="pipe_count_op"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="BR_OFFSET" low="0" high="15" type="uint"/>
++ </reg32>
++</domain>
++
++<domain name="CP_MODIFY_TIMESTAMP" width="32">
++ <enum name="timestamp_op">
++ <value name="MODIFY_TIMESTAMP_CLEAR" value="0"/>
++ <value name="MODIFY_TIMESTAMP_ADD_GLOBAL" value="1"/>
++ <value name="MODIFY_TIMESTAMP_ADD_LOCAL" value="2"/>
++ </enum>
++ <reg32 offset="0" name="0">
++ <bitfield name="ADD" low="0" high="7" type="uint"/>
++ <bitfield name="OP" low="28" high="31" type="timestamp_op"/>
++ </reg32>
++</domain>
++
++<domain name="CP_MEM_TO_SCRATCH_MEM" width="32">
++ <doc>
++ Best guess is that it is a faster way to fetch all the VSC_STATE registers
++ and keep them in a local scratch memory instead of fetching every time
++ when skipping IBs.
++ </doc>
++ <reg32 offset="0" name="0">
++ <bitfield name="CNT" low="0" high="5" type="uint"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <doc>Scratch memory size is 48 dwords`</doc>
++ <bitfield name="OFFSET" low="0" high="5" type="uint"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="SRC" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="SRC_HI" low="0" high="31"/>
++ </reg32>
++</domain>
++
++<domain name="CP_THREAD_CONTROL" width="32">
++ <enum name="cp_thread">
++ <value name="CP_SET_THREAD_BR" value="1"/> <!-- Render -->
++ <value name="CP_SET_THREAD_BV" value="2"/> <!-- Visibility -->
++ <value name="CP_SET_THREAD_BOTH" value="3"/>
++ </enum>
++ <reg32 offset="0" name="0">
++ <bitfield low="0" high="1" name="THREAD" type="cp_thread"/>
++ <bitfield pos="27" name="CONCURRENT_BIN_DISABLE" type="boolean"/>
++ <bitfield pos="31" name="SYNC_THREADS" type="boolean"/>
++ </reg32>
++</domain>
++
++<domain name="CP_FIXED_STRIDE_DRAW_TABLE" width="32">
++ <reg64 offset="0" name="IB_BASE"/>
++ <reg32 offset="2" name="2">
++ <!-- STRIDE * COUNT -->
++ <bitfield name="IB_SIZE" low="0" high="11"/>
++ <bitfield name="STRIDE" low="20" high="31"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <bitfield name="COUNT" low="0" high="31"/>
++ </reg32>
++</domain>
++
++<domain name="CP_RESET_CONTEXT_STATE" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="CLEAR_ON_CHIP_TS" pos="0" type="boolean"/>
++ <bitfield name="CLEAR_RESOURCE_TABLE" pos="1" type="boolean"/>
++ <bitfield name="CLEAR_GLOBAL_LOCAL_TS" pos="2" type="boolean"/>
++ </reg32>
++</domain>
++
++</database>
++
+--
+2.39.5
+
--- /dev/null
+From a0dc6ebe3754f120900255f134f1f5ed7af686ff Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 1 Apr 2024 05:42:38 +0300
+Subject: drm/msm: import A5xx XML display registers database
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 2033659c22132695f6e4a70570c330e735164e55 ]
+
+Import Adreno registers database for A5xx from the Mesa, commit
+639488f924d9 ("freedreno/registers: limit the rules schema").
+
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Patchwork: https://patchwork.freedesktop.org/patch/585857/
+Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-8-4bdb277a85a1@linaro.org
+Stable-dep-of: 588257897058 ("drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG0 updated from driver side")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/registers/adreno/a5xx.xml | 3039 +++++++++++++++++
+ 1 file changed, 3039 insertions(+)
+ create mode 100644 drivers/gpu/drm/msm/registers/adreno/a5xx.xml
+
+diff --git a/drivers/gpu/drm/msm/registers/adreno/a5xx.xml b/drivers/gpu/drm/msm/registers/adreno/a5xx.xml
+new file mode 100644
+index 0000000000000..bd8df59451664
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/adreno/a5xx.xml
+@@ -0,0 +1,3039 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++<import file="adreno/adreno_common.xml"/>
++<import file="adreno/adreno_pm4.xml"/>
++
++<enum name="a5xx_color_fmt">
++ <value value="0x02" name="RB5_A8_UNORM"/>
++ <value value="0x03" name="RB5_R8_UNORM"/>
++ <value value="0x04" name="RB5_R8_SNORM"/>
++ <value value="0x05" name="RB5_R8_UINT"/>
++ <value value="0x06" name="RB5_R8_SINT"/>
++ <value value="0x08" name="RB5_R4G4B4A4_UNORM"/>
++ <value value="0x0a" name="RB5_R5G5B5A1_UNORM"/>
++ <value value="0x0e" name="RB5_R5G6B5_UNORM"/>
++ <value value="0x0f" name="RB5_R8G8_UNORM"/>
++ <value value="0x10" name="RB5_R8G8_SNORM"/>
++ <value value="0x11" name="RB5_R8G8_UINT"/>
++ <value value="0x12" name="RB5_R8G8_SINT"/>
++ <value value="0x15" name="RB5_R16_UNORM"/>
++ <value value="0x16" name="RB5_R16_SNORM"/>
++ <value value="0x17" name="RB5_R16_FLOAT"/>
++ <value value="0x18" name="RB5_R16_UINT"/>
++ <value value="0x19" name="RB5_R16_SINT"/>
++ <value value="0x30" name="RB5_R8G8B8A8_UNORM"/>
++ <value value="0x31" name="RB5_R8G8B8_UNORM"/>
++ <value value="0x32" name="RB5_R8G8B8A8_SNORM"/>
++ <value value="0x33" name="RB5_R8G8B8A8_UINT"/>
++ <value value="0x34" name="RB5_R8G8B8A8_SINT"/>
++ <value value="0x37" name="RB5_R10G10B10A2_UNORM"/> <!-- GL_RGB10_A2 -->
++ <value value="0x3a" name="RB5_R10G10B10A2_UINT"/> <!-- GL_RGB10_A2UI -->
++ <value value="0x42" name="RB5_R11G11B10_FLOAT"/> <!-- GL_R11F_G11F_B10F -->
++ <value value="0x43" name="RB5_R16G16_UNORM"/>
++ <value value="0x44" name="RB5_R16G16_SNORM"/>
++ <value value="0x45" name="RB5_R16G16_FLOAT"/>
++ <value value="0x46" name="RB5_R16G16_UINT"/>
++ <value value="0x47" name="RB5_R16G16_SINT"/>
++ <value value="0x4a" name="RB5_R32_FLOAT"/>
++ <value value="0x4b" name="RB5_R32_UINT"/>
++ <value value="0x4c" name="RB5_R32_SINT"/>
++ <value value="0x60" name="RB5_R16G16B16A16_UNORM"/>
++ <value value="0x61" name="RB5_R16G16B16A16_SNORM"/>
++ <value value="0x62" name="RB5_R16G16B16A16_FLOAT"/>
++ <value value="0x63" name="RB5_R16G16B16A16_UINT"/>
++ <value value="0x64" name="RB5_R16G16B16A16_SINT"/>
++ <value value="0x67" name="RB5_R32G32_FLOAT"/>
++ <value value="0x68" name="RB5_R32G32_UINT"/>
++ <value value="0x69" name="RB5_R32G32_SINT"/>
++ <value value="0x82" name="RB5_R32G32B32A32_FLOAT"/>
++ <value value="0x83" name="RB5_R32G32B32A32_UINT"/>
++ <value value="0x84" name="RB5_R32G32B32A32_SINT"/>
++
++ <value value="0xff" name="RB5_NONE"/>
++</enum>
++
++<enum name="a5xx_tile_mode">
++ <value name="TILE5_LINEAR" value="0"/>
++ <value name="TILE5_2" value="2"/>
++ <value name="TILE5_3" value="3"/>
++</enum>
++
++<enum name="a5xx_vtx_fmt" prefix="chipset">
++ <value value="0x03" name="VFMT5_8_UNORM"/>
++ <value value="0x04" name="VFMT5_8_SNORM"/>
++ <value value="0x05" name="VFMT5_8_UINT"/>
++ <value value="0x06" name="VFMT5_8_SINT"/>
++
++ <value value="0x0f" name="VFMT5_8_8_UNORM"/>
++ <value value="0x10" name="VFMT5_8_8_SNORM"/>
++ <value value="0x11" name="VFMT5_8_8_UINT"/>
++ <value value="0x12" name="VFMT5_8_8_SINT"/>
++
++ <value value="0x15" name="VFMT5_16_UNORM"/>
++ <value value="0x16" name="VFMT5_16_SNORM"/>
++ <value value="0x17" name="VFMT5_16_FLOAT"/>
++ <value value="0x18" name="VFMT5_16_UINT"/>
++ <value value="0x19" name="VFMT5_16_SINT"/>
++
++ <value value="0x21" name="VFMT5_8_8_8_UNORM"/>
++ <value value="0x22" name="VFMT5_8_8_8_SNORM"/>
++ <value value="0x23" name="VFMT5_8_8_8_UINT"/>
++ <value value="0x24" name="VFMT5_8_8_8_SINT"/>
++
++ <value value="0x30" name="VFMT5_8_8_8_8_UNORM"/>
++ <value value="0x32" name="VFMT5_8_8_8_8_SNORM"/>
++ <value value="0x33" name="VFMT5_8_8_8_8_UINT"/>
++ <value value="0x34" name="VFMT5_8_8_8_8_SINT"/>
++
++ <value value="0x36" name="VFMT5_10_10_10_2_UNORM"/>
++ <value value="0x39" name="VFMT5_10_10_10_2_SNORM"/>
++ <value value="0x3a" name="VFMT5_10_10_10_2_UINT"/>
++ <value value="0x3b" name="VFMT5_10_10_10_2_SINT"/>
++
++ <value value="0x42" name="VFMT5_11_11_10_FLOAT"/>
++
++ <value value="0x43" name="VFMT5_16_16_UNORM"/>
++ <value value="0x44" name="VFMT5_16_16_SNORM"/>
++ <value value="0x45" name="VFMT5_16_16_FLOAT"/>
++ <value value="0x46" name="VFMT5_16_16_UINT"/>
++ <value value="0x47" name="VFMT5_16_16_SINT"/>
++
++ <value value="0x48" name="VFMT5_32_UNORM"/>
++ <value value="0x49" name="VFMT5_32_SNORM"/>
++ <value value="0x4a" name="VFMT5_32_FLOAT"/>
++ <value value="0x4b" name="VFMT5_32_UINT"/>
++ <value value="0x4c" name="VFMT5_32_SINT"/>
++ <value value="0x4d" name="VFMT5_32_FIXED"/>
++
++ <value value="0x58" name="VFMT5_16_16_16_UNORM"/>
++ <value value="0x59" name="VFMT5_16_16_16_SNORM"/>
++ <value value="0x5a" name="VFMT5_16_16_16_FLOAT"/>
++ <value value="0x5b" name="VFMT5_16_16_16_UINT"/>
++ <value value="0x5c" name="VFMT5_16_16_16_SINT"/>
++
++ <value value="0x60" name="VFMT5_16_16_16_16_UNORM"/>
++ <value value="0x61" name="VFMT5_16_16_16_16_SNORM"/>
++ <value value="0x62" name="VFMT5_16_16_16_16_FLOAT"/>
++ <value value="0x63" name="VFMT5_16_16_16_16_UINT"/>
++ <value value="0x64" name="VFMT5_16_16_16_16_SINT"/>
++
++ <value value="0x65" name="VFMT5_32_32_UNORM"/>
++ <value value="0x66" name="VFMT5_32_32_SNORM"/>
++ <value value="0x67" name="VFMT5_32_32_FLOAT"/>
++ <value value="0x68" name="VFMT5_32_32_UINT"/>
++ <value value="0x69" name="VFMT5_32_32_SINT"/>
++ <value value="0x6a" name="VFMT5_32_32_FIXED"/>
++
++ <value value="0x70" name="VFMT5_32_32_32_UNORM"/>
++ <value value="0x71" name="VFMT5_32_32_32_SNORM"/>
++ <value value="0x72" name="VFMT5_32_32_32_UINT"/>
++ <value value="0x73" name="VFMT5_32_32_32_SINT"/>
++ <value value="0x74" name="VFMT5_32_32_32_FLOAT"/>
++ <value value="0x75" name="VFMT5_32_32_32_FIXED"/>
++
++ <value value="0x80" name="VFMT5_32_32_32_32_UNORM"/>
++ <value value="0x81" name="VFMT5_32_32_32_32_SNORM"/>
++ <value value="0x82" name="VFMT5_32_32_32_32_FLOAT"/>
++ <value value="0x83" name="VFMT5_32_32_32_32_UINT"/>
++ <value value="0x84" name="VFMT5_32_32_32_32_SINT"/>
++ <value value="0x85" name="VFMT5_32_32_32_32_FIXED"/>
++
++ <value value="0xff" name="VFMT5_NONE"/>
++</enum>
++
++<enum name="a5xx_tex_fmt">
++ <value value="0x02" name="TFMT5_A8_UNORM"/>
++ <value value="0x03" name="TFMT5_8_UNORM"/>
++ <value value="0x04" name="TFMT5_8_SNORM"/>
++ <value value="0x05" name="TFMT5_8_UINT"/>
++ <value value="0x06" name="TFMT5_8_SINT"/>
++ <value value="0x08" name="TFMT5_4_4_4_4_UNORM"/>
++ <value value="0x0a" name="TFMT5_5_5_5_1_UNORM"/>
++ <value value="0x0e" name="TFMT5_5_6_5_UNORM"/>
++ <value value="0x0f" name="TFMT5_8_8_UNORM"/>
++ <value value="0x10" name="TFMT5_8_8_SNORM"/>
++ <value value="0x11" name="TFMT5_8_8_UINT"/>
++ <value value="0x12" name="TFMT5_8_8_SINT"/>
++ <value value="0x13" name="TFMT5_L8_A8_UNORM"/>
++ <value value="0x15" name="TFMT5_16_UNORM"/>
++ <value value="0x16" name="TFMT5_16_SNORM"/>
++ <value value="0x17" name="TFMT5_16_FLOAT"/>
++ <value value="0x18" name="TFMT5_16_UINT"/>
++ <value value="0x19" name="TFMT5_16_SINT"/>
++ <value value="0x30" name="TFMT5_8_8_8_8_UNORM"/>
++ <value value="0x31" name="TFMT5_8_8_8_UNORM"/>
++ <value value="0x32" name="TFMT5_8_8_8_8_SNORM"/>
++ <value value="0x33" name="TFMT5_8_8_8_8_UINT"/>
++ <value value="0x34" name="TFMT5_8_8_8_8_SINT"/>
++ <value value="0x35" name="TFMT5_9_9_9_E5_FLOAT"/>
++ <value value="0x36" name="TFMT5_10_10_10_2_UNORM"/>
++ <value value="0x3a" name="TFMT5_10_10_10_2_UINT"/>
++ <value value="0x42" name="TFMT5_11_11_10_FLOAT"/>
++ <value value="0x43" name="TFMT5_16_16_UNORM"/>
++ <value value="0x44" name="TFMT5_16_16_SNORM"/>
++ <value value="0x45" name="TFMT5_16_16_FLOAT"/>
++ <value value="0x46" name="TFMT5_16_16_UINT"/>
++ <value value="0x47" name="TFMT5_16_16_SINT"/>
++ <value value="0x4a" name="TFMT5_32_FLOAT"/>
++ <value value="0x4b" name="TFMT5_32_UINT"/>
++ <value value="0x4c" name="TFMT5_32_SINT"/>
++ <value value="0x60" name="TFMT5_16_16_16_16_UNORM"/>
++ <value value="0x61" name="TFMT5_16_16_16_16_SNORM"/>
++ <value value="0x62" name="TFMT5_16_16_16_16_FLOAT"/>
++ <value value="0x63" name="TFMT5_16_16_16_16_UINT"/>
++ <value value="0x64" name="TFMT5_16_16_16_16_SINT"/>
++ <value value="0x67" name="TFMT5_32_32_FLOAT"/>
++ <value value="0x68" name="TFMT5_32_32_UINT"/>
++ <value value="0x69" name="TFMT5_32_32_SINT"/>
++ <value value="0x72" name="TFMT5_32_32_32_UINT"/>
++ <value value="0x73" name="TFMT5_32_32_32_SINT"/>
++ <value value="0x74" name="TFMT5_32_32_32_FLOAT"/>
++ <value value="0x82" name="TFMT5_32_32_32_32_FLOAT"/>
++ <value value="0x83" name="TFMT5_32_32_32_32_UINT"/>
++ <value value="0x84" name="TFMT5_32_32_32_32_SINT"/>
++ <value value="0xa0" name="TFMT5_X8Z24_UNORM"/>
++
++ <value value="0xab" name="TFMT5_ETC2_RG11_UNORM"/>
++ <value value="0xac" name="TFMT5_ETC2_RG11_SNORM"/>
++ <value value="0xad" name="TFMT5_ETC2_R11_UNORM"/>
++ <value value="0xae" name="TFMT5_ETC2_R11_SNORM"/>
++ <value value="0xaf" name="TFMT5_ETC1"/>
++ <value value="0xb0" name="TFMT5_ETC2_RGB8"/>
++ <value value="0xb1" name="TFMT5_ETC2_RGBA8"/>
++ <value value="0xb2" name="TFMT5_ETC2_RGB8A1"/>
++ <value value="0xb3" name="TFMT5_DXT1"/>
++ <value value="0xb4" name="TFMT5_DXT3"/>
++ <value value="0xb5" name="TFMT5_DXT5"/>
++ <value value="0xb7" name="TFMT5_RGTC1_UNORM"/>
++ <value value="0xb8" name="TFMT5_RGTC1_SNORM"/>
++ <value value="0xbb" name="TFMT5_RGTC2_UNORM"/>
++ <value value="0xbc" name="TFMT5_RGTC2_SNORM"/>
++ <value value="0xbe" name="TFMT5_BPTC_UFLOAT"/>
++ <value value="0xbf" name="TFMT5_BPTC_FLOAT"/>
++ <value value="0xc0" name="TFMT5_BPTC"/>
++ <value value="0xc1" name="TFMT5_ASTC_4x4"/>
++ <value value="0xc2" name="TFMT5_ASTC_5x4"/>
++ <value value="0xc3" name="TFMT5_ASTC_5x5"/>
++ <value value="0xc4" name="TFMT5_ASTC_6x5"/>
++ <value value="0xc5" name="TFMT5_ASTC_6x6"/>
++ <value value="0xc6" name="TFMT5_ASTC_8x5"/>
++ <value value="0xc7" name="TFMT5_ASTC_8x6"/>
++ <value value="0xc8" name="TFMT5_ASTC_8x8"/>
++ <value value="0xc9" name="TFMT5_ASTC_10x5"/>
++ <value value="0xca" name="TFMT5_ASTC_10x6"/>
++ <value value="0xcb" name="TFMT5_ASTC_10x8"/>
++ <value value="0xcc" name="TFMT5_ASTC_10x10"/>
++ <value value="0xcd" name="TFMT5_ASTC_12x10"/>
++ <value value="0xce" name="TFMT5_ASTC_12x12"/>
++
++ <value value="0xff" name="TFMT5_NONE"/>
++</enum>
++
++<enum name="a5xx_depth_format">
++ <value name="DEPTH5_NONE" value="0"/>
++ <value name="DEPTH5_16" value="1"/>
++ <value name="DEPTH5_24_8" value="2"/>
++ <value name="DEPTH5_32" value="4"/>
++</enum>
++
++<enum name="a5xx_blit_buf">
++ <value value="0" name="BLIT_MRT0"/>
++ <value value="1" name="BLIT_MRT1"/>
++ <value value="2" name="BLIT_MRT2"/>
++ <value value="3" name="BLIT_MRT3"/>
++ <value value="4" name="BLIT_MRT4"/>
++ <value value="5" name="BLIT_MRT5"/>
++ <value value="6" name="BLIT_MRT6"/>
++ <value value="7" name="BLIT_MRT7"/>
++ <value value="8" name="BLIT_ZS"/> <!-- depth or combined depth+stencil -->
++ <value value="9" name="BLIT_S"/> <!-- separate stencil -->
++</enum>
++
++<!-- see comment in a4xx.xml about script to extract countables from test-perf output -->
++<enum name="a5xx_cp_perfcounter_select">
++ <value value="0" name="PERF_CP_ALWAYS_COUNT"/>
++ <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
++ <value value="2" name="PERF_CP_BUSY_CYCLES"/>
++ <value value="3" name="PERF_CP_PFP_IDLE"/>
++ <value value="4" name="PERF_CP_PFP_BUSY_WORKING"/>
++ <value value="5" name="PERF_CP_PFP_STALL_CYCLES_ANY"/>
++ <value value="6" name="PERF_CP_PFP_STARVE_CYCLES_ANY"/>
++ <value value="7" name="PERF_CP_PFP_ICACHE_MISS"/>
++ <value value="8" name="PERF_CP_PFP_ICACHE_HIT"/>
++ <value value="9" name="PERF_CP_PFP_MATCH_PM4_PKT_PROFILE"/>
++ <value value="10" name="PERF_CP_ME_BUSY_WORKING"/>
++ <value value="11" name="PERF_CP_ME_IDLE"/>
++ <value value="12" name="PERF_CP_ME_STARVE_CYCLES_ANY"/>
++ <value value="13" name="PERF_CP_ME_FIFO_EMPTY_PFP_IDLE"/>
++ <value value="14" name="PERF_CP_ME_FIFO_EMPTY_PFP_BUSY"/>
++ <value value="15" name="PERF_CP_ME_FIFO_FULL_ME_BUSY"/>
++ <value value="16" name="PERF_CP_ME_FIFO_FULL_ME_NON_WORKING"/>
++ <value value="17" name="PERF_CP_ME_STALL_CYCLES_ANY"/>
++ <value value="18" name="PERF_CP_ME_ICACHE_MISS"/>
++ <value value="19" name="PERF_CP_ME_ICACHE_HIT"/>
++ <value value="20" name="PERF_CP_NUM_PREEMPTIONS"/>
++ <value value="21" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
++ <value value="22" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
++ <value value="23" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
++ <value value="24" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
++ <value value="25" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
++ <value value="26" name="PERF_CP_MODE_SWITCH"/>
++ <value value="27" name="PERF_CP_ZPASS_DONE"/>
++ <value value="28" name="PERF_CP_CONTEXT_DONE"/>
++ <value value="29" name="PERF_CP_CACHE_FLUSH"/>
++ <value value="30" name="PERF_CP_LONG_PREEMPTIONS"/>
++</enum>
++
++<enum name="a5xx_rbbm_perfcounter_select">
++ <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
++ <value value="1" name="PERF_RBBM_ALWAYS_ON"/>
++ <value value="2" name="PERF_RBBM_TSE_BUSY"/>
++ <value value="3" name="PERF_RBBM_RAS_BUSY"/>
++ <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
++ <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
++ <value value="6" name="PERF_RBBM_STATUS_MASKED"/>
++ <value value="7" name="PERF_RBBM_COM_BUSY"/>
++ <value value="8" name="PERF_RBBM_DCOM_BUSY"/>
++ <value value="9" name="PERF_RBBM_VBIF_BUSY"/>
++ <value value="10" name="PERF_RBBM_VSC_BUSY"/>
++ <value value="11" name="PERF_RBBM_TESS_BUSY"/>
++ <value value="12" name="PERF_RBBM_UCHE_BUSY"/>
++ <value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
++</enum>
++
++<enum name="a5xx_pc_perfcounter_select">
++ <value value="0" name="PERF_PC_BUSY_CYCLES"/>
++ <value value="1" name="PERF_PC_WORKING_CYCLES"/>
++ <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
++ <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
++ <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
++ <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
++ <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
++ <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
++ <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
++ <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
++ <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
++ <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
++ <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
++ <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
++ <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
++ <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
++ <value value="16" name="PERF_PC_INSTANCES"/>
++ <value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
++ <value value="18" name="PERF_PC_DEAD_PRIM"/>
++ <value value="19" name="PERF_PC_LIVE_PRIM"/>
++ <value value="20" name="PERF_PC_VERTEX_HITS"/>
++ <value value="21" name="PERF_PC_IA_VERTICES"/>
++ <value value="22" name="PERF_PC_IA_PRIMITIVES"/>
++ <value value="23" name="PERF_PC_GS_PRIMITIVES"/>
++ <value value="24" name="PERF_PC_HS_INVOCATIONS"/>
++ <value value="25" name="PERF_PC_DS_INVOCATIONS"/>
++ <value value="26" name="PERF_PC_VS_INVOCATIONS"/>
++ <value value="27" name="PERF_PC_GS_INVOCATIONS"/>
++ <value value="28" name="PERF_PC_DS_PRIMITIVES"/>
++ <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
++ <value value="30" name="PERF_PC_3D_DRAWCALLS"/>
++ <value value="31" name="PERF_PC_2D_DRAWCALLS"/>
++ <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
++ <value value="33" name="PERF_TESS_BUSY_CYCLES"/>
++ <value value="34" name="PERF_TESS_WORKING_CYCLES"/>
++ <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
++ <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
++</enum>
++
++<enum name="a5xx_vfd_perfcounter_select">
++ <value value="0" name="PERF_VFD_BUSY_CYCLES"/>
++ <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
++ <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
++ <value value="3" name="PERF_VFD_STALL_CYCLES_MISS_VB"/>
++ <value value="4" name="PERF_VFD_STALL_CYCLES_MISS_Q"/>
++ <value value="5" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
++ <value value="6" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
++ <value value="7" name="PERF_VFD_STALL_CYCLES_VFDP_VB"/>
++ <value value="8" name="PERF_VFD_STALL_CYCLES_VFDP_Q"/>
++ <value value="9" name="PERF_VFD_DECODER_PACKER_STALL"/>
++ <value value="10" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
++ <value value="11" name="PERF_VFD_RBUFFER_FULL"/>
++ <value value="12" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
++ <value value="13" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
++ <value value="14" name="PERF_VFD_NUM_ATTRIBUTES"/>
++ <value value="15" name="PERF_VFD_INSTRUCTIONS"/>
++ <value value="16" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
++ <value value="17" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
++ <value value="18" name="PERF_VFD_MODE_0_FIBERS"/>
++ <value value="19" name="PERF_VFD_MODE_1_FIBERS"/>
++ <value value="20" name="PERF_VFD_MODE_2_FIBERS"/>
++ <value value="21" name="PERF_VFD_MODE_3_FIBERS"/>
++ <value value="22" name="PERF_VFD_MODE_4_FIBERS"/>
++ <value value="23" name="PERF_VFD_TOTAL_VERTICES"/>
++ <value value="24" name="PERF_VFD_NUM_ATTR_MISS"/>
++ <value value="25" name="PERF_VFD_1_BURST_REQ"/>
++ <value value="26" name="PERF_VFDP_STALL_CYCLES_VFD"/>
++ <value value="27" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
++ <value value="28" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
++ <value value="29" name="PERF_VFDP_STARVE_CYCLES_PC"/>
++ <value value="30" name="PERF_VFDP_VS_STAGE_32_WAVES"/>
++</enum>
++
++<enum name="a5xx_hlsq_perfcounter_select">
++ <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
++ <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
++ <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
++ <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
++ <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
++ <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
++ <value value="6" name="PERF_HLSQ_FS_STAGE_32_WAVES"/>
++ <value value="7" name="PERF_HLSQ_FS_STAGE_64_WAVES"/>
++ <value value="8" name="PERF_HLSQ_QUADS"/>
++ <value value="9" name="PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE"/>
++ <value value="10" name="PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE"/>
++ <value value="11" name="PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE"/>
++ <value value="12" name="PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE"/>
++ <value value="13" name="PERF_HLSQ_CS_INVOCATIONS"/>
++ <value value="14" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
++</enum>
++
++<enum name="a5xx_vpc_perfcounter_select">
++ <value value="0" name="PERF_VPC_BUSY_CYCLES"/>
++ <value value="1" name="PERF_VPC_WORKING_CYCLES"/>
++ <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
++ <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
++ <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
++ <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
++ <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
++ <value value="7" name="PERF_VPC_POS_EXPORT_STALL_CYCLES"/>
++ <value value="8" name="PERF_VPC_STARVE_CYCLES_SP"/>
++ <value value="9" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
++ <value value="10" name="PERF_VPC_PC_PRIMITIVES"/>
++ <value value="11" name="PERF_VPC_SP_COMPONENTS"/>
++ <value value="12" name="PERF_VPC_SP_LM_PRIMITIVES"/>
++ <value value="13" name="PERF_VPC_SP_LM_COMPONENTS"/>
++ <value value="14" name="PERF_VPC_SP_LM_DWORDS"/>
++ <value value="15" name="PERF_VPC_STREAMOUT_COMPONENTS"/>
++ <value value="16" name="PERF_VPC_GRANT_PHASES"/>
++</enum>
++
++<enum name="a5xx_tse_perfcounter_select">
++ <value value="0" name="PERF_TSE_BUSY_CYCLES"/>
++ <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
++ <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
++ <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
++ <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
++ <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
++ <value value="6" name="PERF_TSE_INPUT_PRIM"/>
++ <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
++ <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
++ <value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
++ <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
++ <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
++ <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
++ <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
++ <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
++ <value value="15" name="PERF_TSE_CINVOCATION"/>
++ <value value="16" name="PERF_TSE_CPRIMITIVES"/>
++ <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
++ <value value="18" name="PERF_TSE_2D_ALIVE_CLCLES"/>
++</enum>
++
++<enum name="a5xx_ras_perfcounter_select">
++ <value value="0" name="PERF_RAS_BUSY_CYCLES"/>
++ <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
++ <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
++ <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
++ <value value="4" name="PERF_RAS_SUPER_TILES"/>
++ <value value="5" name="PERF_RAS_8X4_TILES"/>
++ <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
++ <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
++ <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
++ <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
++</enum>
++
++<enum name="a5xx_lrz_perfcounter_select">
++ <value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
++ <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
++ <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
++ <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
++ <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
++ <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
++ <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
++ <value value="7" name="PERF_LRZ_LRZ_READ"/>
++ <value value="8" name="PERF_LRZ_LRZ_WRITE"/>
++ <value value="9" name="PERF_LRZ_READ_LATENCY"/>
++ <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
++ <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
++ <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
++ <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
++ <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
++ <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
++ <value value="16" name="PERF_LRZ_TILE_KILLED"/>
++ <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
++ <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
++</enum>
++
++<enum name="a5xx_uche_perfcounter_select">
++ <value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
++ <value value="1" name="PERF_UCHE_STALL_CYCLES_VBIF"/>
++ <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
++ <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
++ <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
++ <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
++ <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
++ <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
++ <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
++ <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
++ <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
++ <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
++ <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
++ <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
++ <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
++ <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
++ <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
++ <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
++ <value value="18" name="PERF_UCHE_EVICTS"/>
++ <value value="19" name="PERF_UCHE_BANK_REQ0"/>
++ <value value="20" name="PERF_UCHE_BANK_REQ1"/>
++ <value value="21" name="PERF_UCHE_BANK_REQ2"/>
++ <value value="22" name="PERF_UCHE_BANK_REQ3"/>
++ <value value="23" name="PERF_UCHE_BANK_REQ4"/>
++ <value value="24" name="PERF_UCHE_BANK_REQ5"/>
++ <value value="25" name="PERF_UCHE_BANK_REQ6"/>
++ <value value="26" name="PERF_UCHE_BANK_REQ7"/>
++ <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
++ <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
++ <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
++ <value value="30" name="PERF_UCHE_FLAG_COUNT"/>
++</enum>
++
++<enum name="a5xx_tp_perfcounter_select">
++ <value value="0" name="PERF_TP_BUSY_CYCLES"/>
++ <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
++ <value value="2" name="PERF_TP_LATENCY_CYCLES"/>
++ <value value="3" name="PERF_TP_LATENCY_TRANS"/>
++ <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
++ <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
++ <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
++ <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
++ <value value="8" name="PERF_TP_SP_TP_TRANS"/>
++ <value value="9" name="PERF_TP_TP_SP_TRANS"/>
++ <value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
++ <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
++ <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
++ <value value="13" name="PERF_TP_QUADS_RECEIVED"/>
++ <value value="14" name="PERF_TP_QUADS_OFFSET"/>
++ <value value="15" name="PERF_TP_QUADS_SHADOW"/>
++ <value value="16" name="PERF_TP_QUADS_ARRAY"/>
++ <value value="17" name="PERF_TP_QUADS_GRADIENT"/>
++ <value value="18" name="PERF_TP_QUADS_1D"/>
++ <value value="19" name="PERF_TP_QUADS_2D"/>
++ <value value="20" name="PERF_TP_QUADS_BUFFER"/>
++ <value value="21" name="PERF_TP_QUADS_3D"/>
++ <value value="22" name="PERF_TP_QUADS_CUBE"/>
++ <value value="23" name="PERF_TP_STATE_CACHE_REQUESTS"/>
++ <value value="24" name="PERF_TP_STATE_CACHE_MISSES"/>
++ <value value="25" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
++ <value value="26" name="PERF_TP_BINDLESS_STATE_CACHE_REQUESTS"/>
++ <value value="27" name="PERF_TP_BINDLESS_STATE_CACHE_MISSES"/>
++ <value value="28" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
++ <value value="29" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
++ <value value="30" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
++ <value value="31" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
++ <value value="32" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
++ <value value="33" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
++ <value value="34" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
++ <value value="35" name="PERF_TP_FLAG_CACHE_MISSES"/>
++ <value value="36" name="PERF_TP_L1_5_L2_REQUESTS"/>
++ <value value="37" name="PERF_TP_2D_OUTPUT_PIXELS"/>
++ <value value="38" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
++ <value value="39" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
++ <value value="40" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
++ <value value="41" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
++</enum>
++
++<enum name="a5xx_sp_perfcounter_select">
++ <value value="0" name="PERF_SP_BUSY_CYCLES"/>
++ <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
++ <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
++ <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
++ <value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
++ <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
++ <value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
++ <value value="7" name="PERF_SP_SCHEDULER_NON_WORKING"/>
++ <value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
++ <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
++ <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
++ <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
++ <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
++ <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
++ <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
++ <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
++ <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
++ <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
++ <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
++ <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
++ <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
++ <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
++ <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
++ <value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
++ <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
++ <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
++ <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
++ <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
++ <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
++ <value value="29" name="PERF_SP_LM_ATOMICS"/>
++ <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
++ <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
++ <value value="32" name="PERF_SP_GM_ATOMICS"/>
++ <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
++ <value value="34" name="PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS"/>
++ <value value="35" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
++ <value value="36" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
++ <value value="37" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
++ <value value="38" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
++ <value value="39" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
++ <value value="40" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
++ <value value="41" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
++ <value value="42" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
++ <value value="43" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
++ <value value="44" name="PERF_SP_VS_INSTRUCTIONS"/>
++ <value value="45" name="PERF_SP_FS_INSTRUCTIONS"/>
++ <value value="46" name="PERF_SP_ADDR_LOCK_COUNT"/>
++ <value value="47" name="PERF_SP_UCHE_READ_TRANS"/>
++ <value value="48" name="PERF_SP_UCHE_WRITE_TRANS"/>
++ <value value="49" name="PERF_SP_EXPORT_VPC_TRANS"/>
++ <value value="50" name="PERF_SP_EXPORT_RB_TRANS"/>
++ <value value="51" name="PERF_SP_PIXELS_KILLED"/>
++ <value value="52" name="PERF_SP_ICL1_REQUESTS"/>
++ <value value="53" name="PERF_SP_ICL1_MISSES"/>
++ <value value="54" name="PERF_SP_ICL0_REQUESTS"/>
++ <value value="55" name="PERF_SP_ICL0_MISSES"/>
++ <value value="56" name="PERF_SP_HS_INSTRUCTIONS"/>
++ <value value="57" name="PERF_SP_DS_INSTRUCTIONS"/>
++ <value value="58" name="PERF_SP_GS_INSTRUCTIONS"/>
++ <value value="59" name="PERF_SP_CS_INSTRUCTIONS"/>
++ <value value="60" name="PERF_SP_GPR_READ"/>
++ <value value="61" name="PERF_SP_GPR_WRITE"/>
++ <value value="62" name="PERF_SP_LM_CH0_REQUESTS"/>
++ <value value="63" name="PERF_SP_LM_CH1_REQUESTS"/>
++ <value value="64" name="PERF_SP_LM_BANK_CONFLICTS"/>
++</enum>
++
++<enum name="a5xx_rb_perfcounter_select">
++ <value value="0" name="PERF_RB_BUSY_CYCLES"/>
++ <value value="1" name="PERF_RB_STALL_CYCLES_CCU"/>
++ <value value="2" name="PERF_RB_STALL_CYCLES_HLSQ"/>
++ <value value="3" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
++ <value value="4" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
++ <value value="5" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
++ <value value="6" name="PERF_RB_STARVE_CYCLES_SP"/>
++ <value value="7" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
++ <value value="8" name="PERF_RB_STARVE_CYCLES_CCU"/>
++ <value value="9" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
++ <value value="10" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
++ <value value="11" name="PERF_RB_Z_WORKLOAD"/>
++ <value value="12" name="PERF_RB_HLSQ_ACTIVE"/>
++ <value value="13" name="PERF_RB_Z_READ"/>
++ <value value="14" name="PERF_RB_Z_WRITE"/>
++ <value value="15" name="PERF_RB_C_READ"/>
++ <value value="16" name="PERF_RB_C_WRITE"/>
++ <value value="17" name="PERF_RB_TOTAL_PASS"/>
++ <value value="18" name="PERF_RB_Z_PASS"/>
++ <value value="19" name="PERF_RB_Z_FAIL"/>
++ <value value="20" name="PERF_RB_S_FAIL"/>
++ <value value="21" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
++ <value value="22" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
++ <value value="23" name="RB_RESERVED"/>
++ <value value="24" name="PERF_RB_2D_ALIVE_CYCLES"/>
++ <value value="25" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
++ <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
++ <value value="27" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
++ <value value="28" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
++ <value value="29" name="PERF_RB_2D_VALID_PIXELS"/>
++</enum>
++
++<enum name="a5xx_rb_samples_perfcounter_select">
++ <value value="0" name="TOTAL_SAMPLES"/>
++ <value value="1" name="ZPASS_SAMPLES"/>
++ <value value="2" name="ZFAIL_SAMPLES"/>
++ <value value="3" name="SFAIL_SAMPLES"/>
++</enum>
++
++<enum name="a5xx_vsc_perfcounter_select">
++ <value value="0" name="PERF_VSC_BUSY_CYCLES"/>
++ <value value="1" name="PERF_VSC_WORKING_CYCLES"/>
++ <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
++ <value value="3" name="PERF_VSC_EOT_NUM"/>
++</enum>
++
++<enum name="a5xx_ccu_perfcounter_select">
++ <value value="0" name="PERF_CCU_BUSY_CYCLES"/>
++ <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
++ <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
++ <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
++ <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
++ <value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
++ <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
++ <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
++ <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
++ <value value="9" name="PERF_CCU_GMEM_READ"/>
++ <value value="10" name="PERF_CCU_GMEM_WRITE"/>
++ <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
++ <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
++ <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
++ <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
++ <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
++ <value value="16" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
++ <value value="17" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
++ <value value="18" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
++ <value value="19" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
++ <value value="20" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
++ <value value="21" name="PERF_CCU_2D_BUSY_CYCLES"/>
++ <value value="22" name="PERF_CCU_2D_RD_REQ"/>
++ <value value="23" name="PERF_CCU_2D_WR_REQ"/>
++ <value value="24" name="PERF_CCU_2D_REORDER_STARVE_CYCLES"/>
++ <value value="25" name="PERF_CCU_2D_PIXELS"/>
++</enum>
++
++<enum name="a5xx_cmp_perfcounter_select">
++ <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_VBIF"/>
++ <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
++ <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
++ <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
++ <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
++ <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
++ <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
++ <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
++ <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
++ <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
++ <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
++ <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
++ <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
++ <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
++ <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
++ <value value="15" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
++ <value value="16" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
++ <value value="17" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
++ <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
++ <value value="19" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
++ <value value="20" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
++ <value value="21" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
++ <value value="22" name="PERF_CMPDECMP_2D_RD_DATA"/>
++ <value value="23" name="PERF_CMPDECMP_2D_WR_DATA"/>
++</enum>
++
++<enum name="a5xx_vbif_perfcounter_select">
++ <value value="0" name="AXI_READ_REQUESTS_ID_0"/>
++ <value value="1" name="AXI_READ_REQUESTS_ID_1"/>
++ <value value="2" name="AXI_READ_REQUESTS_ID_2"/>
++ <value value="3" name="AXI_READ_REQUESTS_ID_3"/>
++ <value value="4" name="AXI_READ_REQUESTS_ID_4"/>
++ <value value="5" name="AXI_READ_REQUESTS_ID_5"/>
++ <value value="6" name="AXI_READ_REQUESTS_ID_6"/>
++ <value value="7" name="AXI_READ_REQUESTS_ID_7"/>
++ <value value="8" name="AXI_READ_REQUESTS_ID_8"/>
++ <value value="9" name="AXI_READ_REQUESTS_ID_9"/>
++ <value value="10" name="AXI_READ_REQUESTS_ID_10"/>
++ <value value="11" name="AXI_READ_REQUESTS_ID_11"/>
++ <value value="12" name="AXI_READ_REQUESTS_ID_12"/>
++ <value value="13" name="AXI_READ_REQUESTS_ID_13"/>
++ <value value="14" name="AXI_READ_REQUESTS_ID_14"/>
++ <value value="15" name="AXI_READ_REQUESTS_ID_15"/>
++ <value value="16" name="AXI0_READ_REQUESTS_TOTAL"/>
++ <value value="17" name="AXI1_READ_REQUESTS_TOTAL"/>
++ <value value="18" name="AXI2_READ_REQUESTS_TOTAL"/>
++ <value value="19" name="AXI3_READ_REQUESTS_TOTAL"/>
++ <value value="20" name="AXI_READ_REQUESTS_TOTAL"/>
++ <value value="21" name="AXI_WRITE_REQUESTS_ID_0"/>
++ <value value="22" name="AXI_WRITE_REQUESTS_ID_1"/>
++ <value value="23" name="AXI_WRITE_REQUESTS_ID_2"/>
++ <value value="24" name="AXI_WRITE_REQUESTS_ID_3"/>
++ <value value="25" name="AXI_WRITE_REQUESTS_ID_4"/>
++ <value value="26" name="AXI_WRITE_REQUESTS_ID_5"/>
++ <value value="27" name="AXI_WRITE_REQUESTS_ID_6"/>
++ <value value="28" name="AXI_WRITE_REQUESTS_ID_7"/>
++ <value value="29" name="AXI_WRITE_REQUESTS_ID_8"/>
++ <value value="30" name="AXI_WRITE_REQUESTS_ID_9"/>
++ <value value="31" name="AXI_WRITE_REQUESTS_ID_10"/>
++ <value value="32" name="AXI_WRITE_REQUESTS_ID_11"/>
++ <value value="33" name="AXI_WRITE_REQUESTS_ID_12"/>
++ <value value="34" name="AXI_WRITE_REQUESTS_ID_13"/>
++ <value value="35" name="AXI_WRITE_REQUESTS_ID_14"/>
++ <value value="36" name="AXI_WRITE_REQUESTS_ID_15"/>
++ <value value="37" name="AXI0_WRITE_REQUESTS_TOTAL"/>
++ <value value="38" name="AXI1_WRITE_REQUESTS_TOTAL"/>
++ <value value="39" name="AXI2_WRITE_REQUESTS_TOTAL"/>
++ <value value="40" name="AXI3_WRITE_REQUESTS_TOTAL"/>
++ <value value="41" name="AXI_WRITE_REQUESTS_TOTAL"/>
++ <value value="42" name="AXI_TOTAL_REQUESTS"/>
++ <value value="43" name="AXI_READ_DATA_BEATS_ID_0"/>
++ <value value="44" name="AXI_READ_DATA_BEATS_ID_1"/>
++ <value value="45" name="AXI_READ_DATA_BEATS_ID_2"/>
++ <value value="46" name="AXI_READ_DATA_BEATS_ID_3"/>
++ <value value="47" name="AXI_READ_DATA_BEATS_ID_4"/>
++ <value value="48" name="AXI_READ_DATA_BEATS_ID_5"/>
++ <value value="49" name="AXI_READ_DATA_BEATS_ID_6"/>
++ <value value="50" name="AXI_READ_DATA_BEATS_ID_7"/>
++ <value value="51" name="AXI_READ_DATA_BEATS_ID_8"/>
++ <value value="52" name="AXI_READ_DATA_BEATS_ID_9"/>
++ <value value="53" name="AXI_READ_DATA_BEATS_ID_10"/>
++ <value value="54" name="AXI_READ_DATA_BEATS_ID_11"/>
++ <value value="55" name="AXI_READ_DATA_BEATS_ID_12"/>
++ <value value="56" name="AXI_READ_DATA_BEATS_ID_13"/>
++ <value value="57" name="AXI_READ_DATA_BEATS_ID_14"/>
++ <value value="58" name="AXI_READ_DATA_BEATS_ID_15"/>
++ <value value="59" name="AXI0_READ_DATA_BEATS_TOTAL"/>
++ <value value="60" name="AXI1_READ_DATA_BEATS_TOTAL"/>
++ <value value="61" name="AXI2_READ_DATA_BEATS_TOTAL"/>
++ <value value="62" name="AXI3_READ_DATA_BEATS_TOTAL"/>
++ <value value="63" name="AXI_READ_DATA_BEATS_TOTAL"/>
++ <value value="64" name="AXI_WRITE_DATA_BEATS_ID_0"/>
++ <value value="65" name="AXI_WRITE_DATA_BEATS_ID_1"/>
++ <value value="66" name="AXI_WRITE_DATA_BEATS_ID_2"/>
++ <value value="67" name="AXI_WRITE_DATA_BEATS_ID_3"/>
++ <value value="68" name="AXI_WRITE_DATA_BEATS_ID_4"/>
++ <value value="69" name="AXI_WRITE_DATA_BEATS_ID_5"/>
++ <value value="70" name="AXI_WRITE_DATA_BEATS_ID_6"/>
++ <value value="71" name="AXI_WRITE_DATA_BEATS_ID_7"/>
++ <value value="72" name="AXI_WRITE_DATA_BEATS_ID_8"/>
++ <value value="73" name="AXI_WRITE_DATA_BEATS_ID_9"/>
++ <value value="74" name="AXI_WRITE_DATA_BEATS_ID_10"/>
++ <value value="75" name="AXI_WRITE_DATA_BEATS_ID_11"/>
++ <value value="76" name="AXI_WRITE_DATA_BEATS_ID_12"/>
++ <value value="77" name="AXI_WRITE_DATA_BEATS_ID_13"/>
++ <value value="78" name="AXI_WRITE_DATA_BEATS_ID_14"/>
++ <value value="79" name="AXI_WRITE_DATA_BEATS_ID_15"/>
++ <value value="80" name="AXI0_WRITE_DATA_BEATS_TOTAL"/>
++ <value value="81" name="AXI1_WRITE_DATA_BEATS_TOTAL"/>
++ <value value="82" name="AXI2_WRITE_DATA_BEATS_TOTAL"/>
++ <value value="83" name="AXI3_WRITE_DATA_BEATS_TOTAL"/>
++ <value value="84" name="AXI_WRITE_DATA_BEATS_TOTAL"/>
++ <value value="85" name="AXI_DATA_BEATS_TOTAL"/>
++</enum>
++
++<domain name="A5XX" width="32">
++ <bitset name="A5XX_INT0">
++ <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
++ <bitfield name="RBBM_AHB_ERROR" pos="1" type="boolean"/>
++ <bitfield name="RBBM_TRANSFER_TIMEOUT" pos="2" type="boolean"/>
++ <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3" type="boolean"/>
++ <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4" type="boolean"/>
++ <bitfield name="RBBM_ETS_MS_TIMEOUT" pos="5" type="boolean"/>
++ <bitfield name="RBBM_ATB_ASYNC_OVERFLOW" pos="6" type="boolean"/>
++ <bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>
++ <bitfield name="CP_SW" pos="8" type="boolean"/>
++ <bitfield name="CP_HW_ERROR" pos="9" type="boolean"/>
++ <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/>
++ <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/>
++ <bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/>
++ <bitfield name="CP_IB2" pos="13" type="boolean"/>
++ <bitfield name="CP_IB1" pos="14" type="boolean"/>
++ <bitfield name="CP_RB" pos="15" type="boolean"/>
++ <bitfield name="CP_UNUSED_1" pos="16" type="boolean"/>
++ <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
++ <bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/>
++ <bitfield name="UNKNOWN_1" pos="19" type="boolean"/>
++ <bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/>
++ <bitfield name="UNUSED_2" pos="21" type="boolean"/>
++ <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/>
++ <bitfield name="MISC_HANG_DETECT" pos="23" type="boolean"/>
++ <bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/>
++ <bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/>
++ <bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/>
++ <bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/>
++ <bitfield name="GPMU_VOLTAGE_DROOP" pos="28" type="boolean"/>
++ <bitfield name="GPMU_FIRMWARE" pos="29" type="boolean"/>
++ <bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/>
++ <bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/>
++ </bitset>
++
++ <!-- CP Interrupt bits -->
++ <bitset name="A5XX_CP_INT">
++ <bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/>
++ <bitfield name="CP_RESERVED_BIT_ERROR" pos="1" type="boolean"/>
++ <bitfield name="CP_HW_FAULT_ERROR" pos="2" type="boolean"/>
++ <bitfield name="CP_DMA_ERROR" pos="3" type="boolean"/>
++ <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4" type="boolean"/>
++ <bitfield name="CP_AHB_ERROR" pos="5" type="boolean"/>
++ </bitset>
++
++ <!-- CP registers -->
++ <reg32 offset="0x0800" name="CP_RB_BASE"/>
++ <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
++ <reg32 offset="0x0802" name="CP_RB_CNTL"/>
++ <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
++ <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
++ <reg32 offset="0x0806" name="CP_RB_RPTR"/>
++ <reg32 offset="0x0807" name="CP_RB_WPTR"/>
++ <reg32 offset="0x0808" name="CP_PFP_STAT_ADDR"/>
++ <reg32 offset="0x0809" name="CP_PFP_STAT_DATA"/>
++ <reg32 offset="0x080b" name="CP_DRAW_STATE_ADDR"/>
++ <reg32 offset="0x080c" name="CP_DRAW_STATE_DATA"/>
++ <reg32 offset="0x080d" name="CP_ME_NRT_ADDR_LO"/>
++ <reg32 offset="0x080e" name="CP_ME_NRT_ADDR_HI"/>
++ <reg32 offset="0x0810" name="CP_ME_NRT_DATA"/>
++ <reg32 offset="0x0817" name="CP_CRASH_SCRIPT_BASE_LO"/>
++ <reg32 offset="0x0818" name="CP_CRASH_SCRIPT_BASE_HI"/>
++ <reg32 offset="0x0819" name="CP_CRASH_DUMP_CNTL"/>
++ <reg32 offset="0x081a" name="CP_ME_STAT_ADDR"/>
++ <reg32 offset="0x081f" name="CP_ROQ_THRESHOLDS_1"/>
++ <reg32 offset="0x0820" name="CP_ROQ_THRESHOLDS_2"/>
++ <reg32 offset="0x0821" name="CP_ROQ_DBG_ADDR"/>
++ <reg32 offset="0x0822" name="CP_ROQ_DBG_DATA"/>
++ <reg32 offset="0x0823" name="CP_MEQ_DBG_ADDR"/>
++ <reg32 offset="0x0824" name="CP_MEQ_DBG_DATA"/>
++ <reg32 offset="0x0825" name="CP_MEQ_THRESHOLDS"/>
++ <reg32 offset="0x0826" name="CP_MERCIU_SIZE"/>
++ <reg32 offset="0x0827" name="CP_MERCIU_DBG_ADDR"/>
++ <reg32 offset="0x0828" name="CP_MERCIU_DBG_DATA_1"/>
++ <reg32 offset="0x0829" name="CP_MERCIU_DBG_DATA_2"/>
++ <reg32 offset="0x082a" name="CP_PFP_UCODE_DBG_ADDR"/>
++ <reg32 offset="0x082b" name="CP_PFP_UCODE_DBG_DATA"/>
++ <reg32 offset="0x082f" name="CP_ME_UCODE_DBG_ADDR"/>
++ <reg32 offset="0x0830" name="CP_ME_UCODE_DBG_DATA"/>
++ <reg32 offset="0x0831" name="CP_CNTL"/>
++ <reg32 offset="0x0832" name="CP_PFP_ME_CNTL"/>
++ <reg32 offset="0x0833" name="CP_CHICKEN_DBG"/>
++ <reg32 offset="0x0835" name="CP_PFP_INSTR_BASE_LO"/>
++ <reg32 offset="0x0836" name="CP_PFP_INSTR_BASE_HI"/>
++ <reg32 offset="0x0838" name="CP_ME_INSTR_BASE_LO"/>
++ <reg32 offset="0x0839" name="CP_ME_INSTR_BASE_HI"/>
++ <reg32 offset="0x083b" name="CP_CONTEXT_SWITCH_CNTL"/>
++ <reg32 offset="0x083c" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_LO"/>
++ <reg32 offset="0x083d" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_HI"/>
++ <reg32 offset="0x083e" name="CP_CONTEXT_SWITCH_SAVE_ADDR_LO"/>
++ <reg32 offset="0x083f" name="CP_CONTEXT_SWITCH_SAVE_ADDR_HI"/>
++ <reg32 offset="0x0840" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
++ <reg32 offset="0x0841" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
++ <reg32 offset="0x0860" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++ <reg32 offset="0x0b14" name="CP_ME_STAT_DATA"/>
++ <reg32 offset="0x0b15" name="CP_WFI_PEND_CTR"/>
++ <reg32 offset="0x0b18" name="CP_INTERRUPT_STATUS"/>
++ <reg32 offset="0x0b1a" name="CP_HW_FAULT"/>
++ <reg32 offset="0x0b1c" name="CP_PROTECT_STATUS"/>
++ <reg32 offset="0x0b1f" name="CP_IB1_BASE"/>
++ <reg32 offset="0x0b20" name="CP_IB1_BASE_HI"/>
++ <reg32 offset="0x0b21" name="CP_IB1_BUFSZ"/>
++ <reg32 offset="0x0b22" name="CP_IB2_BASE"/>
++ <reg32 offset="0x0b23" name="CP_IB2_BASE_HI"/>
++ <reg32 offset="0x0b24" name="CP_IB2_BUFSZ"/>
++ <array offset="0x0b78" name="CP_SCRATCH" stride="1" length="8">
++ <reg32 offset="0x0" name="REG" type="uint"/>
++ </array>
++ <array offset="0x0880" name="CP_PROTECT" stride="1" length="32">
++ <reg32 offset="0x0" name="REG" type="adreno_cp_protect"/>
++ </array>
++ <reg32 offset="0x08a0" name="CP_PROTECT_CNTL"/>
++ <reg32 offset="0x0b1b" name="CP_AHB_FAULT"/>
++ <reg32 offset="0x0bb0" name="CP_PERFCTR_CP_SEL_0" type="a5xx_cp_perfcounter_select"/>
++ <reg32 offset="0x0bb1" name="CP_PERFCTR_CP_SEL_1" type="a5xx_cp_perfcounter_select"/>
++ <reg32 offset="0x0bb2" name="CP_PERFCTR_CP_SEL_2" type="a5xx_cp_perfcounter_select"/>
++ <reg32 offset="0x0bb3" name="CP_PERFCTR_CP_SEL_3" type="a5xx_cp_perfcounter_select"/>
++ <reg32 offset="0x0bb4" name="CP_PERFCTR_CP_SEL_4" type="a5xx_cp_perfcounter_select"/>
++ <reg32 offset="0x0bb5" name="CP_PERFCTR_CP_SEL_5" type="a5xx_cp_perfcounter_select"/>
++ <reg32 offset="0x0bb6" name="CP_PERFCTR_CP_SEL_6" type="a5xx_cp_perfcounter_select"/>
++ <reg32 offset="0x0bb7" name="CP_PERFCTR_CP_SEL_7" type="a5xx_cp_perfcounter_select"/>
++ <reg32 offset="0x0bc1" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++ <reg32 offset="0x0bba" name="CP_POWERCTR_CP_SEL_0"/>
++ <reg32 offset="0x0bbb" name="CP_POWERCTR_CP_SEL_1"/>
++ <reg32 offset="0x0bbc" name="CP_POWERCTR_CP_SEL_2"/>
++ <reg32 offset="0x0bbd" name="CP_POWERCTR_CP_SEL_3"/>
++
++ <!-- RBBM registers -->
++ <reg32 offset="0x0004" name="RBBM_CFG_DBGBUS_SEL_A"/>
++ <reg32 offset="0x0005" name="RBBM_CFG_DBGBUS_SEL_B"/>
++ <reg32 offset="0x0006" name="RBBM_CFG_DBGBUS_SEL_C"/>
++ <reg32 offset="0x0007" name="RBBM_CFG_DBGBUS_SEL_D"/>
++<!--
++#define A5XX_RBBM_CFG_DBGBUS_SEL_PING_INDEX_SHIFT 0x0
++#define A5XX_RBBM_CFG_DBGBUS_SEL_PING_BLK_SEL_SHIFT 0x8
++#define A5XX_RBBM_CFG_DBGBUS_SEL_PONG_INDEX_SHIFT 0x10
++#define A5XX_RBBM_CFG_DBGBUS_SEL_PONG_BLK_SEL_SHIFT 0x18
++ -->
++ <reg32 offset="0x0008" name="RBBM_CFG_DBGBUS_CNTLT"/>
++ <reg32 offset="0x0009" name="RBBM_CFG_DBGBUS_CNTLM"/>
++ <reg32 offset="0x0018" name="RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT"/>
++ <reg32 offset="0x000a" name="RBBM_CFG_DBGBUS_OPL"/>
++ <reg32 offset="0x000b" name="RBBM_CFG_DBGBUS_OPE"/>
++ <reg32 offset="0x000c" name="RBBM_CFG_DBGBUS_IVTL_0"/>
++ <reg32 offset="0x000d" name="RBBM_CFG_DBGBUS_IVTL_1"/>
++ <reg32 offset="0x000e" name="RBBM_CFG_DBGBUS_IVTL_2"/>
++ <reg32 offset="0x000f" name="RBBM_CFG_DBGBUS_IVTL_3"/>
++ <reg32 offset="0x0010" name="RBBM_CFG_DBGBUS_MASKL_0"/>
++ <reg32 offset="0x0011" name="RBBM_CFG_DBGBUS_MASKL_1"/>
++ <reg32 offset="0x0012" name="RBBM_CFG_DBGBUS_MASKL_2"/>
++ <reg32 offset="0x0013" name="RBBM_CFG_DBGBUS_MASKL_3"/>
++ <reg32 offset="0x0014" name="RBBM_CFG_DBGBUS_BYTEL_0"/>
++ <reg32 offset="0x0015" name="RBBM_CFG_DBGBUS_BYTEL_1"/>
++ <reg32 offset="0x0016" name="RBBM_CFG_DBGBUS_IVTE_0"/>
++ <reg32 offset="0x0017" name="RBBM_CFG_DBGBUS_IVTE_1"/>
++ <reg32 offset="0x0018" name="RBBM_CFG_DBGBUS_IVTE_2"/>
++ <reg32 offset="0x0019" name="RBBM_CFG_DBGBUS_IVTE_3"/>
++ <reg32 offset="0x001a" name="RBBM_CFG_DBGBUS_MASKE_0"/>
++ <reg32 offset="0x001b" name="RBBM_CFG_DBGBUS_MASKE_1"/>
++ <reg32 offset="0x001c" name="RBBM_CFG_DBGBUS_MASKE_2"/>
++ <reg32 offset="0x001d" name="RBBM_CFG_DBGBUS_MASKE_3"/>
++ <reg32 offset="0x001e" name="RBBM_CFG_DBGBUS_NIBBLEE"/>
++ <reg32 offset="0x001f" name="RBBM_CFG_DBGBUS_PTRC0"/>
++ <reg32 offset="0x0020" name="RBBM_CFG_DBGBUS_PTRC1"/>
++ <reg32 offset="0x0021" name="RBBM_CFG_DBGBUS_LOADREG"/>
++ <reg32 offset="0x0022" name="RBBM_CFG_DBGBUS_IDX"/>
++ <reg32 offset="0x0023" name="RBBM_CFG_DBGBUS_CLRC"/>
++ <reg32 offset="0x0024" name="RBBM_CFG_DBGBUS_LOADIVT"/>
++ <reg32 offset="0x002f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
++ <reg32 offset="0x0037" name="RBBM_INT_CLEAR_CMD"/>
++ <reg32 offset="0x0038" name="RBBM_INT_0_MASK">
++ <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
++ <bitfield name="RBBM_AHB_ERROR" pos="1" type="boolean"/>
++ <bitfield name="RBBM_TRANSFER_TIMEOUT" pos="2" type="boolean"/>
++ <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3" type="boolean"/>
++ <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4" type="boolean"/>
++ <bitfield name="RBBM_ETS_MS_TIMEOUT" pos="5" type="boolean"/>
++ <bitfield name="RBBM_ATB_ASYNC_OVERFLOW" pos="6" type="boolean"/>
++ <bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>
++ <bitfield name="CP_SW" pos="8" type="boolean"/>
++ <bitfield name="CP_HW_ERROR" pos="9" type="boolean"/>
++ <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/>
++ <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/>
++ <bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/>
++ <bitfield name="CP_IB2" pos="13" type="boolean"/>
++ <bitfield name="CP_IB1" pos="14" type="boolean"/>
++ <bitfield name="CP_RB" pos="15" type="boolean"/>
++ <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
++ <bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/>
++ <bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/>
++ <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/>
++ <bitfield name="MISC_HANG_DETECT" pos="23" type="boolean"/>
++ <bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/>
++ <bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/>
++ <bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/>
++ <bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/>
++ <bitfield name="GPMU_VOLTAGE_DROOP" pos="28" type="boolean"/>
++ <bitfield name="GPMU_FIRMWARE" pos="29" type="boolean"/>
++ <bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/>
++ <bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x003f" name="RBBM_AHB_DBG_CNTL"/>
++ <reg32 offset="0x0041" name="RBBM_EXT_VBIF_DBG_CNTL"/>
++ <reg32 offset="0x0043" name="RBBM_SW_RESET_CMD"/>
++ <reg32 offset="0x0045" name="RBBM_BLOCK_SW_RESET_CMD"/>
++ <reg32 offset="0x0046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
++ <reg32 offset="0x0048" name="RBBM_DBG_LO_HI_GPIO"/>
++ <reg32 offset="0x0049" name="RBBM_EXT_TRACE_BUS_CNTL"/>
++ <reg32 offset="0x004a" name="RBBM_CLOCK_CNTL_TP0"/>
++ <reg32 offset="0x004b" name="RBBM_CLOCK_CNTL_TP1"/>
++ <reg32 offset="0x004c" name="RBBM_CLOCK_CNTL_TP2"/>
++ <reg32 offset="0x004d" name="RBBM_CLOCK_CNTL_TP3"/>
++ <reg32 offset="0x004e" name="RBBM_CLOCK_CNTL2_TP0"/>
++ <reg32 offset="0x004f" name="RBBM_CLOCK_CNTL2_TP1"/>
++ <reg32 offset="0x0050" name="RBBM_CLOCK_CNTL2_TP2"/>
++ <reg32 offset="0x0051" name="RBBM_CLOCK_CNTL2_TP3"/>
++ <reg32 offset="0x0052" name="RBBM_CLOCK_CNTL3_TP0"/>
++ <reg32 offset="0x0053" name="RBBM_CLOCK_CNTL3_TP1"/>
++ <reg32 offset="0x0054" name="RBBM_CLOCK_CNTL3_TP2"/>
++ <reg32 offset="0x0055" name="RBBM_CLOCK_CNTL3_TP3"/>
++ <reg32 offset="0x0059" name="RBBM_READ_AHB_THROUGH_DBG"/>
++ <reg32 offset="0x005a" name="RBBM_CLOCK_CNTL_UCHE"/>
++ <reg32 offset="0x005b" name="RBBM_CLOCK_CNTL2_UCHE"/>
++ <reg32 offset="0x005c" name="RBBM_CLOCK_CNTL3_UCHE"/>
++ <reg32 offset="0x005d" name="RBBM_CLOCK_CNTL4_UCHE"/>
++ <reg32 offset="0x005e" name="RBBM_CLOCK_HYST_UCHE"/>
++ <reg32 offset="0x005f" name="RBBM_CLOCK_DELAY_UCHE"/>
++ <reg32 offset="0x0060" name="RBBM_CLOCK_MODE_GPC"/>
++ <reg32 offset="0x0061" name="RBBM_CLOCK_DELAY_GPC"/>
++ <reg32 offset="0x0062" name="RBBM_CLOCK_HYST_GPC"/>
++ <reg32 offset="0x0063" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
++ <reg32 offset="0x0064" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
++ <reg32 offset="0x0065" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
++ <reg32 offset="0x0066" name="RBBM_CLOCK_DELAY_HLSQ"/>
++ <reg32 offset="0x0067" name="RBBM_CLOCK_CNTL"/>
++ <reg32 offset="0x0068" name="RBBM_CLOCK_CNTL_SP0"/>
++ <reg32 offset="0x0069" name="RBBM_CLOCK_CNTL_SP1"/>
++ <reg32 offset="0x006a" name="RBBM_CLOCK_CNTL_SP2"/>
++ <reg32 offset="0x006b" name="RBBM_CLOCK_CNTL_SP3"/>
++ <reg32 offset="0x006c" name="RBBM_CLOCK_CNTL2_SP0"/>
++ <reg32 offset="0x006d" name="RBBM_CLOCK_CNTL2_SP1"/>
++ <reg32 offset="0x006e" name="RBBM_CLOCK_CNTL2_SP2"/>
++ <reg32 offset="0x006f" name="RBBM_CLOCK_CNTL2_SP3"/>
++ <reg32 offset="0x0070" name="RBBM_CLOCK_HYST_SP0"/>
++ <reg32 offset="0x0071" name="RBBM_CLOCK_HYST_SP1"/>
++ <reg32 offset="0x0072" name="RBBM_CLOCK_HYST_SP2"/>
++ <reg32 offset="0x0073" name="RBBM_CLOCK_HYST_SP3"/>
++ <reg32 offset="0x0074" name="RBBM_CLOCK_DELAY_SP0"/>
++ <reg32 offset="0x0075" name="RBBM_CLOCK_DELAY_SP1"/>
++ <reg32 offset="0x0076" name="RBBM_CLOCK_DELAY_SP2"/>
++ <reg32 offset="0x0077" name="RBBM_CLOCK_DELAY_SP3"/>
++ <reg32 offset="0x0078" name="RBBM_CLOCK_CNTL_RB0"/>
++ <reg32 offset="0x0079" name="RBBM_CLOCK_CNTL_RB1"/>
++ <reg32 offset="0x007a" name="RBBM_CLOCK_CNTL_RB2"/>
++ <reg32 offset="0x007b" name="RBBM_CLOCK_CNTL_RB3"/>
++ <reg32 offset="0x007c" name="RBBM_CLOCK_CNTL2_RB0"/>
++ <reg32 offset="0x007d" name="RBBM_CLOCK_CNTL2_RB1"/>
++ <reg32 offset="0x007e" name="RBBM_CLOCK_CNTL2_RB2"/>
++ <reg32 offset="0x007f" name="RBBM_CLOCK_CNTL2_RB3"/>
++ <reg32 offset="0x0080" name="RBBM_CLOCK_HYST_RAC"/>
++ <reg32 offset="0x0081" name="RBBM_CLOCK_DELAY_RAC"/>
++ <reg32 offset="0x0082" name="RBBM_CLOCK_CNTL_CCU0"/>
++ <reg32 offset="0x0083" name="RBBM_CLOCK_CNTL_CCU1"/>
++ <reg32 offset="0x0084" name="RBBM_CLOCK_CNTL_CCU2"/>
++ <reg32 offset="0x0085" name="RBBM_CLOCK_CNTL_CCU3"/>
++ <reg32 offset="0x0086" name="RBBM_CLOCK_HYST_RB_CCU0"/>
++ <reg32 offset="0x0087" name="RBBM_CLOCK_HYST_RB_CCU1"/>
++ <reg32 offset="0x0088" name="RBBM_CLOCK_HYST_RB_CCU2"/>
++ <reg32 offset="0x0089" name="RBBM_CLOCK_HYST_RB_CCU3"/>
++ <reg32 offset="0x008a" name="RBBM_CLOCK_CNTL_RAC"/>
++ <reg32 offset="0x008b" name="RBBM_CLOCK_CNTL2_RAC"/>
++ <reg32 offset="0x008c" name="RBBM_CLOCK_DELAY_RB_CCU_L1_0"/>
++ <reg32 offset="0x008d" name="RBBM_CLOCK_DELAY_RB_CCU_L1_1"/>
++ <reg32 offset="0x008e" name="RBBM_CLOCK_DELAY_RB_CCU_L1_2"/>
++ <reg32 offset="0x008f" name="RBBM_CLOCK_DELAY_RB_CCU_L1_3"/>
++ <reg32 offset="0x0090" name="RBBM_CLOCK_HYST_VFD"/>
++ <reg32 offset="0x0091" name="RBBM_CLOCK_MODE_VFD"/>
++ <reg32 offset="0x0092" name="RBBM_CLOCK_DELAY_VFD"/>
++ <reg32 offset="0x0093" name="RBBM_AHB_CNTL0"/>
++ <reg32 offset="0x0094" name="RBBM_AHB_CNTL1"/>
++ <reg32 offset="0x0095" name="RBBM_AHB_CNTL2"/>
++ <reg32 offset="0x0096" name="RBBM_AHB_CMD"/>
++ <reg32 offset="0x009c" name="RBBM_INTERFACE_HANG_MASK_CNTL11"/>
++ <reg32 offset="0x009d" name="RBBM_INTERFACE_HANG_MASK_CNTL12"/>
++ <reg32 offset="0x009e" name="RBBM_INTERFACE_HANG_MASK_CNTL13"/>
++ <reg32 offset="0x009f" name="RBBM_INTERFACE_HANG_MASK_CNTL14"/>
++ <reg32 offset="0x00a0" name="RBBM_INTERFACE_HANG_MASK_CNTL15"/>
++ <reg32 offset="0x00a1" name="RBBM_INTERFACE_HANG_MASK_CNTL16"/>
++ <reg32 offset="0x00a2" name="RBBM_INTERFACE_HANG_MASK_CNTL17"/>
++ <reg32 offset="0x00a3" name="RBBM_INTERFACE_HANG_MASK_CNTL18"/>
++ <reg32 offset="0x00a4" name="RBBM_CLOCK_DELAY_TP0"/>
++ <reg32 offset="0x00a5" name="RBBM_CLOCK_DELAY_TP1"/>
++ <reg32 offset="0x00a6" name="RBBM_CLOCK_DELAY_TP2"/>
++ <reg32 offset="0x00a7" name="RBBM_CLOCK_DELAY_TP3"/>
++ <reg32 offset="0x00a8" name="RBBM_CLOCK_DELAY2_TP0"/>
++ <reg32 offset="0x00a9" name="RBBM_CLOCK_DELAY2_TP1"/>
++ <reg32 offset="0x00aa" name="RBBM_CLOCK_DELAY2_TP2"/>
++ <reg32 offset="0x00ab" name="RBBM_CLOCK_DELAY2_TP3"/>
++ <reg32 offset="0x00ac" name="RBBM_CLOCK_DELAY3_TP0"/>
++ <reg32 offset="0x00ad" name="RBBM_CLOCK_DELAY3_TP1"/>
++ <reg32 offset="0x00ae" name="RBBM_CLOCK_DELAY3_TP2"/>
++ <reg32 offset="0x00af" name="RBBM_CLOCK_DELAY3_TP3"/>
++ <reg32 offset="0x00b0" name="RBBM_CLOCK_HYST_TP0"/>
++ <reg32 offset="0x00b1" name="RBBM_CLOCK_HYST_TP1"/>
++ <reg32 offset="0x00b2" name="RBBM_CLOCK_HYST_TP2"/>
++ <reg32 offset="0x00b3" name="RBBM_CLOCK_HYST_TP3"/>
++ <reg32 offset="0x00b4" name="RBBM_CLOCK_HYST2_TP0"/>
++ <reg32 offset="0x00b5" name="RBBM_CLOCK_HYST2_TP1"/>
++ <reg32 offset="0x00b6" name="RBBM_CLOCK_HYST2_TP2"/>
++ <reg32 offset="0x00b7" name="RBBM_CLOCK_HYST2_TP3"/>
++ <reg32 offset="0x00b8" name="RBBM_CLOCK_HYST3_TP0"/>
++ <reg32 offset="0x00b9" name="RBBM_CLOCK_HYST3_TP1"/>
++ <reg32 offset="0x00ba" name="RBBM_CLOCK_HYST3_TP2"/>
++ <reg32 offset="0x00bb" name="RBBM_CLOCK_HYST3_TP3"/>
++ <reg32 offset="0x00c8" name="RBBM_CLOCK_CNTL_GPMU"/>
++ <reg32 offset="0x00c9" name="RBBM_CLOCK_DELAY_GPMU"/>
++ <reg32 offset="0x00ca" name="RBBM_CLOCK_HYST_GPMU"/>
++ <reg32 offset="0x03a0" name="RBBM_PERFCTR_CP_0_LO"/>
++ <reg32 offset="0x03a1" name="RBBM_PERFCTR_CP_0_HI"/>
++ <reg32 offset="0x03a2" name="RBBM_PERFCTR_CP_1_LO"/>
++ <reg32 offset="0x03a3" name="RBBM_PERFCTR_CP_1_HI"/>
++ <reg32 offset="0x03a4" name="RBBM_PERFCTR_CP_2_LO"/>
++ <reg32 offset="0x03a5" name="RBBM_PERFCTR_CP_2_HI"/>
++ <reg32 offset="0x03a6" name="RBBM_PERFCTR_CP_3_LO"/>
++ <reg32 offset="0x03a7" name="RBBM_PERFCTR_CP_3_HI"/>
++ <reg32 offset="0x03a8" name="RBBM_PERFCTR_CP_4_LO"/>
++ <reg32 offset="0x03a9" name="RBBM_PERFCTR_CP_4_HI"/>
++ <reg32 offset="0x03aa" name="RBBM_PERFCTR_CP_5_LO"/>
++ <reg32 offset="0x03ab" name="RBBM_PERFCTR_CP_5_HI"/>
++ <reg32 offset="0x03ac" name="RBBM_PERFCTR_CP_6_LO"/>
++ <reg32 offset="0x03ad" name="RBBM_PERFCTR_CP_6_HI"/>
++ <reg32 offset="0x03ae" name="RBBM_PERFCTR_CP_7_LO"/>
++ <reg32 offset="0x03af" name="RBBM_PERFCTR_CP_7_HI"/>
++ <reg32 offset="0x03b0" name="RBBM_PERFCTR_RBBM_0_LO"/>
++ <reg32 offset="0x03b1" name="RBBM_PERFCTR_RBBM_0_HI"/>
++ <reg32 offset="0x03b2" name="RBBM_PERFCTR_RBBM_1_LO"/>
++ <reg32 offset="0x03b3" name="RBBM_PERFCTR_RBBM_1_HI"/>
++ <reg32 offset="0x03b4" name="RBBM_PERFCTR_RBBM_2_LO"/>
++ <reg32 offset="0x03b5" name="RBBM_PERFCTR_RBBM_2_HI"/>
++ <reg32 offset="0x03b6" name="RBBM_PERFCTR_RBBM_3_LO"/>
++ <reg32 offset="0x03b7" name="RBBM_PERFCTR_RBBM_3_HI"/>
++ <reg32 offset="0x03b8" name="RBBM_PERFCTR_PC_0_LO"/>
++ <reg32 offset="0x03b9" name="RBBM_PERFCTR_PC_0_HI"/>
++ <reg32 offset="0x03ba" name="RBBM_PERFCTR_PC_1_LO"/>
++ <reg32 offset="0x03bb" name="RBBM_PERFCTR_PC_1_HI"/>
++ <reg32 offset="0x03bc" name="RBBM_PERFCTR_PC_2_LO"/>
++ <reg32 offset="0x03bd" name="RBBM_PERFCTR_PC_2_HI"/>
++ <reg32 offset="0x03be" name="RBBM_PERFCTR_PC_3_LO"/>
++ <reg32 offset="0x03bf" name="RBBM_PERFCTR_PC_3_HI"/>
++ <reg32 offset="0x03c0" name="RBBM_PERFCTR_PC_4_LO"/>
++ <reg32 offset="0x03c1" name="RBBM_PERFCTR_PC_4_HI"/>
++ <reg32 offset="0x03c2" name="RBBM_PERFCTR_PC_5_LO"/>
++ <reg32 offset="0x03c3" name="RBBM_PERFCTR_PC_5_HI"/>
++ <reg32 offset="0x03c4" name="RBBM_PERFCTR_PC_6_LO"/>
++ <reg32 offset="0x03c5" name="RBBM_PERFCTR_PC_6_HI"/>
++ <reg32 offset="0x03c6" name="RBBM_PERFCTR_PC_7_LO"/>
++ <reg32 offset="0x03c7" name="RBBM_PERFCTR_PC_7_HI"/>
++ <reg32 offset="0x03c8" name="RBBM_PERFCTR_VFD_0_LO"/>
++ <reg32 offset="0x03c9" name="RBBM_PERFCTR_VFD_0_HI"/>
++ <reg32 offset="0x03ca" name="RBBM_PERFCTR_VFD_1_LO"/>
++ <reg32 offset="0x03cb" name="RBBM_PERFCTR_VFD_1_HI"/>
++ <reg32 offset="0x03cc" name="RBBM_PERFCTR_VFD_2_LO"/>
++ <reg32 offset="0x03cd" name="RBBM_PERFCTR_VFD_2_HI"/>
++ <reg32 offset="0x03ce" name="RBBM_PERFCTR_VFD_3_LO"/>
++ <reg32 offset="0x03cf" name="RBBM_PERFCTR_VFD_3_HI"/>
++ <reg32 offset="0x03d0" name="RBBM_PERFCTR_VFD_4_LO"/>
++ <reg32 offset="0x03d1" name="RBBM_PERFCTR_VFD_4_HI"/>
++ <reg32 offset="0x03d2" name="RBBM_PERFCTR_VFD_5_LO"/>
++ <reg32 offset="0x03d3" name="RBBM_PERFCTR_VFD_5_HI"/>
++ <reg32 offset="0x03d4" name="RBBM_PERFCTR_VFD_6_LO"/>
++ <reg32 offset="0x03d5" name="RBBM_PERFCTR_VFD_6_HI"/>
++ <reg32 offset="0x03d6" name="RBBM_PERFCTR_VFD_7_LO"/>
++ <reg32 offset="0x03d7" name="RBBM_PERFCTR_VFD_7_HI"/>
++ <reg32 offset="0x03d8" name="RBBM_PERFCTR_HLSQ_0_LO"/>
++ <reg32 offset="0x03d9" name="RBBM_PERFCTR_HLSQ_0_HI"/>
++ <reg32 offset="0x03da" name="RBBM_PERFCTR_HLSQ_1_LO"/>
++ <reg32 offset="0x03db" name="RBBM_PERFCTR_HLSQ_1_HI"/>
++ <reg32 offset="0x03dc" name="RBBM_PERFCTR_HLSQ_2_LO"/>
++ <reg32 offset="0x03dd" name="RBBM_PERFCTR_HLSQ_2_HI"/>
++ <reg32 offset="0x03de" name="RBBM_PERFCTR_HLSQ_3_LO"/>
++ <reg32 offset="0x03df" name="RBBM_PERFCTR_HLSQ_3_HI"/>
++ <reg32 offset="0x03e0" name="RBBM_PERFCTR_HLSQ_4_LO"/>
++ <reg32 offset="0x03e1" name="RBBM_PERFCTR_HLSQ_4_HI"/>
++ <reg32 offset="0x03e2" name="RBBM_PERFCTR_HLSQ_5_LO"/>
++ <reg32 offset="0x03e3" name="RBBM_PERFCTR_HLSQ_5_HI"/>
++ <reg32 offset="0x03e4" name="RBBM_PERFCTR_HLSQ_6_LO"/>
++ <reg32 offset="0x03e5" name="RBBM_PERFCTR_HLSQ_6_HI"/>
++ <reg32 offset="0x03e6" name="RBBM_PERFCTR_HLSQ_7_LO"/>
++ <reg32 offset="0x03e7" name="RBBM_PERFCTR_HLSQ_7_HI"/>
++ <reg32 offset="0x03e8" name="RBBM_PERFCTR_VPC_0_LO"/>
++ <reg32 offset="0x03e9" name="RBBM_PERFCTR_VPC_0_HI"/>
++ <reg32 offset="0x03ea" name="RBBM_PERFCTR_VPC_1_LO"/>
++ <reg32 offset="0x03eb" name="RBBM_PERFCTR_VPC_1_HI"/>
++ <reg32 offset="0x03ec" name="RBBM_PERFCTR_VPC_2_LO"/>
++ <reg32 offset="0x03ed" name="RBBM_PERFCTR_VPC_2_HI"/>
++ <reg32 offset="0x03ee" name="RBBM_PERFCTR_VPC_3_LO"/>
++ <reg32 offset="0x03ef" name="RBBM_PERFCTR_VPC_3_HI"/>
++ <reg32 offset="0x03f0" name="RBBM_PERFCTR_CCU_0_LO"/>
++ <reg32 offset="0x03f1" name="RBBM_PERFCTR_CCU_0_HI"/>
++ <reg32 offset="0x03f2" name="RBBM_PERFCTR_CCU_1_LO"/>
++ <reg32 offset="0x03f3" name="RBBM_PERFCTR_CCU_1_HI"/>
++ <reg32 offset="0x03f4" name="RBBM_PERFCTR_CCU_2_LO"/>
++ <reg32 offset="0x03f5" name="RBBM_PERFCTR_CCU_2_HI"/>
++ <reg32 offset="0x03f6" name="RBBM_PERFCTR_CCU_3_LO"/>
++ <reg32 offset="0x03f7" name="RBBM_PERFCTR_CCU_3_HI"/>
++ <reg32 offset="0x03f8" name="RBBM_PERFCTR_TSE_0_LO"/>
++ <reg32 offset="0x03f9" name="RBBM_PERFCTR_TSE_0_HI"/>
++ <reg32 offset="0x03fa" name="RBBM_PERFCTR_TSE_1_LO"/>
++ <reg32 offset="0x03fb" name="RBBM_PERFCTR_TSE_1_HI"/>
++ <reg32 offset="0x03fc" name="RBBM_PERFCTR_TSE_2_LO"/>
++ <reg32 offset="0x03fd" name="RBBM_PERFCTR_TSE_2_HI"/>
++ <reg32 offset="0x03fe" name="RBBM_PERFCTR_TSE_3_LO"/>
++ <reg32 offset="0x03ff" name="RBBM_PERFCTR_TSE_3_HI"/>
++ <reg32 offset="0x0400" name="RBBM_PERFCTR_RAS_0_LO"/>
++ <reg32 offset="0x0401" name="RBBM_PERFCTR_RAS_0_HI"/>
++ <reg32 offset="0x0402" name="RBBM_PERFCTR_RAS_1_LO"/>
++ <reg32 offset="0x0403" name="RBBM_PERFCTR_RAS_1_HI"/>
++ <reg32 offset="0x0404" name="RBBM_PERFCTR_RAS_2_LO"/>
++ <reg32 offset="0x0405" name="RBBM_PERFCTR_RAS_2_HI"/>
++ <reg32 offset="0x0406" name="RBBM_PERFCTR_RAS_3_LO"/>
++ <reg32 offset="0x0407" name="RBBM_PERFCTR_RAS_3_HI"/>
++ <reg32 offset="0x0408" name="RBBM_PERFCTR_UCHE_0_LO"/>
++ <reg32 offset="0x0409" name="RBBM_PERFCTR_UCHE_0_HI"/>
++ <reg32 offset="0x040a" name="RBBM_PERFCTR_UCHE_1_LO"/>
++ <reg32 offset="0x040b" name="RBBM_PERFCTR_UCHE_1_HI"/>
++ <reg32 offset="0x040c" name="RBBM_PERFCTR_UCHE_2_LO"/>
++ <reg32 offset="0x040d" name="RBBM_PERFCTR_UCHE_2_HI"/>
++ <reg32 offset="0x040e" name="RBBM_PERFCTR_UCHE_3_LO"/>
++ <reg32 offset="0x040f" name="RBBM_PERFCTR_UCHE_3_HI"/>
++ <reg32 offset="0x0410" name="RBBM_PERFCTR_UCHE_4_LO"/>
++ <reg32 offset="0x0411" name="RBBM_PERFCTR_UCHE_4_HI"/>
++ <reg32 offset="0x0412" name="RBBM_PERFCTR_UCHE_5_LO"/>
++ <reg32 offset="0x0413" name="RBBM_PERFCTR_UCHE_5_HI"/>
++ <reg32 offset="0x0414" name="RBBM_PERFCTR_UCHE_6_LO"/>
++ <reg32 offset="0x0415" name="RBBM_PERFCTR_UCHE_6_HI"/>
++ <reg32 offset="0x0416" name="RBBM_PERFCTR_UCHE_7_LO"/>
++ <reg32 offset="0x0417" name="RBBM_PERFCTR_UCHE_7_HI"/>
++ <reg32 offset="0x0418" name="RBBM_PERFCTR_TP_0_LO"/>
++ <reg32 offset="0x0419" name="RBBM_PERFCTR_TP_0_HI"/>
++ <reg32 offset="0x041a" name="RBBM_PERFCTR_TP_1_LO"/>
++ <reg32 offset="0x041b" name="RBBM_PERFCTR_TP_1_HI"/>
++ <reg32 offset="0x041c" name="RBBM_PERFCTR_TP_2_LO"/>
++ <reg32 offset="0x041d" name="RBBM_PERFCTR_TP_2_HI"/>
++ <reg32 offset="0x041e" name="RBBM_PERFCTR_TP_3_LO"/>
++ <reg32 offset="0x041f" name="RBBM_PERFCTR_TP_3_HI"/>
++ <reg32 offset="0x0420" name="RBBM_PERFCTR_TP_4_LO"/>
++ <reg32 offset="0x0421" name="RBBM_PERFCTR_TP_4_HI"/>
++ <reg32 offset="0x0422" name="RBBM_PERFCTR_TP_5_LO"/>
++ <reg32 offset="0x0423" name="RBBM_PERFCTR_TP_5_HI"/>
++ <reg32 offset="0x0424" name="RBBM_PERFCTR_TP_6_LO"/>
++ <reg32 offset="0x0425" name="RBBM_PERFCTR_TP_6_HI"/>
++ <reg32 offset="0x0426" name="RBBM_PERFCTR_TP_7_LO"/>
++ <reg32 offset="0x0427" name="RBBM_PERFCTR_TP_7_HI"/>
++ <reg32 offset="0x0428" name="RBBM_PERFCTR_SP_0_LO"/>
++ <reg32 offset="0x0429" name="RBBM_PERFCTR_SP_0_HI"/>
++ <reg32 offset="0x042a" name="RBBM_PERFCTR_SP_1_LO"/>
++ <reg32 offset="0x042b" name="RBBM_PERFCTR_SP_1_HI"/>
++ <reg32 offset="0x042c" name="RBBM_PERFCTR_SP_2_LO"/>
++ <reg32 offset="0x042d" name="RBBM_PERFCTR_SP_2_HI"/>
++ <reg32 offset="0x042e" name="RBBM_PERFCTR_SP_3_LO"/>
++ <reg32 offset="0x042f" name="RBBM_PERFCTR_SP_3_HI"/>
++ <reg32 offset="0x0430" name="RBBM_PERFCTR_SP_4_LO"/>
++ <reg32 offset="0x0431" name="RBBM_PERFCTR_SP_4_HI"/>
++ <reg32 offset="0x0432" name="RBBM_PERFCTR_SP_5_LO"/>
++ <reg32 offset="0x0433" name="RBBM_PERFCTR_SP_5_HI"/>
++ <reg32 offset="0x0434" name="RBBM_PERFCTR_SP_6_LO"/>
++ <reg32 offset="0x0435" name="RBBM_PERFCTR_SP_6_HI"/>
++ <reg32 offset="0x0436" name="RBBM_PERFCTR_SP_7_LO"/>
++ <reg32 offset="0x0437" name="RBBM_PERFCTR_SP_7_HI"/>
++ <reg32 offset="0x0438" name="RBBM_PERFCTR_SP_8_LO"/>
++ <reg32 offset="0x0439" name="RBBM_PERFCTR_SP_8_HI"/>
++ <reg32 offset="0x043a" name="RBBM_PERFCTR_SP_9_LO"/>
++ <reg32 offset="0x043b" name="RBBM_PERFCTR_SP_9_HI"/>
++ <reg32 offset="0x043c" name="RBBM_PERFCTR_SP_10_LO"/>
++ <reg32 offset="0x043d" name="RBBM_PERFCTR_SP_10_HI"/>
++ <reg32 offset="0x043e" name="RBBM_PERFCTR_SP_11_LO"/>
++ <reg32 offset="0x043f" name="RBBM_PERFCTR_SP_11_HI"/>
++ <reg32 offset="0x0440" name="RBBM_PERFCTR_RB_0_LO"/>
++ <reg32 offset="0x0441" name="RBBM_PERFCTR_RB_0_HI"/>
++ <reg32 offset="0x0442" name="RBBM_PERFCTR_RB_1_LO"/>
++ <reg32 offset="0x0443" name="RBBM_PERFCTR_RB_1_HI"/>
++ <reg32 offset="0x0444" name="RBBM_PERFCTR_RB_2_LO"/>
++ <reg32 offset="0x0445" name="RBBM_PERFCTR_RB_2_HI"/>
++ <reg32 offset="0x0446" name="RBBM_PERFCTR_RB_3_LO"/>
++ <reg32 offset="0x0447" name="RBBM_PERFCTR_RB_3_HI"/>
++ <reg32 offset="0x0448" name="RBBM_PERFCTR_RB_4_LO"/>
++ <reg32 offset="0x0449" name="RBBM_PERFCTR_RB_4_HI"/>
++ <reg32 offset="0x044a" name="RBBM_PERFCTR_RB_5_LO"/>
++ <reg32 offset="0x044b" name="RBBM_PERFCTR_RB_5_HI"/>
++ <reg32 offset="0x044c" name="RBBM_PERFCTR_RB_6_LO"/>
++ <reg32 offset="0x044d" name="RBBM_PERFCTR_RB_6_HI"/>
++ <reg32 offset="0x044e" name="RBBM_PERFCTR_RB_7_LO"/>
++ <reg32 offset="0x044f" name="RBBM_PERFCTR_RB_7_HI"/>
++ <reg32 offset="0x0450" name="RBBM_PERFCTR_VSC_0_LO"/>
++ <reg32 offset="0x0451" name="RBBM_PERFCTR_VSC_0_HI"/>
++ <reg32 offset="0x0452" name="RBBM_PERFCTR_VSC_1_LO"/>
++ <reg32 offset="0x0453" name="RBBM_PERFCTR_VSC_1_HI"/>
++ <reg32 offset="0x0454" name="RBBM_PERFCTR_LRZ_0_LO"/>
++ <reg32 offset="0x0455" name="RBBM_PERFCTR_LRZ_0_HI"/>
++ <reg32 offset="0x0456" name="RBBM_PERFCTR_LRZ_1_LO"/>
++ <reg32 offset="0x0457" name="RBBM_PERFCTR_LRZ_1_HI"/>
++ <reg32 offset="0x0458" name="RBBM_PERFCTR_LRZ_2_LO"/>
++ <reg32 offset="0x0459" name="RBBM_PERFCTR_LRZ_2_HI"/>
++ <reg32 offset="0x045a" name="RBBM_PERFCTR_LRZ_3_LO"/>
++ <reg32 offset="0x045b" name="RBBM_PERFCTR_LRZ_3_HI"/>
++ <reg32 offset="0x045c" name="RBBM_PERFCTR_CMP_0_LO"/>
++ <reg32 offset="0x045d" name="RBBM_PERFCTR_CMP_0_HI"/>
++ <reg32 offset="0x045e" name="RBBM_PERFCTR_CMP_1_LO"/>
++ <reg32 offset="0x045f" name="RBBM_PERFCTR_CMP_1_HI"/>
++ <reg32 offset="0x0460" name="RBBM_PERFCTR_CMP_2_LO"/>
++ <reg32 offset="0x0461" name="RBBM_PERFCTR_CMP_2_HI"/>
++ <reg32 offset="0x0462" name="RBBM_PERFCTR_CMP_3_LO"/>
++ <reg32 offset="0x0463" name="RBBM_PERFCTR_CMP_3_HI"/>
++ <reg32 offset="0x046b" name="RBBM_PERFCTR_RBBM_SEL_0" type="a5xx_rbbm_perfcounter_select"/>
++ <reg32 offset="0x046c" name="RBBM_PERFCTR_RBBM_SEL_1" type="a5xx_rbbm_perfcounter_select"/>
++ <reg32 offset="0x046d" name="RBBM_PERFCTR_RBBM_SEL_2" type="a5xx_rbbm_perfcounter_select"/>
++ <reg32 offset="0x046e" name="RBBM_PERFCTR_RBBM_SEL_3" type="a5xx_rbbm_perfcounter_select"/>
++ <reg32 offset="0x04d2" name="RBBM_ALWAYSON_COUNTER_LO"/>
++ <reg32 offset="0x04d3" name="RBBM_ALWAYSON_COUNTER_HI"/>
++ <reg32 offset="0x04f5" name="RBBM_STATUS">
++ <bitfield high="31" low="31" name="GPU_BUSY_IGN_AHB" />
++ <bitfield high="30" low="30" name="GPU_BUSY_IGN_AHB_CP" />
++ <bitfield high="29" low="29" name="HLSQ_BUSY" />
++ <bitfield high="28" low="28" name="VSC_BUSY" />
++ <bitfield high="27" low="27" name="TPL1_BUSY" />
++ <bitfield high="26" low="26" name="SP_BUSY" />
++ <bitfield high="25" low="25" name="UCHE_BUSY" />
++ <bitfield high="24" low="24" name="VPC_BUSY" />
++ <bitfield high="23" low="23" name="VFDP_BUSY" />
++ <bitfield high="22" low="22" name="VFD_BUSY" />
++ <bitfield high="21" low="21" name="TESS_BUSY" />
++ <bitfield high="20" low="20" name="PC_VSD_BUSY" />
++ <bitfield high="19" low="19" name="PC_DCALL_BUSY" />
++ <bitfield high="18" low="18" name="GPMU_SLAVE_BUSY" />
++ <bitfield high="17" low="17" name="DCOM_BUSY" />
++ <bitfield high="16" low="16" name="COM_BUSY" />
++ <bitfield high="15" low="15" name="LRZ_BUZY" />
++ <bitfield high="14" low="14" name="A2D_DSP_BUSY" />
++ <bitfield high="13" low="13" name="CCUFCHE_BUSY" />
++ <bitfield high="12" low="12" name="RB_BUSY" />
++ <bitfield high="11" low="11" name="RAS_BUSY" />
++ <bitfield high="10" low="10" name="TSE_BUSY" />
++ <bitfield high="9" low="9" name="VBIF_BUSY" />
++ <bitfield high="8" low="8" name="GPU_BUSY_IGN_AHB_HYST" />
++ <bitfield high="7" low="7" name="CP_BUSY_IGN_HYST" />
++ <bitfield high="6" low="6" name="CP_BUSY" />
++ <bitfield high="5" low="5" name="GPMU_MASTER_BUSY" />
++ <bitfield high="4" low="4" name="CP_CRASH_BUSY" />
++ <bitfield high="3" low="3" name="CP_ETS_BUSY" />
++ <bitfield high="2" low="2" name="CP_PFP_BUSY" />
++ <bitfield high="1" low="1" name="CP_ME_BUSY" />
++ <bitfield high="0" low="0" name="HI_BUSY" />
++ </reg32>
++ <reg32 offset="0x0530" name="RBBM_STATUS3">
++ <bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x04e1" name="RBBM_INT_0_STATUS"/>
++ <reg32 offset="0x04f0" name="RBBM_AHB_ME_SPLIT_STATUS"/>
++ <reg32 offset="0x04f1" name="RBBM_AHB_PFP_SPLIT_STATUS"/>
++ <reg32 offset="0x04f3" name="RBBM_AHB_ETS_SPLIT_STATUS"/>
++ <reg32 offset="0x04f4" name="RBBM_AHB_ERROR_STATUS"/>
++ <reg32 offset="0x0464" name="RBBM_PERFCTR_CNTL"/>
++ <reg32 offset="0x0465" name="RBBM_PERFCTR_LOAD_CMD0"/>
++ <reg32 offset="0x0466" name="RBBM_PERFCTR_LOAD_CMD1"/>
++ <reg32 offset="0x0467" name="RBBM_PERFCTR_LOAD_CMD2"/>
++ <reg32 offset="0x0468" name="RBBM_PERFCTR_LOAD_CMD3"/>
++ <reg32 offset="0x0469" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
++ <reg32 offset="0x046a" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
++ <reg32 offset="0x046f" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
++ <reg32 offset="0x04ed" name="RBBM_AHB_ERROR"/>
++ <reg32 offset="0x0504" name="RBBM_CFG_DBGBUS_EVENT_LOGIC"/>
++ <reg32 offset="0x0505" name="RBBM_CFG_DBGBUS_OVER"/>
++ <reg32 offset="0x0506" name="RBBM_CFG_DBGBUS_COUNT0"/>
++ <reg32 offset="0x0507" name="RBBM_CFG_DBGBUS_COUNT1"/>
++ <reg32 offset="0x0508" name="RBBM_CFG_DBGBUS_COUNT2"/>
++ <reg32 offset="0x0509" name="RBBM_CFG_DBGBUS_COUNT3"/>
++ <reg32 offset="0x050a" name="RBBM_CFG_DBGBUS_COUNT4"/>
++ <reg32 offset="0x050b" name="RBBM_CFG_DBGBUS_COUNT5"/>
++ <reg32 offset="0x050c" name="RBBM_CFG_DBGBUS_TRACE_ADDR"/>
++ <reg32 offset="0x050d" name="RBBM_CFG_DBGBUS_TRACE_BUF0"/>
++ <reg32 offset="0x050e" name="RBBM_CFG_DBGBUS_TRACE_BUF1"/>
++ <reg32 offset="0x050f" name="RBBM_CFG_DBGBUS_TRACE_BUF2"/>
++ <reg32 offset="0x0510" name="RBBM_CFG_DBGBUS_TRACE_BUF3"/>
++ <reg32 offset="0x0511" name="RBBM_CFG_DBGBUS_TRACE_BUF4"/>
++ <reg32 offset="0x0512" name="RBBM_CFG_DBGBUS_MISR0"/>
++ <reg32 offset="0x0513" name="RBBM_CFG_DBGBUS_MISR1"/>
++ <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
++ <reg32 offset="0xf000" name="RBBM_SECVID_TRUST_CONFIG"/>
++ <reg32 offset="0xf400" name="RBBM_SECVID_TRUST_CNTL"/>
++ <reg32 offset="0xf800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
++ <reg32 offset="0xf801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
++ <reg32 offset="0xf802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
++ <reg32 offset="0xf803" name="RBBM_SECVID_TSB_CNTL"/>
++ <reg32 offset="0xf804" name="RBBM_SECVID_TSB_COMP_STATUS_LO"/>
++ <reg32 offset="0xf805" name="RBBM_SECVID_TSB_COMP_STATUS_HI"/>
++ <reg32 offset="0xf806" name="RBBM_SECVID_TSB_UCHE_STATUS_LO"/>
++ <reg32 offset="0xf807" name="RBBM_SECVID_TSB_UCHE_STATUS_HI"/>
++ <reg32 offset="0xf810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++
++ <!-- VSC registers -->
++ <reg32 offset="0x0bc2" name="VSC_BIN_SIZE">
++ <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
++ <bitfield name="HEIGHT" low="9" high="16" shr="5" type="uint"/>
++ <!-- b17 maybe BYPASS like RB_CNTL, but reg not written for bypass -->
++ </reg32>
++ <reg32 offset="0x0bc3" name="VSC_SIZE_ADDRESS_LO"/>
++ <reg32 offset="0x0bc4" name="VSC_SIZE_ADDRESS_HI"/>
++ <reg32 offset="0x0bc5" name="UNKNOWN_0BC5"/> <!-- always 00000000? -->
++ <reg32 offset="0x0bc6" name="UNKNOWN_0BC6"/> <!-- always 00000000? -->
++ <array offset="0x0bd0" name="VSC_PIPE_CONFIG" stride="1" length="16">
++ <reg32 offset="0x0" name="REG">
++ <doc>
++ Configures the mapping between VSC_PIPE buffer and
++ bin, X/Y specify the bin index in the horiz/vert
++ direction (0,0 is upper left, 0,1 is leftmost bin
++ on second row, and so on). W/H specify the number
++ of bins assigned to this VSC_PIPE in the horiz/vert
++ dimension.
++ </doc>
++ <bitfield name="X" low="0" high="9" type="uint"/>
++ <bitfield name="Y" low="10" high="19" type="uint"/>
++ <bitfield name="W" low="20" high="23" type="uint"/>
++ <bitfield name="H" low="24" high="27" type="uint"/>
++ </reg32>
++ </array>
++ <array offset="0x0be0" name="VSC_PIPE_DATA_ADDRESS" stride="2" length="16">
++ <reg32 offset="0x0" name="LO"/>
++ <reg32 offset="0x1" name="HI"/>
++ </array>
++ <array offset="0x0c00" name="VSC_PIPE_DATA_LENGTH" stride="1" length="16">
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++ <reg32 offset="0x0c60" name="VSC_PERFCTR_VSC_SEL_0" type="a5xx_vsc_perfcounter_select"/>
++ <reg32 offset="0x0c61" name="VSC_PERFCTR_VSC_SEL_1" type="a5xx_vsc_perfcounter_select"/>
++
++ <!-- used for some blits?? -->
++ <reg32 offset="0x0cdd" name="VSC_RESOLVE_CNTL" type="adreno_reg_xy"/>
++
++ <!-- GRAS registers -->
++ <reg32 offset="0x0c81" name="GRAS_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++ <reg32 offset="0x0c90" name="GRAS_PERFCTR_TSE_SEL_0" type="a5xx_tse_perfcounter_select"/>
++ <reg32 offset="0x0c91" name="GRAS_PERFCTR_TSE_SEL_1" type="a5xx_tse_perfcounter_select"/>
++ <reg32 offset="0x0c92" name="GRAS_PERFCTR_TSE_SEL_2" type="a5xx_tse_perfcounter_select"/>
++ <reg32 offset="0x0c93" name="GRAS_PERFCTR_TSE_SEL_3" type="a5xx_tse_perfcounter_select"/>
++ <reg32 offset="0x0c94" name="GRAS_PERFCTR_RAS_SEL_0" type="a5xx_ras_perfcounter_select"/>
++ <reg32 offset="0x0c95" name="GRAS_PERFCTR_RAS_SEL_1" type="a5xx_ras_perfcounter_select"/>
++ <reg32 offset="0x0c96" name="GRAS_PERFCTR_RAS_SEL_2" type="a5xx_ras_perfcounter_select"/>
++ <reg32 offset="0x0c97" name="GRAS_PERFCTR_RAS_SEL_3" type="a5xx_ras_perfcounter_select"/>
++ <reg32 offset="0x0c98" name="GRAS_PERFCTR_LRZ_SEL_0" type="a5xx_lrz_perfcounter_select"/>
++ <reg32 offset="0x0c99" name="GRAS_PERFCTR_LRZ_SEL_1" type="a5xx_lrz_perfcounter_select"/>
++ <reg32 offset="0x0c9a" name="GRAS_PERFCTR_LRZ_SEL_2" type="a5xx_lrz_perfcounter_select"/>
++ <reg32 offset="0x0c9b" name="GRAS_PERFCTR_LRZ_SEL_3" type="a5xx_lrz_perfcounter_select"/>
++
++ <reg32 offset="0x0cc4" name="RB_DBG_ECO_CNTL"/> <!-- always 00100000? -->
++ <reg32 offset="0x0cc5" name="RB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++ <reg32 offset="0x0cc6" name="RB_MODE_CNTL"/> <!-- always 00000044? -->
++ <reg32 offset="0x0cc7" name="RB_CCU_CNTL"/> <!-- always b0056080 or 10000000? -->
++ <reg32 offset="0x0cd0" name="RB_PERFCTR_RB_SEL_0" type="a5xx_rb_perfcounter_select"/>
++ <reg32 offset="0x0cd1" name="RB_PERFCTR_RB_SEL_1" type="a5xx_rb_perfcounter_select"/>
++ <reg32 offset="0x0cd2" name="RB_PERFCTR_RB_SEL_2" type="a5xx_rb_perfcounter_select"/>
++ <reg32 offset="0x0cd3" name="RB_PERFCTR_RB_SEL_3" type="a5xx_rb_perfcounter_select"/>
++ <reg32 offset="0x0cd4" name="RB_PERFCTR_RB_SEL_4" type="a5xx_rb_perfcounter_select"/>
++ <reg32 offset="0x0cd5" name="RB_PERFCTR_RB_SEL_5" type="a5xx_rb_perfcounter_select"/>
++ <reg32 offset="0x0cd6" name="RB_PERFCTR_RB_SEL_6" type="a5xx_rb_perfcounter_select"/>
++ <reg32 offset="0x0cd7" name="RB_PERFCTR_RB_SEL_7" type="a5xx_rb_perfcounter_select"/>
++ <reg32 offset="0x0cd8" name="RB_PERFCTR_CCU_SEL_0" type="a5xx_ccu_perfcounter_select"/>
++ <reg32 offset="0x0cd9" name="RB_PERFCTR_CCU_SEL_1" type="a5xx_ccu_perfcounter_select"/>
++ <reg32 offset="0x0cda" name="RB_PERFCTR_CCU_SEL_2" type="a5xx_ccu_perfcounter_select"/>
++ <reg32 offset="0x0cdb" name="RB_PERFCTR_CCU_SEL_3" type="a5xx_ccu_perfcounter_select"/>
++ <reg32 offset="0x0ce0" name="RB_POWERCTR_RB_SEL_0"/>
++ <reg32 offset="0x0ce1" name="RB_POWERCTR_RB_SEL_1"/>
++ <reg32 offset="0x0ce2" name="RB_POWERCTR_RB_SEL_2"/>
++ <reg32 offset="0x0ce3" name="RB_POWERCTR_RB_SEL_3"/>
++ <reg32 offset="0x0ce4" name="RB_POWERCTR_CCU_SEL_0"/>
++ <reg32 offset="0x0ce5" name="RB_POWERCTR_CCU_SEL_1"/>
++ <reg32 offset="0x0cec" name="RB_PERFCTR_CMP_SEL_0" type="a5xx_cmp_perfcounter_select"/>
++ <reg32 offset="0x0ced" name="RB_PERFCTR_CMP_SEL_1" type="a5xx_cmp_perfcounter_select"/>
++ <reg32 offset="0x0cee" name="RB_PERFCTR_CMP_SEL_2" type="a5xx_cmp_perfcounter_select"/>
++ <reg32 offset="0x0cef" name="RB_PERFCTR_CMP_SEL_3" type="a5xx_cmp_perfcounter_select"/>
++
++ <reg32 offset="0x0d00" name="PC_DBG_ECO_CNTL">
++ <bitfield name="TWOPASSUSEWFI" pos="8" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0d01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++ <reg32 offset="0x0d02" name="PC_MODE_CNTL"/> <!-- always 0000001f? -->
++ <reg32 offset="0x0d04" name="PC_INDEX_BUF_LO"/>
++ <reg32 offset="0x0d05" name="PC_INDEX_BUF_HI"/>
++ <reg32 offset="0x0d06" name="PC_START_INDEX"/>
++ <reg32 offset="0x0d07" name="PC_MAX_INDEX"/>
++ <reg32 offset="0x0d08" name="PC_TESSFACTOR_ADDR_LO"/>
++ <reg32 offset="0x0d09" name="PC_TESSFACTOR_ADDR_HI"/>
++ <reg32 offset="0x0d10" name="PC_PERFCTR_PC_SEL_0" type="a5xx_pc_perfcounter_select"/>
++ <reg32 offset="0x0d11" name="PC_PERFCTR_PC_SEL_1" type="a5xx_pc_perfcounter_select"/>
++ <reg32 offset="0x0d12" name="PC_PERFCTR_PC_SEL_2" type="a5xx_pc_perfcounter_select"/>
++ <reg32 offset="0x0d13" name="PC_PERFCTR_PC_SEL_3" type="a5xx_pc_perfcounter_select"/>
++ <reg32 offset="0x0d14" name="PC_PERFCTR_PC_SEL_4" type="a5xx_pc_perfcounter_select"/>
++ <reg32 offset="0x0d15" name="PC_PERFCTR_PC_SEL_5" type="a5xx_pc_perfcounter_select"/>
++ <reg32 offset="0x0d16" name="PC_PERFCTR_PC_SEL_6" type="a5xx_pc_perfcounter_select"/>
++ <reg32 offset="0x0d17" name="PC_PERFCTR_PC_SEL_7" type="a5xx_pc_perfcounter_select"/>
++
++ <reg32 offset="0x0e00" name="HLSQ_TIMEOUT_THRESHOLD_0"/>
++ <reg32 offset="0x0e01" name="HLSQ_TIMEOUT_THRESHOLD_1"/>
++ <reg32 offset="0x0e04" name="HLSQ_DBG_ECO_CNTL"/>
++ <reg32 offset="0x0e05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++ <reg32 offset="0x0e06" name="HLSQ_MODE_CNTL"/> <!-- always 00000001? -->
++ <reg32 offset="0x0e10" name="HLSQ_PERFCTR_HLSQ_SEL_0" type="a5xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e11" name="HLSQ_PERFCTR_HLSQ_SEL_1" type="a5xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e12" name="HLSQ_PERFCTR_HLSQ_SEL_2" type="a5xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e13" name="HLSQ_PERFCTR_HLSQ_SEL_3" type="a5xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e14" name="HLSQ_PERFCTR_HLSQ_SEL_4" type="a5xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e15" name="HLSQ_PERFCTR_HLSQ_SEL_5" type="a5xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e16" name="HLSQ_PERFCTR_HLSQ_SEL_6" type="a5xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0e17" name="HLSQ_PERFCTR_HLSQ_SEL_7" type="a5xx_hlsq_perfcounter_select"/>
++ <reg32 offset="0x0f08" name="HLSQ_SPTP_RDSEL"/>
++ <reg32 offset="0xbc00" name="HLSQ_DBG_READ_SEL"/>
++ <reg32 offset="0xa000" name="HLSQ_DBG_AHB_READ_APERTURE"/>
++
++ <reg32 offset="0x0e41" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++ <reg32 offset="0x0e42" name="VFD_MODE_CNTL"/> <!-- always 00000000? -->
++ <reg32 offset="0x0e50" name="VFD_PERFCTR_VFD_SEL_0" type="a5xx_vfd_perfcounter_select"/>
++ <reg32 offset="0x0e51" name="VFD_PERFCTR_VFD_SEL_1" type="a5xx_vfd_perfcounter_select"/>
++ <reg32 offset="0x0e52" name="VFD_PERFCTR_VFD_SEL_2" type="a5xx_vfd_perfcounter_select"/>
++ <reg32 offset="0x0e53" name="VFD_PERFCTR_VFD_SEL_3" type="a5xx_vfd_perfcounter_select"/>
++ <reg32 offset="0x0e54" name="VFD_PERFCTR_VFD_SEL_4" type="a5xx_vfd_perfcounter_select"/>
++ <reg32 offset="0x0e55" name="VFD_PERFCTR_VFD_SEL_5" type="a5xx_vfd_perfcounter_select"/>
++ <reg32 offset="0x0e56" name="VFD_PERFCTR_VFD_SEL_6" type="a5xx_vfd_perfcounter_select"/>
++ <reg32 offset="0x0e57" name="VFD_PERFCTR_VFD_SEL_7" type="a5xx_vfd_perfcounter_select"/>
++ <reg32 offset="0x0e60" name="VPC_DBG_ECO_CNTL">
++ <bitfield name="ALLFLATOPTDIS" pos="10" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0e61" name="VPC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++ <reg32 offset="0x0e62" name="VPC_MODE_CNTL">
++ <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0e64" name="VPC_PERFCTR_VPC_SEL_0" type="a5xx_vpc_perfcounter_select"/>
++ <reg32 offset="0x0e65" name="VPC_PERFCTR_VPC_SEL_1" type="a5xx_vpc_perfcounter_select"/>
++ <reg32 offset="0x0e66" name="VPC_PERFCTR_VPC_SEL_2" type="a5xx_vpc_perfcounter_select"/>
++ <reg32 offset="0x0e67" name="VPC_PERFCTR_VPC_SEL_3" type="a5xx_vpc_perfcounter_select"/>
++
++ <reg32 offset="0x0e80" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++ <reg32 offset="0x0e81" name="UCHE_MODE_CNTL"/>
++ <reg32 offset="0x0e82" name="UCHE_SVM_CNTL"/>
++ <reg32 offset="0x0e87" name="UCHE_WRITE_THRU_BASE_LO"/>
++ <reg32 offset="0x0e88" name="UCHE_WRITE_THRU_BASE_HI"/>
++ <reg32 offset="0x0e89" name="UCHE_TRAP_BASE_LO"/>
++ <reg32 offset="0x0e8a" name="UCHE_TRAP_BASE_HI"/>
++ <reg32 offset="0x0e8b" name="UCHE_GMEM_RANGE_MIN_LO"/>
++ <reg32 offset="0x0e8c" name="UCHE_GMEM_RANGE_MIN_HI"/>
++ <reg32 offset="0x0e8d" name="UCHE_GMEM_RANGE_MAX_LO"/>
++ <reg32 offset="0x0e8e" name="UCHE_GMEM_RANGE_MAX_HI"/>
++ <reg32 offset="0x0e8f" name="UCHE_DBG_ECO_CNTL_2"/>
++ <reg32 offset="0x0e90" name="UCHE_DBG_ECO_CNTL"/>
++ <reg32 offset="0x0e91" name="UCHE_CACHE_INVALIDATE_MIN_LO"/>
++ <reg32 offset="0x0e92" name="UCHE_CACHE_INVALIDATE_MIN_HI"/>
++ <reg32 offset="0x0e93" name="UCHE_CACHE_INVALIDATE_MAX_LO"/>
++ <reg32 offset="0x0e94" name="UCHE_CACHE_INVALIDATE_MAX_HI"/>
++ <reg32 offset="0x0e95" name="UCHE_CACHE_INVALIDATE"/>
++ <reg32 offset="0x0e96" name="UCHE_CACHE_WAYS"/>
++ <reg32 offset="0x0ea0" name="UCHE_PERFCTR_UCHE_SEL_0" type="a5xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0ea1" name="UCHE_PERFCTR_UCHE_SEL_1" type="a5xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0ea2" name="UCHE_PERFCTR_UCHE_SEL_2" type="a5xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0ea3" name="UCHE_PERFCTR_UCHE_SEL_3" type="a5xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0ea4" name="UCHE_PERFCTR_UCHE_SEL_4" type="a5xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0ea5" name="UCHE_PERFCTR_UCHE_SEL_5" type="a5xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0ea6" name="UCHE_PERFCTR_UCHE_SEL_6" type="a5xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0ea7" name="UCHE_PERFCTR_UCHE_SEL_7" type="a5xx_uche_perfcounter_select"/>
++ <reg32 offset="0x0ea8" name="UCHE_POWERCTR_UCHE_SEL_0"/>
++ <reg32 offset="0x0ea9" name="UCHE_POWERCTR_UCHE_SEL_1"/>
++ <reg32 offset="0x0eaa" name="UCHE_POWERCTR_UCHE_SEL_2"/>
++ <reg32 offset="0x0eab" name="UCHE_POWERCTR_UCHE_SEL_3"/>
++ <reg32 offset="0x0eb1" name="UCHE_TRAP_LOG_LO"/>
++ <reg32 offset="0x0eb2" name="UCHE_TRAP_LOG_HI"/>
++
++ <reg32 offset="0x0ec0" name="SP_DBG_ECO_CNTL"/>
++ <reg32 offset="0x0ec1" name="SP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++ <reg32 offset="0x0ec2" name="SP_MODE_CNTL"/> <!-- always 0000001e? -->
++ <reg32 offset="0x0ed0" name="SP_PERFCTR_SP_SEL_0" type="a5xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ed1" name="SP_PERFCTR_SP_SEL_1" type="a5xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ed2" name="SP_PERFCTR_SP_SEL_2" type="a5xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ed3" name="SP_PERFCTR_SP_SEL_3" type="a5xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ed4" name="SP_PERFCTR_SP_SEL_4" type="a5xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ed5" name="SP_PERFCTR_SP_SEL_5" type="a5xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ed6" name="SP_PERFCTR_SP_SEL_6" type="a5xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ed7" name="SP_PERFCTR_SP_SEL_7" type="a5xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ed8" name="SP_PERFCTR_SP_SEL_8" type="a5xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0ed9" name="SP_PERFCTR_SP_SEL_9" type="a5xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0eda" name="SP_PERFCTR_SP_SEL_10" type="a5xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0edb" name="SP_PERFCTR_SP_SEL_11" type="a5xx_sp_perfcounter_select"/>
++ <reg32 offset="0x0edc" name="SP_POWERCTR_SP_SEL_0"/>
++ <reg32 offset="0x0edd" name="SP_POWERCTR_SP_SEL_1"/>
++ <reg32 offset="0x0ede" name="SP_POWERCTR_SP_SEL_2"/>
++ <reg32 offset="0x0edf" name="SP_POWERCTR_SP_SEL_3"/>
++
++ <reg32 offset="0x0f01" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++ <reg32 offset="0x0f02" name="TPL1_MODE_CNTL"/> <!-- always 00000544? -->
++ <reg32 offset="0x0f10" name="TPL1_PERFCTR_TP_SEL_0" type="a5xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f11" name="TPL1_PERFCTR_TP_SEL_1" type="a5xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f12" name="TPL1_PERFCTR_TP_SEL_2" type="a5xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f13" name="TPL1_PERFCTR_TP_SEL_3" type="a5xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f14" name="TPL1_PERFCTR_TP_SEL_4" type="a5xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f15" name="TPL1_PERFCTR_TP_SEL_5" type="a5xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f16" name="TPL1_PERFCTR_TP_SEL_6" type="a5xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f17" name="TPL1_PERFCTR_TP_SEL_7" type="a5xx_tp_perfcounter_select"/>
++ <reg32 offset="0x0f18" name="TPL1_POWERCTR_TP_SEL_0"/>
++ <reg32 offset="0x0f19" name="TPL1_POWERCTR_TP_SEL_1"/>
++ <reg32 offset="0x0f1a" name="TPL1_POWERCTR_TP_SEL_2"/>
++ <reg32 offset="0x0f1b" name="TPL1_POWERCTR_TP_SEL_3"/>
++
++ <reg32 offset="0x3000" name="VBIF_VERSION"/>
++ <reg32 offset="0x3001" name="VBIF_CLKON"/>
++<!--
++#define A5XX_VBIF_CLKON_FORCE_ON_TESTBUS_MASK 0x1
++#define A5XX_VBIF_CLKON_FORCE_ON_TESTBUS_SHIFT 0x1
++ -->
++ <reg32 offset="0x3028" name="VBIF_ABIT_SORT"/>
++ <reg32 offset="0x3029" name="VBIF_ABIT_SORT_CONF"/>
++ <reg32 offset="0x3049" name="VBIF_ROUND_ROBIN_QOS_ARB"/>
++ <reg32 offset="0x302a" name="VBIF_GATE_OFF_WRREQ_EN"/>
++ <reg32 offset="0x302c" name="VBIF_IN_RD_LIM_CONF0"/>
++ <reg32 offset="0x302d" name="VBIF_IN_RD_LIM_CONF1"/>
++ <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
++<!--
++#define A5XX_VBIF_XIN_HALT_CTRL0_MASK 0xF
++#define A510_VBIF_XIN_HALT_CTRL0_MASK 0x7
++ -->
++ <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
++ <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
++<!--
++#define A5XX_VBIF_TEST_BUS_OUT_CTRL_EN_MASK 0x1
++#define A5XX_VBIF_TEST_BUS_OUT_CTRL_EN_SHIFT 0x0
++ -->
++ <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
++ <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1"/>
++<!--
++#define A5XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL_MASK 0xF
++#define A5XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL_SHIFT 0x0
++ -->
++ <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
++ <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1"/>
++<!--
++#define A5XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL_MASK 0xF
++#define A5XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL_SHIFT 0x0
++ -->
++ <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
++ <reg32 offset="0x30c0" name="VBIF_PERF_CNT_EN0"/>
++ <reg32 offset="0x30c1" name="VBIF_PERF_CNT_EN1"/>
++ <reg32 offset="0x30c2" name="VBIF_PERF_CNT_EN2"/>
++ <reg32 offset="0x30c3" name="VBIF_PERF_CNT_EN3"/>
++ <reg32 offset="0x30c8" name="VBIF_PERF_CNT_CLR0"/>
++ <reg32 offset="0x30c9" name="VBIF_PERF_CNT_CLR1"/>
++ <reg32 offset="0x30ca" name="VBIF_PERF_CNT_CLR2"/>
++ <reg32 offset="0x30cb" name="VBIF_PERF_CNT_CLR3"/>
++ <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0" type="a5xx_vbif_perfcounter_select"/>
++ <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1" type="a5xx_vbif_perfcounter_select"/>
++ <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2" type="a5xx_vbif_perfcounter_select"/>
++ <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3" type="a5xx_vbif_perfcounter_select"/>
++ <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
++ <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
++ <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
++ <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
++ <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
++ <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
++ <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
++ <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
++ <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
++ <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
++ <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
++ <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
++ <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
++ <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
++ <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
++ <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
++ <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
++
++ <reg32 offset="0x8800" name="GPMU_INST_RAM_BASE"/>
++ <reg32 offset="0x9800" name="GPMU_DATA_RAM_BASE"/>
++
++<!--
++/* COUNTABLE FOR SP PERFCOUNTER */
++#define A5XX_SP_ALU_ACTIVE_CYCLES 0x1
++#define A5XX_SP0_ICL1_MISSES 0x35
++#define A5XX_SP_FS_CFLOW_INSTRUCTIONS 0x27
++
++/* COUNTABLE FOR TSE PERFCOUNTER */
++#define A5XX_TSE_INPUT_PRIM_NUM 0x6
++ -->
++ <reg32 offset="0xa840" name="SP_POWER_COUNTER_0_LO"/>
++ <reg32 offset="0xa841" name="SP_POWER_COUNTER_0_HI"/>
++ <reg32 offset="0xa842" name="SP_POWER_COUNTER_1_LO"/>
++ <reg32 offset="0xa843" name="SP_POWER_COUNTER_1_HI"/>
++ <reg32 offset="0xa844" name="SP_POWER_COUNTER_2_LO"/>
++ <reg32 offset="0xa845" name="SP_POWER_COUNTER_2_HI"/>
++ <reg32 offset="0xa846" name="SP_POWER_COUNTER_3_LO"/>
++ <reg32 offset="0xa847" name="SP_POWER_COUNTER_3_HI"/>
++ <reg32 offset="0xa848" name="TP_POWER_COUNTER_0_LO"/>
++ <reg32 offset="0xa849" name="TP_POWER_COUNTER_0_HI"/>
++ <reg32 offset="0xa84a" name="TP_POWER_COUNTER_1_LO"/>
++ <reg32 offset="0xa84b" name="TP_POWER_COUNTER_1_HI"/>
++ <reg32 offset="0xa84c" name="TP_POWER_COUNTER_2_LO"/>
++ <reg32 offset="0xa84d" name="TP_POWER_COUNTER_2_HI"/>
++ <reg32 offset="0xa84e" name="TP_POWER_COUNTER_3_LO"/>
++ <reg32 offset="0xa84f" name="TP_POWER_COUNTER_3_HI"/>
++ <reg32 offset="0xa850" name="RB_POWER_COUNTER_0_LO"/>
++ <reg32 offset="0xa851" name="RB_POWER_COUNTER_0_HI"/>
++ <reg32 offset="0xa852" name="RB_POWER_COUNTER_1_LO"/>
++ <reg32 offset="0xa853" name="RB_POWER_COUNTER_1_HI"/>
++ <reg32 offset="0xa854" name="RB_POWER_COUNTER_2_LO"/>
++ <reg32 offset="0xa855" name="RB_POWER_COUNTER_2_HI"/>
++ <reg32 offset="0xa856" name="RB_POWER_COUNTER_3_LO"/>
++ <reg32 offset="0xa857" name="RB_POWER_COUNTER_3_HI"/>
++ <reg32 offset="0xa858" name="CCU_POWER_COUNTER_0_LO"/>
++ <reg32 offset="0xa859" name="CCU_POWER_COUNTER_0_HI"/>
++ <reg32 offset="0xa85a" name="CCU_POWER_COUNTER_1_LO"/>
++ <reg32 offset="0xa85b" name="CCU_POWER_COUNTER_1_HI"/>
++ <reg32 offset="0xa85c" name="UCHE_POWER_COUNTER_0_LO"/>
++ <reg32 offset="0xa85d" name="UCHE_POWER_COUNTER_0_HI"/>
++ <reg32 offset="0xa85e" name="UCHE_POWER_COUNTER_1_LO"/>
++ <reg32 offset="0xa85f" name="UCHE_POWER_COUNTER_1_HI"/>
++ <reg32 offset="0xa860" name="UCHE_POWER_COUNTER_2_LO"/>
++ <reg32 offset="0xa861" name="UCHE_POWER_COUNTER_2_HI"/>
++ <reg32 offset="0xa862" name="UCHE_POWER_COUNTER_3_LO"/>
++ <reg32 offset="0xa863" name="UCHE_POWER_COUNTER_3_HI"/>
++ <reg32 offset="0xa864" name="CP_POWER_COUNTER_0_LO"/>
++ <reg32 offset="0xa865" name="CP_POWER_COUNTER_0_HI"/>
++ <reg32 offset="0xa866" name="CP_POWER_COUNTER_1_LO"/>
++ <reg32 offset="0xa867" name="CP_POWER_COUNTER_1_HI"/>
++ <reg32 offset="0xa868" name="CP_POWER_COUNTER_2_LO"/>
++ <reg32 offset="0xa869" name="CP_POWER_COUNTER_2_HI"/>
++ <reg32 offset="0xa86a" name="CP_POWER_COUNTER_3_LO"/>
++ <reg32 offset="0xa86b" name="CP_POWER_COUNTER_3_HI"/>
++ <reg32 offset="0xa86c" name="GPMU_POWER_COUNTER_0_LO"/>
++ <reg32 offset="0xa86d" name="GPMU_POWER_COUNTER_0_HI"/>
++ <reg32 offset="0xa86e" name="GPMU_POWER_COUNTER_1_LO"/>
++ <reg32 offset="0xa86f" name="GPMU_POWER_COUNTER_1_HI"/>
++ <reg32 offset="0xa870" name="GPMU_POWER_COUNTER_2_LO"/>
++ <reg32 offset="0xa871" name="GPMU_POWER_COUNTER_2_HI"/>
++ <reg32 offset="0xa872" name="GPMU_POWER_COUNTER_3_LO"/>
++ <reg32 offset="0xa873" name="GPMU_POWER_COUNTER_3_HI"/>
++ <reg32 offset="0xa874" name="GPMU_POWER_COUNTER_4_LO"/>
++ <reg32 offset="0xa875" name="GPMU_POWER_COUNTER_4_HI"/>
++ <reg32 offset="0xa876" name="GPMU_POWER_COUNTER_5_LO"/>
++ <reg32 offset="0xa877" name="GPMU_POWER_COUNTER_5_HI"/>
++ <reg32 offset="0xa878" name="GPMU_POWER_COUNTER_ENABLE"/>
++ <reg32 offset="0xa879" name="GPMU_ALWAYS_ON_COUNTER_LO"/>
++ <reg32 offset="0xa87a" name="GPMU_ALWAYS_ON_COUNTER_HI"/>
++ <reg32 offset="0xa87b" name="GPMU_ALWAYS_ON_COUNTER_RESET"/>
++ <reg32 offset="0xa87c" name="GPMU_POWER_COUNTER_SELECT_0"/>
++ <reg32 offset="0xa87d" name="GPMU_POWER_COUNTER_SELECT_1"/>
++
++ <reg32 offset="0xa880" name="GPMU_GPMU_SP_CLOCK_CONTROL"/>
++ <reg32 offset="0xa881" name="GPMU_SP_POWER_CNTL"/>
++ <reg32 offset="0xa886" name="GPMU_RBCCU_CLOCK_CNTL"/>
++ <reg32 offset="0xa887" name="GPMU_RBCCU_POWER_CNTL"/>
++ <reg32 offset="0xa88b" name="GPMU_SP_PWR_CLK_STATUS">
++ <bitfield name="PWR_ON" pos="20" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xa88d" name="GPMU_RBCCU_PWR_CLK_STATUS">
++ <bitfield name="PWR_ON" pos="20" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xa891" name="GPMU_PWR_COL_STAGGER_DELAY"/>
++ <reg32 offset="0xa892" name="GPMU_PWR_COL_INTER_FRAME_CTRL"/>
++ <reg32 offset="0xa893" name="GPMU_PWR_COL_INTER_FRAME_HYST"/>
++ <reg32 offset="0xa894" name="GPMU_PWR_COL_BINNING_CTRL"/>
++ <reg32 offset="0xa8a3" name="GPMU_CLOCK_THROTTLE_CTRL"/>
++ <reg32 offset="0xa8a8" name="GPMU_THROTTLE_UNMASK_FORCE_CTRL"/>
++ <reg32 offset="0xa8c1" name="GPMU_WFI_CONFIG"/>
++ <reg32 offset="0xa8d6" name="GPMU_RBBM_INTR_INFO"/>
++ <reg32 offset="0xa8d8" name="GPMU_CM3_SYSRESET"/>
++ <reg32 offset="0xa8e0" name="GPMU_GENERAL_0"/>
++ <reg32 offset="0xa8e1" name="GPMU_GENERAL_1"/>
++ <reg32 offset="0xac00" name="GPMU_TEMP_SENSOR_ID"/>
++ <reg32 offset="0xac01" name="GPMU_TEMP_SENSOR_CONFIG"/>
++ <reg32 offset="0xac02" name="GPMU_TEMP_VAL"/>
++ <reg32 offset="0xac03" name="GPMU_DELTA_TEMP_THRESHOLD"/>
++ <reg32 offset="0xac05" name="GPMU_TEMP_THRESHOLD_INTR_STATUS"/>
++ <reg32 offset="0xac06" name="GPMU_TEMP_THRESHOLD_INTR_EN_MASK"/>
++ <reg32 offset="0xac40" name="GPMU_LEAKAGE_TEMP_COEFF_0_1"/>
++ <reg32 offset="0xac41" name="GPMU_LEAKAGE_TEMP_COEFF_2_3"/>
++ <reg32 offset="0xac42" name="GPMU_LEAKAGE_VTG_COEFF_0_1"/>
++ <reg32 offset="0xac43" name="GPMU_LEAKAGE_VTG_COEFF_2_3"/>
++ <reg32 offset="0xac46" name="GPMU_BASE_LEAKAGE"/>
++ <reg32 offset="0xac60" name="GPMU_GPMU_VOLTAGE"/>
++ <reg32 offset="0xac61" name="GPMU_GPMU_VOLTAGE_INTR_STATUS"/>
++ <reg32 offset="0xac62" name="GPMU_GPMU_VOLTAGE_INTR_EN_MASK"/>
++ <reg32 offset="0xac80" name="GPMU_GPMU_PWR_THRESHOLD"/>
++ <reg32 offset="0xacc4" name="GPMU_GPMU_LLM_GLM_SLEEP_CTRL"/>
++ <reg32 offset="0xacc5" name="GPMU_GPMU_LLM_GLM_SLEEP_STATUS"/>
++ <reg32 offset="0xb80c" name="GDPM_CONFIG1"/>
++ <reg32 offset="0xb80d" name="GDPM_CONFIG2"/>
++ <reg32 offset="0xb80f" name="GDPM_INT_EN"/>
++ <reg32 offset="0xb811" name="GDPM_INT_MASK"/>
++ <reg32 offset="0xb9a0" name="GPMU_BEC_ENABLE"/>
++ <reg32 offset="0xc41a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
++ <reg32 offset="0xc41d" name="GPU_CS_AMP_CALIBRATION_STATUS1_0"/>
++ <reg32 offset="0xc41f" name="GPU_CS_AMP_CALIBRATION_STATUS1_2"/>
++ <reg32 offset="0xc421" name="GPU_CS_AMP_CALIBRATION_STATUS1_4"/>
++ <reg32 offset="0xc520" name="GPU_CS_ENABLE_REG"/>
++ <reg32 offset="0xc557" name="GPU_CS_AMP_CALIBRATION_CONTROL1"/>
++
++
++ <reg32 offset="0xe000" name="GRAS_CL_CNTL">
++ <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>
++ </reg32>
++ <bitset name="a5xx_gras_xs_cl_cntl" inline="yes">
++ <bitfield name="CLIP_MASK" low="0" high="7"/>
++ <bitfield name="CULL_MASK" low="8" high="15"/>
++ </bitset>
++ <reg32 offset="0xe001" name="GRAS_VS_CL_CNTL" type="a5xx_gras_xs_cl_cntl"/>
++ <reg32 offset="0xe004" name="UNKNOWN_E004"/> <!-- always 00000000? -->
++ <reg32 offset="0xe005" name="GRAS_CNTL">
++ <!-- see also RB_RENDER_CONTROL0 -->
++ <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
++ <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
++ <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
++ <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>
++ <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
++ <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
++ <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
++ </reg32>
++ <reg32 offset="0xe006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
++ <bitfield name="HORZ" low="0" high="9" type="uint"/>
++ <bitfield name="VERT" low="10" high="19" type="uint"/>
++ </reg32>
++ <reg32 offset="0xe010" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/>
++ <reg32 offset="0xe011" name="GRAS_CL_VPORT_XSCALE_0" type="float"/>
++ <reg32 offset="0xe012" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/>
++ <reg32 offset="0xe013" name="GRAS_CL_VPORT_YSCALE_0" type="float"/>
++ <reg32 offset="0xe014" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
++ <reg32 offset="0xe015" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
++ <reg32 offset="0xe090" name="GRAS_SU_CNTL">
++ <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
++ <bitfield name="CULL_BACK" pos="1" type="boolean"/>
++ <bitfield name="FRONT_CW" pos="2" type="boolean"/>
++ <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
++ <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
++ <bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/>
++ <!-- probably LINEHALFWIDTH is the same as a4xx.. -->
++ </reg32>
++ <reg32 offset="0xe091" name="GRAS_SU_POINT_MINMAX">
++ <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
++ <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
++ </reg32>
++ <reg32 offset="0xe092" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
++ <reg32 offset="0xe093" name="GRAS_SU_LAYERED"/>
++ <reg32 offset="0xe094" name="GRAS_SU_DEPTH_PLANE_CNTL">
++ <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
++ <bitfield name="UNK1" pos="1" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xe095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
++ <reg32 offset="0xe096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
++ <reg32 offset="0xe097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/>
++ <!-- duplicates RB_DEPTH_INFO0: -->
++ <reg32 offset="0xe098" name="GRAS_SU_DEPTH_BUFFER_INFO">
++ <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a5xx_depth_format"/>
++ </reg32>
++ <reg32 offset="0xe099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL"/> <!-- always 00000000? -->
++ <!--
++ guessing about window/screen/extent, I think they can in the end be
++ used interchangeably?
++ -->
++ <reg32 offset="0xe0a0" name="GRAS_SC_CNTL">
++ <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
++ <bitfield name="SAMPLES_PASSED" pos="15" type="boolean"/>
++ </reg32>
++ <!-- note, 0x4 for binning pass when frag writes z?? -->
++ <reg32 offset="0xe0a1" name="GRAS_SC_BIN_CNTL"/> <!-- always 00000000? -->
++ <reg32 offset="0xe0a2" name="GRAS_SC_RAS_MSAA_CNTL">
++ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
++ </reg32>
++ <reg32 offset="0xe0a3" name="GRAS_SC_DEST_MSAA_CNTL">
++ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
++ <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xe0a4" name="GRAS_SC_SCREEN_SCISSOR_CNTL"/> <!-- always 00000000? -->
++ <reg32 offset="0xe0aa" name="GRAS_SC_SCREEN_SCISSOR_TL_0" type="adreno_reg_xy"/>
++ <reg32 offset="0xe0ab" name="GRAS_SC_SCREEN_SCISSOR_BR_0" type="adreno_reg_xy"/>
++ <reg32 offset="0xe0ca" name="GRAS_SC_VIEWPORT_SCISSOR_TL_0" type="adreno_reg_xy"/>
++ <reg32 offset="0xe0cb" name="GRAS_SC_VIEWPORT_SCISSOR_BR_0" type="adreno_reg_xy"/>
++ <reg32 offset="0xe0ea" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
++ <reg32 offset="0xe0eb" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
++
++ <doc>
++ LRZ: (Low Resolution Z ??)
++ ----
++
++ I think it serves two functions, early discard of primitives in binning
++ pass without needing full resolution depth buffer, and also functions as
++ a depth-prepass, used during the GMEM draws to discard primitives that
++ would not be visible due to later draws.
++
++ The LRZ buffer always seems to be z16 format, regardless of actual
++ depth buffer format.
++
++ Note that LRZ write should be disabled when blend/stencil/etc is enabled,
++ since the occluded primitive can still contribute to final color value
++ of a fragment.
++
++ Only enabled for GL_LESS/GL_LEQUAL/GL_GREATER/GL_GEQUAL?
++ </doc>
++ <reg32 offset="0xe100" name="GRAS_LRZ_CNTL">
++ <bitfield name="ENABLE" pos="0" type="boolean"/>
++ <doc>LRZ write also disabled for blend/etc.</doc>
++ <bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
++ <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
++ <bitfield name="GREATER" pos="2" type="boolean"/>
++ <!--
++ b3 set sometimes, when depth buffer isn't cleared.. maybe it
++ invalidates the LRZ buffer? (Or just the covered positions?
++ -->
++ </reg32>
++ <reg32 offset="0xe101" name="GRAS_LRZ_BUFFER_BASE_LO"/>
++ <reg32 offset="0xe102" name="GRAS_LRZ_BUFFER_BASE_HI"/>
++ <!--
++ lzr pitch is depth pitch (in pixels) / 8 (aligned to 32)..
++ -->
++ <doc>
++ Pitch is depth width (in pixels) / 8 (aligned to 32). Height
++ is also divided by 8 (ie. covers 8x8 pixels)
++ </doc>
++ <reg32 offset="0xe103" name="GRAS_LRZ_BUFFER_PITCH" shr="5" type="uint"/>
++ <reg32 offset="0xe104" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
++ <reg32 offset="0xe105" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
++
++ <reg32 offset="0xe140" name="RB_CNTL">
++ <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
++ <bitfield name="HEIGHT" low="9" high="16" shr="5" type="uint"/>
++ <bitfield name="BYPASS" pos="17" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xe141" name="RB_RENDER_CNTL">
++<!--
++bit 3 set for normal draws
++bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
++ for z32 with no stencil, but maybe in that case separate z/s not used?
++ see mrt-fbo-* zs=2)
++ -->
++ <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
++ <bitfield name="SAMPLES_PASSED" pos="6" type="boolean"/>
++ <bitfield name="DISABLE_COLOR_PIPE" pos="7" type="boolean"/>
++ <!-- why everything twice?? maybe read vs write? -->
++ <!-- UBWC flag buffer enabled for depth/stencil: -->
++ <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
++ <bitfield name="FLAG_DEPTH2" pos="15" type="boolean"/>
++ <!-- bitmask of MRTs using UBWC flag buffer: -->
++ <bitfield name="FLAG_MRTS" low="16" high="23"/>
++ <bitfield name="FLAG_MRTS2" low="24" high="31"/>
++ </reg32>
++ <reg32 offset="0xe142" name="RB_RAS_MSAA_CNTL">
++ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
++ </reg32>
++ <reg32 offset="0xe143" name="RB_DEST_MSAA_CNTL">
++ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
++ <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
++ </reg32>
++ <!--
++ note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
++ name comes from kernel and is probably right)
++ -->
++ <reg32 offset="0xe144" name="RB_RENDER_CONTROL0">
++ <!-- see also GRAS_CNTL -->
++ <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
++ <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
++ <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
++ <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>
++ <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
++ <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
++ <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
++ </reg32>
++ <reg32 offset="0xe145" name="RB_RENDER_CONTROL1">
++ <bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
++ <bitfield name="FACENESS" pos="1" type="boolean"/>
++ <bitfield name="SAMPLEID" pos="2" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xe146" name="RB_FS_OUTPUT_CNTL">
++ <!-- bit0 set except for binning pass.. -->
++ <bitfield name="MRT" low="0" high="3" type="uint"/>
++ <bitfield name="FRAG_WRITES_Z" pos="5" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xe147" name="RB_RENDER_COMPONENTS">
++ <bitfield name="RT0" low="0" high="3"/>
++ <bitfield name="RT1" low="4" high="7"/>
++ <bitfield name="RT2" low="8" high="11"/>
++ <bitfield name="RT3" low="12" high="15"/>
++ <bitfield name="RT4" low="16" high="19"/>
++ <bitfield name="RT5" low="20" high="23"/>
++ <bitfield name="RT6" low="24" high="27"/>
++ <bitfield name="RT7" low="28" high="31"/>
++ </reg32>
++ <array offset="0xe150" name="RB_MRT" stride="7" length="8">
++ <reg32 offset="0x0" name="CONTROL">
++ <bitfield name="BLEND" pos="0" type="boolean"/>
++ <bitfield name="BLEND2" pos="1" type="boolean"/>
++ <bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
++ <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
++ <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
++ </reg32>
++ <reg32 offset="0x1" name="BLEND_CONTROL">
++ <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
++ <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
++ <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
++ <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
++ <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
++ <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
++ </reg32>
++ <reg32 offset="0x2" name="BUF_INFO">
++ <!--
++ not sure if there is a separate COLOR_SWAP field like on a3xx/a4xx,
++ or if it is inherent in the format. Will have to play with bits
++ once we get things working and see what happens. If it is a diff
++ field, it doesn't seem to have the same encoding as a3xx/a4xx.
++ -->
++ <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
++ <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a5xx_tile_mode"/>
++ <bitfield name="DITHER_MODE" low="11" high="12" type="adreno_rb_dither_mode"/>
++ <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
++ <bitfield name="COLOR_SRGB" pos="15" type="boolean"/>
++ </reg32>
++ <!--
++ at least in gmem, things seem to be aligned to pitch of 64..
++ maybe an artifact of tiled format used in gmem?
++ -->
++ <reg32 offset="0x3" name="PITCH" shr="6" type="uint"/>
++ <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" type="uint"/>
++ <reg32 offset="0x5" name="BASE_LO"/>
++ <reg32 offset="0x6" name="BASE_HI"/>
++ </array>
++ <reg32 offset="0xe1a0" name="RB_BLEND_RED">
++ <bitfield name="UINT" low="0" high="7" type="hex"/>
++ <bitfield name="SINT" low="8" high="15" type="hex"/>
++ <bitfield name="FLOAT" low="16" high="31" type="float"/>
++ </reg32>
++ <reg32 offset="0xe1a1" name="RB_BLEND_RED_F32" type="float"/>
++ <reg32 offset="0xe1a2" name="RB_BLEND_GREEN">
++ <bitfield name="UINT" low="0" high="7" type="hex"/>
++ <bitfield name="SINT" low="8" high="15" type="hex"/>
++ <bitfield name="FLOAT" low="16" high="31" type="float"/>
++ </reg32>
++ <reg32 offset="0xe1a3" name="RB_BLEND_GREEN_F32" type="float"/>
++ <reg32 offset="0xe1a4" name="RB_BLEND_BLUE">
++ <bitfield name="UINT" low="0" high="7" type="hex"/>
++ <bitfield name="SINT" low="8" high="15" type="hex"/>
++ <bitfield name="FLOAT" low="16" high="31" type="float"/>
++ </reg32>
++ <reg32 offset="0xe1a5" name="RB_BLEND_BLUE_F32" type="float"/>
++ <reg32 offset="0xe1a6" name="RB_BLEND_ALPHA">
++ <bitfield name="UINT" low="0" high="7" type="hex"/>
++ <bitfield name="SINT" low="8" high="15" type="hex"/>
++ <bitfield name="FLOAT" low="16" high="31" type="float"/>
++ </reg32>
++ <reg32 offset="0xe1a7" name="RB_BLEND_ALPHA_F32" type="float"/>
++ <reg32 offset="0xe1a8" name="RB_ALPHA_CONTROL">
++ <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
++ <bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
++ <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
++ </reg32>
++ <reg32 offset="0xe1a9" name="RB_BLEND_CNTL">
++ <!-- per-mrt enable bit -->
++ <bitfield name="ENABLE_BLEND" low="0" high="7"/>
++ <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
++ <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
++ <!-- a guess? -->
++ <bitfield name="SAMPLE_MASK" low="16" high="31"/>
++ </reg32>
++ <reg32 offset="0xe1b0" name="RB_DEPTH_PLANE_CNTL">
++ <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
++ <bitfield name="UNK1" pos="1" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xe1b1" name="RB_DEPTH_CNTL">
++ <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>
++ <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
++ <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
++ <doc>Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
++ <bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xe1b2" name="RB_DEPTH_BUFFER_INFO">
++ <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a5xx_depth_format"/>
++ </reg32>
++ <reg32 offset="0xe1b3" name="RB_DEPTH_BUFFER_BASE_LO"/>
++ <reg32 offset="0xe1b4" name="RB_DEPTH_BUFFER_BASE_HI"/>
++ <reg32 offset="0xe1b5" name="RB_DEPTH_BUFFER_PITCH" shr="6" type="uint">
++ <doc>stride of depth/stencil buffer</doc>
++ </reg32>
++ <reg32 offset="0xe1b6" name="RB_DEPTH_BUFFER_ARRAY_PITCH" shr="6" type="uint">
++ <doc>size of layer</doc>
++ </reg32>
++ <reg32 offset="0xe1c0" name="RB_STENCIL_CONTROL">
++ <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
++ <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
++ <!--
++ set for stencil operations that require read from stencil
++ buffer, but not for example for stencil clear (which does
++ not require read).. so guessing this is analogous to
++ READ_DEST_ENABLE for color buffer..
++ -->
++ <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
++ <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
++ <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
++ <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
++ <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
++ <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
++ <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
++ <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
++ <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
++ </reg32>
++ <reg32 offset="0xe1c1" name="RB_STENCIL_INFO">
++ <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xe1c2" name="RB_STENCIL_BASE_LO"/>
++ <reg32 offset="0xe1c3" name="RB_STENCIL_BASE_HI"/>
++ <reg32 offset="0xe1c4" name="RB_STENCIL_PITCH" shr="6" type="uint"/>
++ <reg32 offset="0xe1c5" name="RB_STENCIL_ARRAY_PITCH" shr="6" type="uint"/>
++ <reg32 offset="0xe1c6" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
++ <reg32 offset="0xe1c7" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
++ <reg32 offset="0xe1d0" name="RB_WINDOW_OFFSET" type="adreno_reg_xy"/>
++ <reg32 offset="0xe1d1" name="RB_SAMPLE_COUNT_CONTROL">
++ <bitfield name="COPY" pos="1" type="boolean"/>
++ </reg32>
++
++ <doc>
++ Blits:
++ ------
++
++ Blits are triggered by CP_EVENT_WRITE:BLIT, compared to previous
++ generations where they shared most of the gl pipeline and were
++ triggered by CP_DRAW_INDX*
++
++ For gmem->mem blob uses RB_BLIT_CNTL.BUF to specify src of
++ blit (ie MRTn, ZS, etc) and RB_BLIT_DST_LO/HI for destination
++ gpuaddr. The gmem offset is taken from RB_MRT[n].BASE_LO/HI
++
++ For mem->gmem blob uses just MRT0 or ZS and RB_BLIT_DST_LO/HI
++ for the GMEM offset, and gpuaddr from RB_MRT[0].BASE_LO/HI
++ (I suppose this is just to avoid trashing RB_MRT[1..7]??)
++ </doc>
++ <reg32 offset="0xe210" name="RB_BLIT_CNTL">
++ <bitfield name="BUF" low="0" high="3" type="a5xx_blit_buf"/>
++ </reg32>
++ <reg32 offset="0xe211" name="RB_RESOLVE_CNTL_1" type="adreno_reg_xy"/>
++ <reg32 offset="0xe212" name="RB_RESOLVE_CNTL_2" type="adreno_reg_xy"/>
++ <reg32 offset="0xe213" name="RB_RESOLVE_CNTL_3">
++ <!-- if b0 set, output is in TILE5_3 format -->
++ <bitfield name="TILED" pos="0" type="boolean"/>
++ <!--
++ 0xe213:
++ 0x0 mem->gmem
++ 0xf gmem->mem with flag buffer (color)
++ 0x4 gmem->mem without flag buffer (color)
++ 0x7 BYPASS mode flag buffer result (ie. on readpix)
++ also for gmem->mem preserving tiling
++ -->
++ </reg32>
++ <reg32 offset="0xe214" name="RB_BLIT_DST_LO"/>
++ <reg32 offset="0xe215" name="RB_BLIT_DST_HI"/>
++ <reg32 offset="0xe216" name="RB_BLIT_DST_PITCH" shr="6" type="uint"/>
++ <!-- array-pitch is size of layer -->
++ <reg32 offset="0xe217" name="RB_BLIT_DST_ARRAY_PITCH" shr="6" type="uint"/>
++ <reg32 offset="0xe218" name="RB_CLEAR_COLOR_DW0"/>
++ <reg32 offset="0xe219" name="RB_CLEAR_COLOR_DW1"/>
++ <reg32 offset="0xe21a" name="RB_CLEAR_COLOR_DW2"/>
++ <reg32 offset="0xe21b" name="RB_CLEAR_COLOR_DW3"/>
++ <reg32 offset="0xe21c" name="RB_CLEAR_CNTL">
++ <bitfield name="FAST_CLEAR" pos="1" type="boolean"/>
++ <bitfield name="MSAA_RESOLVE" pos="2" type="boolean"/>
++ <doc>
++ For MASK, if RB_BLIT_CNTL.BUF=BLIT_ZS:
++ 1 - depth
++ 2 - stencil
++ 3 - depth+stencil
++ if RB_BLIT_CNTL.BUF=BLIT_MRTn
++ then probably a component mask, I always see 0xf
++ </doc>
++ <bitfield name="MASK" low="4" high="7"/>
++ </reg32>
++
++ <doc>
++ Buffer Metadata (flag buffers):
++ -------------------------------
++
++ Blob seems to stick some metadata at the front of the buffer,
++ both z/s and MRT. I think this is same as UBWC (bandwidth
++ compression) metadata that mdp 1.7 and later supports. See
++ 1d3fae5698ce5358caab87a15383b690941697e8 in downstream kernel.
++ UBWC seems to stand for "universal bandwidth compression".
++
++ Before glReadPixels() it does a pair of BYPASS blits (at least
++ if metadata is used) presumably to resolve metadata.
++
++ NOTES: see: getUBwcBlockSize(), getUBwcMetaBufferSize() at
++ https://android.googlesource.com/platform/hardware/qcom/display/+/android-6.0.1_r40/msm8994/libgralloc/alloc_controller.cpp
++ (note that bpp in bytes, not bits, so really cpp)
++
++ Example Layout 2d w/ mipmap levels:
++
++ 100x2000, ifmt=GL_RG, fmt=GL_RG16F, type=GL_FLOAT, meta=64x512@0x8000 (7x500)
++ base=c072e000, offset=16384, size=1703936
++
++ color flags
++ 0 c073a000 c0732000 - level 0 flags is address
++ 1 c0838000 c0834000 programmed in texture state
++ 2 c0879000 c0877000
++ 3 c089a000 c0899000
++ 4 c08ab000 c08aa000
++ 5 c08b4000 c08b3000
++ 6 c08b9000 c08b8000
++ 7 c08bc000 c08bb000
++ 8 c08be000 c08bd000
++ 9 c08c0000 c08bf000
++ 10 c08c2000 c08c1000
++
++ ARRAY_PITCH is the combined size of all the levels plus flags,
++ so 0xc08c3000 - 0xc0732000 = 0x00191000 (1642496); each level
++ takes up a minimum of 2 pages (since color and flags parts are
++ each page aligned.
++
++ { TILE_MODE = TILE5_3 | SWIZ_X = A5XX_TEX_X | SWIZ_Y = A5XX_TEX_Y | SWIZ_Z = A5XX_TEX_ZERO | SWIZ_W = A5XX_TEX_ONE | MIPLVLS = 0 | FMT = TFMT5_16_16_FLOAT | SWAP = WZYX }
++ { WIDTH = 100 | HEIGHT = 2000 }
++ { FETCHSIZE = TFETCH5_4_BYTE | PITCH = 512 | TYPE = A5XX_TEX_2D }
++ { ARRAY_PITCH = 1642496 | 0x18800000 } - NOTE c2dc always has 0x18800000 but
++ { BASE_LO = 0xc0732000 } this varies for blob gles driver..
++ { BASE_HI = 0 | DEPTH = 1 } not sure what it is
++
++
++ </doc>
++ <reg32 offset="0xe240" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
++ <reg32 offset="0xe241" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
++ <reg32 offset="0xe242" name="RB_DEPTH_FLAG_BUFFER_PITCH">
++ </reg32>
++ <array offset="0xe243" name="RB_MRT_FLAG_BUFFER" stride="4" length="8">
++ <reg32 offset="0" name="ADDR_LO"/>
++ <reg32 offset="1" name="ADDR_HI"/>
++ <reg32 offset="2" name="PITCH" shr="6" type="uint"/>
++ <!-- array-pitch is size of layer -->
++ <reg32 offset="3" name="ARRAY_PITCH" shr="6" type="uint"/>
++ </array>
++ <reg32 offset="0xe263" name="RB_BLIT_FLAG_DST_LO"/>
++ <reg32 offset="0xe264" name="RB_BLIT_FLAG_DST_HI"/>
++ <reg32 offset="0xe265" name="RB_BLIT_FLAG_DST_PITCH" shr="6" type="uint"/>
++ <!-- array-pitch is size of layer -->
++ <reg32 offset="0xe266" name="RB_BLIT_FLAG_DST_ARRAY_PITCH" shr="6" type="uint"/>
++
++ <reg32 offset="0xe267" name="RB_SAMPLE_COUNT_ADDR_LO"/>
++ <reg32 offset="0xe268" name="RB_SAMPLE_COUNT_ADDR_HI"/>
++
++ <reg32 offset="0xe280" name="VPC_CNTL_0">
++ <doc>
++ num of varyings plus four for gl_Position (plus one if gl_PointSize)
++ plus # of transform-feedback (streamout) varyings if using the
++ hw streamout (rather than stg instructions in shader)
++ </doc>
++ <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
++ <bitfield name="VARYING" pos="11" type="boolean"/>
++ </reg32>
++ <array offset="0xe282" name="VPC_VARYING_INTERP" stride="1" length="8">
++ <reg32 offset="0x0" name="MODE"/>
++ </array>
++ <array offset="0xe28a" name="VPC_VARYING_PS_REPL" stride="1" length="8">
++ <reg32 offset="0x0" name="MODE"/>
++ </array>
++ <reg32 offset="0xe292" name="UNKNOWN_E292"/>
++ <reg32 offset="0xe293" name="UNKNOWN_E293"/>
++ <array offset="0xe294" name="VPC_VAR" stride="1" length="4">
++ <!-- one bit per varying component: -->
++ <reg32 offset="0" name="DISABLE"/>
++ </array>
++ <reg32 offset="0xe298" name="VPC_GS_SIV_CNTL"/>
++ <reg32 offset="0xe29a" name="VPC_CLIP_CNTL">
++ <bitfield name="CLIP_MASK" low="0" high="7" type="uint"/>
++ <!-- there can be up to 8 total clip/cull distance outputs,
++ but apparenly VPC can only deal with vec4, so when there are
++ more than 4 outputs a second location needs to be programmed
++ -->
++ <bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/>
++ <bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0xe29d" name="VPC_PACK">
++ <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
++ <!--
++ This seems to be the OUTLOC for the psize output. It could possibly
++ be the max-OUTLOC position, but it is only set when VS writes psize
++ (and blob always puts psize at highest OUTLOC)
++ -->
++ <bitfield name="PSIZELOC" low="8" high="15" type="uint"/>
++ </reg32>
++ <reg32 offset="0xe2a0" name="VPC_FS_PRIMITIVEID_CNTL"/>
++
++ <doc>
++ Stream-Out:
++ -----------
++
++ VPC_SO[0..3] registers setup details about streamout buffers, and
++ number of components to write to each.
++
++ VPC_SO_PROG provides the mapping between output varyings and the SO
++ buffers. It is written multiple times (via a CP_CONTEXT_REG_BUNCH
++ packet, not sure if that matters), each write can handle up to two
++ components of stream-out output. Order matches up to OUTLOC,
++ including padding. So, if outputting first 3 varyings:
++
++ SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0x7 }
++ SP_VS_OUT[0x1].REG: { A_REGID = r1.w | A_COMPMASK = 0x3 | B_REGID = r2.y | B_COMPMASK = 0xf }
++ SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 4 | OUTLOC2 = 8 | OUTLOC3 = 12 }
++
++ Then:
++
++ VPC_SO_PROG: { A_BUF = 0 | A_OFF = 0 | A_EN | A_BUF = 0 | B_OFF = 4 | B_EN }
++ VPC_SO_PROG: { A_BUF = 0 | A_OFF = 8 | A_EN | A_BUF = 0 | B_OFF = 12 | B_EN }
++ VPC_SO_PROG: { A_BUF = 2 | A_OFF = 0 | A_EN | A_BUF = 2 | B_OFF = 4 | B_EN }
++ VPC_SO_PROG: { A_BUF = 2 | A_OFF = 8 | A_EN | A_BUF = 0 | B_OFF = 0 }
++ VPC_SO_PROG: { A_BUF = 1 | A_OFF = 0 | A_EN | A_BUF = 1 | B_OFF = 4 | B_EN }
++
++ Note that varying order is OUTLOC0, OUTLOC2, OUTLOC1, and note
++ the padding between OUTLOC1 and OUTLOC2.
++
++ The BUF bitfield indicates which of the four streamout buffers
++ to write into at the specified offset.
++
++ The VPC_SO[n].FLUSH_BASE_LO/HI is used for hw to write back next
++ offset which gets loaded back into VPC_SO[n].BUFFER_OFFSET via a
++ CP_MEM_TO_REG. Probably can be ignored until we have GS/etc, at
++ which point we can't calculate the offset on the CPU.
++ </doc>
++ <reg32 offset="0xe2a1" name="VPC_SO_BUF_CNTL">
++ <bitfield name="BUF0" pos="0" type="boolean"/>
++ <bitfield name="BUF1" pos="3" type="boolean"/>
++ <bitfield name="BUF2" pos="6" type="boolean"/>
++ <bitfield name="BUF3" pos="9" type="boolean"/>
++ <bitfield name="ENABLE" pos="15" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xe2a2" name="VPC_SO_OVERRIDE">
++ <bitfield name="SO_DISABLE" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xe2a3" name="VPC_SO_CNTL">
++ <!-- always 0x10000 when SO enabled.. -->
++ <bitfield name="ENABLE" pos="16" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xe2a4" name="VPC_SO_PROG">
++ <bitfield name="A_BUF" low="0" high="1" type="uint"/>
++ <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
++ <bitfield name="A_EN" pos="11" type="boolean"/>
++ <bitfield name="B_BUF" low="12" high="13" type="uint"/>
++ <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
++ <bitfield name="B_EN" pos="23" type="boolean"/>
++ </reg32>
++ <array offset="0xe2a7" name="VPC_SO" stride="7" length="4">
++ <reg32 offset="0" name="BUFFER_BASE_LO"/>
++ <reg32 offset="1" name="BUFFER_BASE_HI"/>
++ <reg32 offset="2" name="BUFFER_SIZE"/>
++ <reg32 offset="3" name="NCOMP"/> <!-- component count -->
++ <reg32 offset="4" name="BUFFER_OFFSET"/>
++ <reg32 offset="5" name="FLUSH_BASE_LO"/>
++ <reg32 offset="6" name="FLUSH_BASE_HI"/>
++ </array>
++
++ <reg32 offset="0xe384" name="PC_PRIMITIVE_CNTL">
++ <!-- # of varyings plus four for gl_Position (plus one if gl_PointSize) -->
++ <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
++ <bitfield name="PRIMITIVE_RESTART" pos="8" type="boolean"/>
++ <bitfield name="COUNT_PRIMITIVES" pos="9" type="boolean"/><!-- enabled when gl_PrimitiveIDIn is used -->
++ <bitfield name="PROVOKING_VTX_LAST" pos="10" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xe385" name="PC_PRIM_VTX_CNTL">
++ <bitfield name="PSIZE" pos="11" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xe388" name="PC_RASTER_CNTL">
++ <bitfield name="POLYMODE_FRONT_PTYPE" low="0" high="2" type="adreno_pa_su_sc_draw"/>
++ <bitfield name="POLYMODE_BACK_PTYPE" low="3" high="5" type="adreno_pa_su_sc_draw"/>
++ <bitfield name="POLYMODE_ENABLE" pos="6" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xe389" name="PC_CLIP_CNTL">
++ <bitfield name="CLIP_MASK" low="0" high="7"/>
++ </reg32>
++ <reg32 offset="0xe38c" name="PC_RESTART_INDEX"/>
++ <reg32 offset="0xe38d" name="PC_GS_LAYERED"/>
++ <reg32 offset="0xe38e" name="PC_GS_PARAM">
++ <bitfield name="MAX_VERTICES" low="0" high="9" type="uint"/><!-- vertices - 1 -->
++ <bitfield name="INVOCATIONS" low="11" high="15" type="uint"/><!-- invoc - 1 -->
++ <bitfield name="PRIMTYPE" low="23" high="24" type="adreno_pa_su_sc_draw"/>
++ </reg32>
++ <reg32 offset="0xe38f" name="PC_HS_PARAM">
++ <bitfield name="VERTICES_OUT" low="0" high="5" type="uint"/>
++ <bitfield name="SPACING" low="21" high="22" type="a4xx_tess_spacing"/>
++ <bitfield name="CW" pos="23" type="boolean"/>
++ <bitfield name="CONNECTED" pos="24" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xe3b0" name="PC_POWER_CNTL"/>
++
++ <reg32 offset="0xe400" name="VFD_CONTROL_0">
++ <bitfield name="VTXCNT" low="0" high="5" type="uint"/>
++ </reg32>
++ <reg32 offset="0xe401" name="VFD_CONTROL_1">
++ <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0xe402" name="VFD_CONTROL_2">
++ <bitfield name="REGID_PATCHID" low="0" high="7" type="a3xx_regid"/><!-- same as VFD_CONTROL_3.REGID_PATCHID? -->
++ </reg32>
++ <reg32 offset="0xe403" name="VFD_CONTROL_3">
++ <bitfield name="REGID_PATCHID" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0xe404" name="VFD_CONTROL_4">
++ </reg32>
++ <reg32 offset="0xe405" name="VFD_CONTROL_5">
++ <!-- b0 set if gl_PrimitiveID used in fs ?? -->
++ </reg32>
++ <reg32 offset="0xe408" name="VFD_INDEX_OFFSET"/>
++ <reg32 offset="0xe409" name="VFD_INSTANCE_START_OFFSET"/>
++ <array offset="0xe40a" name="VFD_FETCH" stride="4" length="32">
++ <reg32 offset="0x0" name="BASE_LO"/>
++ <reg32 offset="0x1" name="BASE_HI"/>
++ <reg32 offset="0x2" name="SIZE" type="uint"/>
++ <reg32 offset="0x3" name="STRIDE" type="uint"/>
++ </array>
++ <array offset="0xe48a" name="VFD_DECODE" stride="2" length="32">
++ <reg32 offset="0x0" name="INSTR">
++ <!-- IDX appears to index into VFD_FETCH[] -->
++ <bitfield name="IDX" low="0" high="4" type="uint"/>
++ <bitfield name="INSTANCED" pos="17" type="boolean"/>
++ <bitfield name="FORMAT" low="20" high="27" type="a5xx_vtx_fmt"/>
++ <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
++ <bitfield name="UNK30" pos="30" type="boolean"/>
++ <bitfield name="FLOAT" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x1" name="STEP_RATE"/> <!-- ??? -->
++ </array>
++ <array offset="0xe4ca" name="VFD_DEST_CNTL" stride="1" length="32">
++ <reg32 offset="0x0" name="INSTR">
++ <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
++ <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
++ </reg32>
++ </array>
++ <reg32 offset="0xe4f0" name="VFD_POWER_CNTL"/>
++
++ <!-- 0x0 for compute, 0x10 for 3d? -->
++ <reg32 offset="0xe580" name="SP_SP_CNTL"/>
++
++ <bitset name="a5xx_xs_config" inline="yes">
++ <bitfield name="ENABLED" pos="0" type="boolean"/>
++ <bitfield name="CONSTOBJECTOFFSET" low="1" high="7" type="uint"/>
++ <bitfield name="SHADEROBJOFFSET" low="8" high="14" type="uint"/>
++ </bitset>
++ <bitset name="a5xx_xs_cntl" inline="yes">
++ <bitfield name="SSBO_ENABLE" pos="0" type="boolean"/>
++ <!--
++ no idea high bit.. could be this is amount of on-chip memory used
++ rather than total size?
++ -->
++ <bitfield name="INSTRLEN" low="1" high="31" type="uint"/>
++ </bitset>
++ <bitset name="a5xx_sp_xs_ctrl_reg0" inline="yes">
++ <!-- bit1 almost always set -->
++ <!-- set for "buffer mode" (ie. shader small enough to fit internally) -->
++ <bitfield name="BUFFER" pos="2" type="boolean"/>
++ <!-- 24 or more (full size) GPRS and blob uses TWO_QUADS instead of FOUR_QUADS -->
++ <bitfield name="THREADSIZE" pos="3" type="a3xx_threadsize"/>
++ <bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>
++ <bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>
++ <bitfield name="VARYING" pos="16" type="boolean"/>
++ <bitfield name="PIXLODENABLE" pos="20" type="boolean"/>
++ <!-- seems to be nesting level for flow control:.. -->
++ <bitfield name="BRANCHSTACK" low="25" high="31" type="uint"/>
++ </bitset>
++ <!-- assuming things appear in same relative order as a4xx: -->
++ <!-- duplicated exactly w/ corresponding HLSQ_ regs starting at 0xe78b.. -->
++ <reg32 offset="0xe584" name="SP_VS_CONFIG" type="a5xx_xs_config"/>
++ <reg32 offset="0xe585" name="SP_FS_CONFIG" type="a5xx_xs_config"/>
++ <reg32 offset="0xe586" name="SP_HS_CONFIG" type="a5xx_xs_config"/>
++ <reg32 offset="0xe587" name="SP_DS_CONFIG" type="a5xx_xs_config"/>
++ <reg32 offset="0xe588" name="SP_GS_CONFIG" type="a5xx_xs_config"/>
++ <reg32 offset="0xe589" name="SP_CS_CONFIG" type="a5xx_xs_config"/>
++ <reg32 offset="0xe58a" name="SP_VS_CONFIG_MAX_CONST"/>
++ <reg32 offset="0xe58b" name="SP_FS_CONFIG_MAX_CONST"/>
++ <reg32 offset="0xe590" name="SP_VS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
++ <reg32 offset="0xe592" name="SP_PRIMITIVE_CNTL">
++ <!-- # of VS outputs including pos/psize -->
++ <bitfield name="VSOUT" low="0" high="4" type="uint"/>
++ </reg32>
++ <array offset="0xe593" name="SP_VS_OUT" stride="1" length="16">
++ <reg32 offset="0x0" name="REG">
++ <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
++ <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
++ </reg32>
++ </array>
++ <!--
++ Starting with a5xx, position/psize outputs from shader end up in the
++ SP_VS_OUT map, with highest OUTLOCn position. (Generally they are
++ the last entries too, except when gl_PointCoord is used, blob inserts
++ an extra varying after, but with a lower OUTLOC position. If present,
++ psize is last, preceded by position.
++ -->
++ <array offset="0xe5a3" name="SP_VS_VPC_DST" stride="1" length="8">
++ <reg32 offset="0x0" name="REG">
++ <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
++ <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
++ <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
++ <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
++ </reg32>
++ </array>
++ <reg32 offset="0xe5ab" name="UNKNOWN_E5AB"/>
++ <reg32 offset="0xe5ac" name="SP_VS_OBJ_START_LO"/>
++ <reg32 offset="0xe5ad" name="SP_VS_OBJ_START_HI"/>
++
++ <bitset name="a5xx_sp_xs_pvt_mem_param" inline="yes">
++ <bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="9">
++ <doc>The size of memory that ldp/stp can address.</doc>
++ </bitfield>
++ <bitfield name="HWSTACKOFFSET" low="8" high="23" shr="11" type="uint"/>
++ <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31">
++ <doc>Guessing that this is the same as a3xx/a6xx.</doc>
++ </bitfield>
++ </bitset>
++
++ <bitset name="a5xx_sp_xs_pvt_mem_size" inline="yes">
++ <bitfield name="TOTALPVTMEMSIZE" low="0" high="17" shr="12"/>
++ </bitset>
++
++ <reg32 offset="0xe5ae" name="SP_VS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
++ <reg64 offset="0xe5af" name="SP_VS_PVT_MEM_ADDR" type="waddress" align="32"/>
++ <reg32 offset="0xe5b1" name="SP_VS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
++ <reg32 offset="0xe5c0" name="SP_FS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
++ <reg32 offset="0xe5c2" name="UNKNOWN_E5C2"/>
++ <reg32 offset="0xe5c3" name="SP_FS_OBJ_START_LO"/>
++ <reg32 offset="0xe5c4" name="SP_FS_OBJ_START_HI"/>
++ <reg32 offset="0xe5c5" name="SP_FS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
++ <reg64 offset="0xe5c6" name="SP_FS_PVT_MEM_ADDR" type="waddress" align="32"/>
++ <reg32 offset="0xe5c8" name="SP_FS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
++ <reg32 offset="0xe5c9" name="SP_BLEND_CNTL">
++ <!-- per-mrt enable bit -->
++ <bitfield name="ENABLE_BLEND" low="0" high="7"/>
++ <bitfield name="UNK8" pos="8" type="boolean"/>
++ <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xe5ca" name="SP_FS_OUTPUT_CNTL">
++ <bitfield name="MRT" low="0" high="3" type="uint"/>
++ <bitfield name="DEPTH_REGID" low="5" high="12" type="a3xx_regid"/>
++ <bitfield name="SAMPLEMASK_REGID" low="13" high="20" type="a3xx_regid"/>
++ </reg32>
++ <array offset="0xe5cb" name="SP_FS_OUTPUT" stride="1" length="8">
++ <doc>per MRT</doc>
++ <reg32 offset="0x0" name="REG">
++ <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
++ </reg32>
++ </array>
++ <array offset="0xe5d3" name="SP_FS_MRT" stride="1" length="8">
++ <reg32 offset="0" name="REG">
++ <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
++ <bitfield name="COLOR_SINT" pos="8" type="boolean"/>
++ <bitfield name="COLOR_UINT" pos="9" type="boolean"/>
++ <bitfield name="COLOR_SRGB" pos="10" type="boolean"/>
++ </reg32>
++ </array>
++ <!--
++ e5db/e5dc seems to look related to some optimization to do sample from
++ texture using varying value directly before shader thread starts? I
++ guess that could optimize common simple frag shaders..
++ -->
++ <reg32 offset="0xe5db" name="UNKNOWN_E5DB"/>
++ <reg32 offset="0xe5f0" name="SP_CS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
++ <reg32 offset="0xe5f2" name="UNKNOWN_E5F2"/>
++ <reg32 offset="0xe5f3" name="SP_CS_OBJ_START_LO"/>
++ <reg32 offset="0xe5f4" name="SP_CS_OBJ_START_HI"/>
++ <reg32 offset="0xe5f5" name="SP_CS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
++ <reg64 offset="0xe5f6" name="SP_CS_PVT_MEM_ADDR" type="waddress" align="32"/>
++ <reg32 offset="0xe5f8" name="SP_CS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
++
++ <!-- e5f9 something compute related.. seems to change when HLSQ_CS_CNTL_1 changes -->
++
++ <reg32 offset="0xe600" name="SP_HS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
++ <reg32 offset="0xe602" name="UNKNOWN_E602"/>
++ <reg32 offset="0xe603" name="SP_HS_OBJ_START_LO"/>
++ <reg32 offset="0xe604" name="SP_HS_OBJ_START_HI"/>
++ <reg32 offset="0xe605" name="SP_HS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
++ <reg64 offset="0xe606" name="SP_HS_PVT_MEM_ADDR" type="waddress" align="32"/>
++ <reg32 offset="0xe608" name="SP_HS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
++ <reg32 offset="0xe610" name="SP_DS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
++ <reg32 offset="0xe62b" name="UNKNOWN_E62B"/>
++ <reg32 offset="0xe62c" name="SP_DS_OBJ_START_LO"/>
++ <reg32 offset="0xe62d" name="SP_DS_OBJ_START_HI"/>
++ <reg32 offset="0xe62e" name="SP_DS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
++ <reg64 offset="0xe62f" name="SP_DS_PVT_MEM_ADDR" type="waddress" align="32"/>
++ <reg32 offset="0xe631" name="SP_DS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
++ <reg32 offset="0xe640" name="SP_GS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
++ <reg32 offset="0xe65b" name="UNKNOWN_E65B"/>
++ <reg32 offset="0xe65c" name="SP_GS_OBJ_START_LO"/>
++ <reg32 offset="0xe65d" name="SP_GS_OBJ_START_HI"/>
++ <reg32 offset="0xe65e" name="SP_GS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
++ <reg64 offset="0xe65f" name="SP_GS_PVT_MEM_ADDR" type="waddress" align="32"/>
++ <reg32 offset="0xe661" name="SP_GS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
++
++ <reg32 offset="0xe704" name="TPL1_TP_RAS_MSAA_CNTL">
++ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
++ </reg32>
++ <reg32 offset="0xe705" name="TPL1_TP_DEST_MSAA_CNTL">
++ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
++ <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
++ </reg32>
++ <!-- either blob is doing it wrong, or this is not per-stage anymore: -->
++ <reg32 offset="0xe706" name="TPL1_TP_BORDER_COLOR_BASE_ADDR_LO"/>
++ <reg32 offset="0xe707" name="TPL1_TP_BORDER_COLOR_BASE_ADDR_HI"/>
++
++ <!--
++ so these have the same info that is normally in the CP_LOAD_STATE
++ packets.. not sure if they are normally written by pm4/me or if the
++ CP_LOAD_STATE mechanism is deprecated?
++ -->
++ <reg32 offset="0xe700" name="TPL1_VS_TEX_COUNT" type="uint"/>
++ <reg32 offset="0xe701" name="TPL1_HS_TEX_COUNT" type="uint"/>
++ <reg32 offset="0xe702" name="TPL1_DS_TEX_COUNT" type="uint"/>
++ <reg32 offset="0xe703" name="TPL1_GS_TEX_COUNT" type="uint"/>
++
++ <reg32 offset="0xe722" name="TPL1_VS_TEX_SAMP_LO"/>
++ <reg32 offset="0xe723" name="TPL1_VS_TEX_SAMP_HI"/>
++ <reg32 offset="0xe724" name="TPL1_HS_TEX_SAMP_LO"/>
++ <reg32 offset="0xe725" name="TPL1_HS_TEX_SAMP_HI"/>
++ <reg32 offset="0xe726" name="TPL1_DS_TEX_SAMP_LO"/>
++ <reg32 offset="0xe727" name="TPL1_DS_TEX_SAMP_HI"/>
++ <reg32 offset="0xe728" name="TPL1_GS_TEX_SAMP_LO"/>
++ <reg32 offset="0xe729" name="TPL1_GS_TEX_SAMP_HI"/>
++
++ <reg32 offset="0xe72a" name="TPL1_VS_TEX_CONST_LO"/>
++ <reg32 offset="0xe72b" name="TPL1_VS_TEX_CONST_HI"/>
++ <reg32 offset="0xe72c" name="TPL1_HS_TEX_CONST_LO"/>
++ <reg32 offset="0xe72d" name="TPL1_HS_TEX_CONST_HI"/>
++ <reg32 offset="0xe72e" name="TPL1_DS_TEX_CONST_LO"/>
++ <reg32 offset="0xe72f" name="TPL1_DS_TEX_CONST_HI"/>
++ <reg32 offset="0xe730" name="TPL1_GS_TEX_CONST_LO"/>
++ <reg32 offset="0xe731" name="TPL1_GS_TEX_CONST_HI"/>
++
++ <reg32 offset="0xe750" name="TPL1_FS_TEX_COUNT" type="uint"/>
++ <reg32 offset="0xe751" name="TPL1_CS_TEX_COUNT" type="uint"/>
++
++ <reg32 offset="0xe75a" name="TPL1_FS_TEX_SAMP_LO"/>
++ <reg32 offset="0xe75b" name="TPL1_FS_TEX_SAMP_HI"/>
++ <reg32 offset="0xe75c" name="TPL1_CS_TEX_SAMP_LO"/>
++ <reg32 offset="0xe75d" name="TPL1_CS_TEX_SAMP_HI"/>
++ <reg32 offset="0xe75e" name="TPL1_FS_TEX_CONST_LO"/>
++ <reg32 offset="0xe75f" name="TPL1_FS_TEX_CONST_HI"/>
++ <reg32 offset="0xe760" name="TPL1_CS_TEX_CONST_LO"/>
++ <reg32 offset="0xe761" name="TPL1_CS_TEX_CONST_HI"/>
++
++ <reg32 offset="0xe764" name="TPL1_TP_FS_ROTATION_CNTL"/>
++
++ <reg32 offset="0xe784" name="HLSQ_CONTROL_0_REG">
++ <!-- 24 or more (full size) GPRS and blob uses TWO_QUADS instead of FOUR_QUADS -->
++ <bitfield name="FSTHREADSIZE" pos="0" type="a3xx_threadsize"/>
++ <bitfield name="CSTHREADSIZE" pos="2" type="a3xx_threadsize"/>
++ </reg32>
++ <reg32 offset="0xe785" name="HLSQ_CONTROL_1_REG">
++ <!-- I guess.. not set exactly same as a4xx, but similar: -->
++ <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="5" type="uint"/>
++ </reg32>
++ <reg32 offset="0xe786" name="HLSQ_CONTROL_2_REG">
++ <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
++ <!-- SAMPLEID is loaded into a half-precision register: -->
++ <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0xe787" name="HLSQ_CONTROL_3_REG">
++ <!-- register loaded with position (bary.f) -->
++ <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0xe788" name="HLSQ_CONTROL_4_REG">
++ <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <!--
++ 0x020fffff for normal draws, 0x1f00000 for compute.. maybe what state
++ is enabled? We could probably try disabling different bits and see
++ what breaks to figure out which is what:
++ -->
++ <reg32 offset="0xe78a" name="HLSQ_UPDATE_CNTL"/>
++ <reg32 offset="0xe78b" name="HLSQ_VS_CONFIG" type="a5xx_xs_config"/>
++ <reg32 offset="0xe78c" name="HLSQ_FS_CONFIG" type="a5xx_xs_config"/>
++ <reg32 offset="0xe78d" name="HLSQ_HS_CONFIG" type="a5xx_xs_config"/>
++ <reg32 offset="0xe78e" name="HLSQ_DS_CONFIG" type="a5xx_xs_config"/>
++ <reg32 offset="0xe78f" name="HLSQ_GS_CONFIG" type="a5xx_xs_config"/>
++ <reg32 offset="0xe790" name="HLSQ_CS_CONFIG" type="a5xx_xs_config"/>
++ <reg32 offset="0xe791" name="HLSQ_VS_CNTL" type="a5xx_xs_cntl"/>
++ <reg32 offset="0xe792" name="HLSQ_FS_CNTL" type="a5xx_xs_cntl"/>
++ <reg32 offset="0xe793" name="HLSQ_HS_CNTL" type="a5xx_xs_cntl"/>
++ <reg32 offset="0xe794" name="HLSQ_DS_CNTL" type="a5xx_xs_cntl"/>
++ <reg32 offset="0xe795" name="HLSQ_GS_CNTL" type="a5xx_xs_cntl"/>
++ <reg32 offset="0xe796" name="HLSQ_CS_CNTL" type="a5xx_xs_cntl"/>
++ <reg32 offset="0xe7b9" name="HLSQ_CS_KERNEL_GROUP_X"/>
++ <reg32 offset="0xe7ba" name="HLSQ_CS_KERNEL_GROUP_Y"/>
++ <reg32 offset="0xe7bb" name="HLSQ_CS_KERNEL_GROUP_Z"/>
++ <reg32 offset="0xe7b0" name="HLSQ_CS_NDRANGE_0">
++ <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
++ <!-- localsize is value minus one: -->
++ <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
++ <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
++ <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xe7b1" name="HLSQ_CS_NDRANGE_1">
++ <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xe7b2" name="HLSQ_CS_NDRANGE_2">
++ <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xe7b3" name="HLSQ_CS_NDRANGE_3">
++ <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xe7b4" name="HLSQ_CS_NDRANGE_4">
++ <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xe7b5" name="HLSQ_CS_NDRANGE_5">
++ <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xe7b6" name="HLSQ_CS_NDRANGE_6">
++ <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xe7b7" name="HLSQ_CS_CNTL_0">
++ <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
++ <!-- possibly one of these is KERNELDIMCONSTID? -->
++ <!--
++ UNK0 appears to be NUMWGCONSTID.. but only works in certain
++ cases? Blob doesn't appear to use it, but instead emits
++ these via const (uniform). Which requires some shenanigans
++ for indirect draws when the offset is not strongly aligned
++ enough to use as EXT_SRC_ADDR in CP_LOAD_STATE
++ -->
++ <bitfield name="UNK0" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="UNK1" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0xe7b8" name="HLSQ_CS_CNTL_1"/>
++ <reg32 offset="0xe7c0" name="UNKNOWN_E7C0"/>
++ <reg32 offset="0xe7c3" name="HLSQ_VS_CONSTLEN" type="uint"/>
++ <reg32 offset="0xe7c4" name="HLSQ_VS_INSTRLEN" type="uint"/>
++ <reg32 offset="0xe7c5" name="UNKNOWN_E7C5"/>
++ <reg32 offset="0xe7c8" name="HLSQ_HS_CONSTLEN" type="uint"/>
++ <reg32 offset="0xe7c9" name="HLSQ_HS_INSTRLEN" type="uint"/>
++ <reg32 offset="0xe7ca" name="UNKNOWN_E7CA"/>
++ <reg32 offset="0xe7cd" name="HLSQ_DS_CONSTLEN" type="uint"/>
++ <reg32 offset="0xe7ce" name="HLSQ_DS_INSTRLEN" type="uint"/>
++ <reg32 offset="0xe7cf" name="UNKNOWN_E7CF"/>
++ <reg32 offset="0xe7d2" name="HLSQ_GS_CONSTLEN" type="uint"/>
++ <reg32 offset="0xe7d3" name="HLSQ_GS_INSTRLEN" type="uint"/>
++ <reg32 offset="0xe7d4" name="UNKNOWN_E7D4"/>
++ <reg32 offset="0xe7d7" name="HLSQ_FS_CONSTLEN" type="uint"/>
++ <reg32 offset="0xe7d8" name="HLSQ_FS_INSTRLEN" type="uint"/>
++ <reg32 offset="0xe7d9" name="UNKNOWN_E7D9"/>
++ <reg32 offset="0xe7dc" name="HLSQ_CS_CONSTLEN" type="uint"/>
++ <reg32 offset="0xe7dd" name="HLSQ_CS_INSTRLEN" type="uint"/>
++
++ <!--
++ Separate blit/2d or dma engine? Seems to get used sometimes for
++ texture uploads, where a4xx blob would use normal draws. Used
++ in render-mode 0x5..
++
++ Note seems mostly to be used for small blits, large blits seem
++ to use the CP_EVENT_WRITE:BLIT style of doing things. See
++ cubemap-0003 (40x40) vs cubemap-0004 (256x256).
++
++ see cube-0000, cubemap-(1..3 but not 4+), quad-textured-10..17
++
++ Other nearby registers are probably color formats, etc. The
++ blit coords are in CP packet. Play more w/ glTexSubImage2D()
++ to work it out.
++
++ Separate this into a different domain?? Would that help to
++ restrict which registers we dump based on mode?
++
++ regs 0x2000 to 0x2004 (plus all-zero regs 0x2005-0x2009) look
++ like 2nd source for blending? Used in mipmap generation.. but
++ maybe layout is a bit different. (Possibly used for reading
++ src via sampler, to enable scaling??) 0x2040 also used in this
++ case.
++ -->
++ <reg32 offset="0x2100" name="RB_2D_BLIT_CNTL"/> <!-- same as 0x2180 -->
++ <reg32 offset="0x2101" name="RB_2D_SRC_SOLID_DW0"/>
++ <reg32 offset="0x2102" name="RB_2D_SRC_SOLID_DW1"/>
++ <reg32 offset="0x2103" name="RB_2D_SRC_SOLID_DW2"/>
++ <reg32 offset="0x2104" name="RB_2D_SRC_SOLID_DW3"/>
++
++ <bitset name="a5xx_2d_surf_info" inline="yes">
++ <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
++ <bitfield name="TILE_MODE" low="8" high="9" type="a5xx_tile_mode"/>
++ <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
++ <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
++ <bitfield name="FLAGS" pos="12" type="boolean"/>
++ <bitfield name="SRGB" pos="13" type="boolean"/>
++ </bitset>
++
++ <reg32 offset="0x2107" name="RB_2D_SRC_INFO" type="a5xx_2d_surf_info"/>
++ <reg32 offset="0x2108" name="RB_2D_SRC_LO"/>
++ <reg32 offset="0x2109" name="RB_2D_SRC_HI"/>
++ <reg32 offset="0x210a" name="RB_2D_SRC_SIZE">
++ <bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
++ <bitfield name="ARRAY_PITCH" low="16" high="31" shr="6" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x2110" name="RB_2D_DST_INFO" type="a5xx_2d_surf_info"/>
++ <reg32 offset="0x2111" name="RB_2D_DST_LO"/>
++ <reg32 offset="0x2112" name="RB_2D_DST_HI"/>
++ <reg32 offset="0x2113" name="RB_2D_DST_SIZE">
++ <bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
++ <bitfield name="ARRAY_PITCH" low="16" high="31" shr="6" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2140" name="RB_2D_SRC_FLAGS_LO"/>
++ <reg32 offset="0x2141" name="RB_2D_SRC_FLAGS_HI"/>
++ <reg32 offset="0x2142" name="RB_2D_SRC_FLAGS_PITCH" shr="6" type="uint"/>
++ <reg32 offset="0x2143" name="RB_2D_DST_FLAGS_LO"/>
++ <reg32 offset="0x2144" name="RB_2D_DST_FLAGS_HI"/>
++ <reg32 offset="0x2145" name="RB_2D_DST_FLAGS_PITCH" shr="6" type="uint"/>
++ <reg32 offset="0x2180" name="GRAS_2D_BLIT_CNTL"/> <!-- same as 0x2100 -->
++ <!-- looks same as 0x2107: -->
++ <reg32 offset="0x2181" name="GRAS_2D_SRC_INFO" type="a5xx_2d_surf_info"/>
++ <!-- looks same as 0x2110: -->
++ <reg32 offset="0x2182" name="GRAS_2D_DST_INFO" type="a5xx_2d_surf_info"/>
++<!--
++0x2100 and 0x2180 look like same thing (RB and GRAS versions)..
++ 0x86000000 for copy, 0x00000000 for fill?
++
++0x2184 0x9 for copy, 0x1 for blit (maybe bitmask of enabled src/dst???)
++ -->
++ <reg32 offset="0x2184" name="UNKNOWN_2184"/>
++</domain>
++
++<domain name="A5XX_TEX_SAMP" width="32">
++ <doc>Texture sampler dwords</doc>
++ <enum name="a5xx_tex_filter"> <!-- same as a4xx? -->
++ <value name="A5XX_TEX_NEAREST" value="0"/>
++ <value name="A5XX_TEX_LINEAR" value="1"/>
++ <value name="A5XX_TEX_ANISO" value="2"/>
++ </enum>
++ <enum name="a5xx_tex_clamp"> <!-- same as a4xx? -->
++ <value name="A5XX_TEX_REPEAT" value="0"/>
++ <value name="A5XX_TEX_CLAMP_TO_EDGE" value="1"/>
++ <value name="A5XX_TEX_MIRROR_REPEAT" value="2"/>
++ <value name="A5XX_TEX_CLAMP_TO_BORDER" value="3"/>
++ <value name="A5XX_TEX_MIRROR_CLAMP" value="4"/>
++ </enum>
++ <enum name="a5xx_tex_aniso"> <!-- same as a4xx? -->
++ <value name="A5XX_TEX_ANISO_1" value="0"/>
++ <value name="A5XX_TEX_ANISO_2" value="1"/>
++ <value name="A5XX_TEX_ANISO_4" value="2"/>
++ <value name="A5XX_TEX_ANISO_8" value="3"/>
++ <value name="A5XX_TEX_ANISO_16" value="4"/>
++ </enum>
++ <reg32 offset="0" name="0">
++ <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
++ <bitfield name="XY_MAG" low="1" high="2" type="a5xx_tex_filter"/>
++ <bitfield name="XY_MIN" low="3" high="4" type="a5xx_tex_filter"/>
++ <bitfield name="WRAP_S" low="5" high="7" type="a5xx_tex_clamp"/>
++ <bitfield name="WRAP_T" low="8" high="10" type="a5xx_tex_clamp"/>
++ <bitfield name="WRAP_R" low="11" high="13" type="a5xx_tex_clamp"/>
++ <bitfield name="ANISO" low="14" high="16" type="a5xx_tex_aniso"/>
++ <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
++ <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
++ <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
++ <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
++ <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
++ <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <!--
++ offset into border-color buffer? Blob always uses 0x80 for FS state
++ if both VS and FS have border-color.
++Seems like when both VS and FS have bcolor, one starts 0x300 after other..
++and 0x80 in TEX_SAMP.2 .. blob doesn't seem to be able to cope w/ multiple
++different border-color states per texture.. Looks something like:
++0000: 3f000000 00000000 00000000 3f800000 00008000 ffff0000 00004000 7fff0000
++0020: 00003800 3c000000 80100010 0000f008 ff000080 7f000040 c0000200 00800000
++0040: 00003800 3c000000 00000000 00000000 00000000 00000000 00000000 00000000
++*
++0300: 3f800000 3f800000 3f800000 3f800000 ffffffff ffffffff 7fff7fff 7fff7fff
++0320: 3c003c00 3c003c00 ffffffff 0000ffff ffffffff 7f7f7f7f ffffffff 00ffffff
++0340: 3c003c00 3c003c00 00000000 00000000 00000000 00000000 00000000 00000000
++
++ -->
++ <bitfield name="BCOLOR_OFFSET" low="7" high="31"/>
++ </reg32>
++ <reg32 offset="3" name="3"/>
++</domain>
++
++<domain name="A5XX_TEX_CONST" width="32">
++ <doc>Texture constant dwords</doc>
++ <enum name="a5xx_tex_swiz"> <!-- same as a4xx? -->
++ <value name="A5XX_TEX_X" value="0"/>
++ <value name="A5XX_TEX_Y" value="1"/>
++ <value name="A5XX_TEX_Z" value="2"/>
++ <value name="A5XX_TEX_W" value="3"/>
++ <value name="A5XX_TEX_ZERO" value="4"/>
++ <value name="A5XX_TEX_ONE" value="5"/>
++ </enum>
++ <enum name="a5xx_tex_type"> <!-- same as a4xx? -->
++ <value name="A5XX_TEX_1D" value="0"/>
++ <value name="A5XX_TEX_2D" value="1"/>
++ <value name="A5XX_TEX_CUBE" value="2"/>
++ <value name="A5XX_TEX_3D" value="3"/>
++ <value name="A5XX_TEX_BUFFER" value="4"/>
++ </enum>
++ <reg32 offset="0" name="0">
++ <bitfield name="TILE_MODE" low="0" high="1" type="a5xx_tile_mode"/>
++ <bitfield name="SRGB" pos="2" type="boolean"/>
++ <bitfield name="SWIZ_X" low="4" high="6" type="a5xx_tex_swiz"/>
++ <bitfield name="SWIZ_Y" low="7" high="9" type="a5xx_tex_swiz"/>
++ <bitfield name="SWIZ_Z" low="10" high="12" type="a5xx_tex_swiz"/>
++ <bitfield name="SWIZ_W" low="13" high="15" type="a5xx_tex_swiz"/>
++ <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
++ <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
++ <bitfield name="FMT" low="22" high="29" type="a5xx_tex_fmt"/>
++ <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="WIDTH" low="0" high="14" type="uint"/>
++ <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <!--
++ b4 and b31 set for buffer/ssbo case, in which case low 15 bits
++ of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
++
++ b31 is probably the 'BUFFER' bit.. it is the one that changes
++ behavior of texture in dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.buffer_size_131071
++ -->
++ <bitfield name="BUFFER" pos="4" type="boolean"/>
++ <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
++ <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
++ <doc>Pitch in bytes (so actually stride)</doc>
++ <bitfield name="PITCH" low="7" high="28" type="uint"/>
++ <bitfield name="TYPE" low="29" high="31" type="a5xx_tex_type"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <!--
++ ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
++ for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
++ layer size at the point that it stops being reduced moving to
++ higher (smaller) mipmap levels
++ -->
++ <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
++ <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
++ <!--
++ by default levels with w < 16 are linear
++ TILE_ALL makes all levels have tiling
++ seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
++ -->
++ <bitfield name="TILE_ALL" pos="27" type="boolean"/>
++ <bitfield name="FLAG" pos="28" type="boolean"/>
++ </reg32>
++ <reg32 offset="4" name="4">
++ <bitfield name="BASE_LO" low="5" high="31" shr="5"/>
++ </reg32>
++ <reg32 offset="5" name="5">
++ <bitfield name="BASE_HI" low="0" high="16"/>
++ <bitfield name="DEPTH" low="17" high="29" type="uint"/>
++ </reg32>
++ <reg32 offset="6" name="6"/>
++ <reg32 offset="7" name="7"/>
++ <reg32 offset="8" name="8"/>
++ <reg32 offset="9" name="9"/>
++ <reg32 offset="10" name="10"/>
++ <reg32 offset="11" name="11"/>
++</domain>
++
++<!--
++Note the "SSBO" state blocks are actually used for both images and SSBOs,
++naming is just because I r/e'd SSBOs first. I should probably come up
++with a better name.
++-->
++<domain name="A5XX_SSBO_0" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="BASE_LO" low="5" high="31" shr="5"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <!-- no BASE_HI here? Maybe this is only used for 32b mode? -->
++ <doc>Pitch in bytes (so actually stride)</doc>
++ <bitfield name="PITCH" low="0" high="21" type="uint"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="ARRAY_PITCH" low="12" high="25" shr="12" type="uint"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <!-- bytes per pixel: -->
++ <bitfield name="CPP" low="0" high="5" type="uint"/>
++ </reg32>
++</domain>
++
++<domain name="A5XX_SSBO_1" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="FMT" low="8" high="15" type="a5xx_tex_fmt"/>
++ <bitfield name="WIDTH" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="HEIGHT" low="0" high="15" type="uint"/>
++ <bitfield name="DEPTH" low="16" high="31" type="uint"/>
++ </reg32>
++</domain>
++
++<domain name="A5XX_SSBO_2" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="BASE_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="BASE_HI" low="0" high="31"/>
++ </reg32>
++</domain>
++
++<domain name="A5XX_UBO" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="BASE_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="BASE_HI" low="0" high="16"/>
++ <!-- size probably in high bits -->
++ </reg32>
++</domain>
++
++</database>
+--
+2.39.5
+
--- /dev/null
+From 615167bebc153937487be2a8108f51378f1863ad Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 1 Apr 2024 05:42:39 +0300
+Subject: drm/msm: import A6xx XML display registers database
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 9cd078bbe52f8d96a224e7c9631d614407f3b338 ]
+
+Import Adreno registers database for A6xx from the Mesa, commit
+639488f924d9 ("freedreno/registers: limit the rules schema").
+
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Patchwork: https://patchwork.freedesktop.org/patch/585856/
+Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-9-4bdb277a85a1@linaro.org
+Stable-dep-of: 588257897058 ("drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG0 updated from driver side")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 4970 +++++++++++++++++
+ .../gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 228 +
+ 2 files changed, 5198 insertions(+)
+ create mode 100644 drivers/gpu/drm/msm/registers/adreno/a6xx.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
+
+diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
+new file mode 100644
+index 0000000000000..78524aaab9d4a
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
+@@ -0,0 +1,4970 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++<import file="adreno/adreno_common.xml"/>
++<import file="adreno/adreno_pm4.xml"/>
++
++<!--
++Each register that is actually being used by driver should have "usage" defined,
++currently there are following usages:
++- "cmd" - the register is used outside of renderpass and blits,
++ roughly corresponds to registers used in ib1 for Freedreno
++- "rp_blit" - the register is used inside renderpass or blits
++ (ib2 for Freedreno)
++
++It is expected that register with "cmd" usage may be written into only at
++the start of the command buffer (ib1), while "rp_blit" usage indicates that register
++is either overwritten by renderpass/blit (ib2) or not used if not overwritten
++by a particular renderpass/blit.
++-->
++
++<!-- these might be same as a5xx -->
++<enum name="a6xx_tile_mode">
++ <value name="TILE6_LINEAR" value="0"/>
++ <value name="TILE6_2" value="2"/>
++ <value name="TILE6_3" value="3"/>
++</enum>
++
++<enum name="a6xx_format">
++ <value value="0x02" name="FMT6_A8_UNORM"/>
++ <value value="0x03" name="FMT6_8_UNORM"/>
++ <value value="0x04" name="FMT6_8_SNORM"/>
++ <value value="0x05" name="FMT6_8_UINT"/>
++ <value value="0x06" name="FMT6_8_SINT"/>
++
++ <value value="0x08" name="FMT6_4_4_4_4_UNORM"/>
++ <value value="0x0a" name="FMT6_5_5_5_1_UNORM"/>
++ <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
++ <value value="0x0e" name="FMT6_5_6_5_UNORM"/>
++
++ <value value="0x0f" name="FMT6_8_8_UNORM"/>
++ <value value="0x10" name="FMT6_8_8_SNORM"/>
++ <value value="0x11" name="FMT6_8_8_UINT"/>
++ <value value="0x12" name="FMT6_8_8_SINT"/>
++ <value value="0x13" name="FMT6_L8_A8_UNORM"/>
++
++ <value value="0x15" name="FMT6_16_UNORM"/>
++ <value value="0x16" name="FMT6_16_SNORM"/>
++ <value value="0x17" name="FMT6_16_FLOAT"/>
++ <value value="0x18" name="FMT6_16_UINT"/>
++ <value value="0x19" name="FMT6_16_SINT"/>
++
++ <value value="0x21" name="FMT6_8_8_8_UNORM"/>
++ <value value="0x22" name="FMT6_8_8_8_SNORM"/>
++ <value value="0x23" name="FMT6_8_8_8_UINT"/>
++ <value value="0x24" name="FMT6_8_8_8_SINT"/>
++
++ <value value="0x30" name="FMT6_8_8_8_8_UNORM"/>
++ <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
++ <value value="0x32" name="FMT6_8_8_8_8_SNORM"/>
++ <value value="0x33" name="FMT6_8_8_8_8_UINT"/>
++ <value value="0x34" name="FMT6_8_8_8_8_SINT"/>
++
++ <value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/>
++
++ <value value="0x36" name="FMT6_10_10_10_2_UNORM"/>
++ <value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/>
++ <value value="0x39" name="FMT6_10_10_10_2_SNORM"/>
++ <value value="0x3a" name="FMT6_10_10_10_2_UINT"/>
++ <value value="0x3b" name="FMT6_10_10_10_2_SINT"/>
++
++ <value value="0x42" name="FMT6_11_11_10_FLOAT"/>
++
++ <value value="0x43" name="FMT6_16_16_UNORM"/>
++ <value value="0x44" name="FMT6_16_16_SNORM"/>
++ <value value="0x45" name="FMT6_16_16_FLOAT"/>
++ <value value="0x46" name="FMT6_16_16_UINT"/>
++ <value value="0x47" name="FMT6_16_16_SINT"/>
++
++ <value value="0x48" name="FMT6_32_UNORM"/>
++ <value value="0x49" name="FMT6_32_SNORM"/>
++ <value value="0x4a" name="FMT6_32_FLOAT"/>
++ <value value="0x4b" name="FMT6_32_UINT"/>
++ <value value="0x4c" name="FMT6_32_SINT"/>
++ <value value="0x4d" name="FMT6_32_FIXED"/>
++
++ <value value="0x58" name="FMT6_16_16_16_UNORM"/>
++ <value value="0x59" name="FMT6_16_16_16_SNORM"/>
++ <value value="0x5a" name="FMT6_16_16_16_FLOAT"/>
++ <value value="0x5b" name="FMT6_16_16_16_UINT"/>
++ <value value="0x5c" name="FMT6_16_16_16_SINT"/>
++
++ <value value="0x60" name="FMT6_16_16_16_16_UNORM"/>
++ <value value="0x61" name="FMT6_16_16_16_16_SNORM"/>
++ <value value="0x62" name="FMT6_16_16_16_16_FLOAT"/>
++ <value value="0x63" name="FMT6_16_16_16_16_UINT"/>
++ <value value="0x64" name="FMT6_16_16_16_16_SINT"/>
++
++ <value value="0x65" name="FMT6_32_32_UNORM"/>
++ <value value="0x66" name="FMT6_32_32_SNORM"/>
++ <value value="0x67" name="FMT6_32_32_FLOAT"/>
++ <value value="0x68" name="FMT6_32_32_UINT"/>
++ <value value="0x69" name="FMT6_32_32_SINT"/>
++ <value value="0x6a" name="FMT6_32_32_FIXED"/>
++
++ <value value="0x70" name="FMT6_32_32_32_UNORM"/>
++ <value value="0x71" name="FMT6_32_32_32_SNORM"/>
++ <value value="0x72" name="FMT6_32_32_32_UINT"/>
++ <value value="0x73" name="FMT6_32_32_32_SINT"/>
++ <value value="0x74" name="FMT6_32_32_32_FLOAT"/>
++ <value value="0x75" name="FMT6_32_32_32_FIXED"/>
++
++ <value value="0x80" name="FMT6_32_32_32_32_UNORM"/>
++ <value value="0x81" name="FMT6_32_32_32_32_SNORM"/>
++ <value value="0x82" name="FMT6_32_32_32_32_FLOAT"/>
++ <value value="0x83" name="FMT6_32_32_32_32_UINT"/>
++ <value value="0x84" name="FMT6_32_32_32_32_SINT"/>
++ <value value="0x85" name="FMT6_32_32_32_32_FIXED"/>
++
++ <value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/> <!-- UYVY -->
++ <value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/> <!-- YUYV -->
++ <value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/> <!-- NV12 -->
++ <value value="0x8f" name="FMT6_NV21"/>
++ <value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/> <!-- YV12 -->
++
++ <value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/>
++
++ <!-- Note: tiling/UBWC for these may be different from equivalent formats
++ For example FMT6_NV12_Y is not compatible with FMT6_8_UNORM
++ -->
++ <value value="0x94" name="FMT6_NV12_Y"/>
++ <value value="0x95" name="FMT6_NV12_UV"/>
++ <value value="0x96" name="FMT6_NV12_VU"/>
++ <value value="0x97" name="FMT6_NV12_4R"/>
++ <value value="0x98" name="FMT6_NV12_4R_Y"/>
++ <value value="0x99" name="FMT6_NV12_4R_UV"/>
++ <value value="0x9a" name="FMT6_P010"/>
++ <value value="0x9b" name="FMT6_P010_Y"/>
++ <value value="0x9c" name="FMT6_P010_UV"/>
++ <value value="0x9d" name="FMT6_TP10"/>
++ <value value="0x9e" name="FMT6_TP10_Y"/>
++ <value value="0x9f" name="FMT6_TP10_UV"/>
++
++ <value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/>
++
++ <value value="0xab" name="FMT6_ETC2_RG11_UNORM"/>
++ <value value="0xac" name="FMT6_ETC2_RG11_SNORM"/>
++ <value value="0xad" name="FMT6_ETC2_R11_UNORM"/>
++ <value value="0xae" name="FMT6_ETC2_R11_SNORM"/>
++ <value value="0xaf" name="FMT6_ETC1"/>
++ <value value="0xb0" name="FMT6_ETC2_RGB8"/>
++ <value value="0xb1" name="FMT6_ETC2_RGBA8"/>
++ <value value="0xb2" name="FMT6_ETC2_RGB8A1"/>
++ <value value="0xb3" name="FMT6_DXT1"/>
++ <value value="0xb4" name="FMT6_DXT3"/>
++ <value value="0xb5" name="FMT6_DXT5"/>
++ <value value="0xb7" name="FMT6_RGTC1_UNORM"/>
++ <value value="0xb8" name="FMT6_RGTC1_SNORM"/>
++ <value value="0xbb" name="FMT6_RGTC2_UNORM"/>
++ <value value="0xbc" name="FMT6_RGTC2_SNORM"/>
++ <value value="0xbe" name="FMT6_BPTC_UFLOAT"/>
++ <value value="0xbf" name="FMT6_BPTC_FLOAT"/>
++ <value value="0xc0" name="FMT6_BPTC"/>
++ <value value="0xc1" name="FMT6_ASTC_4x4"/>
++ <value value="0xc2" name="FMT6_ASTC_5x4"/>
++ <value value="0xc3" name="FMT6_ASTC_5x5"/>
++ <value value="0xc4" name="FMT6_ASTC_6x5"/>
++ <value value="0xc5" name="FMT6_ASTC_6x6"/>
++ <value value="0xc6" name="FMT6_ASTC_8x5"/>
++ <value value="0xc7" name="FMT6_ASTC_8x6"/>
++ <value value="0xc8" name="FMT6_ASTC_8x8"/>
++ <value value="0xc9" name="FMT6_ASTC_10x5"/>
++ <value value="0xca" name="FMT6_ASTC_10x6"/>
++ <value value="0xcb" name="FMT6_ASTC_10x8"/>
++ <value value="0xcc" name="FMT6_ASTC_10x10"/>
++ <value value="0xcd" name="FMT6_ASTC_12x10"/>
++ <value value="0xce" name="FMT6_ASTC_12x12"/>
++
++ <!-- for sampling stencil (integer, 2nd channel), not available on a630 -->
++ <value value="0xea" name="FMT6_Z24_UINT_S8_UINT"/>
++
++ <!-- Not a hw enum, used internally in driver -->
++ <value value="0xff" name="FMT6_NONE"/>
++
++</enum>
++
++<!-- probably same as a5xx -->
++<enum name="a6xx_polygon_mode">
++ <value name="POLYMODE6_POINTS" value="1"/>
++ <value name="POLYMODE6_LINES" value="2"/>
++ <value name="POLYMODE6_TRIANGLES" value="3"/>
++</enum>
++
++<enum name="a6xx_depth_format">
++ <value name="DEPTH6_NONE" value="0"/>
++ <value name="DEPTH6_16" value="1"/>
++ <value name="DEPTH6_24_8" value="2"/>
++ <value name="DEPTH6_32" value="4"/>
++</enum>
++
++<bitset name="a6x_cp_protect" inline="yes">
++ <bitfield name="BASE_ADDR" low="0" high="17"/>
++ <bitfield name="MASK_LEN" low="18" high="30"/>
++ <bitfield name="READ" pos="31" type="boolean"/>
++</bitset>
++
++<enum name="a6xx_shader_id">
++ <value value="0x9" name="A6XX_TP0_TMO_DATA"/>
++ <value value="0xa" name="A6XX_TP0_SMO_DATA"/>
++ <value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/>
++ <value value="0x19" name="A6XX_TP1_TMO_DATA"/>
++ <value value="0x1a" name="A6XX_TP1_SMO_DATA"/>
++ <value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/>
++ <value value="0x29" name="A6XX_SP_INST_DATA"/>
++ <value value="0x2a" name="A6XX_SP_LB_0_DATA"/>
++ <value value="0x2b" name="A6XX_SP_LB_1_DATA"/>
++ <value value="0x2c" name="A6XX_SP_LB_2_DATA"/>
++ <value value="0x2d" name="A6XX_SP_LB_3_DATA"/>
++ <value value="0x2e" name="A6XX_SP_LB_4_DATA"/>
++ <value value="0x2f" name="A6XX_SP_LB_5_DATA"/>
++ <value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/>
++ <value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/>
++ <value value="0x32" name="A6XX_SP_UAV_DATA"/>
++ <value value="0x33" name="A6XX_SP_INST_TAG"/>
++ <value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/>
++ <value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/>
++ <value value="0x36" name="A6XX_SP_SMO_TAG"/>
++ <value value="0x37" name="A6XX_SP_STATE_DATA"/>
++ <value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/>
++ <value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/>
++ <value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
++ <value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
++ <value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
++ <value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
++ <value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/>
++ <value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/>
++ <value value="0x52" name="A6XX_HLSQ_INST_RAM"/>
++ <value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/>
++ <value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/>
++ <value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/>
++ <value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/>
++ <value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/>
++ <value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
++ <value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
++ <value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/>
++ <value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/>
++ <value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/>
++ <value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/>
++ <value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/>
++ <value value="0x63" name="A6XX_HLSQ_BACKEND_META"/>
++ <value value="0x70" name="A6XX_SP_LB_6_DATA"/>
++ <value value="0x71" name="A6XX_SP_LB_7_DATA"/>
++ <value value="0x73" name="A6XX_HLSQ_INST_RAM_1"/>
++</enum>
++
++<enum name="a7xx_statetype_id">
++ <value value="0" name="A7XX_TP0_NCTX_REG"/>
++ <value value="1" name="A7XX_TP0_CTX0_3D_CVS_REG"/>
++ <value value="2" name="A7XX_TP0_CTX0_3D_CPS_REG"/>
++ <value value="3" name="A7XX_TP0_CTX1_3D_CVS_REG"/>
++ <value value="4" name="A7XX_TP0_CTX1_3D_CPS_REG"/>
++ <value value="5" name="A7XX_TP0_CTX2_3D_CPS_REG"/>
++ <value value="6" name="A7XX_TP0_CTX3_3D_CPS_REG"/>
++ <value value="9" name="A7XX_TP0_TMO_DATA"/>
++ <value value="10" name="A7XX_TP0_SMO_DATA"/>
++ <value value="11" name="A7XX_TP0_MIPMAP_BASE_DATA"/>
++ <value value="32" name="A7XX_SP_NCTX_REG"/>
++ <value value="33" name="A7XX_SP_CTX0_3D_CVS_REG"/>
++ <value value="34" name="A7XX_SP_CTX0_3D_CPS_REG"/>
++ <value value="35" name="A7XX_SP_CTX1_3D_CVS_REG"/>
++ <value value="36" name="A7XX_SP_CTX1_3D_CPS_REG"/>
++ <value value="37" name="A7XX_SP_CTX2_3D_CPS_REG"/>
++ <value value="38" name="A7XX_SP_CTX3_3D_CPS_REG"/>
++ <value value="39" name="A7XX_SP_INST_DATA"/>
++ <value value="40" name="A7XX_SP_INST_DATA_1"/>
++ <value value="41" name="A7XX_SP_LB_0_DATA"/>
++ <value value="42" name="A7XX_SP_LB_1_DATA"/>
++ <value value="43" name="A7XX_SP_LB_2_DATA"/>
++ <value value="44" name="A7XX_SP_LB_3_DATA"/>
++ <value value="45" name="A7XX_SP_LB_4_DATA"/>
++ <value value="46" name="A7XX_SP_LB_5_DATA"/>
++ <value value="47" name="A7XX_SP_LB_6_DATA"/>
++ <value value="48" name="A7XX_SP_LB_7_DATA"/>
++ <value value="49" name="A7XX_SP_CB_RAM"/>
++ <value value="50" name="A7XX_SP_LB_13_DATA"/>
++ <value value="51" name="A7XX_SP_LB_14_DATA"/>
++ <value value="52" name="A7XX_SP_INST_TAG"/>
++ <value value="53" name="A7XX_SP_INST_DATA_2"/>
++ <value value="54" name="A7XX_SP_TMO_TAG"/>
++ <value value="55" name="A7XX_SP_SMO_TAG"/>
++ <value value="56" name="A7XX_SP_STATE_DATA"/>
++ <value value="57" name="A7XX_SP_HWAVE_RAM"/>
++ <value value="58" name="A7XX_SP_L0_INST_BUF"/>
++ <value value="59" name="A7XX_SP_LB_8_DATA"/>
++ <value value="60" name="A7XX_SP_LB_9_DATA"/>
++ <value value="61" name="A7XX_SP_LB_10_DATA"/>
++ <value value="62" name="A7XX_SP_LB_11_DATA"/>
++ <value value="63" name="A7XX_SP_LB_12_DATA"/>
++ <value value="64" name="A7XX_HLSQ_DATAPATH_DSTR_META"/>
++ <value value="67" name="A7XX_HLSQ_L2STC_TAG_RAM"/>
++ <value value="68" name="A7XX_HLSQ_L2STC_INFO_CMD"/>
++ <value value="69" name="A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG"/>
++ <value value="70" name="A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG"/>
++ <value value="71" name="A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM"/>
++ <value value="72" name="A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM"/>
++ <value value="73" name="A7XX_HLSQ_CHUNK_CVS_RAM"/>
++ <value value="74" name="A7XX_HLSQ_CHUNK_CPS_RAM"/>
++ <value value="75" name="A7XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
++ <value value="76" name="A7XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
++ <value value="77" name="A7XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
++ <value value="78" name="A7XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
++ <value value="79" name="A7XX_HLSQ_CVS_MISC_RAM"/>
++ <value value="80" name="A7XX_HLSQ_CPS_MISC_RAM"/>
++ <value value="81" name="A7XX_HLSQ_CPS_MISC_RAM_1"/>
++ <value value="82" name="A7XX_HLSQ_INST_RAM"/>
++ <value value="83" name="A7XX_HLSQ_GFX_CVS_CONST_RAM"/>
++ <value value="84" name="A7XX_HLSQ_GFX_CPS_CONST_RAM"/>
++ <value value="85" name="A7XX_HLSQ_CVS_MISC_RAM_TAG"/>
++ <value value="86" name="A7XX_HLSQ_CPS_MISC_RAM_TAG"/>
++ <value value="87" name="A7XX_HLSQ_INST_RAM_TAG"/>
++ <value value="88" name="A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
++ <value value="89" name="A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
++ <value value="90" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM"/>
++ <value value="91" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG"/>
++ <value value="92" name="A7XX_HLSQ_INST_RAM_1"/>
++ <value value="93" name="A7XX_HLSQ_STPROC_META"/>
++ <value value="94" name="A7XX_HLSQ_BV_BE_META"/>
++ <value value="95" name="A7XX_HLSQ_INST_RAM_2"/>
++ <value value="96" name="A7XX_HLSQ_DATAPATH_META"/>
++ <value value="97" name="A7XX_HLSQ_FRONTEND_META"/>
++ <value value="98" name="A7XX_HLSQ_INDIRECT_META"/>
++ <value value="99" name="A7XX_HLSQ_BACKEND_META"/>
++</enum>
++
++<enum name="a6xx_debugbus_id">
++ <value value="0x1" name="A6XX_DBGBUS_CP"/>
++ <value value="0x2" name="A6XX_DBGBUS_RBBM"/>
++ <value value="0x3" name="A6XX_DBGBUS_VBIF"/>
++ <value value="0x4" name="A6XX_DBGBUS_HLSQ"/>
++ <value value="0x5" name="A6XX_DBGBUS_UCHE"/>
++ <value value="0x6" name="A6XX_DBGBUS_DPM"/>
++ <value value="0x7" name="A6XX_DBGBUS_TESS"/>
++ <value value="0x8" name="A6XX_DBGBUS_PC"/>
++ <value value="0x9" name="A6XX_DBGBUS_VFDP"/>
++ <value value="0xa" name="A6XX_DBGBUS_VPC"/>
++ <value value="0xb" name="A6XX_DBGBUS_TSE"/>
++ <value value="0xc" name="A6XX_DBGBUS_RAS"/>
++ <value value="0xd" name="A6XX_DBGBUS_VSC"/>
++ <value value="0xe" name="A6XX_DBGBUS_COM"/>
++ <value value="0x10" name="A6XX_DBGBUS_LRZ"/>
++ <value value="0x11" name="A6XX_DBGBUS_A2D"/>
++ <value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/>
++ <value value="0x13" name="A6XX_DBGBUS_GMU_CX"/>
++ <value value="0x14" name="A6XX_DBGBUS_RBP"/>
++ <value value="0x15" name="A6XX_DBGBUS_DCS"/>
++ <value value="0x16" name="A6XX_DBGBUS_DBGC"/>
++ <value value="0x17" name="A6XX_DBGBUS_CX"/>
++ <value value="0x18" name="A6XX_DBGBUS_GMU_GX"/>
++ <value value="0x19" name="A6XX_DBGBUS_TPFCHE"/>
++ <value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/>
++ <value value="0x1d" name="A6XX_DBGBUS_GPC"/>
++ <value value="0x1e" name="A6XX_DBGBUS_LARC"/>
++ <value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/>
++ <value value="0x20" name="A6XX_DBGBUS_RB_0"/>
++ <value value="0x21" name="A6XX_DBGBUS_RB_1"/>
++ <value value="0x22" name="A6XX_DBGBUS_RB_2"/>
++ <value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/>
++ <value value="0x28" name="A6XX_DBGBUS_CCU_0"/>
++ <value value="0x29" name="A6XX_DBGBUS_CCU_1"/>
++ <value value="0x2a" name="A6XX_DBGBUS_CCU_2"/>
++ <value value="0x38" name="A6XX_DBGBUS_VFD_0"/>
++ <value value="0x39" name="A6XX_DBGBUS_VFD_1"/>
++ <value value="0x3a" name="A6XX_DBGBUS_VFD_2"/>
++ <value value="0x3b" name="A6XX_DBGBUS_VFD_3"/>
++ <value value="0x3c" name="A6XX_DBGBUS_VFD_4"/>
++ <value value="0x3d" name="A6XX_DBGBUS_VFD_5"/>
++ <value value="0x40" name="A6XX_DBGBUS_SP_0"/>
++ <value value="0x41" name="A6XX_DBGBUS_SP_1"/>
++ <value value="0x42" name="A6XX_DBGBUS_SP_2"/>
++ <value value="0x48" name="A6XX_DBGBUS_TPL1_0"/>
++ <value value="0x49" name="A6XX_DBGBUS_TPL1_1"/>
++ <value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/>
++ <value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/>
++ <value value="0x4c" name="A6XX_DBGBUS_TPL1_4"/>
++ <value value="0x4d" name="A6XX_DBGBUS_TPL1_5"/>
++ <value value="0x58" name="A6XX_DBGBUS_SPTP_0"/>
++ <value value="0x59" name="A6XX_DBGBUS_SPTP_1"/>
++ <value value="0x5a" name="A6XX_DBGBUS_SPTP_2"/>
++ <value value="0x5b" name="A6XX_DBGBUS_SPTP_3"/>
++ <value value="0x5c" name="A6XX_DBGBUS_SPTP_4"/>
++ <value value="0x5d" name="A6XX_DBGBUS_SPTP_5"/>
++</enum>
++
++<enum name="a7xx_state_location">
++ <value value="0" name="A7XX_HLSQ_STATE"/>
++ <value value="1" name="A7XX_HLSQ_DP"/>
++ <value value="2" name="A7XX_SP_TOP"/>
++ <value value="3" name="A7XX_USPTP"/>
++</enum>
++
++<enum name="a7xx_pipe">
++ <value value="0" name="A7XX_PIPE_NONE"/>
++ <value value="1" name="A7XX_PIPE_BR"/>
++ <value value="2" name="A7XX_PIPE_BV"/>
++ <value value="3" name="A7XX_PIPE_LPAC"/>
++</enum>
++
++<enum name="a7xx_cluster">
++ <value value="0" name="A7XX_CLUSTER_NONE"/>
++ <value value="1" name="A7XX_CLUSTER_FE"/>
++ <value value="2" name="A7XX_CLUSTER_SP_VS"/>
++ <value value="3" name="A7XX_CLUSTER_PC_VS"/>
++ <value value="4" name="A7XX_CLUSTER_GRAS"/>
++ <value value="5" name="A7XX_CLUSTER_SP_PS"/>
++ <value value="6" name="A7XX_CLUSTER_VPC_PS"/>
++ <value value="7" name="A7XX_CLUSTER_PS"/>
++</enum>
++
++<enum name="a7xx_debugbus_id">
++ <value value="1" name="A7XX_DBGBUS_CP_0_0"/>
++ <value value="2" name="A7XX_DBGBUS_CP_0_1"/>
++ <value value="3" name="A7XX_DBGBUS_RBBM"/>
++ <value value="5" name="A7XX_DBGBUS_GBIF_GX"/>
++ <value value="6" name="A7XX_DBGBUS_GBIF_CX"/>
++ <value value="7" name="A7XX_DBGBUS_HLSQ"/>
++ <value value="9" name="A7XX_DBGBUS_UCHE_0"/>
++ <value value="10" name="A7XX_DBGBUS_UCHE_1"/>
++ <value value="13" name="A7XX_DBGBUS_TESS_BR"/>
++ <value value="14" name="A7XX_DBGBUS_TESS_BV"/>
++ <value value="17" name="A7XX_DBGBUS_PC_BR"/>
++ <value value="18" name="A7XX_DBGBUS_PC_BV"/>
++ <value value="21" name="A7XX_DBGBUS_VFDP_BR"/>
++ <value value="22" name="A7XX_DBGBUS_VFDP_BV"/>
++ <value value="25" name="A7XX_DBGBUS_VPC_BR"/>
++ <value value="26" name="A7XX_DBGBUS_VPC_BV"/>
++ <value value="29" name="A7XX_DBGBUS_TSE_BR"/>
++ <value value="30" name="A7XX_DBGBUS_TSE_BV"/>
++ <value value="33" name="A7XX_DBGBUS_RAS_BR"/>
++ <value value="34" name="A7XX_DBGBUS_RAS_BV"/>
++ <value value="37" name="A7XX_DBGBUS_VSC"/>
++ <value value="39" name="A7XX_DBGBUS_COM_0"/>
++ <value value="43" name="A7XX_DBGBUS_LRZ_BR"/>
++ <value value="44" name="A7XX_DBGBUS_LRZ_BV"/>
++ <value value="47" name="A7XX_DBGBUS_UFC_0"/>
++ <value value="48" name="A7XX_DBGBUS_UFC_1"/>
++ <value value="55" name="A7XX_DBGBUS_GMU_GX"/>
++ <value value="59" name="A7XX_DBGBUS_DBGC"/>
++ <value value="60" name="A7XX_DBGBUS_CX"/>
++ <value value="61" name="A7XX_DBGBUS_GMU_CX"/>
++ <value value="62" name="A7XX_DBGBUS_GPC_BR"/>
++ <value value="63" name="A7XX_DBGBUS_GPC_BV"/>
++ <value value="66" name="A7XX_DBGBUS_LARC"/>
++ <value value="68" name="A7XX_DBGBUS_HLSQ_SPTP"/>
++ <value value="70" name="A7XX_DBGBUS_RB_0"/>
++ <value value="71" name="A7XX_DBGBUS_RB_1"/>
++ <value value="72" name="A7XX_DBGBUS_RB_2"/>
++ <value value="73" name="A7XX_DBGBUS_RB_3"/>
++ <value value="74" name="A7XX_DBGBUS_RB_4"/>
++ <value value="75" name="A7XX_DBGBUS_RB_5"/>
++ <value value="102" name="A7XX_DBGBUS_UCHE_WRAPPER"/>
++ <value value="106" name="A7XX_DBGBUS_CCU_0"/>
++ <value value="107" name="A7XX_DBGBUS_CCU_1"/>
++ <value value="108" name="A7XX_DBGBUS_CCU_2"/>
++ <value value="109" name="A7XX_DBGBUS_CCU_3"/>
++ <value value="110" name="A7XX_DBGBUS_CCU_4"/>
++ <value value="111" name="A7XX_DBGBUS_CCU_5"/>
++ <value value="138" name="A7XX_DBGBUS_VFD_BR_0"/>
++ <value value="139" name="A7XX_DBGBUS_VFD_BR_1"/>
++ <value value="140" name="A7XX_DBGBUS_VFD_BR_2"/>
++ <value value="141" name="A7XX_DBGBUS_VFD_BR_3"/>
++ <value value="142" name="A7XX_DBGBUS_VFD_BR_4"/>
++ <value value="143" name="A7XX_DBGBUS_VFD_BR_5"/>
++ <value value="144" name="A7XX_DBGBUS_VFD_BR_6"/>
++ <value value="145" name="A7XX_DBGBUS_VFD_BR_7"/>
++ <value value="202" name="A7XX_DBGBUS_VFD_BV_0"/>
++ <value value="203" name="A7XX_DBGBUS_VFD_BV_1"/>
++ <value value="204" name="A7XX_DBGBUS_VFD_BV_2"/>
++ <value value="205" name="A7XX_DBGBUS_VFD_BV_3"/>
++ <value value="234" name="A7XX_DBGBUS_USP_0"/>
++ <value value="235" name="A7XX_DBGBUS_USP_1"/>
++ <value value="236" name="A7XX_DBGBUS_USP_2"/>
++ <value value="237" name="A7XX_DBGBUS_USP_3"/>
++ <value value="238" name="A7XX_DBGBUS_USP_4"/>
++ <value value="239" name="A7XX_DBGBUS_USP_5"/>
++ <value value="266" name="A7XX_DBGBUS_TP_0"/>
++ <value value="267" name="A7XX_DBGBUS_TP_1"/>
++ <value value="268" name="A7XX_DBGBUS_TP_2"/>
++ <value value="269" name="A7XX_DBGBUS_TP_3"/>
++ <value value="270" name="A7XX_DBGBUS_TP_4"/>
++ <value value="271" name="A7XX_DBGBUS_TP_5"/>
++ <value value="272" name="A7XX_DBGBUS_TP_6"/>
++ <value value="273" name="A7XX_DBGBUS_TP_7"/>
++ <value value="274" name="A7XX_DBGBUS_TP_8"/>
++ <value value="275" name="A7XX_DBGBUS_TP_9"/>
++ <value value="276" name="A7XX_DBGBUS_TP_10"/>
++ <value value="277" name="A7XX_DBGBUS_TP_11"/>
++ <value value="330" name="A7XX_DBGBUS_USPTP_0"/>
++ <value value="331" name="A7XX_DBGBUS_USPTP_1"/>
++ <value value="332" name="A7XX_DBGBUS_USPTP_2"/>
++ <value value="333" name="A7XX_DBGBUS_USPTP_3"/>
++ <value value="334" name="A7XX_DBGBUS_USPTP_4"/>
++ <value value="335" name="A7XX_DBGBUS_USPTP_5"/>
++ <value value="336" name="A7XX_DBGBUS_USPTP_6"/>
++ <value value="337" name="A7XX_DBGBUS_USPTP_7"/>
++ <value value="338" name="A7XX_DBGBUS_USPTP_8"/>
++ <value value="339" name="A7XX_DBGBUS_USPTP_9"/>
++ <value value="340" name="A7XX_DBGBUS_USPTP_10"/>
++ <value value="341" name="A7XX_DBGBUS_USPTP_11"/>
++ <value value="396" name="A7XX_DBGBUS_CCHE_0"/>
++ <value value="397" name="A7XX_DBGBUS_CCHE_1"/>
++ <value value="398" name="A7XX_DBGBUS_CCHE_2"/>
++ <value value="408" name="A7XX_DBGBUS_VPC_DSTR_0"/>
++ <value value="409" name="A7XX_DBGBUS_VPC_DSTR_1"/>
++ <value value="410" name="A7XX_DBGBUS_VPC_DSTR_2"/>
++ <value value="411" name="A7XX_DBGBUS_HLSQ_DP_STR_0"/>
++ <value value="412" name="A7XX_DBGBUS_HLSQ_DP_STR_1"/>
++ <value value="413" name="A7XX_DBGBUS_HLSQ_DP_STR_2"/>
++ <value value="414" name="A7XX_DBGBUS_HLSQ_DP_STR_3"/>
++ <value value="415" name="A7XX_DBGBUS_HLSQ_DP_STR_4"/>
++ <value value="416" name="A7XX_DBGBUS_HLSQ_DP_STR_5"/>
++ <value value="443" name="A7XX_DBGBUS_UFC_DSTR_0"/>
++ <value value="444" name="A7XX_DBGBUS_UFC_DSTR_1"/>
++ <value value="445" name="A7XX_DBGBUS_UFC_DSTR_2"/>
++ <value value="446" name="A7XX_DBGBUS_CGC_SUBCORE"/>
++ <value value="447" name="A7XX_DBGBUS_CGC_CORE"/>
++</enum>
++
++<enum name="a6xx_cp_perfcounter_select">
++ <value value="0" name="PERF_CP_ALWAYS_COUNT"/>
++ <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
++ <value value="2" name="PERF_CP_BUSY_CYCLES"/>
++ <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/>
++ <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
++ <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
++ <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
++ <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
++ <value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
++ <value value="9" name="PERF_CP_MODE_SWITCH"/>
++ <value value="10" name="PERF_CP_ZPASS_DONE"/>
++ <value value="11" name="PERF_CP_CONTEXT_DONE"/>
++ <value value="12" name="PERF_CP_CACHE_FLUSH"/>
++ <value value="13" name="PERF_CP_LONG_PREEMPTIONS"/>
++ <value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/>
++ <value value="15" name="PERF_CP_SQE_IDLE"/>
++ <value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/>
++ <value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/>
++ <value value="18" name="PERF_CP_SQE_MRB_STARVE"/>
++ <value value="19" name="PERF_CP_SQE_RRB_STARVE"/>
++ <value value="20" name="PERF_CP_SQE_VSD_STARVE"/>
++ <value value="21" name="PERF_CP_VSD_DECODE_STARVE"/>
++ <value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/>
++ <value value="23" name="PERF_CP_SQE_SYNC_STALL"/>
++ <value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/>
++ <value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/>
++ <value value="26" name="PERF_CP_SQE_T4_EXEC"/>
++ <value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/>
++ <value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/>
++ <value value="29" name="PERF_CP_SQE_DRAW_EXEC"/>
++ <value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>
++ <value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/>
++ <value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/>
++ <value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/>
++ <value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>
++ <value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>
++ <value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/>
++ <value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/>
++ <value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/>
++ <value value="39" name="PERF_CP_CLUSTER0_EMPTY"/>
++ <value value="40" name="PERF_CP_CLUSTER1_EMPTY"/>
++ <value value="41" name="PERF_CP_CLUSTER2_EMPTY"/>
++ <value value="42" name="PERF_CP_CLUSTER3_EMPTY"/>
++ <value value="43" name="PERF_CP_CLUSTER4_EMPTY"/>
++ <value value="44" name="PERF_CP_CLUSTER5_EMPTY"/>
++ <value value="45" name="PERF_CP_PM4_DATA"/>
++ <value value="46" name="PERF_CP_PM4_HEADERS"/>
++ <value value="47" name="PERF_CP_VBIF_READ_BEATS"/>
++ <value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/>
++ <value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/>
++</enum>
++
++<enum name="a6xx_rbbm_perfcounter_select">
++ <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
++ <value value="1" name="PERF_RBBM_ALWAYS_ON"/>
++ <value value="2" name="PERF_RBBM_TSE_BUSY"/>
++ <value value="3" name="PERF_RBBM_RAS_BUSY"/>
++ <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
++ <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
++ <value value="6" name="PERF_RBBM_STATUS_MASKED"/>
++ <value value="7" name="PERF_RBBM_COM_BUSY"/>
++ <value value="8" name="PERF_RBBM_DCOM_BUSY"/>
++ <value value="9" name="PERF_RBBM_VBIF_BUSY"/>
++ <value value="10" name="PERF_RBBM_VSC_BUSY"/>
++ <value value="11" name="PERF_RBBM_TESS_BUSY"/>
++ <value value="12" name="PERF_RBBM_UCHE_BUSY"/>
++ <value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
++</enum>
++
++<enum name="a6xx_pc_perfcounter_select">
++ <value value="0" name="PERF_PC_BUSY_CYCLES"/>
++ <value value="1" name="PERF_PC_WORKING_CYCLES"/>
++ <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
++ <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
++ <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
++ <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
++ <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
++ <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
++ <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
++ <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
++ <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
++ <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
++ <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
++ <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
++ <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
++ <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
++ <value value="16" name="PERF_PC_INSTANCES"/>
++ <value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
++ <value value="18" name="PERF_PC_DEAD_PRIM"/>
++ <value value="19" name="PERF_PC_LIVE_PRIM"/>
++ <value value="20" name="PERF_PC_VERTEX_HITS"/>
++ <value value="21" name="PERF_PC_IA_VERTICES"/>
++ <value value="22" name="PERF_PC_IA_PRIMITIVES"/>
++ <value value="23" name="PERF_PC_GS_PRIMITIVES"/>
++ <value value="24" name="PERF_PC_HS_INVOCATIONS"/>
++ <value value="25" name="PERF_PC_DS_INVOCATIONS"/>
++ <value value="26" name="PERF_PC_VS_INVOCATIONS"/>
++ <value value="27" name="PERF_PC_GS_INVOCATIONS"/>
++ <value value="28" name="PERF_PC_DS_PRIMITIVES"/>
++ <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
++ <value value="30" name="PERF_PC_3D_DRAWCALLS"/>
++ <value value="31" name="PERF_PC_2D_DRAWCALLS"/>
++ <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
++ <value value="33" name="PERF_TESS_BUSY_CYCLES"/>
++ <value value="34" name="PERF_TESS_WORKING_CYCLES"/>
++ <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
++ <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
++ <value value="37" name="PERF_PC_TSE_TRANSACTION"/>
++ <value value="38" name="PERF_PC_TSE_VERTEX"/>
++ <value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/>
++ <value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/>
++ <value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/>
++</enum>
++
++<enum name="a6xx_vfd_perfcounter_select">
++ <value value="0" name="PERF_VFD_BUSY_CYCLES"/>
++ <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
++ <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
++ <value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
++ <value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
++ <value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
++ <value value="6" name="PERF_VFD_RBUFFER_FULL"/>
++ <value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
++ <value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
++ <value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/>
++ <value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
++ <value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
++ <value value="12" name="PERF_VFD_MODE_0_FIBERS"/>
++ <value value="13" name="PERF_VFD_MODE_1_FIBERS"/>
++ <value value="14" name="PERF_VFD_MODE_2_FIBERS"/>
++ <value value="15" name="PERF_VFD_MODE_3_FIBERS"/>
++ <value value="16" name="PERF_VFD_MODE_4_FIBERS"/>
++ <value value="17" name="PERF_VFD_TOTAL_VERTICES"/>
++ <value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/>
++ <value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
++ <value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
++ <value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/>
++ <value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/>
++</enum>
++
++<enum name="a6xx_hlsq_perfcounter_select">
++ <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
++ <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
++ <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
++ <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
++ <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
++ <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
++ <value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/>
++ <value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/>
++ <value value="8" name="PERF_HLSQ_QUADS"/>
++ <value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/>
++ <value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
++ <value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/>
++ <value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/>
++ <value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/>
++ <value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/>
++ <value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/>
++ <value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/>
++ <value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/>
++ <value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/>
++ <value value="19" name="PERF_HLSQ_PIXELS"/>
++ <value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/>
++</enum>
++
++<enum name="a6xx_vpc_perfcounter_select">
++ <value value="0" name="PERF_VPC_BUSY_CYCLES"/>
++ <value value="1" name="PERF_VPC_WORKING_CYCLES"/>
++ <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
++ <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
++ <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
++ <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
++ <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
++ <value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/>
++ <value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
++ <value value="9" name="PERF_VPC_PC_PRIMITIVES"/>
++ <value value="10" name="PERF_VPC_SP_COMPONENTS"/>
++ <value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/>
++ <value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/>
++ <value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/>
++ <value value="14" name="PERF_VPC_LM_TRANSACTION"/>
++ <value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/>
++ <value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/>
++ <value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/>
++ <value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/>
++ <value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/>
++ <value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/>
++ <value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/>
++ <value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/>
++ <value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/>
++ <value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/>
++ <value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/>
++ <value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/>
++ <value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/>
++</enum>
++
++<enum name="a6xx_tse_perfcounter_select">
++ <value value="0" name="PERF_TSE_BUSY_CYCLES"/>
++ <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
++ <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
++ <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
++ <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
++ <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
++ <value value="6" name="PERF_TSE_INPUT_PRIM"/>
++ <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
++ <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
++ <value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
++ <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
++ <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
++ <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
++ <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
++ <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
++ <value value="15" name="PERF_TSE_CINVOCATION"/>
++ <value value="16" name="PERF_TSE_CPRIMITIVES"/>
++ <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
++ <value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/>
++ <value value="19" name="PERF_TSE_CLIP_PLANES"/>
++</enum>
++
++<enum name="a6xx_ras_perfcounter_select">
++ <value value="0" name="PERF_RAS_BUSY_CYCLES"/>
++ <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
++ <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
++ <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
++ <value value="4" name="PERF_RAS_SUPER_TILES"/>
++ <value value="5" name="PERF_RAS_8X4_TILES"/>
++ <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
++ <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
++ <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
++ <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
++ <value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/>
++ <value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/>
++ <value value="12" name="PERF_RAS_BLOCKS"/>
++</enum>
++
++<enum name="a6xx_uche_perfcounter_select">
++ <value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
++ <value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/>
++ <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
++ <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
++ <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
++ <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
++ <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
++ <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
++ <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
++ <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
++ <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
++ <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
++ <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
++ <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
++ <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
++ <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
++ <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
++ <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
++ <value value="18" name="PERF_UCHE_EVICTS"/>
++ <value value="19" name="PERF_UCHE_BANK_REQ0"/>
++ <value value="20" name="PERF_UCHE_BANK_REQ1"/>
++ <value value="21" name="PERF_UCHE_BANK_REQ2"/>
++ <value value="22" name="PERF_UCHE_BANK_REQ3"/>
++ <value value="23" name="PERF_UCHE_BANK_REQ4"/>
++ <value value="24" name="PERF_UCHE_BANK_REQ5"/>
++ <value value="25" name="PERF_UCHE_BANK_REQ6"/>
++ <value value="26" name="PERF_UCHE_BANK_REQ7"/>
++ <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
++ <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
++ <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
++ <value value="30" name="PERF_UCHE_TPH_REF_FULL"/>
++ <value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/>
++ <value value="32" name="PERF_UCHE_TPH_EXT_FULL"/>
++ <value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/>
++ <value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/>
++ <value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/>
++ <value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/>
++ <value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/>
++ <value value="38" name="PERF_UCHE_RAM_READ_REQ"/>
++ <value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/>
++</enum>
++
++<enum name="a6xx_tp_perfcounter_select">
++ <value value="0" name="PERF_TP_BUSY_CYCLES"/>
++ <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
++ <value value="2" name="PERF_TP_LATENCY_CYCLES"/>
++ <value value="3" name="PERF_TP_LATENCY_TRANS"/>
++ <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
++ <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
++ <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
++ <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
++ <value value="8" name="PERF_TP_SP_TP_TRANS"/>
++ <value value="9" name="PERF_TP_TP_SP_TRANS"/>
++ <value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
++ <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
++ <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
++ <value value="13" name="PERF_TP_QUADS_RECEIVED"/>
++ <value value="14" name="PERF_TP_QUADS_OFFSET"/>
++ <value value="15" name="PERF_TP_QUADS_SHADOW"/>
++ <value value="16" name="PERF_TP_QUADS_ARRAY"/>
++ <value value="17" name="PERF_TP_QUADS_GRADIENT"/>
++ <value value="18" name="PERF_TP_QUADS_1D"/>
++ <value value="19" name="PERF_TP_QUADS_2D"/>
++ <value value="20" name="PERF_TP_QUADS_BUFFER"/>
++ <value value="21" name="PERF_TP_QUADS_3D"/>
++ <value value="22" name="PERF_TP_QUADS_CUBE"/>
++ <value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
++ <value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
++ <value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
++ <value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
++ <value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
++ <value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
++ <value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
++ <value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
++ <value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/>
++ <value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/>
++ <value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/>
++ <value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
++ <value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
++ <value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
++ <value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
++ <value value="38" name="PERF_TP_TPA2TPC_TRANS"/>
++ <value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/>
++ <value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/>
++ <value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/>
++ <value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/>
++ <value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/>
++ <value value="44" name="PERF_TP_L1_BANK_CONFLICT"/>
++ <value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/>
++ <value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/>
++ <value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/>
++ <value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/>
++ <value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/>
++ <value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/>
++ <value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/>
++ <value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/>
++ <value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/>
++ <value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/>
++ <value value="55" name="PERF_TP_STARVE_CYCLES_SP"/>
++ <value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/>
++</enum>
++
++<enum name="a6xx_sp_perfcounter_select">
++ <value value="0" name="PERF_SP_BUSY_CYCLES"/>
++ <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
++ <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
++ <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
++ <value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
++ <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
++ <value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
++ <value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/>
++ <value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
++ <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
++ <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
++ <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
++ <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
++ <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
++ <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
++ <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
++ <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
++ <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
++ <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
++ <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
++ <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
++ <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
++ <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
++ <value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
++ <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
++ <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
++ <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
++ <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
++ <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
++ <value value="29" name="PERF_SP_LM_ATOMICS"/>
++ <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
++ <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
++ <value value="32" name="PERF_SP_GM_ATOMICS"/>
++ <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
++ <value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
++ <value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
++ <value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
++ <value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
++ <value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
++ <value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
++ <value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
++ <value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
++ <value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
++ <value value="43" name="PERF_SP_VS_INSTRUCTIONS"/>
++ <value value="44" name="PERF_SP_FS_INSTRUCTIONS"/>
++ <value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/>
++ <value value="46" name="PERF_SP_UCHE_READ_TRANS"/>
++ <value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/>
++ <value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/>
++ <value value="49" name="PERF_SP_EXPORT_RB_TRANS"/>
++ <value value="50" name="PERF_SP_PIXELS_KILLED"/>
++ <value value="51" name="PERF_SP_ICL1_REQUESTS"/>
++ <value value="52" name="PERF_SP_ICL1_MISSES"/>
++ <value value="53" name="PERF_SP_HS_INSTRUCTIONS"/>
++ <value value="54" name="PERF_SP_DS_INSTRUCTIONS"/>
++ <value value="55" name="PERF_SP_GS_INSTRUCTIONS"/>
++ <value value="56" name="PERF_SP_CS_INSTRUCTIONS"/>
++ <value value="57" name="PERF_SP_GPR_READ"/>
++ <value value="58" name="PERF_SP_GPR_WRITE"/>
++ <value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/>
++ <value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/>
++ <value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/>
++ <value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/>
++ <value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/>
++ <value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/>
++ <value value="65" name="PERF_SP_LM_WORKING_CYCLES"/>
++ <value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/>
++ <value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/>
++ <value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/>
++ <value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/>
++ <value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/>
++ <value value="71" name="PERF_SP_WORKING_EU"/>
++ <value value="72" name="PERF_SP_ANY_EU_WORKING"/>
++ <value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/>
++ <value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/>
++ <value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/>
++ <value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/>
++ <value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/>
++ <value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/>
++ <value value="79" name="PERF_SP_GPR_READ_PREFETCH"/>
++ <value value="80" name="PERF_SP_GPR_READ_CONFLICT"/>
++ <value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/>
++ <value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/>
++ <value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/>
++ <value value="84" name="PERF_SP_EXECUTABLE_WAVES"/>
++</enum>
++
++<enum name="a6xx_rb_perfcounter_select">
++ <value value="0" name="PERF_RB_BUSY_CYCLES"/>
++ <value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/>
++ <value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
++ <value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
++ <value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
++ <value value="5" name="PERF_RB_STARVE_CYCLES_SP"/>
++ <value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
++ <value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/>
++ <value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
++ <value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
++ <value value="10" name="PERF_RB_Z_WORKLOAD"/>
++ <value value="11" name="PERF_RB_HLSQ_ACTIVE"/>
++ <value value="12" name="PERF_RB_Z_READ"/>
++ <value value="13" name="PERF_RB_Z_WRITE"/>
++ <value value="14" name="PERF_RB_C_READ"/>
++ <value value="15" name="PERF_RB_C_WRITE"/>
++ <value value="16" name="PERF_RB_TOTAL_PASS"/>
++ <value value="17" name="PERF_RB_Z_PASS"/>
++ <value value="18" name="PERF_RB_Z_FAIL"/>
++ <value value="19" name="PERF_RB_S_FAIL"/>
++ <value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
++ <value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
++ <value value="22" name="PERF_RB_PS_INVOCATIONS"/>
++ <value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/>
++ <value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
++ <value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
++ <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
++ <value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
++ <value value="28" name="PERF_RB_2D_VALID_PIXELS"/>
++ <value value="29" name="PERF_RB_3D_PIXELS"/>
++ <value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/>
++ <value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/>
++ <value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/>
++ <value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/>
++ <value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/>
++ <value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/>
++ <value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/>
++ <value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/>
++ <value value="38" name="PERF_RB_STALL_CYCLES_VPC"/>
++ <value value="39" name="PERF_RB_2D_INPUT_TRANS"/>
++ <value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/>
++ <value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/>
++ <value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/>
++ <value value="43" name="PERF_RB_COLOR_PIX_TILES"/>
++ <value value="44" name="PERF_RB_STALL_CYCLES_CCU"/>
++ <value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/>
++ <value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/>
++ <value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/>
++</enum>
++
++<enum name="a6xx_vsc_perfcounter_select">
++ <value value="0" name="PERF_VSC_BUSY_CYCLES"/>
++ <value value="1" name="PERF_VSC_WORKING_CYCLES"/>
++ <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
++ <value value="3" name="PERF_VSC_EOT_NUM"/>
++ <value value="4" name="PERF_VSC_INPUT_TILES"/>
++</enum>
++
++<enum name="a6xx_ccu_perfcounter_select">
++ <value value="0" name="PERF_CCU_BUSY_CYCLES"/>
++ <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
++ <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
++ <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
++ <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
++ <value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
++ <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
++ <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
++ <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
++ <value value="9" name="PERF_CCU_GMEM_READ"/>
++ <value value="10" name="PERF_CCU_GMEM_WRITE"/>
++ <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
++ <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
++ <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
++ <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
++ <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
++ <value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/>
++ <value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/>
++ <value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/>
++ <value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
++ <value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
++ <value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
++ <value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
++ <value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
++ <value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/>
++ <value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/>
++ <value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/>
++ <value value="27" name="PERF_CCU_2D_RD_REQ"/>
++ <value value="28" name="PERF_CCU_2D_WR_REQ"/>
++</enum>
++
++<enum name="a6xx_lrz_perfcounter_select">
++ <value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
++ <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
++ <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
++ <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
++ <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
++ <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
++ <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
++ <value value="7" name="PERF_LRZ_LRZ_READ"/>
++ <value value="8" name="PERF_LRZ_LRZ_WRITE"/>
++ <value value="9" name="PERF_LRZ_READ_LATENCY"/>
++ <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
++ <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
++ <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
++ <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
++ <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
++ <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
++ <value value="16" name="PERF_LRZ_TILE_KILLED"/>
++ <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
++ <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
++ <value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/>
++ <value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/>
++ <value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/>
++ <value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/>
++ <value value="23" name="PERF_LRZ_FEEDBACK_STALL"/>
++ <value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/>
++ <value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/>
++ <value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/>
++ <value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/>
++</enum>
++
++<enum name="a6xx_cmp_perfcounter_select">
++ <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/>
++ <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
++ <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
++ <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
++ <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
++ <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
++ <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
++ <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
++ <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
++ <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
++ <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
++ <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
++ <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
++ <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
++ <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
++ <value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/>
++ <value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/>
++ <value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/>
++ <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
++ <value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
++ <value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
++ <value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
++ <value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/>
++ <value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/>
++ <value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/>
++ <value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
++ <value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
++ <value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
++ <value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/>
++ <value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/>
++ <value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/>
++ <value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/>
++ <value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/>
++ <value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/>
++ <value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/>
++ <value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/>
++ <value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/>
++ <value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/>
++ <value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/>
++ <value value="39" name="PERF_CMPDECMP_2D_PIXELS"/>
++</enum>
++
++<!--
++Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the
++component type/size, so I think it relates to internal format used for
++blending? The one exception is that 16b unorm and 32b float use the
++same value... maybe 16b unorm is uncommon enough that it was just easier
++to upconvert to 32b float internally?
++
++ 8b unorm: 10 (sometimes 0, is the high bit part of something else?)
++16b unorm: 4
++
++32b int: 7
++16b int: 6
++ 8b int: 5
++
++32b float: 4
++16b float: 3
++ -->
++<enum name="a6xx_2d_ifmt">
++ <value value="0x10" name="R2D_UNORM8"/>
++ <value value="0x7" name="R2D_INT32"/>
++ <value value="0x6" name="R2D_INT16"/>
++ <value value="0x5" name="R2D_INT8"/>
++ <value value="0x4" name="R2D_FLOAT32"/>
++ <value value="0x3" name="R2D_FLOAT16"/>
++ <value value="0x1" name="R2D_UNORM8_SRGB"/>
++ <value value="0x0" name="R2D_RAW"/>
++</enum>
++
++<enum name="a6xx_ztest_mode">
++ <doc>Allow early z-test and early-lrz (if applicable)</doc>
++ <value value="0x0" name="A6XX_EARLY_Z"/>
++ <doc>Disable early z-test and early-lrz test (if applicable)</doc>
++ <value value="0x1" name="A6XX_LATE_Z"/>
++ <doc>
++ A special mode that allows early-lrz test but disables
++ early-z test. Which might sound a bit funny, since
++ lrz-test happens before z-test. But as long as a couple
++ conditions are maintained this allows using lrz-test in
++ cases where fragment shader has kill/discard:
++
++ 1) Disable lrz-write in cases where it is uncertain during
++ binning pass that a fragment will pass. Ie. if frag
++ shader has-kill, writes-z, or alpha/stencil test is
++ enabled. (For correctness, lrz-write must be disabled
++ when blend is enabled.) This is analogous to how a
++ z-prepass works.
++
++ 2) Disable lrz-write and test if a depth-test direction
++ reversal is detected. Due to condition (1), the contents
++ of the lrz buffer are a conservative estimation of the
++ depth buffer during the draw pass. Meaning that geometry
++ that we know for certain will not be visible will not pass
++ lrz-test. But geometry which may be (or contributes to
++ blend) will pass the lrz-test.
++
++ This allows us to keep early-lrz-test in cases where the frag
++ shader does not write-z (ie. we know the z-value before FS)
++ and does not have side-effects (image/ssbo writes, etc), but
++ does have kill/discard. Which turns out to be a common
++ enough case that it is useful to keep early-lrz test against
++ the conservative lrz buffer to discard fragments that we
++ know will definitely not be visible.
++ </doc>
++ <value value="0x2" name="A6XX_EARLY_LRZ_LATE_Z"/>
++ <doc>Not a real hw value, used internally by mesa</doc>
++ <value value="0x3" name="A6XX_INVALID_ZTEST"/>
++</enum>
++
++<enum name="a6xx_tess_spacing">
++ <value value="0x0" name="TESS_EQUAL"/>
++ <value value="0x2" name="TESS_FRACTIONAL_ODD"/>
++ <value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
++</enum>
++<enum name="a6xx_tess_output">
++ <value value="0x0" name="TESS_POINTS"/>
++ <value value="0x1" name="TESS_LINES"/>
++ <value value="0x2" name="TESS_CW_TRIS"/>
++ <value value="0x3" name="TESS_CCW_TRIS"/>
++</enum>
++
++<domain name="A6XX" width="32" prefix="variant" varset="chip">
++ <bitset name="A6XX_RBBM_INT_0_MASK" inline="no" varset="chip">
++ <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
++ <bitfield name="CP_AHB_ERROR" pos="1" type="boolean"/>
++ <bitfield name="CP_IPC_INTR_0" pos="4" type="boolean" variants="A7XX-"/>
++ <bitfield name="CP_IPC_INTR_1" pos="5" type="boolean" variants="A7XX-"/>
++ <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6" type="boolean"/>
++ <bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>
++ <bitfield name="CP_SW" pos="8" type="boolean"/>
++ <bitfield name="CP_HW_ERROR" pos="9" type="boolean"/>
++ <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/>
++ <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/>
++ <bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/>
++ <bitfield name="CP_IB2" pos="13" type="boolean"/>
++ <bitfield name="CP_IB1" pos="14" type="boolean"/>
++ <bitfield name="CP_RB" pos="15" type="boolean" variants="A6XX"/>
++ <!-- Same as above but different name??: -->
++ <bitfield name="PM4CPINTERRUPT" pos="15" type="boolean" variants="A7XX-"/>
++ <bitfield name="PM4CPINTERRUPTLPAC" pos="16" type="boolean" variants="A7XX-"/>
++ <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
++ <bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/>
++ <bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/>
++ <bitfield name="CP_CACHE_FLUSH_TS_LPAC" pos="21" type="boolean" variants="A7XX-"/>
++ <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/>
++ <bitfield name="RBBM_HANG_DETECT" pos="23" type="boolean"/>
++ <bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/>
++ <bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/>
++ <bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/>
++ <bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/>
++ <bitfield name="TSBWRITEERROR" pos="28" type="boolean" variants="A7XX-"/>
++ <bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/>
++ <bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/>
++ </bitset>
++
++ <!--
++ Note the _LPAC bits probably *actually* first appeared in a660, but the
++ _BV bits are new in a7xx
++ -->
++ <bitset name="A6XX_CP_INT" varset="chip">
++ <bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/>
++ <bitfield name="CP_UCODE_ERROR" pos="1" type="boolean"/>
++ <bitfield name="CP_HW_FAULT_ERROR" pos="2" type="boolean"/>
++ <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4" type="boolean"/>
++ <bitfield name="CP_AHB_ERROR" pos="5" type="boolean"/>
++ <bitfield name="CP_VSD_PARITY_ERROR" pos="6" type="boolean"/>
++ <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7" type="boolean"/>
++ <bitfield name="CP_OPCODE_ERROR_LPAC" pos="8" type="boolean" variants="A7XX-"/>
++ <bitfield name="CP_UCODE_ERROR_LPAC" pos="9" type="boolean" variants="A7XX-"/>
++ <bitfield name="CP_HW_FAULT_ERROR_LPAC" pos="10" type="boolean" variants="A7XX-"/>
++ <bitfield name="CP_REGISTER_PROTECTION_ERROR_LPAC" pos="11" type="boolean" variants="A7XX-"/>
++ <bitfield name="CP_ILLEGAL_INSTR_ERROR_LPAC" pos="12" type="boolean" variants="A7XX-"/>
++ <bitfield name="CP_OPCODE_ERROR_BV" pos="13" type="boolean" variants="A7XX-"/>
++ <bitfield name="CP_UCODE_ERROR_BV" pos="14" type="boolean" variants="A7XX-"/>
++ <bitfield name="CP_HW_FAULT_ERROR_BV" pos="15" type="boolean" variants="A7XX-"/>
++ <bitfield name="CP_REGISTER_PROTECTION_ERROR_BV" pos="16" type="boolean" variants="A7XX-"/>
++ <bitfield name="CP_ILLEGAL_INSTR_ERROR_BV" pos="17" type="boolean" variants="A7XX-"/>
++ </bitset>
++
++ <reg64 offset="0x0800" name="CP_RB_BASE"/>
++ <reg32 offset="0x0802" name="CP_RB_CNTL"/>
++ <reg64 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
++ <reg32 offset="0x0806" name="CP_RB_RPTR"/>
++ <reg32 offset="0x0807" name="CP_RB_WPTR"/>
++ <reg32 offset="0x0808" name="CP_SQE_CNTL"/>
++ <reg32 offset="0x0812" name="CP_CP2GMU_STATUS">
++ <bitfield name="IFPC" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0821" name="CP_HW_FAULT"/>
++ <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS" type="A6XX_CP_INT"/>
++ <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
++ <reg32 offset="0x0825" name="CP_STATUS_1"/>
++ <reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/>
++ <reg32 offset="0x0840" name="CP_MISC_CNTL"/>
++ <reg32 offset="0x0844" name="CP_APRIV_CNTL">
++ <!-- Crashdumper writes -->
++ <bitfield pos="6" name="CDWRITE" type="boolean"/>
++ <!-- Crashdumper reads -->
++ <bitfield pos="5" name="CDREAD" type="boolean"/>
++
++ <!-- 4 is unknown -->
++
++ <!-- RPTR shadow writes -->
++ <bitfield pos="3" name="RBRPWB" type="boolean"/>
++ <!-- Memory accesses from PM4 packets in the ringbuffer -->
++ <bitfield pos="2" name="RBPRIVLEVEL" type="boolean"/>
++ <!-- Ringbuffer reads -->
++ <bitfield pos="1" name="RBFETCH" type="boolean"/>
++ <!-- Instruction cache fetches -->
++ <bitfield pos="0" name="ICACHE" type="boolean"/>
++ </reg32>
++ <!-- Preemptions taking longer than this threshold increment PERF_CP_LONG_PREEMPTIONS: -->
++ <reg32 offset="0x08C0" name="CP_PREEMPT_THRESHOLD"/>
++ <!-- all the threshold values seem to be in units of quad-dwords: -->
++ <reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1">
++ <doc>
++ b0..7 identifies where MRB data starts (and RB data ends)
++ b8.15 identifies where VSD data starts (and MRB data ends)
++ b16..23 identifies where IB1 data starts (and RB data ends)
++ b24..31 identifies where IB2 data starts (and IB1 data ends)
++ </doc>
++ <bitfield name="MRB_START" low="0" high="7" shr="2"/>
++ <bitfield name="VSD_START" low="8" high="15" shr="2"/>
++ <bitfield name="IB1_START" low="16" high="23" shr="2"/>
++ <bitfield name="IB2_START" low="24" high="31" shr="2"/>
++ </reg32>
++ <reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2">
++ <doc>
++ low bits identify where CP_SET_DRAW_STATE stateobj
++ processing starts (and IB2 data ends). I'm guessing
++ b8 is part of this since (from downstream kgsl):
++
++ /* ROQ sizes are twice as big on a640/a680 than on a630 */
++ if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) {
++ kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
++ kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);
++ } ...
++ </doc>
++ <bitfield name="SDS_START" low="0" high="8" shr="2"/>
++ <!-- total ROQ size: -->
++ <bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/>
++ </reg32>
++ <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
++ <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
++ <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++ <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
++ <reg32 offset="0x084F" name="CP_PROTECT_CNTL">
++ <bitfield pos="3" name="LAST_SPAN_INF_RANGE" type="boolean"/>
++ <bitfield pos="1" name="ACCESS_FAULT_ON_VIOL_EN" type="boolean"/>
++ <bitfield pos="0" name="ACCESS_PROT_EN" type="boolean"/>
++ </reg32>
++
++ <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
++ <reg32 offset="0x0" name="REG" type="uint"/>
++ </array>
++ <array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
++ <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
++ </array>
++
++ <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
++ <reg64 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/>
++ <reg64 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/>
++ <reg64 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/>
++ <reg64 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR"/>
++ <reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX-"/>
++ <array offset="0x08D0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/>
++ <array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX-"/>
++ <reg64 offset="0x0900" name="CP_CRASH_SCRIPT_BASE"/>
++ <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
++ <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
++ <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
++ <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
++ <reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
++ <reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
++ <reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
++ <reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
++ <reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
++ <reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
++ <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
++ <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
++ <reg64 offset="0x0928" name="CP_IB1_BASE"/>
++ <reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
++ <reg64 offset="0x092B" name="CP_IB2_BASE"/>
++ <reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
++ <!-- SDS == CP_SET_DRAW_STATE: -->
++ <reg64 offset="0x092e" name="CP_SDS_BASE"/>
++ <reg32 offset="0x0930" name="CP_SDS_REM_SIZE"/>
++ <!-- MRB == MEM_READ_ADDR/$addr in SQE firmware -->
++ <reg64 offset="0x0931" name="CP_MRB_BASE"/>
++ <reg32 offset="0x0933" name="CP_MRB_REM_SIZE"/>
++ <!--
++ VSD == Visibility Stream Decode
++ This is used by CP to read the draw stream and skip empty draws
++ -->
++ <reg64 offset="0x0934" name="CP_VSD_BASE"/>
++
++ <bitset name="a6xx_roq_stat" inline="yes">
++ <bitfield name="RPTR" low="0" high="9"/>
++ <bitfield name="WPTR" low="16" high="25"/>
++ </bitset>
++ <reg32 offset="0x0939" name="CP_ROQ_RB_STAT" type="a6xx_roq_stat"/>
++ <reg32 offset="0x093a" name="CP_ROQ_IB1_STAT" type="a6xx_roq_stat"/>
++ <reg32 offset="0x093b" name="CP_ROQ_IB2_STAT" type="a6xx_roq_stat"/>
++ <reg32 offset="0x093c" name="CP_ROQ_SDS_STAT" type="a6xx_roq_stat"/>
++ <reg32 offset="0x093d" name="CP_ROQ_MRB_STAT" type="a6xx_roq_stat"/>
++ <reg32 offset="0x093e" name="CP_ROQ_VSD_STAT" type="a6xx_roq_stat"/>
++
++ <reg32 offset="0x0943" name="CP_IB1_DWORDS"/>
++ <reg32 offset="0x0944" name="CP_IB2_DWORDS"/>
++ <reg32 offset="0x0945" name="CP_SDS_DWORDS"/>
++ <reg32 offset="0x0946" name="CP_MRB_DWORDS"/>
++ <reg32 offset="0x0947" name="CP_VSD_DWORDS"/>
++
++ <reg32 offset="0x0948" name="CP_ROQ_AVAIL_RB">
++ <doc>number of remaining dwords incl current dword being consumed?</doc>
++ <bitfield name="REM" low="16" high="31"/>
++ </reg32>
++ <reg32 offset="0x0949" name="CP_ROQ_AVAIL_IB1">
++ <doc>number of remaining dwords incl current dword being consumed?</doc>
++ <bitfield name="REM" low="16" high="31"/>
++ </reg32>
++ <reg32 offset="0x094a" name="CP_ROQ_AVAIL_IB2">
++ <doc>number of remaining dwords incl current dword being consumed?</doc>
++ <bitfield name="REM" low="16" high="31"/>
++ </reg32>
++ <reg32 offset="0x094b" name="CP_ROQ_AVAIL_SDS">
++ <doc>number of remaining dwords incl current dword being consumed?</doc>
++ <bitfield name="REM" low="16" high="31"/>
++ </reg32>
++ <reg32 offset="0x094c" name="CP_ROQ_AVAIL_MRB">
++ <doc>number of dwords that have already been read but haven't been consumed by $addr</doc>
++ <bitfield name="REM" low="16" high="31"/>
++ </reg32>
++ <reg32 offset="0x094d" name="CP_ROQ_AVAIL_VSD">
++ <doc>number of remaining dwords incl current dword being consumed?</doc>
++ <bitfield name="REM" low="16" high="31"/>
++ </reg32>
++
++ <bitset name="a7xx_aperture_cntl" inline="yes">
++ <bitfield name="PIPE" low="12" high="13" type="a7xx_pipe"/>
++ <bitfield name="CLUSTER" low="8" high="10" type="a7xx_cluster"/>
++ <bitfield name="CONTEXT" low="4" high="5"/>
++ </bitset>
++ <reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER"/>
++ <reg32 offset="0x098D" name="CP_AHB_CNTL"/>
++ <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" variants="A6XX"/>
++ <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX-"/>
++ <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" variants="A6XX"/>
++ <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" type="a7xx_aperture_cntl" variants="A7XX-"/>
++
++ <reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS" variants="A7XX-"/>
++ <reg32 offset="0x0a64" name="CP_BV_HW_FAULT" variants="A7XX-"/>
++ <reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR" variants="A7XX-"/>
++ <reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA" variants="A7XX-"/>
++ <reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR" variants="A7XX-"/>
++ <reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA" variants="A7XX-"/>
++ <reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR" variants="A7XX-"/>
++ <reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA" variants="A7XX-"/>
++ <reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR" variants="A7XX-"/>
++ <reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA" variants="A7XX-"/>
++ <reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR" variants="A7XX-"/>
++ <reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX-"/>
++ <reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX-"/>
++
++ <reg32 offset="0x0a9a" name="CP_RESOURCE_TBL_DBG_ADDR" variants="A7XX-"/>
++ <reg32 offset="0x0a9b" name="CP_RESOURCE_TBL_DBG_DATA" variants="A7XX-"/>
++ <reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX-"/>
++ <reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX-"/>
++
++ <reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR" variants="A7XX-"/>
++ <reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA" variants="A7XX-"/>
++ <reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR" variants="A7XX-"/>
++ <reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR" variants="A7XX-"/>
++ <reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA" variants="A7XX-"/>
++ <reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR" variants="A7XX-"/>
++ <reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA" variants="A7XX-"/>
++
++ <reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL" variants="A7XX-"/>
++ <reg32 offset="0x0B34" name="CP_LPAC_PROG_FIFO_SIZE"/>
++ <reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX-"/>
++ <reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX-"/>
++ <reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX-"/>
++ <reg32 offset="0x0b81" name="CP_LPAC_SQE_CNTL"/>
++ <reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE"/>
++ <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++ <reg32 offset="0x0018" name="RBBM_GPR0_CNTL"/>
++ <reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/>
++ <reg32 offset="0x0210" name="RBBM_STATUS">
++ <bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/>
++ <bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/>
++ <bitfield pos="21" name="HLSQ_BUSY" type="boolean"/>
++ <bitfield pos="20" name="VSC_BUSY" type="boolean"/>
++ <bitfield pos="19" name="TPL1_BUSY" type="boolean"/>
++ <bitfield pos="18" name="SP_BUSY" type="boolean"/>
++ <bitfield pos="17" name="UCHE_BUSY" type="boolean"/>
++ <bitfield pos="16" name="VPC_BUSY" type="boolean"/>
++ <bitfield pos="15" name="VFD_BUSY" type="boolean"/>
++ <bitfield pos="14" name="TESS_BUSY" type="boolean"/>
++ <bitfield pos="13" name="PC_VSD_BUSY" type="boolean"/>
++ <bitfield pos="12" name="PC_DCALL_BUSY" type="boolean"/>
++ <bitfield pos="11" name="COM_DCOM_BUSY" type="boolean"/>
++ <bitfield pos="10" name="LRZ_BUSY" type="boolean"/>
++ <bitfield pos="9" name="A2D_BUSY" type="boolean"/>
++ <bitfield pos="8" name="CCU_BUSY" type="boolean"/>
++ <bitfield pos="7" name="RB_BUSY" type="boolean"/>
++ <bitfield pos="6" name="RAS_BUSY" type="boolean"/>
++ <bitfield pos="5" name="TSE_BUSY" type="boolean"/>
++ <bitfield pos="4" name="VBIF_BUSY" type="boolean"/>
++ <bitfield pos="3" name="GFX_DBGC_BUSY" type="boolean"/>
++ <bitfield pos="2" name="CP_BUSY" type="boolean"/>
++ <bitfield pos="1" name="CP_AHB_BUSY_CP_MASTER" type="boolean"/>
++ <bitfield pos="0" name="CP_AHB_BUSY_CX_MASTER" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0211" name="RBBM_STATUS1"/>
++ <reg32 offset="0x0212" name="RBBM_STATUS2"/>
++ <reg32 offset="0x0213" name="RBBM_STATUS3">
++ <bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
++
++ <reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP" variants="A7XX-"/>
++ <reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ" variants="A7XX-"/>
++ <reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS" variants="A7XX-"/>
++ <reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS" variants="A7XX-"/>
++ <reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD" variants="A7XX-"/>
++ <reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC" variants="A7XX-"/>
++
++ <array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A6XX"/>
++ <array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A6XX"/>
++ <array offset="0x0424" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A6XX"/>
++ <array offset="0x0434" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A6XX"/>
++ <array offset="0x0444" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A6XX"/>
++ <array offset="0x0450" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A6XX"/>
++ <array offset="0x045c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A6XX"/>
++ <array offset="0x0466" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A6XX"/>
++ <array offset="0x046e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A6XX"/>
++ <array offset="0x0476" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A6XX"/>
++ <array offset="0x048e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A6XX"/>
++ <array offset="0x04a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A6XX"/>
++ <array offset="0x04d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A6XX"/>
++ <array offset="0x04e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A6XX"/>
++ <array offset="0x04ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A6XX"/>
++ <array offset="0x04f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A6XX"/>
++
++ <array offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A7XX-"/>
++ <array offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A7XX-"/>
++ <array offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A7XX-"/>
++ <array offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A7XX-"/>
++ <array offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A7XX-"/>
++ <array offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A7XX-"/>
++ <array offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A7XX-"/>
++ <array offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A7XX-"/>
++ <array offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A7XX-"/>
++ <array offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A7XX-"/>
++ <array offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A7XX-"/>
++ <array offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A7XX-"/>
++ <array offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A7XX-"/>
++ <array offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A7XX-"/>
++ <array offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A7XX-"/>
++ <array offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A7XX-"/>
++ <array offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A7XX-"/>
++ <array offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A7XX-"/>
++ <array offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A7XX-"/>
++ <array offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A7XX-"/>
++ <array offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6" variants="A7XX-"/>
++ <array offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A7XX-"/>
++ <array offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A7XX-"/>
++ <array offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A7XX-"/>
++ <array offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A7XX-"/>
++ <array offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A7XX-"/>
++ <array offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A7XX-"/>
++ <array offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A7XX-"/>
++
++ <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
++ <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
++ <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
++ <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
++ <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
++ <reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
++ <reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
++ <array offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4"/>
++ <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
++ <reg32 offset="0x050e" name="RBBM_PERFCTR_SRAM_INIT_CMD"/>
++ <reg32 offset="0x050f" name="RBBM_PERFCTR_SRAM_INIT_STATUS"/>
++ <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
++ <reg32 offset="0x0534" name="RBBM_NC_MODE_CNTL" variants="A7XX-"/>
++ <reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS" variants="A7XX-"/>
++
++ <!---
++ This block of registers aren't tied to perf counters. They
++ count various geometry stats, for example number of
++ vertices in, number of primnitives assembled etc.
++ -->
++
++ <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/> <!-- vs vertices in -->
++ <reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/>
++ <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/> <!-- vs primitives out -->
++ <reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/>
++ <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/> <!-- hs vertices in -->
++ <reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/>
++ <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/> <!-- hs patches out -->
++ <reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/>
++ <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/> <!-- dss vertices in -->
++ <reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/>
++ <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/> <!-- ds primitives out -->
++ <reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/>
++ <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/> <!-- gs primitives in -->
++ <reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/>
++ <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/> <!-- gs primitives out -->
++ <reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/>
++ <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/> <!-- gs primitives out -->
++ <reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/>
++ <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/> <!-- raster primitives in -->
++ <reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/>
++ <reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/>
++ <reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/>
++
++ <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
++ <reg64 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE"/>
++ <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
++ <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
++ <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++ <reg64 offset="0xfc00" name="RBBM_SECVID_TSB_STATUS" variants="A7XX-"/>
++ <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
++ <reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/>
++ <reg32 offset="0x00016" name="RBBM_GBIF_HALT"/>
++ <reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK"/>
++ <reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD">
++ <bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x00016" name="RBBM_GBIF_HALT" variants="A7XX-"/>
++ <reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK" variants="A7XX-"/>
++ <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
++ <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK"/>
++ <reg32 offset="0x00038" name="RBBM_INT_0_MASK" type="A6XX_RBBM_INT_0_MASK"/>
++ <reg32 offset="0x0003a" name="RBBM_INT_2_MASK" variants="A7XX-"/>
++ <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
++ <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
++ <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
++ <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
++ <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
++ <reg32 offset="0x000ad" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A7XX-"/>
++ <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
++ <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
++ <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
++ <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
++ <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
++ <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
++ <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
++ <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
++ <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
++ <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
++ <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
++ <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
++ <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
++ <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
++ <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
++ <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
++ <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
++ <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
++ <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
++ <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
++ <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
++ <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
++ <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
++ <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
++ <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
++ <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
++ <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
++ <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
++ <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
++ <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
++ <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
++ <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
++ <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
++ <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
++ <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
++ <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
++ <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
++ <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
++ <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
++ <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
++ <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
++ <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
++ <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
++ <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
++ <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
++ <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
++ <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
++ <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
++ <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
++ <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
++ <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
++ <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
++ <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
++ <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
++ <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
++ <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
++ <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
++ <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
++ <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
++ <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
++ <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
++ <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
++ <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
++ <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
++ <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
++ <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
++ <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
++ <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
++ <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
++ <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
++ <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
++ <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
++ <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
++ <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
++ <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
++ <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
++ <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
++ <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
++ <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
++ <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
++ <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
++ <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
++ <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
++ <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
++ <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
++ <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
++ <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
++ <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
++ <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
++ <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
++ <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
++ <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
++ <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
++ <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
++ <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
++ <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
++ <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
++ <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
++ <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
++ <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
++ <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
++ <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
++ <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
++ <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
++ <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
++ <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
++ <reg32 offset="0x0011d" name="RBBM_CLOCK_HYST_HLSQ"/>
++ <reg32 offset="0x0011e" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A7XX-"/>
++ <reg32 offset="0x0011f" name="RBBM_CGC_P2S_TRIG_CMD" variants="A7XX-"/>
++ <reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE"/>
++ <reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE"/>
++ <reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE"/>
++ <reg32 offset="0x00122" name="RBBM_CGC_P2S_STATUS" variants="A7XX-">
++ <bitfield name="TXDONE" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00123" name="RBBM_CLOCK_CNTL_FCHE"/>
++ <reg32 offset="0x00124" name="RBBM_CLOCK_DELAY_FCHE"/>
++ <reg32 offset="0x00125" name="RBBM_CLOCK_HYST_FCHE"/>
++ <reg32 offset="0x00126" name="RBBM_CLOCK_CNTL_MHUB"/>
++ <reg32 offset="0x00127" name="RBBM_CLOCK_DELAY_MHUB"/>
++ <reg32 offset="0x00128" name="RBBM_CLOCK_HYST_MHUB"/>
++ <reg32 offset="0x00129" name="RBBM_CLOCK_DELAY_GLC"/>
++ <reg32 offset="0x0012a" name="RBBM_CLOCK_HYST_GLC"/>
++ <reg32 offset="0x0012b" name="RBBM_CLOCK_CNTL_GLC"/>
++ <reg32 offset="0x0012f" name="RBBM_CLOCK_HYST2_VFD" variants="A7XX-"/>
++ <reg32 offset="0x005ff" name="RBBM_LPAC_GBIF_CLIENT_QOS_CNTL"/>
++
++ <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
++ <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
++ <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>
++ <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D">
++ <bitfield high="7" low="0" name="PING_INDEX"/>
++ <bitfield high="15" low="8" name="PING_BLK_SEL"/>
++ </reg32>
++ <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT">
++ <bitfield high="5" low="0" name="TRACEEN"/>
++ <bitfield high="14" low="12" name="GRANU"/>
++ <bitfield high="31" low="28" name="SEGT"/>
++ </reg32>
++ <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">
++ <bitfield high="27" low="24" name="ENABLE"/>
++ </reg32>
++ <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
++ <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
++ <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
++ <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>
++ <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>
++ <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>
++ <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>
++ <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>
++ <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0">
++ <bitfield high="3" low="0" name="BYTEL0"/>
++ <bitfield high="7" low="4" name="BYTEL1"/>
++ <bitfield high="11" low="8" name="BYTEL2"/>
++ <bitfield high="15" low="12" name="BYTEL3"/>
++ <bitfield high="19" low="16" name="BYTEL4"/>
++ <bitfield high="23" low="20" name="BYTEL5"/>
++ <bitfield high="27" low="24" name="BYTEL6"/>
++ <bitfield high="31" low="28" name="BYTEL7"/>
++ </reg32>
++ <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1">
++ <bitfield high="3" low="0" name="BYTEL8"/>
++ <bitfield high="7" low="4" name="BYTEL9"/>
++ <bitfield high="11" low="8" name="BYTEL10"/>
++ <bitfield high="15" low="12" name="BYTEL11"/>
++ <bitfield high="19" low="16" name="BYTEL12"/>
++ <bitfield high="23" low="20" name="BYTEL13"/>
++ <bitfield high="27" low="24" name="BYTEL14"/>
++ <bitfield high="31" low="28" name="BYTEL15"/>
++ </reg32>
++ <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
++ <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
++ <array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2"/>
++ <reg32 offset="0x0CD8" name="VSC_UNKNOWN_0CD8" variants="A7XX">
++ <doc>
++ Set to true when binning, isn't changed afterwards
++ </doc>
++ <bitfield name="BINNING" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
++ <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
++ <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++ <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
++ <reg64 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX"/>
++ <reg64 offset="0x0E07" name="UCHE_WRITE_THRU_BASE"/>
++ <reg64 offset="0x0E09" name="UCHE_TRAP_BASE"/>
++ <reg64 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN"/>
++ <reg64 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX"/>
++ <reg32 offset="0x0E17" name="UCHE_CACHE_WAYS" usage="cmd"/>
++ <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
++ <reg32 offset="0x0E19" name="UCHE_CLIENT_PF" usage="cmd">
++ <bitfield high="7" low="0" name="PERFSEL"/>
++ </reg32>
++ <array offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/>
++ <reg32 offset="0x0e3a" name="UCHE_GBIF_GX_CONFIG"/>
++ <reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG"/>
++
++ <reg32 offset="0x3000" name="VBIF_VERSION"/>
++ <reg32 offset="0x3001" name="VBIF_CLKON">
++ <bitfield pos="1" name="FORCE_ON_TESTBUS" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
++ <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
++ <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
++ <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
++ <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
++ <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">
++ <bitfield low="0" high="3" name="DATA_SEL"/>
++ </reg32>
++ <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
++ <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">
++ <bitfield low="0" high="8" name="DATA_SEL"/>
++ </reg32>
++ <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
++ <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
++ <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
++ <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
++ <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
++ <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
++ <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
++ <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
++ <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
++ <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
++ <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
++ <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
++ <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
++ <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
++ <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
++ <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
++ <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
++ <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
++ <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
++ <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
++ <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
++ <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
++
++ <reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/>
++ <reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
++ <reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
++ <reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/>
++ <reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/>
++ <reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/>
++ <reg32 offset="0x3c45" name="GBIF_HALT"/>
++ <reg32 offset="0x3c46" name="GBIF_HALT_ACK"/>
++ <reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/>
++ <reg32 offset="0x3cc1" name="GBIF_PERF_PWR_CNT_CLR"/>
++ <reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/>
++ <reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/>
++ <reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/>
++ <reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/>
++ <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/>
++ <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/>
++ <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/>
++ <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/>
++ <reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/>
++ <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/>
++ <reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/>
++ <reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/>
++ <reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/>
++ <reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/>
++ <reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/>
++ <reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/>
++
++ <reg32 offset="0x0c00" name="VSC_DBG_ECO_CNTL"/>
++ <reg32 offset="0x0c02" name="VSC_BIN_SIZE" usage="rp_blit">
++ <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
++ <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
++ </reg32>
++ <reg64 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS" type="waddress" usage="cmd"/>
++ <reg32 offset="0x0c06" name="VSC_BIN_COUNT" usage="rp_blit">
++ <bitfield name="NX" low="1" high="10" type="uint"/>
++ <bitfield name="NY" low="11" high="20" type="uint"/>
++ </reg32>
++ <array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32" usage="rp_blit">
++ <reg32 offset="0x0" name="REG">
++ <doc>
++ Configures the mapping between VSC_PIPE buffer and
++ bin, X/Y specify the bin index in the horiz/vert
++ direction (0,0 is upper left, 0,1 is leftmost bin
++ on second row, and so on). W/H specify the number
++ of bins assigned to this VSC_PIPE in the horiz/vert
++ dimension.
++ </doc>
++ <bitfield name="X" low="0" high="9" type="uint"/>
++ <bitfield name="Y" low="10" high="19" type="uint"/>
++ <bitfield name="W" low="20" high="25" type="uint"/>
++ <bitfield name="H" low="26" high="31" type="uint"/>
++ </reg32>
++ </array>
++ <!--
++ HW binning primitive & draw streams, which enable draws and primitives
++ within a draw to be skipped in the main tile pass. See:
++ https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format
++
++ Compared to a5xx and earlier, we just program the address of the first
++ stream and hw adds (pipe_num * VSC_*_STRM_PITCH)
++
++ LIMIT is set to PITCH - 64, to make room for a bit of overflow
++ -->
++ <reg64 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS" type="waddress" usage="cmd"/>
++ <reg32 offset="0x0c32" name="VSC_PRIM_STRM_PITCH" usage="cmd"/>
++ <reg32 offset="0x0c33" name="VSC_PRIM_STRM_LIMIT" usage="cmd"/>
++ <reg64 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS" type="waddress" usage="cmd"/>
++ <reg32 offset="0x0c36" name="VSC_DRAW_STRM_PITCH" usage="cmd"/>
++ <reg32 offset="0x0c37" name="VSC_DRAW_STRM_LIMIT" usage="cmd"/>
++
++ <array offset="0x0c38" name="VSC_STATE" stride="1" length="32" usage="rp_blit">
++ <doc>
++ Seems to be a bitmap of which tiles mapped to the VSC
++ pipe contain geometry.
++
++ I suppose we can connect a maximum of 32 tiles to a
++ single VSC pipe.
++ </doc>
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++
++ <array offset="0x0c58" name="VSC_PRIM_STRM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit">
++ <doc>
++ Has the size of data written to corresponding VSC_PRIM_STRM
++ buffer.
++ </doc>
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++
++ <array offset="0x0c78" name="VSC_DRAW_STRM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit">
++ <doc>
++ Has the size of data written to corresponding VSC pipe, ie.
++ same thing that is written out to VSC_DRAW_STRM_SIZE_ADDRESS_LO/HI
++ </doc>
++ <reg32 offset="0x0" name="REG"/>
++ </array>
++
++ <reg32 offset="0x0d08" name="VSC_UNKNOWN_0D08" variants="A7XX-" usage="rp_blit"/>
++
++ <reg32 offset="0x0E10" name="UCHE_UNKNOWN_0E10" variants="A7XX-" usage="cmd"/>
++ <reg32 offset="0x0E11" name="UCHE_UNKNOWN_0E11" variants="A7XX-" usage="cmd"/>
++ <!-- always 0x03200000 ? -->
++ <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12" usage="cmd"/>
++
++ <!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 -->
++ <bitset name="a6xx_reg_xy" inline="yes">
++ <bitfield name="X" low="0" high="13" type="uint"/>
++ <bitfield name="Y" low="16" high="29" type="uint"/>
++ </bitset>
++
++ <reg32 offset="0x8000" name="GRAS_CL_CNTL" usage="rp_blit">
++ <bitfield name="CLIP_DISABLE" pos="0" type="boolean"/>
++ <bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/>
++ <bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/>
++ <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
++ <!-- controls near z clip behavior (set for vulkan) -->
++ <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>
++ <!-- guess based on a3xx and meaning of bits 8 and 9
++ if the guess is right then this is related to point sprite clipping -->
++ <bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/>
++ <bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/>
++ <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/>
++ </reg32>
++
++ <bitset name="a6xx_gras_xs_cl_cntl" inline="yes">
++ <bitfield name="CLIP_MASK" low="0" high="7"/>
++ <bitfield name="CULL_MASK" low="8" high="15"/>
++ </bitset>
++ <reg32 offset="0x8001" name="GRAS_VS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/>
++ <reg32 offset="0x8002" name="GRAS_DS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/>
++ <reg32 offset="0x8003" name="GRAS_GS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/>
++ <reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" low="0" high="10" type="uint" usage="rp_blit"/>
++
++ <reg32 offset="0x8005" name="GRAS_CNTL" usage="rp_blit">
++ <!-- see also RB_RENDER_CONTROL0 -->
++ <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
++ <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
++ <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
++ <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>
++ <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
++ <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
++ <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
++ <bitfield name="UNK10" pos="10" type="boolean" variants="A7XX-"/>
++ <bitfield name="UNK11" pos="11" type="boolean" variants="A7XX-"/>
++ </reg32>
++ <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ" usage="rp_blit">
++ <bitfield name="HORZ" low="0" high="8" type="uint"/>
++ <bitfield name="VERT" low="10" high="18" type="uint"/>
++ </reg32>
++
++ <!-- Something connected to depth-stencil attachment size -->
++ <reg32 offset="0x8007" name="GRAS_UNKNOWN_8007" variants="A7XX-" usage="rp_blit"/>
++
++ <reg32 offset="0x8008" name="GRAS_UNKNOWN_8008" variants="A7XX-" usage="cmd"/>
++
++ <reg32 offset="0x8009" name="GRAS_UNKNOWN_8009" variants="A7XX-" usage="cmd"/>
++ <reg32 offset="0x800a" name="GRAS_UNKNOWN_800A" variants="A7XX-" usage="cmd"/>
++ <reg32 offset="0x800b" name="GRAS_UNKNOWN_800B" variants="A7XX-" usage="cmd"/>
++ <reg32 offset="0x800c" name="GRAS_UNKNOWN_800C" variants="A7XX-" usage="cmd"/>
++
++ <!-- <reg32 offset="0x80f0" name="GRAS_UNKNOWN_80F0" type="a6xx_reg_xy"/> -->
++
++ <!-- 0x8006-0x800f invalid -->
++ <array offset="0x8010" name="GRAS_CL_VPORT" stride="6" length="16" usage="rp_blit">
++ <reg32 offset="0" name="XOFFSET" type="float"/>
++ <reg32 offset="1" name="XSCALE" type="float"/>
++ <reg32 offset="2" name="YOFFSET" type="float"/>
++ <reg32 offset="3" name="YSCALE" type="float"/>
++ <reg32 offset="4" name="ZOFFSET" type="float"/>
++ <reg32 offset="5" name="ZSCALE" type="float"/>
++ </array>
++ <array offset="0x8070" name="GRAS_CL_Z_CLAMP" stride="2" length="16" usage="rp_blit">
++ <reg32 offset="0" name="MIN" type="float"/>
++ <reg32 offset="1" name="MAX" type="float"/>
++ </array>
++
++ <reg32 offset="0x8090" name="GRAS_SU_CNTL" usage="rp_blit">
++ <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
++ <bitfield name="CULL_BACK" pos="1" type="boolean"/>
++ <bitfield name="FRONT_CW" pos="2" type="boolean"/>
++ <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
++ <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
++ <bitfield name="UNK12" pos="12"/>
++ <bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/>
++ <bitfield name="UNK15" low="15" high="16"/>
++ <!--
++ On gen1 only MULTIVIEW_ENABLE exists. On gen3 we have
++ the ability to add the view index to either the RT array
++ index or the viewport index, and it seems that
++ MULTIVIEW_ENABLE doesn't do anything, instead we need to
++ set at least one of RENDERTARGETINDEXINCR or
++ VIEWPORTINDEXINCR to enable multiview. The blob still
++ sets MULTIVIEW_ENABLE regardless.
++ TODO: what about gen2 (a640)?
++ -->
++ <bitfield name="MULTIVIEW_ENABLE" pos="17" type="boolean"/>
++ <bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean"/>
++ <bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean"/>
++ <bitfield name="UNK20" low="20" high="22"/>
++ </reg32>
++ <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX" usage="rp_blit">
++ <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
++ <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
++ </reg32>
++ <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" usage="rp_blit"/>
++ <!-- 0x8093 invalid -->
++ <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL" usage="rp_blit">
++ <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
++ </reg32>
++ <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" usage="rp_blit"/>
++ <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" usage="rp_blit"/>
++ <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" usage="rp_blit"/>
++ <!-- duplicates RB_DEPTH_BUFFER_INFO: -->
++ <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO" usage="rp_blit">
++ <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
++ <bitfield name="UNK3" pos="3"/>
++ </reg32>
++
++ <reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" usage="cmd">
++ <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/>
++ <bitfield name="SHIFTAMOUNT" low="1" high="2"/>
++ <bitfield name="INNERCONSERVATIVERASEN" pos="3" type="boolean"/>
++ <bitfield name="UNK4" low="4" high="5"/>
++ </reg32>
++ <reg32 offset="0x809a" name="GRAS_SU_PATH_RENDERING_CNTL">
++ <bitfield name="UNK0" pos="0" type="boolean"/>
++ <bitfield name="LINELENGTHEN" pos="1" type="boolean"/>
++ </reg32>
++
++ <bitset name="a6xx_gras_layer_cntl" inline="yes">
++ <bitfield name="WRITES_LAYER" pos="0" type="boolean"/>
++ <bitfield name="WRITES_VIEW" pos="1" type="boolean"/>
++ </bitset>
++ <reg32 offset="0x809b" name="GRAS_VS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/>
++ <reg32 offset="0x809c" name="GRAS_GS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/>
++ <reg32 offset="0x809d" name="GRAS_DS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/>
++ <!-- 0x809e/0x809f invalid -->
++
++ <enum name="a6xx_sequenced_thread_dist">
++ <value value="0x0" name="DIST_SCREEN_COORD"/>
++ <value value="0x1" name="DIST_ALL_TO_RB0"/>
++ </enum>
++
++ <enum name="a6xx_single_prim_mode">
++ <value value="0x0" name="NO_FLUSH"/>
++ <doc>
++ In addition to FLUSH_PER_OVERLAP, guarantee that UCHE
++ and CCU don't get out of sync when fetching the previous
++ value for the current pixel. With NO_FLUSH, there's the
++ possibility that the flags for the current pixel are
++ flushed before the data or vice-versa, leading to
++ texture fetches via UCHE getting out of sync values.
++ This mode should eliminate that. It's used in bypass
++ mode for coherent blending
++ (GL_KHR_blend_equation_advanced_coherent) as well as
++ non-coherent blending.
++ </doc>
++ <value value="0x1" name="FLUSH_PER_OVERLAP_AND_OVERWRITE"/>
++ <doc>
++ Invalidate UCHE and wait for any pending work to finish
++ if there was possibly an overlapping primitive prior to
++ the current one. This is similar to a combination of
++ GRAS_SC_CONTROL::INJECT_L2_INVALIDATE_EVENT and
++ WAIT_RB_IDLE_ALL_TRI on a3xx. It's used in GMEM mode for
++ coherent blending
++ (GL_KHR_blend_equation_advanced_coherent).
++ </doc>
++ <value value="0x3" name="FLUSH_PER_OVERLAP"/>
++ </enum>
++
++ <!-- this probably has the same meaning as a3xx GRAS_SC_CONTROL::RASTER_MODE -->
++ <enum name="a6xx_raster_mode">
++ <value value="0x0" name="TYPE_TILED"/>
++ <value value="0x1" name="TYPE_WRITER"/>
++ </enum>
++
++ <!-- I'm guessing this is the same as a3xx -->
++ <enum name="a6xx_raster_direction">
++ <value value="0x0" name="LR_TB"/>
++ <value value="0x1" name="RL_TB"/>
++ <value value="0x2" name="LR_BT"/>
++ <value value="0x3" name="RB_BT"/>
++ </enum>
++
++ <reg32 offset="0x80a0" name="GRAS_SC_CNTL" usage="rp_blit">
++ <bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2"/>
++ <bitfield name="SINGLE_PRIM_MODE" low="3" high="4" type="a6xx_single_prim_mode"/>
++ <bitfield name="RASTER_MODE" pos="5" type="a6xx_raster_mode"/>
++ <bitfield name="RASTER_DIRECTION" low="6" high="7" type="a6xx_raster_direction"/>
++ <bitfield name="SEQUENCED_THREAD_DISTRIBUTION" pos="8" type="a6xx_sequenced_thread_dist"/>
++ <!-- CCUSINGLECACHELINESIZE is ignored unless bit 9 is set -->
++ <bitfield name="UNK9" pos="9" type="boolean"/>
++ <bitfield name="ROTATION" low="10" high="11" type="uint"/>
++ <bitfield name="EARLYVIZOUTEN" pos="12" type="boolean"/>
++ </reg32>
++
++ <enum name="a6xx_render_mode">
++ <value value="0x0" name="RENDERING_PASS"/>
++ <value value="0x1" name="BINNING_PASS"/>
++ </enum>
++
++ <enum name="a6xx_buffers_location">
++ <value value="0" name="BUFFERS_IN_GMEM"/>
++ <value value="3" name="BUFFERS_IN_SYSMEM"/>
++ </enum>
++
++ <reg32 offset="0x80a1" name="GRAS_BIN_CONTROL" usage="rp_blit">
++ <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
++ <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
++ <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
++ <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>
++ <bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location" variants="A6XX"/>
++ <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26"/>
++ <bitfield name="UNK27" pos="27"/>
++ </reg32>
++
++ <reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL" usage="rp_blit">
++ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
++ <bitfield name="UNK2" pos="2"/>
++ <bitfield name="UNK3" pos="3"/>
++ </reg32>
++ <reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL" usage="rp_blit">
++ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
++ <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
++ </reg32>
++
++ <bitset name="a6xx_sample_config" inline="yes">
++ <bitfield name="UNK0" pos="0"/>
++ <bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/>
++ </bitset>
++
++ <bitset name="a6xx_sample_locations" inline="yes">
++ <bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/>
++ <bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/>
++ <bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/>
++ <bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/>
++ <bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/>
++ <bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/>
++ <bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/>
++ <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/>
++ </bitset>
++
++ <reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/>
++ <reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/>
++ <reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/>
++
++ <reg32 offset="0x80a7" name="GRAS_UNKNOWN_80A7" variants="A7XX-" usage="cmd"/>
++
++ <!-- 0x80a7-0x80ae invalid -->
++ <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF" pos="0" usage="cmd"/>
++
++ <bitset name="a6xx_scissor_xy" inline="yes">
++ <bitfield name="X" low="0" high="15" type="uint"/>
++ <bitfield name="Y" low="16" high="31" type="uint"/>
++ </bitset>
++ <array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16" usage="rp_blit">
++ <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
++ <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
++ </array>
++ <array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" usage="rp_blit">
++ <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
++ <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
++ </array>
++
++ <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/>
++ <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/>
++
++ <!-- 0x80f4 - 0x80fa are used for VK_KHR_fragment_shading_rate -->
++ <reg64 offset="0x80f4" name="GRAS_UNKNOWN_80F4" variants="A7XX-" usage="cmd"/>
++ <reg64 offset="0x80f5" name="GRAS_UNKNOWN_80F5" variants="A7XX-" usage="cmd"/>
++ <reg64 offset="0x80f6" name="GRAS_UNKNOWN_80F6" variants="A7XX-" usage="cmd"/>
++ <reg64 offset="0x80f8" name="GRAS_UNKNOWN_80F8" variants="A7XX-" usage="cmd"/>
++ <reg64 offset="0x80f9" name="GRAS_UNKNOWN_80F9" variants="A7XX-" usage="cmd"/>
++ <reg64 offset="0x80fa" name="GRAS_UNKNOWN_80FA" variants="A7XX-" usage="cmd"/>
++
++ <enum name="a6xx_lrz_dir_status">
++ <value value="0x1" name="LRZ_DIR_LE"/>
++ <value value="0x2" name="LRZ_DIR_GE"/>
++ <value value="0x3" name="LRZ_DIR_INVALID"/>
++ </enum>
++
++ <reg32 offset="0x8100" name="GRAS_LRZ_CNTL" usage="rp_blit">
++ <bitfield name="ENABLE" pos="0" type="boolean"/>
++ <doc>LRZ write also disabled for blend/etc.</doc>
++ <bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
++ <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
++ <bitfield name="GREATER" pos="2" type="boolean"/>
++ <doc>
++ Clears the LRZ block being touched to:
++ - 0.0 if GREATER
++ - 1.0 if LESS
++ </doc>
++ <bitfield name="FC_ENABLE" pos="3" type="boolean"/>
++ <!-- set when depth-test + depth-write enabled -->
++ <bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/>
++ <bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/>
++ <bitfield name="DIR" low="6" high="7" type="a6xx_lrz_dir_status"/>
++ <doc>
++ If DISABLE_ON_WRONG_DIR enabled - write new LRZ direction into
++ buffer, in case of mismatched direction writes 0 (disables LRZ).
++ </doc>
++ <bitfield name="DIR_WRITE" pos="8" type="boolean"/>
++ <doc>
++ Disable LRZ based on previous direction and the current one.
++ If DIR_WRITE is not enabled - there is no write to direction buffer.
++ </doc>
++ <bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean"/>
++ <bitfield name="Z_FUNC" low="11" high="13" type="adreno_compare_func" variants="A7XX-"/>
++ </reg32>
++
++ <enum name="a6xx_fragcoord_sample_mode">
++ <value value="0" name="FRAGCOORD_CENTER"/>
++ <value value="3" name="FRAGCOORD_SAMPLE"/>
++ </enum>
++
++ <reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" low="0" high="2" usage="rp_blit">
++ <bitfield name="SAMPLEID" pos="0" type="boolean"/>
++ <bitfield name="FRAGCOORDSAMPLEMODE" low="1" high="2" type="a6xx_fragcoord_sample_mode"/>
++ </reg32>
++
++ <reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUF_INFO_0" usage="rp_blit">
++ <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
++ </reg32>
++ <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit"/>
++ <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH" usage="rp_blit">
++ <!-- TODO: fix the shr fields -->
++ <bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/>
++ <bitfield name="ARRAY_PITCH" low="10" high="28" shr="4" type="uint"/>
++ </reg32>
++
++ <!--
++ The LRZ "fast clear" buffer is initialized to zero's by blob, and
++ read/written when GRAS_LRZ_CNTL.FC_ENABLE (b3) is set. It appears
++ to store 1b/block. It appears that '0' means block has original
++ depth clear value, and '1' means that the corresponding block in
++ LRZ has been modified. Ignoring alignment/padding, the size is
++ given by the formula:
++
++ // calculate LRZ size from depth size:
++ if (nr_samples == 4) {
++ width *= 2;
++ height *= 2;
++ } else if (nr_samples == 2) {
++ height *= 2;
++ }
++
++ lrz_width = div_round_up(width, 8);
++ lrz_heigh = div_round_up(height, 8);
++
++ // calculate # of blocks:
++ nblocksx = div_round_up(lrz_width, 16);
++ nblocksy = div_round_up(lrz_height, 4);
++
++ // fast-clear buffer is 1bit/block:
++ fc_sz = div_round_up(nblocksx * nblocksy, 8);
++
++ In practice the blob seems to switch off FC_ENABLE once the size
++ increases beyond 1 page. Not sure if that is an actual limit or
++ not.
++ -->
++ <reg64 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress" usage="rp_blit"/>
++ <!-- 0x8108 invalid -->
++ <reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL" usage="rp_blit">
++ <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
++ </reg32>
++ <!--
++ LRZ buffer represents a single array layer + mip level, and there is
++ a single buffer per depth image. Thus to reuse LRZ between renderpasses
++ it is necessary to track the depth view used in the past renderpass, which
++ GRAS_LRZ_DEPTH_VIEW is for.
++ GRAS_LRZ_CNTL checks if current value of GRAS_LRZ_DEPTH_VIEW is equal to
++ the value stored in the LRZ buffer, if not - LRZ is disabled.
++ -->
++ <reg32 offset="0x810a" name="GRAS_LRZ_DEPTH_VIEW" usage="cmd">
++ <bitfield name="BASE_LAYER" low="0" high="10" type="uint"/>
++ <bitfield name="LAYER_COUNT" low="16" high="26" type="uint"/>
++ <bitfield name="BASE_MIP_LEVEL" low="28" high="31" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x810b" name="GRAS_UNKNOWN_810B" variants="A7XX-" usage="cmd"/>
++
++ <!-- 0x810c-0x810f invalid -->
++
++ <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1" usage="cmd"/>
++
++ <!-- A bit tentative but it's a color and it is followed by LRZ_CLEAR -->
++ <reg32 offset="0x8111" name="GRAS_LRZ_CLEAR_DEPTH_F32" type="float" variants="A7XX-"/>
++
++ <reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit"/>
++
++ <!-- Always written together and always equal 09510840 00000a62 -->
++ <reg32 offset="0x8120" name="GRAS_UNKNOWN_8120" variants="A7XX-" usage="cmd"/>
++ <reg32 offset="0x8121" name="GRAS_UNKNOWN_8121" variants="A7XX-" usage="cmd"/>
++
++ <!-- 0x8112-0x83ff invalid -->
++
++ <enum name="a6xx_rotation">
++ <value value="0x0" name="ROTATE_0"/>
++ <value value="0x1" name="ROTATE_90"/>
++ <value value="0x2" name="ROTATE_180"/>
++ <value value="0x3" name="ROTATE_270"/>
++ <value value="0x4" name="ROTATE_HFLIP"/>
++ <value value="0x5" name="ROTATE_VFLIP"/>
++ </enum>
++
++ <bitset name="a6xx_2d_blit_cntl" inline="yes">
++ <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
++ <bitfield name="OVERWRITEEN" pos="3" type="boolean"/>
++ <bitfield name="UNK4" low="4" high="6"/>
++ <bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
++ <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/>
++ <bitfield name="SCISSOR" pos="16" type="boolean"/>
++ <bitfield name="UNK17" low="17" high="18"/>
++ <!-- required when blitting D24S8/D24X8 -->
++ <bitfield name="D24S8" pos="19" type="boolean"/>
++ <!-- some sort of channel mask, disabled channels are set to zero ? -->
++ <bitfield name="MASK" low="20" high="23"/>
++ <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
++ <bitfield name="RASTER_MODE" pos="29" type="a6xx_raster_mode"/>
++ <bitfield name="UNK30" pos="30" type="boolean" variants="A7XX-"/>
++ </bitset>
++
++ <reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl" usage="rp_blit"/>
++ <!-- note: the low 8 bits for src coords are valid, probably fixed point
++ it would be a bit weird though, since we subtract 1 from BR coords
++ apparently signed, gallium driver uses negative coords and it works?
++ -->
++ <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X" low="8" high="24" type="int" usage="rp_blit"/>
++ <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X" low="8" high="24" type="int" usage="rp_blit"/>
++ <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y" low="8" high="24" type="int" usage="rp_blit"/>
++ <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y" low="8" high="24" type="int" usage="rp_blit"/>
++ <reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="a6xx_reg_xy" usage="rp_blit"/>
++ <reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="a6xx_reg_xy" usage="rp_blit"/>
++ <reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/>
++ <reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/>
++ <reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/>
++ <reg32 offset="0x840a" name="GRAS_2D_RESOLVE_CNTL_1" type="a6xx_reg_xy" usage="rp_blit"/>
++ <reg32 offset="0x840b" name="GRAS_2D_RESOLVE_CNTL_2" type="a6xx_reg_xy" usage="rp_blit"/>
++ <!-- 0x840c-0x85ff invalid -->
++
++ <!-- always 0x880 ? (and 0 in a640/a650 traces?) -->
++ <reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL" usage="cmd">
++ <bitfield name="UNK7" pos="7" type="boolean"/>
++ <bitfield name="LRZCACHELOCKDIS" pos="11" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
++ <reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL" variants="A7XX-"/>
++ <array offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4"/>
++ <array offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4"/>
++ <array offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4"/>
++
++ <!-- note 0x8620-0x87ff are not all invalid
++ (in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords)
++ -->
++
++ <!-- same as GRAS_BIN_CONTROL, but without bit 27: -->
++ <reg32 offset="0x8800" name="RB_BIN_CONTROL" variants="A6XX" usage="rp_blit">
++ <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
++ <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
++ <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
++ <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>
++ <bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location"/>
++ <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26"/>
++ </reg32>
++
++ <reg32 offset="0x8800" name="RB_BIN_CONTROL" variants="A7XX-" usage="rp_blit">
++ <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
++ <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
++ <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
++ <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>
++ <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26"/>
++ </reg32>
++
++ <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A6XX" usage="rp_blit">
++ <bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/>
++ <bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/>
++ <!-- set during binning pass: -->
++ <bitfield name="BINNING" pos="7" type="boolean"/>
++ <bitfield name="UNK8" low="8" high="10"/>
++ <bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/>
++ <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/>
++ <bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/>
++ <bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/>
++ <!-- bit seems to be set whenever depth buffer enabled: -->
++ <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
++ <!-- bitmask of MRTs using UBWC flag buffer: -->
++ <bitfield name="FLAG_MRTS" low="16" high="23"/>
++ </reg32>
++ <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A7XX-" usage="rp_blit">
++ <bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/>
++ <!-- set during binning pass: -->
++ <bitfield name="BINNING" pos="7" type="boolean"/>
++ <bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/>
++ <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/>
++ <bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/>
++ <bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" variants="A7XX-" usage="rp_blit">
++ <bitfield name="BINNING" pos="7" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL" usage="rp_blit">
++ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
++ <bitfield name="UNK2" pos="2"/>
++ <bitfield name="UNK3" pos="3"/>
++ </reg32>
++ <reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL" usage="rp_blit">
++ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
++ <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/>
++ <reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/>
++ <reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/>
++ <!-- 0x8807-0x8808 invalid -->
++ <!--
++ note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
++ name comes from kernel and is probably right)
++ -->
++ <reg32 offset="0x8809" name="RB_RENDER_CONTROL0" usage="rp_blit">
++ <!-- see also GRAS_CNTL -->
++ <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
++ <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
++ <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
++ <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>
++ <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
++ <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
++ <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
++ <bitfield name="UNK10" pos="10" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x880a" name="RB_RENDER_CONTROL1" usage="rp_blit">
++ <!-- enable bits for various FS sysvalue regs: -->
++ <bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
++ <bitfield name="POSTDEPTHCOVERAGE" pos="1" type="boolean"/>
++ <bitfield name="FACENESS" pos="2" type="boolean"/>
++ <bitfield name="SAMPLEID" pos="3" type="boolean"/>
++ <bitfield name="FRAGCOORDSAMPLEMODE" low="4" high="5" type="a6xx_fragcoord_sample_mode"/>
++ <bitfield name="CENTERRHW" pos="6" type="boolean"/>
++ <bitfield name="LINELENGTHEN" pos="7" type="boolean"/>
++ <bitfield name="FOVEATION" pos="8" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0" usage="rp_blit">
++ <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
++ <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
++ <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
++ <bitfield name="FRAG_WRITES_STENCILREF" pos="3" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1" usage="rp_blit">
++ <bitfield name="MRT" low="0" high="3" type="uint"/>
++ </reg32>
++ <reg32 offset="0x880d" name="RB_RENDER_COMPONENTS" usage="rp_blit">
++ <bitfield name="RT0" low="0" high="3"/>
++ <bitfield name="RT1" low="4" high="7"/>
++ <bitfield name="RT2" low="8" high="11"/>
++ <bitfield name="RT3" low="12" high="15"/>
++ <bitfield name="RT4" low="16" high="19"/>
++ <bitfield name="RT5" low="20" high="23"/>
++ <bitfield name="RT6" low="24" high="27"/>
++ <bitfield name="RT7" low="28" high="31"/>
++ </reg32>
++ <reg32 offset="0x880e" name="RB_DITHER_CNTL" usage="cmd">
++ <bitfield name="DITHER_MODE_MRT0" low="0" high="1" type="adreno_rb_dither_mode"/>
++ <bitfield name="DITHER_MODE_MRT1" low="2" high="3" type="adreno_rb_dither_mode"/>
++ <bitfield name="DITHER_MODE_MRT2" low="4" high="5" type="adreno_rb_dither_mode"/>
++ <bitfield name="DITHER_MODE_MRT3" low="6" high="7" type="adreno_rb_dither_mode"/>
++ <bitfield name="DITHER_MODE_MRT4" low="8" high="9" type="adreno_rb_dither_mode"/>
++ <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/>
++ <bitfield name="DITHER_MODE_MRT6" low="12" high="13" type="adreno_rb_dither_mode"/>
++ <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/>
++ </reg32>
++ <reg32 offset="0x880f" name="RB_SRGB_CNTL" usage="rp_blit">
++ <!-- Same as SP_SRGB_CNTL -->
++ <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
++ <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
++ <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
++ <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
++ <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
++ <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
++ <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
++ <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x8810" name="RB_SAMPLE_CNTL" usage="rp_blit">
++ <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x8811" name="RB_UNKNOWN_8811" low="4" high="6" usage="cmd"/>
++ <reg32 offset="0x8812" name="RB_UNKNOWN_8812" variants="A7XX-" usage="rp_blit"/>
++ <!-- 0x8813-0x8817 invalid -->
++ <!-- always 0x0 ? -->
++ <reg32 offset="0x8818" name="RB_UNKNOWN_8818" low="0" high="6" usage="cmd"/>
++ <!-- 0x8819-0x881e all 32 bits -->
++ <reg32 offset="0x8819" name="RB_UNKNOWN_8819" usage="cmd"/>
++ <reg32 offset="0x881a" name="RB_UNKNOWN_881A" usage="cmd"/>
++ <reg32 offset="0x881b" name="RB_UNKNOWN_881B" usage="cmd"/>
++ <reg32 offset="0x881c" name="RB_UNKNOWN_881C" usage="cmd"/>
++ <reg32 offset="0x881d" name="RB_UNKNOWN_881D" usage="cmd"/>
++ <reg32 offset="0x881e" name="RB_UNKNOWN_881E" usage="cmd"/>
++ <!-- 0x881f invalid -->
++ <array offset="0x8820" name="RB_MRT" stride="8" length="8" usage="rp_blit">
++ <reg32 offset="0x0" name="CONTROL">
++ <bitfield name="BLEND" pos="0" type="boolean"/>
++ <bitfield name="BLEND2" pos="1" type="boolean"/>
++ <bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
++ <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
++ <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
++ </reg32>
++ <reg32 offset="0x1" name="BLEND_CONTROL">
++ <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
++ <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
++ <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
++ <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
++ <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
++ <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
++ </reg32>
++ <reg32 offset="0x2" name="BUF_INFO" variants="A6XX">
++ <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
++ <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
++ <bitfield name="UNK10" pos="10"/>
++ <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
++ </reg32>
++ <reg32 offset="0x2" name="BUF_INFO" variants="A7XX-">
++ <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
++ <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
++ <bitfield name="UNK10" pos="10"/>
++ <bitfield name="LOSSLESSCOMPEN" pos="11" type="boolean"/>
++ <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
++ </reg32>
++ <!--
++ at least in gmem, things seem to be aligned to pitch of 64..
++ maybe an artifact of tiled format used in gmem?
++ -->
++ <reg32 offset="0x3" name="PITCH" shr="6" high="15" type="uint"/>
++ <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" high="28" type="uint"/>
++ <!--
++ Compared to a5xx and before, we configure both a GMEM base and
++ external base. Not sure if this is to facilitate GMEM save/
++ restore for context switch, or just to simplify state setup to
++ not have to care about GMEM vs BYPASS mode.
++ -->
++ <!-- maybe something in low bits since alignment of 1 doesn't make sense? -->
++ <reg64 offset="0x5" name="BASE" type="waddress" align="1"/>
++
++ <reg32 offset="0x7" name="BASE_GMEM" low="12" high="31" shr="12"/>
++ </array>
++
++ <reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float" usage="rp_blit"/>
++ <reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float" usage="rp_blit"/>
++ <reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float" usage="rp_blit"/>
++ <reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float" usage="rp_blit"/>
++ <reg32 offset="0x8864" name="RB_ALPHA_CONTROL" usage="cmd">
++ <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
++ <bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
++ <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
++ </reg32>
++ <reg32 offset="0x8865" name="RB_BLEND_CNTL" usage="rp_blit">
++ <!-- per-mrt enable bit -->
++ <bitfield name="ENABLE_BLEND" low="0" high="7"/>
++ <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
++ <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
++ <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
++ <bitfield name="ALPHA_TO_ONE" pos="11" type="boolean"/>
++ <bitfield name="SAMPLE_MASK" low="16" high="31"/>
++ </reg32>
++ <!-- 0x8866-0x886f invalid -->
++ <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL" usage="rp_blit">
++ <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
++ </reg32>
++
++ <reg32 offset="0x8871" name="RB_DEPTH_CNTL" usage="rp_blit">
++ <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>
++ <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
++ <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
++ <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
++ <doc>
++ Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER
++ also set when Z_BOUNDS_ENABLE is set
++ </doc>
++ <bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/>
++ <bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x8114" name="GRAS_SU_DEPTH_CNTL" usage="rp_blit">
++ <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>
++ </reg32>
++ <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
++ <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A6XX" usage="rp_blit">
++ <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
++ <bitfield name="UNK3" low="3" high="4"/>
++ </reg32>
++ <!-- first 4 bits duplicates GRAS_SU_DEPTH_BUFFER_INFO -->
++ <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit">
++ <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
++ <bitfield name="UNK3" low="3" high="4"/>
++ <bitfield name="TILEMODE" low="5" high="6" type="a6xx_tile_mode"/>
++ <bitfield name="LOSSLESSCOMPEN" pos="7" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint" usage="rp_blit"/>
++ <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint" usage="rp_blit"/>
++ <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/>
++ <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/>
++
++ <reg32 offset="0x8878" name="RB_Z_BOUNDS_MIN" type="float" usage="rp_blit"/>
++ <reg32 offset="0x8879" name="RB_Z_BOUNDS_MAX" type="float" usage="rp_blit"/>
++ <!-- 0x887a-0x887f invalid -->
++ <reg32 offset="0x8880" name="RB_STENCIL_CONTROL" usage="rp_blit">
++ <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
++ <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
++ <!--
++ set for stencil operations that require read from stencil
++ buffer, but not for example for stencil clear (which does
++ not require read).. so guessing this is analogous to
++ READ_DEST_ENABLE for color buffer..
++ -->
++ <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
++ <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
++ <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
++ <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
++ <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
++ <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
++ <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
++ <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
++ <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
++ </reg32>
++ <reg32 offset="0x8115" name="GRAS_SU_STENCIL_CNTL" usage="rp_blit">
++ <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x8881" name="RB_STENCIL_INFO" variants="A6XX" usage="rp_blit">
++ <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
++ <bitfield name="UNK1" pos="1" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x8881" name="RB_STENCIL_INFO" variants="A7XX-" usage="rp_blit">
++ <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
++ <bitfield name="UNK1" pos="1" type="boolean"/>
++ <bitfield name="TILEMODE" low="2" high="3" type="a6xx_tile_mode"/>
++ </reg32>
++ <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint" usage="rp_blit"/>
++ <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint" usage="rp_blit"/>
++ <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/>
++ <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/>
++ <reg32 offset="0x8887" name="RB_STENCILREF" usage="rp_blit">
++ <bitfield name="REF" low="0" high="7"/>
++ <bitfield name="BFREF" low="8" high="15"/>
++ </reg32>
++ <reg32 offset="0x8888" name="RB_STENCILMASK" usage="rp_blit">
++ <bitfield name="MASK" low="0" high="7"/>
++ <bitfield name="BFMASK" low="8" high="15"/>
++ </reg32>
++ <reg32 offset="0x8889" name="RB_STENCILWRMASK" usage="rp_blit">
++ <bitfield name="WRMASK" low="0" high="7"/>
++ <bitfield name="BFWRMASK" low="8" high="15"/>
++ </reg32>
++ <!-- 0x888a-0x888f invalid -->
++ <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/>
++ <reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL" usage="cmd">
++ <bitfield name="DISABLE" pos="0" type="boolean"/>
++ <bitfield name="COPY" pos="1" type="boolean"/>
++ </reg32>
++ <!-- 0x8892-0x8897 invalid -->
++ <reg32 offset="0x8898" name="RB_LRZ_CNTL" usage="rp_blit">
++ <bitfield name="ENABLE" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x8899" name="RB_UNKNOWN_8899" variants="A7XX-" usage="cmd"/>
++ <!-- 0x8899-0x88bf invalid -->
++ <!-- clamps depth value for depth test/write -->
++ <reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float" usage="rp_blit"/>
++ <reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float" usage="rp_blit"/>
++ <!-- 0x88c2-0x88cf invalid-->
++ <reg32 offset="0x88d0" name="RB_UNKNOWN_88D0" usage="rp_blit">
++ <bitfield name="UNK0" low="0" high="12"/>
++ <bitfield name="UNK16" low="16" high="26"/>
++ </reg32>
++ <reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/>
++ <reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/>
++ <!-- weird to duplicate other regs from same block?? -->
++ <reg32 offset="0x88d3" name="RB_BIN_CONTROL2" usage="rp_blit">
++ <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
++ <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
++ </reg32>
++ <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="a6xx_reg_xy" usage="rp_blit"/>
++ <reg32 offset="0x88d5" name="RB_BLIT_GMEM_MSAA_CNTL" usage="rp_blit">
++ <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
++ </reg32>
++ <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/>
++ <!-- s/DST_FORMAT/DST_INFO/ probably: -->
++ <reg32 offset="0x88d7" name="RB_BLIT_DST_INFO" usage="rp_blit">
++ <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
++ <bitfield name="FLAGS" pos="2" type="boolean"/>
++ <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
++ <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>
++ <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/>
++ <bitfield name="UNK15" pos="15" type="boolean"/>
++ </reg32>
++ <reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress" align="64" usage="rp_blit"/>
++ <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/>
++ <!-- array-pitch is size of layer -->
++ <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint" usage="rp_blit"/>
++ <reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress" align="64" usage="rp_blit"/>
++ <reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH" usage="rp_blit">
++ <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
++ <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0" usage="rp_blit"/>
++ <reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1" usage="rp_blit"/>
++ <reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2" usage="rp_blit"/>
++ <reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3" usage="rp_blit"/>
++
++ <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
++ <reg32 offset="0x88e3" name="RB_BLIT_INFO" usage="rp_blit">
++ <bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear? But also color restore? -->
++ <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
++ <bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging -->
++ <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
++ <doc>
++ For clearing depth/stencil
++ 1 - depth
++ 2 - stencil
++ 3 - depth+stencil
++ For clearing color buffer:
++ then probably a component mask, I always see 0xf
++ </doc>
++ <bitfield name="CLEAR_MASK" low="4" high="7"/>
++ <!-- set when this is the last resolve on a650+ -->
++ <bitfield name="LAST" low="8" high="9"/>
++ <!--
++ a618 GLES: color render target number being resolved for RM6_RESOLVE, 0x8 for depth, 0x9 for separate stencil.
++ a618 VK: 0x8 for depth RM6_RESOLVE, 0x9 for separate stencil, 0 otherwise.
++
++ We believe this is related to concurrent resolves
++ -->
++ <bitfield name="BUFFER_ID" low="12" high="15"/>
++ </reg32>
++ <reg32 offset="0x88e4" name="RB_UNKNOWN_88E4" variants="A7XX-" usage="rp_blit">
++ <!-- Value conditioned based on predicate, changed before blits -->
++ <bitfield name="UNK0" pos="0" type="boolean"/>
++ </reg32>
++
++ <enum name="a6xx_ccu_cache_size">
++ <value value="0x0" name="CCU_CACHE_SIZE_FULL"/>
++ <value value="0x1" name="CCU_CACHE_SIZE_HALF"/>
++ <value value="0x2" name="CCU_CACHE_SIZE_QUARTER"/>
++ <value value="0x3" name="CCU_CACHE_SIZE_EIGHTH"/>
++ </enum>
++ <reg32 offset="0x88e5" name="RB_CCU_CNTL2" variants="A7XX-" usage="cmd">
++ <bitfield name="DEPTH_OFFSET_HI" pos="0" type="hex"/>
++ <bitfield name="COLOR_OFFSET_HI" pos="2" type="hex"/>
++ <bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/>
++ <!-- GMEM offset of CCU depth cache -->
++ <bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/>
++ <bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/>
++ <!-- GMEM offset of CCU color cache
++ for GMEM rendering, we set it to GMEM size minus the minimum
++ CCU color cache size. CCU color cache will be needed in some
++ resolve cases, and in those cases we need to reserve the end
++ of GMEM for color cache.
++ -->
++ <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/>
++ </reg32>
++ <!-- 0x88e6-0x88ef invalid -->
++ <!-- always 0x0 ? -->
++ <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11" usage="cmd"/>
++ <!-- could be for separate stencil? (or may not be a flag buffer at all) -->
++ <reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64"/>
++ <reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH">
++ <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
++ <bitfield name="ARRAY_PITCH" low="11" high="23" shr="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x88f4" name="RB_UNKNOWN_88F4" low="0" high="2"/>
++ <!-- Connected to VK_EXT_fragment_density_map? -->
++ <reg32 offset="0x88f5" name="RB_UNKNOWN_88F5" variants="A7XX-"/>
++ <!-- 0x88f6-0x88ff invalid -->
++ <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/>
++ <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH" usage="rp_blit">
++ <bitfield name="PITCH" low="0" high="6" shr="6" type="uint"/>
++ <!-- TODO: actually part of array pitch -->
++ <bitfield name="UNK8" low="8" high="10"/>
++ <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
++ </reg32>
++ <array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8" usage="rp_blit">
++ <reg64 offset="0" name="ADDR" type="waddress" align="64"/>
++ <reg32 offset="2" name="PITCH">
++ <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
++ <bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/>
++ </reg32>
++ </array>
++ <!-- 0x891b-0x8926 invalid -->
++ <reg64 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR" type="waddress" align="16" usage="cmd" variants="A6XX"/>
++ <!-- 0x8929-0x89ff invalid -->
++
++ <!-- TODO: there are some registers in the 0x8a00-0x8bff range -->
++
++ <!--
++ These show up in a6xx gen3+ but so far haven't found an example of
++ blob writing non-zero:
++ -->
++ <reg32 offset="0x8a00" name="RB_UNKNOWN_8A00" variants="A6XX" usage="rp_blit"/>
++ <reg32 offset="0x8a10" name="RB_UNKNOWN_8A10" variants="A6XX" usage="rp_blit"/>
++ <reg32 offset="0x8a20" name="RB_UNKNOWN_8A20" variants="A6XX" usage="rp_blit"/>
++ <reg32 offset="0x8a30" name="RB_UNKNOWN_8A30" variants="A6XX" usage="rp_blit"/>
++
++ <reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl" usage="rp_blit"/>
++ <reg32 offset="0x8c01" name="RB_2D_UNKNOWN_8C01" low="0" high="31" usage="rp_blit"/>
++
++ <bitset name="a6xx_2d_surf_info" inline="yes">
++ <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
++ <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
++ <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
++ <bitfield name="FLAGS" pos="12" type="boolean"/>
++ <bitfield name="SRGB" pos="13" type="boolean"/>
++ <!-- the rest is only for src -->
++ <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
++ <bitfield name="FILTER" pos="16" type="boolean"/>
++ <bitfield name="UNK17" pos="17" type="boolean"/>
++ <bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/>
++ <bitfield name="UNK19" pos="19" type="boolean"/>
++ <bitfield name="UNK20" pos="20" type="boolean"/>
++ <bitfield name="UNK21" pos="21" type="boolean"/>
++ <bitfield name="UNK22" pos="22" type="boolean"/>
++ <bitfield name="UNK23" low="23" high="26"/>
++ <bitfield name="UNK28" pos="28" type="boolean"/>
++ </bitset>
++
++ <!-- 0x8c02-0x8c16 invalid -->
++ <!-- TODO: RB_2D_DST_INFO has 17 valid bits (doesn't match a6xx_2d_surf_info) -->
++ <reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info" usage="rp_blit"/>
++ <reg64 offset="0x8c18" name="RB_2D_DST" type="waddress" align="64" usage="rp_blit"/>
++ <reg32 offset="0x8c1a" name="RB_2D_DST_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/>
++ <!-- this is a guess but seems likely (for NV12/IYUV): -->
++ <reg64 offset="0x8c1b" name="RB_2D_DST_PLANE1" type="waddress" align="64" usage="rp_blit"/>
++ <reg32 offset="0x8c1d" name="RB_2D_DST_PLANE_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/>
++ <reg64 offset="0x8c1e" name="RB_2D_DST_PLANE2" type="waddress" align="64" usage="rp_blit"/>
++
++ <reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress" align="64" usage="rp_blit"/>
++ <reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" usage="rp_blit"/>
++ <!-- this is a guess but seems likely (for NV12 with UBWC): -->
++ <reg64 offset="0x8c23" name="RB_2D_DST_FLAGS_PLANE" type="waddress" align="64" usage="rp_blit"/>
++ <reg32 offset="0x8c25" name="RB_2D_DST_FLAGS_PLANE_PITCH" low="0" high="7" shr="6" type="uint" usage="rp_blit"/>
++
++ <!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers -->
++ <!-- unlike a5xx, these are per channel values rather than packed -->
++ <reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0" usage="rp_blit"/>
++ <reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1" usage="rp_blit"/>
++ <reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2" usage="rp_blit"/>
++ <reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3" usage="rp_blit"/>
++ <!-- 0x8c34-0x8dff invalid -->
++
++ <!-- always 0x1 ? either doesn't exist for a650 or write-only: -->
++ <reg32 offset="0x8e01" name="RB_UNKNOWN_8E01" usage="cmd"/>
++ <!-- 0x8e00-0x8e03 invalid -->
++ <reg32 offset="0x8e04" name="RB_DBG_ECO_CNTL" usage="cmd"/> <!-- TODO: valid mask 0xfffffeff -->
++ <reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
++ <!-- 0x02080000 in GMEM, zero otherwise? -->
++ <reg32 offset="0x8e06" name="RB_UNKNOWN_8E06" variants="A7XX-" usage="cmd"/>
++
++ <reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A6XX">
++ <bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/>
++ <!-- concurrent resolves are apparently a 2-bit enum on a650+ -->
++ <bitfield name="CONCURRENT_RESOLVE" pos="2" type="boolean"/>
++ <bitfield name="DEPTH_OFFSET_HI" pos="7" type="hex"/>
++ <bitfield name="COLOR_OFFSET_HI" pos="9" type="hex"/>
++ <bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/>
++ <!-- GMEM offset of CCU depth cache -->
++ <bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/>
++ <bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/>
++ <!-- GMEM offset of CCU color cache
++ for GMEM rendering, we set it to GMEM size minus the minimum
++ CCU color cache size. CCU color cache will be needed in some
++ resolve cases, and in those cases we need to reserve the end
++ of GMEM for color cache.
++ -->
++ <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/>
++ <!--TODO: valid mask 0xfffffc1f -->
++ </reg32>
++ <reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A7XX-">
++ <bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/>
++ <bitfield name="CONCURRENT_RESOLVE" pos="2" type="boolean"/>
++ <!-- rest of the bits were moved to RB_CCU_CNTL2 -->
++ </reg32>
++ <reg32 offset="0x8e08" name="RB_NC_MODE_CNTL">
++ <bitfield name="MODE" pos="0" type="boolean"/>
++ <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>
++ <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
++ <bitfield name="AMSBC" pos="4" type="boolean"/>
++ <bitfield name="UPPER_BIT" pos="10" type="uint"/>
++ <bitfield name="RGB565_PREDICATOR" pos="11" type="boolean"/>
++ <bitfield name="UNK12" low="12" high="13"/>
++ </reg32>
++ <reg32 offset="0x8e09" name="RB_UNKNOWN_8E09" variants="A7XX-" usage="cmd"/>
++ <!-- 0x8e09-0x8e0f invalid -->
++ <array offset="0x8e10" name="RB_PERFCTR_RB_SEL" stride="1" length="8"/>
++ <array offset="0x8e18" name="RB_PERFCTR_CCU_SEL" stride="1" length="5"/>
++ <!-- 0x8e1d-0x8e1f invalid -->
++ <!-- 0x8e20-0x8e25 more perfcntr sel? -->
++ <!-- 0x8e26-0x8e27 invalid -->
++ <reg32 offset="0x8e28" name="RB_UNKNOWN_8E28" low="0" high="10"/>
++ <!-- 0x8e29-0x8e2b invalid -->
++ <array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4"/>
++ <array offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A7XX-"/>
++ <reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/>
++ <reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
++ <!-- 0x8e3e-0x8e4f invalid -->
++ <!-- GMEM save/restore for preemption: -->
++ <reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE" pos="0" type="boolean"/>
++ <!-- address for GMEM save/restore? -->
++ <reg32 offset="0x8e51" name="RB_UNKNOWN_8E51" type="waddress" align="1"/>
++ <!-- 0x8e53-0x8e7f invalid -->
++ <reg32 offset="0x8e79" name="RB_UNKNOWN_8E79" variants="A7XX-" usage="cmd"/>
++ <!-- 0x8e80-0x8e83 are valid -->
++ <!-- 0x8e84-0x90ff invalid -->
++
++ <!-- 0x9000-0x90ff invalid -->
++
++ <reg32 offset="0x9100" name="VPC_GS_PARAM" variants="A6XX" usage="rp_blit">
++ <bitfield name="LINELENGTHLOC" low="0" high="7" type="uint"/>
++ </reg32>
++
++ <bitset name="a6xx_vpc_xs_clip_cntl" inline="yes">
++ <bitfield name="CLIP_MASK" low="0" high="7" type="uint"/>
++ <!-- there can be up to 8 total clip/cull distance outputs,
++ but apparenly VPC can only deal with vec4, so when there are
++ more than 4 outputs a second location needs to be programmed
++ -->
++ <bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/>
++ <bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/>
++ </bitset>
++ <reg32 offset="0x9101" name="VPC_VS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
++ <reg32 offset="0x9102" name="VPC_GS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
++ <reg32 offset="0x9103" name="VPC_DS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
++
++ <reg32 offset="0x9311" name="VPC_VS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
++ <reg32 offset="0x9312" name="VPC_GS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
++ <reg32 offset="0x9313" name="VPC_DS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
++
++ <bitset name="a6xx_vpc_xs_layer_cntl" inline="yes">
++ <bitfield name="LAYERLOC" low="0" high="7" type="uint"/>
++ <bitfield name="VIEWLOC" low="8" high="15" type="uint"/>
++ <bitfield name="SHADINGRATELOC" low="16" high="23" type="uint" variants="A7XX-"/>
++ </bitset>
++
++ <reg32 offset="0x9104" name="VPC_VS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
++ <reg32 offset="0x9105" name="VPC_GS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
++ <reg32 offset="0x9106" name="VPC_DS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
++
++ <reg32 offset="0x9314" name="VPC_VS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
++ <reg32 offset="0x9315" name="VPC_GS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
++ <reg32 offset="0x9316" name="VPC_DS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
++
++ <reg32 offset="0x9107" name="VPC_UNKNOWN_9107" variants="A6XX" usage="rp_blit">
++ <!-- this mirrors PC_RASTER_CNTL::DISCARD, although it seems it's unused -->
++ <bitfield name="RASTER_DISCARD" pos="0" type="boolean"/>
++ <bitfield name="UNK2" pos="2" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x9108" name="VPC_POLYGON_MODE" usage="rp_blit">
++ <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
++ </reg32>
++
++ <bitset name="a6xx_primitive_cntl_0" inline="yes">
++ <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
++ <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
++ <bitfield name="D3D_VERTEX_ORDERING" pos="2" type="boolean">
++ <doc>
++ Swaps TESS_CW_TRIS/TESS_CCW_TRIS, and also makes
++ triangle fans and triangle strips use the D3D
++ order instead of the OpenGL order.
++ </doc>
++ </bitfield>
++ <bitfield name="UNK3" pos="3" type="boolean"/>
++ </bitset>
++
++ <bitset name="a6xx_primitive_cntl_5" inline="yes">
++ <doc>
++ geometry shader
++ </doc>
++ <!-- TODO: first 16 bits are valid so something is wrong or missing here -->
++ <bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
++ <bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>
++ <bitfield name="LINELENGTHEN" pos="15" type="boolean"/>
++ <bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>
++ <bitfield name="UNK18" pos="18"/>
++ </bitset>
++
++ <bitset name="a6xx_multiview_cntl" inline="yes">
++ <bitfield name="ENABLE" pos="0" type="boolean"/>
++ <bitfield name="DISABLEMULTIPOS" pos="1" type="boolean">
++ <doc>
++ Multi-position output lets the last geometry
++ stage shader write multiple copies of
++ gl_Position. If disabled then the VS is run once
++ for each view, and ViewID is passed as a
++ register to the VS.
++ </doc>
++ </bitfield>
++ <bitfield name="VIEWS" low="2" high="6" type="uint"/>
++ </bitset>
++
++ <reg32 offset="0x9109" name="VPC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" variants="A7XX-" usage="rp_blit"/>
++ <reg32 offset="0x910a" name="VPC_PRIMITIVE_CNTL_5" type="a6xx_primitive_cntl_5" variants="A7XX-" usage="rp_blit"/>
++ <reg32 offset="0x910b" name="VPC_MULTIVIEW_MASK" type="hex" low="0" high="15" variants="A7XX-" usage="rp_blit"/>
++ <reg32 offset="0x910c" name="VPC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" variants="A7XX-" usage="rp_blit"/>
++
++ <enum name="a6xx_varying_interp_mode">
++ <value value="0" name="INTERP_SMOOTH"/>
++ <value value="1" name="INTERP_FLAT"/>
++ <value value="2" name="INTERP_ZERO"/>
++ <value value="3" name="INTERP_ONE"/>
++ </enum>
++
++ <enum name="a6xx_varying_ps_repl_mode">
++ <value value="0" name="PS_REPL_NONE"/>
++ <value value="1" name="PS_REPL_S"/>
++ <value value="2" name="PS_REPL_T"/>
++ <value value="3" name="PS_REPL_ONE_MINUS_T"/>
++ </enum>
++
++ <!-- 0x9109-0x91ff invalid -->
++ <array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8" usage="rp_blit">
++ <doc>Packed array of a6xx_varying_interp_mode</doc>
++ <reg32 offset="0x0" name="MODE"/>
++ </array>
++ <array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8" usage="rp_blit">
++ <doc>Packed array of a6xx_varying_ps_repl_mode</doc>
++ <reg32 offset="0x0" name="MODE"/>
++ </array>
++
++ <!-- always 0x0 -->
++ <reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31" variants="A6XX" usage="cmd"/>
++ <reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31" variants="A6XX" usage="cmd"/>
++
++ <array offset="0x9212" name="VPC_VAR" stride="1" length="4" usage="rp_blit">
++ <!-- one bit per varying component: -->
++ <reg32 offset="0" name="DISABLE"/>
++ </array>
++
++ <reg32 offset="0x9216" name="VPC_SO_CNTL" usage="rp_blit">
++ <!--
++ Choose which DWORD to write to. There is an array of
++ (4 * 64) DWORD's, dumped in the devcoredump at
++ HLSQ_INST_RAM dword 0x400. Each DWORD corresponds to a
++ (VPC location, stream) pair like so:
++
++ location 0, stream 0
++ location 2, stream 0
++ ...
++ location 126, stream 0
++ location 0, stream 1
++ location 2, stream 1
++ ...
++ location 126, stream 1
++ location 0, stream 2
++ ...
++
++ When EmitStreamVertex(N) happens, the HW goes to DWORD
++ 64 * N and then "executes" the next 64 DWORD's.
++
++ This field is auto-incremented when VPC_SO_PROG is
++ written to.
++ -->
++ <bitfield name="ADDR" low="0" high="7" type="hex"/>
++ <!-- clear all A_EN and B_EN bits for all DWORD's -->
++ <bitfield name="RESET" pos="16" type="boolean"/>
++ </reg32>
++ <!-- special register, write multiple times to load SO program (not readable) -->
++ <reg32 offset="0x9217" name="VPC_SO_PROG" usage="rp_blit">
++ <bitfield name="A_BUF" low="0" high="1" type="uint"/>
++ <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
++ <bitfield name="A_EN" pos="11" type="boolean"/>
++ <bitfield name="B_BUF" low="12" high="13" type="uint"/>
++ <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
++ <bitfield name="B_EN" pos="23" type="boolean"/>
++ </reg32>
++
++ <reg64 offset="0x9218" name="VPC_SO_STREAM_COUNTS" type="waddress" align="32" usage="cmd"/>
++
++ <array offset="0x921a" name="VPC_SO" stride="7" length="4" usage="cmd">
++ <reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/>
++ <reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/>
++ <reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/>
++ <reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/>
++ <reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/>
++ </array>
++
++ <reg32 offset="0x9236" name="VPC_POINT_COORD_INVERT" usage="cmd">
++ <bitfield name="INVERT" pos="0" type="boolean"/>
++ </reg32>
++ <!-- 0x9237-0x92ff invalid -->
++ <!-- always 0x0 ? -->
++ <reg32 offset="0x9300" name="VPC_UNKNOWN_9300" low="0" high="2" usage="cmd"/>
++
++ <bitset name="a6xx_vpc_xs_pack" inline="yes">
++ <doc>
++ num of varyings plus four for gl_Position (plus one if gl_PointSize)
++ plus # of transform-feedback (streamout) varyings if using the
++ hw streamout (rather than stg instructions in shader)
++ </doc>
++ <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
++ <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
++ <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
++ <bitfield name="EXTRAPOS" low="24" high="27" type="uint">
++ <doc>
++ The number of extra copies of POSITION, i.e.
++ number of views minus one when multi-position
++ output is enabled, otherwise 0.
++ </doc>
++ </bitfield>
++ </bitset>
++ <reg32 offset="0x9301" name="VPC_VS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/>
++ <reg32 offset="0x9302" name="VPC_GS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/>
++ <reg32 offset="0x9303" name="VPC_DS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/>
++
++ <reg32 offset="0x9304" name="VPC_CNTL_0" usage="rp_blit">
++ <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
++ <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS -->
++ <bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/>
++ <bitfield name="VARYING" pos="16" type="boolean"/>
++ <bitfield name="VIEWIDLOC" low="24" high="31" type="uint">
++ <doc>
++ This VPC location will be overwritten with
++ ViewID when multiview is enabled. It's used when
++ fragment shaders read ViewID. It's only
++ strictly required for multi-position output,
++ where the same VS invocation is used for all the
++ views at once, but it can be used when multi-pos
++ output is disabled too, to avoid having to pass
++ ViewID through the VS.
++ </doc>
++ </bitfield>
++ </reg32>
++
++ <reg32 offset="0x9305" name="VPC_SO_STREAM_CNTL" usage="rp_blit">
++ <!--
++ It's offset by 1, and 0 means "disabled"
++ -->
++ <bitfield name="BUF0_STREAM" low="0" high="2" type="uint"/>
++ <bitfield name="BUF1_STREAM" low="3" high="5" type="uint"/>
++ <bitfield name="BUF2_STREAM" low="6" high="8" type="uint"/>
++ <bitfield name="BUF3_STREAM" low="9" high="11" type="uint"/>
++ <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/>
++ </reg32>
++ <reg32 offset="0x9306" name="VPC_SO_DISABLE" usage="rp_blit">
++ <bitfield name="DISABLE" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x9307" name="VPC_POLYGON_MODE2" variants="A7XX-" usage="rp_blit">
++ <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
++ </reg32>
++ <reg32 offset="0x9308" name="VPC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit">
++ <bitfield name="SIZE_GMEM" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="0x9309" name="VPC_ATTR_BUF_BASE_GMEM" variants="A7XX-" usage="rp_blit">
++ <bitfield name="BASE_GMEM" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="0x9b09" name="PC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit">
++ <bitfield name="SIZE_GMEM" low="0" high="31"/>
++ </reg32>
++
++ <!-- 0x9307-0x95ff invalid -->
++
++ <!-- TODO: 0x9600-0x97ff range -->
++ <reg32 offset="0x9600" name="VPC_DBG_ECO_CNTL" usage="cmd"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask -->
++ <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" usage="cmd"/>
++ <reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0" usage="cmd"/> <!-- always 0x0 ? -->
++ <reg32 offset="0x9603" name="VPC_UNKNOWN_9603" low="0" high="26"/>
++ <array offset="0x9604" name="VPC_PERFCTR_VPC_SEL" stride="1" length="6" variants="A6XX"/>
++ <array offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A7XX-"/>
++ <!-- 0x960a-0x9623 invalid -->
++ <!-- TODO: regs from 0x9624-0x963a -->
++ <!-- 0x963b-0x97ff invalid -->
++
++ <reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX" low="0" high="5" type="uint" usage="rp_blit"/>
++
++ <!-- always 0x0 ? -->
++ <reg32 offset="0x9801" name="PC_HS_INPUT_SIZE" usage="rp_blit">
++ <bitfield name="SIZE" low="0" high="10" type="uint"/>
++ <bitfield name="UNK13" pos="13"/>
++ </reg32>
++
++ <reg32 offset="0x9802" name="PC_TESS_CNTL" usage="rp_blit">
++ <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
++ <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>
++ </reg32>
++
++ <reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint" usage="rp_blit"/>
++ <reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7" usage="rp_blit"/>
++
++ <reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2" usage="rp_blit"/>
++
++ <reg32 offset="0x9806" name="PC_PS_CNTL" usage="rp_blit">
++ <bitfield name="PRIMITIVEIDEN" pos="0" type="boolean"/>
++ </reg32>
++
++ <!-- New in a6xx gen3+ -->
++ <reg32 offset="0x9808" name="PC_SO_STREAM_CNTL" usage="rp_blit">
++ <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/>
++ </reg32>
++
++ <reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL">
++ <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/>
++ </reg32>
++ <!-- 0x980b-0x983f invalid -->
++
++ <!-- 0x9840 - 0x9842 are not readable -->
++ <reg32 offset="0x9840" name="PC_DRAW_CMD">
++ <bitfield name="STATE_ID" low="0" high="7"/>
++ </reg32>
++
++ <reg32 offset="0x9841" name="PC_DISPATCH_CMD">
++ <bitfield name="STATE_ID" low="0" high="7"/>
++ </reg32>
++
++ <reg32 offset="0x9842" name="PC_EVENT_CMD">
++ <!-- I think only the low bit is actually used? -->
++ <bitfield name="STATE_ID" low="16" high="23"/>
++ <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
++ </reg32>
++
++ <!--
++ 0x9880 written in a lot of places by SQE, same value gets written
++ to control reg 0x12a. Set by CP_SET_MARKER, so lets name it after
++ that
++ -->
++ <reg32 offset="0x9880" name="PC_MARKER"/>
++
++ <!-- 0x9843-0x997f invalid -->
++
++ <reg32 offset="0x9981" name="PC_POLYGON_MODE" variants="A6XX" usage="rp_blit">
++ <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
++ </reg32>
++ <reg32 offset="0x9809" name="PC_POLYGON_MODE" variants="A7XX-" usage="rp_blit">
++ <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
++ </reg32>
++
++ <reg32 offset="0x9980" name="PC_RASTER_CNTL" variants="A6XX" usage="rp_blit">
++ <!-- which stream to send to GRAS -->
++ <bitfield name="STREAM" low="0" high="1" type="uint"/>
++ <!-- discard primitives before rasterization -->
++ <bitfield name="DISCARD" pos="2" type="boolean"/>
++ </reg32>
++ <!-- VPC_RASTER_CNTL -->
++ <reg32 offset="0x9107" name="PC_RASTER_CNTL" variants="A7XX-" usage="rp_blit">
++ <!-- which stream to send to GRAS -->
++ <bitfield name="STREAM" low="0" high="1" type="uint"/>
++ <!-- discard primitives before rasterization -->
++ <bitfield name="DISCARD" pos="2" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x9317" name="PC_RASTER_CNTL_V2" variants="A7XX-" usage="rp_blit">
++ <!-- which stream to send to GRAS -->
++ <bitfield name="STREAM" low="0" high="1" type="uint"/>
++ <!-- discard primitives before rasterization -->
++ <bitfield name="DISCARD" pos="2" type="boolean"/>
++ </reg32>
++
++ <!-- 0x9982-0x9aff invalid -->
++
++ <reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" usage="rp_blit"/>
++
++ <bitset name="a6xx_xs_out_cntl" inline="yes">
++ <doc>
++ num of varyings plus four for gl_Position (plus one if gl_PointSize)
++ plus # of transform-feedback (streamout) varyings if using the
++ hw streamout (rather than stg instructions in shader)
++ </doc>
++ <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
++ <bitfield name="PSIZE" pos="8" type="boolean"/>
++ <bitfield name="LAYER" pos="9" type="boolean"/>
++ <bitfield name="VIEW" pos="10" type="boolean"/>
++ <!-- note: PC_VS_OUT_CNTL doesn't have the PRIMITIVE_ID bit -->
++ <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>
++ <bitfield name="CLIP_MASK" low="16" high="23" type="uint"/>
++ <bitfield name="SHADINGRATE" pos="24" type="boolean" variants="A7XX-"/>
++ </bitset>
++
++ <reg32 offset="0x9b01" name="PC_VS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>
++ <reg32 offset="0x9b02" name="PC_GS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>
++ <!-- since HS can't output anything, only PRIMITIVE_ID is valid -->
++ <reg32 offset="0x9b03" name="PC_HS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>
++ <reg32 offset="0x9b04" name="PC_DS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>
++
++ <reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5" type="a6xx_primitive_cntl_5" usage="rp_blit"/>
++
++ <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6" variants="A6XX" usage="rp_blit">
++ <doc>
++ size in vec4s of per-primitive storage for gs. TODO: not actually in VPC
++ </doc>
++ <bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x9b07" name="PC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" usage="rp_blit"/>
++ <!-- mask of enabled views, doesn't exist on A630 -->
++ <reg32 offset="0x9b08" name="PC_MULTIVIEW_MASK" type="hex" low="0" high="15" usage="rp_blit"/>
++ <!-- 0x9b09-0x9bff invalid -->
++ <reg32 offset="0x9c00" name="PC_2D_EVENT_CMD">
++ <!-- special register (but note first 8 bits can be written/read) -->
++ <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
++ <bitfield name="STATE_ID" low="8" high="15"/>
++ </reg32>
++ <!-- 0x9c01-0x9dff invalid -->
++ <!-- TODO: 0x9e00-0xa000 range incomplete -->
++ <reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/>
++ <reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++ <reg64 offset="0x9e04" name="PC_DRAW_INDX_BASE"/>
++ <reg32 offset="0x9e06" name="PC_DRAW_FIRST_INDX" type="uint"/>
++ <reg32 offset="0x9e07" name="PC_DRAW_MAX_INDICES" type="uint"/>
++ <reg64 offset="0x9e08" name="PC_TESSFACTOR_ADDR" variants="A6XX" type="waddress" align="32" usage="cmd"/>
++ <reg64 offset="0x9810" name="PC_TESSFACTOR_ADDR" variants="A7XX-" type="waddress" align="32" usage="cmd"/>
++
++ <reg32 offset="0x9e0b" name="PC_DRAW_INITIATOR" type="vgt_draw_initiator_a4xx">
++ <doc>
++ Possibly not really "initiating" the draw but the layout is similar
++ to VGT_DRAW_INITIATOR on older gens
++ </doc>
++ </reg32>
++ <reg32 offset="0x9e0c" name="PC_DRAW_NUM_INSTANCES" type="uint"/>
++ <reg32 offset="0x9e0d" name="PC_DRAW_NUM_INDICES" type="uint"/>
++
++ <!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
++ <reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL">
++ <bitfield name="UNK0" low="0" high="15"/>
++ <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
++ <bitfield name="VSC_N" low="22" high="26" type="uint"/>
++ </reg32>
++ <reg64 offset="0x9e12" name="PC_BIN_PRIM_STRM" type="waddress" align="32"/>
++ <reg64 offset="0x9e14" name="PC_BIN_DRAW_STRM" type="waddress" align="32"/>
++
++ <reg32 offset="0x9e1c" name="PC_VISIBILITY_OVERRIDE">
++ <doc>Written by CP_SET_VISIBILITY_OVERRIDE handler</doc>
++ <bitfield name="OVERRIDE" pos="0" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x9e24" name="PC_UNKNOWN_9E24" variants="A7XX-" usage="cmd"/>
++
++ <array offset="0x9e34" name="PC_PERFCTR_PC_SEL" stride="1" length="8" variants="A6XX"/>
++ <array offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A7XX-"/>
++
++ <!-- always 0x0 -->
++ <reg32 offset="0x9e72" name="PC_UNKNOWN_9E72" usage="cmd"/>
++
++ <reg32 offset="0xa000" name="VFD_CONTROL_0" usage="rp_blit">
++ <bitfield name="FETCH_CNT" low="0" high="5" type="uint"/>
++ <bitfield name="DECODE_CNT" low="8" high="13" type="uint"/>
++ </reg32>
++ <reg32 offset="0xa001" name="VFD_CONTROL_1" usage="rp_blit">
++ <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
++ <!-- only used for VS in non-multi-position-output case -->
++ <bitfield name="REGID4VIEWID" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0xa002" name="VFD_CONTROL_2" usage="rp_blit">
++ <bitfield name="REGID_HSRELPATCHID" low="0" high="7" type="a3xx_regid">
++ <doc>
++ This is the ID of the current patch within the
++ subdraw, used to calculate the offset of the
++ patch within the HS->DS buffers. When a draw is
++ split into multiple subdraws then this differs
++ from gl_PrimitiveID on the second, third, etc.
++ subdraws.
++ </doc>
++ </bitfield>
++ <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0xa003" name="VFD_CONTROL_3" usage="rp_blit">
++ <bitfield name="REGID_DSPRIMID" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="REGID_DSRELPATCHID" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0xa004" name="VFD_CONTROL_4" usage="rp_blit">
++ <bitfield name="UNK0" low="0" high="7" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0xa005" name="VFD_CONTROL_5" usage="rp_blit">
++ <bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="UNK8" low="8" high="15" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0xa006" name="VFD_CONTROL_6" usage="rp_blit">
++ <!--
++ True if gl_PrimitiveID is read via the FS
++ -->
++ <bitfield name="PRIMID4PSEN" pos="0" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0xa007" name="VFD_MODE_CNTL" usage="cmd">
++ <bitfield name="RENDER_MODE" low="0" high="2" type="a6xx_render_mode"/>
++ </reg32>
++
++ <reg32 offset="0xa008" name="VFD_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" usage="rp_blit"/>
++ <reg32 offset="0xa009" name="VFD_ADD_OFFSET" usage="cmd">
++ <!-- add VFD_INDEX_OFFSET to REGID4VTX -->
++ <bitfield name="VERTEX" pos="0" type="boolean"/>
++ <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST -->
++ <bitfield name="INSTANCE" pos="1" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET" usage="rp_blit"/>
++ <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET" usage="rp_blit"/>
++ <array offset="0xa010" name="VFD_FETCH" stride="4" length="32" usage="rp_blit">
++ <reg64 offset="0x0" name="BASE" type="address" align="1"/>
++ <reg32 offset="0x2" name="SIZE" type="uint"/>
++ <reg32 offset="0x3" name="STRIDE" low="0" high="11" type="uint"/>
++ </array>
++ <array offset="0xa090" name="VFD_DECODE" stride="2" length="32" usage="rp_blit">
++ <reg32 offset="0x0" name="INSTR">
++ <!-- IDX and byte OFFSET into VFD_FETCH -->
++ <bitfield name="IDX" low="0" high="4" type="uint"/>
++ <bitfield name="OFFSET" low="5" high="16"/>
++ <bitfield name="INSTANCED" pos="17" type="boolean"/>
++ <bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/>
++ <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
++ <bitfield name="UNK30" pos="30" type="boolean"/>
++ <bitfield name="FLOAT" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x1" name="STEP_RATE" type="uint"/>
++ </array>
++ <array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32" usage="rp_blit">
++ <reg32 offset="0x0" name="INSTR">
++ <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
++ <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
++ </reg32>
++ </array>
++
++ <reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2" usage="rp_blit"/>
++
++ <reg32 offset="0xa600" name="VFD_UNKNOWN_A600" variants="A7XX-" usage="cmd"/>
++
++ <reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++ <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8" variants="A6XX"/>
++ <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="16" variants="A7XX-"/>
++
++ <!--
++ Note: this seems to always be paired with another bit in another
++ block.
++ -->
++ <enum name="a6xx_threadsize">
++ <value value="0" name="THREAD64"/>
++ <value value="1" name="THREAD128"/>
++ </enum>
++
++ <bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes">
++ <!-- if set to SINGLE, only use 1 concurrent wave on each SP -->
++ <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
++ <!--
++ When b31 set we just see FULLREGFOOTPRINT set. The pattern of
++ used registers is a bit odd too:
++ - used (half): 0-15 68-179 (cnt=128, max=179)
++ - used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127>
++ whereas we usually see a (mostly) contiguous range of regs used. But if
++ I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)),
++ then:
++ - used (merged): 0-191 (cnt=192, max=191)
++ So I think if b31 is set, then the half precision registers overlap
++ the full precision registers. (Which seems like a pretty sensible
++ feature, actually I'm not sure when you *wouldn't* want to use that,
++ since it gives register allocation more flexibility)
++ -->
++ <bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/>
++ <bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/>
++ <!-- could it be a low bit of branchstack? -->
++ <bitfield name="UNK13" pos="13" type="boolean"/>
++ <!-- seems to be nesting level for flow control:.. -->
++ <bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/>
++ </bitset>
++
++ <bitset name="a6xx_sp_xs_config" inline="yes">
++ <!--
++ Each of these are set if the given resource type is used
++ with the Vulkan/bindless binding model.
++ -->
++ <bitfield name="BINDLESS_TEX" pos="0" type="boolean"/>
++ <bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/>
++ <bitfield name="BINDLESS_IBO" pos="2" type="boolean"/>
++ <bitfield name="BINDLESS_UBO" pos="3" type="boolean"/>
++
++ <bitfield name="ENABLED" pos="8" type="boolean"/>
++ <!--
++ number of textures and samplers.. these might be swapped, with GL I
++ always see the same value for both.
++ -->
++ <bitfield name="NTEX" low="9" high="16" type="uint"/>
++ <bitfield name="NSAMP" low="17" high="21" type="uint"/>
++ <bitfield name="NIBO" low="22" high="28" type="uint"/>
++ </bitset>
++
++ <bitset name="a6xx_sp_xs_prim_cntl" inline="yes">
++ <!-- # of VS outputs including pos/psize -->
++ <bitfield name="OUT" low="0" high="5" type="uint"/>
++ <!-- FLAGS_REGID only for GS -->
++ <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
++ </bitset>
++
++ <reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
++ <!--
++ This field actually controls all geometry stages. TCS, TES, and
++ GS must have the same mergedregs setting as VS.
++ -->
++ <bitfield name="MERGEDREGS" pos="20" type="boolean"/>
++ <!--
++ Creates a separate preamble-only thread?
++
++ Early preamble has the following limitations:
++ - Only shared, a1, and consts regs could be used
++ (accessing other regs would result in GPU fault);
++ - No cat5/cat6, only stc/ldc variants are working;
++ - Values writen to shared regs are not accessible by the rest
++ of the shader;
++ - Instructions before shps are also considered to be a part of
++ early preamble;
++
++ Note, for all shaders from d3d11 games blob produced preambles
++ compatible with early preamble mode.
++ -->
++ <bitfield name="EARLYPREAMBLE" pos="21" type="boolean"/>
++ </reg32>
++ <!-- bitmask of true/false conditions for VS brac.N instructions,
++ bit N corresponds to brac.N -->
++ <reg32 offset="0xa801" name="SP_VS_BRANCH_COND" type="hex"/>
++ <!-- # of VS outputs including pos/psize -->
++ <reg32 offset="0xa802" name="SP_VS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/>
++ <array offset="0xa803" name="SP_VS_OUT" stride="1" length="16" usage="rp_blit">
++ <reg32 offset="0x0" name="REG">
++ <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
++ <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
++ </reg32>
++ </array>
++ <!--
++ Starting with a5xx, position/psize outputs from shader end up in the
++ SP_VS_OUT map, with highest OUTLOCn position. (Generally they are
++ the last entries too, except when gl_PointCoord is used, blob inserts
++ an extra varying after, but with a lower OUTLOC position. If present,
++ psize is last, preceded by position.
++ -->
++ <array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8" usage="rp_blit">
++ <reg32 offset="0x0" name="REG">
++ <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
++ <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
++ <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
++ <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
++ </reg32>
++ </array>
++
++ <bitset name="a6xx_sp_xs_pvt_mem_param" inline="yes">
++ <bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="9">
++ <doc>The size of memory that ldp/stp can address.</doc>
++ </bitfield>
++ <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31">
++ <doc>
++ Seems to be the same as a3xx. The maximum stack
++ size in units of 4 calls, so a call depth of 7
++ would result in a value of 2.
++ TODO: What's the actual size per call, i.e. the
++ size of the PC? a3xx docs say it's 16 bits
++ there, but the length register now takes 28 bits
++ so it's probably been bumped to 32 bits.
++ </doc>
++ </bitfield>
++ </bitset>
++
++ <bitset name="a6xx_sp_xs_pvt_mem_size" inline="yes">
++ <bitfield name="TOTALPVTMEMSIZE" low="0" high="17" shr="12"/>
++ <bitfield name="PERWAVEMEMLAYOUT" pos="31" type="boolean">
++ <doc>
++ There are four indices used to compute the
++ private memory location for an access:
++
++ - stp/ldp offset
++ - fiber id
++ - wavefront id (a swizzled version of what "getwid" returns)
++ - SP ID (the same as what "getspid" returns)
++
++ The stride for the SP ID is always set by
++ TOTALPVTMEMSIZE. In the per-wave layout, the
++ indices are used in this order:
++
++ - offset % 4 (offset within dword)
++ - fiber id
++ - offset / 4
++ - wavefront id
++ - SP ID
++
++ and the stride for the wavefront ID is
++ MEMSIZEPERITEM, multiplied by 128 (fibers per
++ wavefront). In the per-fiber layout, the indices
++ are used in this order:
++
++ - offset
++ - fiber id % 4
++ - wavefront id
++ - fiber id / 4
++ - SP ID
++
++ and the stride for the fiber id/wavefront id
++ combo is MEMSIZEPERITEM.
++
++ Note: Accesses of more than 1 dword do not work
++ with per-fiber layout. The blob will fall back
++ to per-wave instead.
++ </doc>
++ </bitfield>
++ </bitset>
++
++ <bitset name="a6xx_sp_xs_pvt_mem_hw_stack_offset" inline="yes">
++ <doc>
++ This seems to be be the equivalent of HWSTACKOFFSET in
++ a3xx. The ldp/stp offset formula above isn't affected by
++ HWSTACKSIZEPERTHREAD at all, so the HW return address
++ stack seems to be after all the normal per-SP private
++ memory.
++ </doc>
++ <bitfield name="OFFSET" low="0" high="18" shr="11"/>
++ </bitset>
++
++ <reg32 offset="0xa81b" name="SP_VS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
++ <reg64 offset="0xa81c" name="SP_VS_OBJ_START" type="address" align="32" usage="rp_blit"/>
++ <reg32 offset="0xa81e" name="SP_VS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
++ <reg64 offset="0xa81f" name="SP_VS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
++ <reg32 offset="0xa821" name="SP_VS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
++ <reg32 offset="0xa822" name="SP_VS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
++ <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
++ <reg32 offset="0xa824" name="SP_VS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
++ <reg32 offset="0xa825" name="SP_VS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>
++ <reg32 offset="0xa82d" name="SP_VS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
++
++ <reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
++ <!-- There is no mergedregs bit, that comes from the VS. -->
++ <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/>
++ </reg32>
++ <!--
++ Total size of local storage in dwords divided by the wave size.
++ The maximum value is 64. With the wave size being always 64 for HS,
++ the maximum size of local storage should be:
++ 64 (wavesize) * 64 (SP_HS_WAVE_INPUT_SIZE) * 4 = 16k
++ -->
++ <reg32 offset="0xa831" name="SP_HS_WAVE_INPUT_SIZE" low="0" high="7" type="uint" usage="rp_blit"/>
++ <reg32 offset="0xa832" name="SP_HS_BRANCH_COND" type="hex" usage="rp_blit"/>
++
++ <!-- TODO: exact same layout as 0xa81b-0xa825 -->
++ <reg32 offset="0xa833" name="SP_HS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
++ <reg64 offset="0xa834" name="SP_HS_OBJ_START" type="address" align="32" usage="rp_blit"/>
++ <reg32 offset="0xa836" name="SP_HS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
++ <reg64 offset="0xa837" name="SP_HS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
++ <reg32 offset="0xa839" name="SP_HS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
++ <reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
++ <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
++ <reg32 offset="0xa83c" name="SP_HS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
++ <reg32 offset="0xa83d" name="SP_HS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>
++ <reg32 offset="0xa82f" name="SP_HS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
++
++ <reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
++ <!-- There is no mergedregs bit, that comes from the VS. -->
++ <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xa841" name="SP_DS_BRANCH_COND" type="hex"/>
++
++ <!-- TODO: exact same layout as 0xa802-0xa81a -->
++ <reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/>
++ <array offset="0xa843" name="SP_DS_OUT" stride="1" length="16" usage="rp_blit">
++ <reg32 offset="0x0" name="REG">
++ <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
++ <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
++ </reg32>
++ </array>
++ <array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8" usage="rp_blit">
++ <reg32 offset="0x0" name="REG">
++ <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
++ <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
++ <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
++ <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
++ </reg32>
++ </array>
++
++ <!-- TODO: exact same layout as 0xa81b-0xa825 -->
++ <reg32 offset="0xa85b" name="SP_DS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
++ <reg64 offset="0xa85c" name="SP_DS_OBJ_START" type="address" align="32" usage="rp_blit"/>
++ <reg32 offset="0xa85e" name="SP_DS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
++ <reg64 offset="0xa85f" name="SP_DS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
++ <reg32 offset="0xa861" name="SP_DS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
++ <reg32 offset="0xa862" name="SP_DS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
++ <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
++ <reg32 offset="0xa864" name="SP_DS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
++ <reg32 offset="0xa865" name="SP_DS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>
++ <reg32 offset="0xa868" name="SP_DS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
++
++ <reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
++ <!-- There is no mergedregs bit, that comes from the VS. -->
++ <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xa871" name="SP_GS_PRIM_SIZE" low="0" high="7" type="uint" usage="rp_blit">
++ <doc>
++ Normally the size of the output of the last stage in
++ dwords. It should be programmed as follows:
++
++ size less than 63 - size
++ size of 63 (?) or 64 - 63
++ size greater than 64 - 64
++
++ What to program when the size is 61-63 is a guess, but
++ both the blob and ir3 align the size to 4 dword's so it
++ doesn't matter in practice.
++ </doc>
++ </reg32>
++ <reg32 offset="0xa872" name="SP_GS_BRANCH_COND" type="hex" usage="rp_blit"/>
++
++ <!-- TODO: exact same layout as 0xa802-0xa81a -->
++ <reg32 offset="0xa873" name="SP_GS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/>
++ <array offset="0xa874" name="SP_GS_OUT" stride="1" length="16" usage="rp_blit">
++ <reg32 offset="0x0" name="REG">
++ <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
++ <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
++ </reg32>
++ </array>
++
++ <array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8" usage="rp_blit">
++ <reg32 offset="0x0" name="REG">
++ <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
++ <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
++ <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
++ <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
++ </reg32>
++ </array>
++
++ <!-- TODO: exact same layout as 0xa81b-0xa825 -->
++ <reg32 offset="0xa88c" name="SP_GS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
++ <reg64 offset="0xa88d" name="SP_GS_OBJ_START" type="address" align="32" usage="rp_blit"/>
++ <reg32 offset="0xa88f" name="SP_GS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
++ <reg64 offset="0xa890" name="SP_GS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
++ <reg32 offset="0xa892" name="SP_GS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
++ <reg32 offset="0xa893" name="SP_GS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
++ <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
++ <reg32 offset="0xa895" name="SP_GS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
++ <reg32 offset="0xa896" name="SP_GS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>
++ <reg32 offset="0xa899" name="SP_GS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
++
++ <reg64 offset="0xa8a0" name="SP_VS_TEX_SAMP" type="address" align="16" usage="cmd"/>
++ <reg64 offset="0xa8a2" name="SP_HS_TEX_SAMP" type="address" align="16" usage="cmd"/>
++ <reg64 offset="0xa8a4" name="SP_DS_TEX_SAMP" type="address" align="16" usage="cmd"/>
++ <reg64 offset="0xa8a6" name="SP_GS_TEX_SAMP" type="address" align="16" usage="cmd"/>
++ <reg64 offset="0xa8a8" name="SP_VS_TEX_CONST" type="address" align="64" usage="cmd"/>
++ <reg64 offset="0xa8aa" name="SP_HS_TEX_CONST" type="address" align="64" usage="cmd"/>
++ <reg64 offset="0xa8ac" name="SP_DS_TEX_CONST" type="address" align="64" usage="cmd"/>
++ <reg64 offset="0xa8ae" name="SP_GS_TEX_CONST" type="address" align="64" usage="cmd"/>
++
++ <!-- TODO: 4 unknown bool registers 0xa8c0-0xa8c3 -->
++
++ <reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
++ <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/>
++ <bitfield name="UNK21" pos="21" type="boolean"/>
++ <bitfield name="VARYING" pos="22" type="boolean"/>
++ <bitfield name="LODPIXMASK" pos="23" type="boolean">
++ <doc>
++ Enable ALL helper invocations in a quad. Necessary for
++ fine derivatives and quad subgroup ops.
++ </doc>
++ </bitfield>
++ <!-- note: vk blob uses bit24 -->
++ <bitfield name="UNK24" pos="24" type="boolean"/>
++ <bitfield name="UNK25" pos="25" type="boolean"/>
++ <bitfield name="PIXLODENABLE" pos="26" type="boolean">
++ <doc>
++ Enable helper invocations. Enables 3 out of 4 fragments,
++ because the coarse derivatives only use half of the quad
++ and so one pixel's value is always unused.
++ </doc>
++ </bitfield>
++ <bitfield name="UNK27" pos="27" type="boolean"/>
++ <bitfield name="EARLYPREAMBLE" pos="28" type="boolean"/>
++ <bitfield name="MERGEDREGS" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xa981" name="SP_FS_BRANCH_COND" type="hex"/>
++ <reg32 offset="0xa982" name="SP_FS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
++ <reg64 offset="0xa983" name="SP_FS_OBJ_START" type="address" align="32" usage="rp_blit"/>
++ <reg32 offset="0xa985" name="SP_FS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
++ <reg64 offset="0xa986" name="SP_FS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
++ <reg32 offset="0xa988" name="SP_FS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
++
++ <reg32 offset="0xa989" name="SP_BLEND_CNTL" usage="rp_blit">
++ <!-- per-mrt enable bit -->
++ <bitfield name="ENABLE_BLEND" low="0" high="7"/>
++ <bitfield name="UNK8" pos="8" type="boolean"/>
++ <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
++ <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xa98a" name="SP_SRGB_CNTL" usage="rp_blit">
++ <!-- Same as RB_SRGB_CNTL -->
++ <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
++ <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
++ <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
++ <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
++ <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
++ <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
++ <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
++ <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS" usage="rp_blit">
++ <bitfield name="RT0" low="0" high="3"/>
++ <bitfield name="RT1" low="4" high="7"/>
++ <bitfield name="RT2" low="8" high="11"/>
++ <bitfield name="RT3" low="12" high="15"/>
++ <bitfield name="RT4" low="16" high="19"/>
++ <bitfield name="RT5" low="20" high="23"/>
++ <bitfield name="RT6" low="24" high="27"/>
++ <bitfield name="RT7" low="28" high="31"/>
++ </reg32>
++ <reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0" usage="rp_blit">
++ <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
++ <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="STENCILREF_REGID" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1" usage="rp_blit">
++ <bitfield name="MRT" low="0" high="3" type="uint"/>
++ </reg32>
++
++ <array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8" usage="rp_blit">
++ <doc>per MRT</doc>
++ <reg32 offset="0x0" name="REG">
++ <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
++ </reg32>
++ </array>
++
++ <array offset="0xa996" name="SP_FS_MRT" stride="1" length="8" usage="rp_blit">
++ <reg32 offset="0" name="REG">
++ <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
++ <bitfield name="COLOR_SINT" pos="8" type="boolean"/>
++ <bitfield name="COLOR_UINT" pos="9" type="boolean"/>
++ <bitfield name="UNK10" pos="10" type="boolean"/>
++ </reg32>
++ </array>
++
++ <reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL" usage="rp_blit">
++ <bitfield name="COUNT" low="0" high="2" type="uint"/>
++ <bitfield name="IJ_WRITE_DISABLE" pos="3" type="boolean"/>
++ <doc>
++ Similar to "(eq)" flag but disables helper invocations
++ after the texture prefetch.
++ </doc>
++ <bitfield name="ENDOFQUAD" pos="4" type="boolean" />
++ <doc>
++ Bypass writing to regs and overwrite output with color from
++ CONSTSLOTID const regs.
++ </doc>
++ <bitfield name="WRITE_COLOR_TO_OUTPUT" pos="5" type="boolean"/>
++ <bitfield name="CONSTSLOTID" low="6" high="14" type="uint"/>
++ <!-- Blob never uses it -->
++ <bitfield name="CONSTSLOTID4COORD" low="16" high="24" type="uint" variants="A7XX-"/>
++ </reg32>
++ <array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A6XX" usage="rp_blit">
++ <reg32 offset="0" name="CMD" variants="A6XX">
++ <bitfield name="SRC" low="0" high="6" type="uint"/>
++ <bitfield name="SAMP_ID" low="7" high="10" type="uint"/>
++ <bitfield name="TEX_ID" low="11" high="15" type="uint"/>
++ <bitfield name="DST" low="16" high="21" type="a3xx_regid"/>
++ <bitfield name="WRMASK" low="22" high="25" type="hex"/>
++ <bitfield name="HALF" pos="26" type="boolean"/>
++ <doc>Results in color being zero</doc>
++ <bitfield name="UNK27" pos="27" type="boolean"/>
++ <bitfield name="BINDLESS" pos="28" type="boolean"/>
++ <bitfield name="CMD" low="29" high="31" type="a6xx_tex_prefetch_cmd"/>
++ </reg32>
++ </array>
++ <array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A7XX-" usage="rp_blit">
++ <reg32 offset="0" name="CMD" variants="A7XX-">
++ <bitfield name="SRC" low="0" high="6" type="uint"/>
++ <bitfield name="SAMP_ID" low="7" high="9" type="uint"/>
++ <bitfield name="TEX_ID" low="10" high="12" type="uint"/>
++ <bitfield name="DST" low="13" high="18" type="a3xx_regid"/>
++ <bitfield name="WRMASK" low="19" high="22" type="hex"/>
++ <bitfield name="HALF" pos="23" type="boolean"/>
++ <bitfield name="BINDLESS" pos="25" type="boolean"/>
++ <bitfield name="CMD" low="26" high="29" type="a6xx_tex_prefetch_cmd"/>
++ </reg32>
++ </array>
++ <array offset="0xa9a3" name="SP_FS_BINDLESS_PREFETCH" stride="1" length="4" usage="rp_blit">
++ <reg32 offset="0" name="CMD">
++ <bitfield name="SAMP_ID" low="0" high="15" type="uint"/>
++ <bitfield name="TEX_ID" low="16" high="31" type="uint"/>
++ </reg32>
++ </array>
++ <reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
++ <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" usage="cmd"/> <!-- always 0x0 ? -->
++ <reg32 offset="0xa9a9" name="SP_FS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>
++
++ <!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS -->
++
++
++
++
++ <reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="cmd">
++ <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/>
++ <!-- seems to make SP use less concurrent threads when possible? -->
++ <bitfield name="UNK21" pos="21" type="boolean"/>
++ <!-- has a small impact on performance, not clear what it does -->
++ <bitfield name="UNK22" pos="22" type="boolean"/>
++ <bitfield name="EARLYPREAMBLE" pos="23" type="boolean"/>
++ <bitfield name="MERGEDREGS" pos="31" type="boolean"/>
++ </reg32>
++
++ <!-- set for compute shaders -->
++ <reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" usage="cmd">
++ <bitfield name="SHARED_SIZE" low="0" high="4" type="uint">
++ <doc>
++ If 0 - all 32k of shared storage is enabled, otherwise
++ (SHARED_SIZE + 1) * 1k is enabled.
++ The ldl/stl offset seems to be rewritten to 0 when it is beyond
++ this limit. This is different from ldlw/stlw, which wraps at
++ 64k (and has 36k of storage on A640 - reads between 36k-64k
++ always return 0)
++ </doc>
++ </bitfield>
++ <bitfield name="UNK5" pos="5" type="boolean"/>
++ <!-- always 1 ? -->
++ <bitfield name="UNK6" pos="6" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xa9b2" name="SP_CS_BRANCH_COND" type="hex" usage="cmd"/>
++ <reg32 offset="0xa9b3" name="SP_CS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="cmd"/>
++ <reg64 offset="0xa9b4" name="SP_CS_OBJ_START" type="address" align="32" usage="cmd"/>
++ <reg32 offset="0xa9b6" name="SP_CS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="cmd"/>
++ <reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_ADDR" align="32" usage="cmd"/>
++ <reg32 offset="0xa9b9" name="SP_CS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="cmd"/>
++ <reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" low="0" high="7" type="uint" usage="cmd"/>
++ <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config" usage="cmd"/>
++ <reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" low="0" high="27" type="uint" usage="cmd"/>
++ <reg32 offset="0xa9bd" name="SP_CS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="cmd"/>
++ <reg32 offset="0xa9be" name="SP_CS_UNKNOWN_A9BE" variants="A7XX-" usage="cmd"/>
++ <reg32 offset="0xa9c5" name="SP_CS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
++
++ <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_0 -->
++ <reg32 offset="0xa9c2" name="SP_CS_CNTL_0" usage="cmd">
++ <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_1 -->
++ <reg32 offset="0xa9c3" name="SP_CS_CNTL_1" variants="A6XX" usage="cmd">
++ <!-- gl_LocalInvocationIndex -->
++ <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
++ <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only
++ one of those 6 "SP cores" -->
++ <bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/>
++ <!-- Must match SP_CS_CTRL -->
++ <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/>
++ <!-- 1 thread per wave (ignored if bit9 set) -->
++ <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0xa9c3" name="SP_CS_CNTL_1" variants="A7XX-" usage="cmd">
++ <!-- gl_LocalInvocationIndex -->
++ <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
++ <!-- Must match SP_CS_CTRL -->
++ <bitfield name="THREADSIZE" pos="8" type="a6xx_threadsize"/>
++ <!-- 1 thread per wave (would hang if THREAD128 is also set) -->
++ <bitfield name="THREADSIZE_SCALAR" pos="9" type="boolean"/>
++
++ <!-- Affects getone. If enabled, getone sometimes executed 1? less times
++ than there are subgroups.
++ -->
++ <bitfield name="UNK15" pos="15" type="boolean"/>
++ </reg32>
++
++ <!-- TODO: two 64kb aligned addresses at a9d0/a9d2 -->
++
++ <reg64 offset="0xa9e0" name="SP_FS_TEX_SAMP" type="address" align="16" usage="rp_blit"/>
++ <reg64 offset="0xa9e2" name="SP_CS_TEX_SAMP" type="address" align="16" usage="cmd"/>
++ <reg64 offset="0xa9e4" name="SP_FS_TEX_CONST" type="address" align="64" usage="rp_blit"/>
++ <reg64 offset="0xa9e6" name="SP_CS_TEX_CONST" type="address" align="64" usage="cmd"/>
++
++ <enum name="a6xx_bindless_descriptor_size">
++ <doc>
++ This can alternatively be interpreted as a pitch shift, ie, the
++ descriptor size is 2 << N dwords
++ </doc>
++ <value value="1" name="BINDLESS_DESCRIPTOR_16B"/>
++ <value value="3" name="BINDLESS_DESCRIPTOR_64B"/>
++ </enum>
++
++ <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="cmd">
++ <reg64 offset="0" name="DESCRIPTOR" variants="A6XX">
++ <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
++ <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
++ </reg64>
++ </array>
++ <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="cmd">
++ <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-">
++ <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
++ <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
++ </reg64>
++ </array>
++
++ <!--
++ IBO state for compute shader:
++ -->
++ <reg64 offset="0xa9f2" name="SP_CS_IBO" type="address" align="16"/>
++ <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" low="0" high="6" type="uint"/>
++
++ <!-- Correlated with avgs/uvgs usage in FS -->
++ <reg32 offset="0xaa01" name="SP_FS_VGPR_CONFIG" type="uint" variants="A7XX-" usage="cmd"/>
++
++ <reg32 offset="0xaa02" name="SP_PS_ALIASED_COMPONENTS_CONTROL" variants="A7XX-" usage="cmd">
++ <bitfield name="ENABLED" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0xaa03" name="SP_PS_ALIASED_COMPONENTS" variants="A7XX-" usage="cmd">
++ <doc>
++ Specify for which components the output color should be read
++ from alias, e.g. for:
++
++ alias.1.b32.0 r3.x, c8.x
++ alias.1.b32.0 r2.x, c4.x
++ alias.1.b32.0 r1.x, c4.x
++ alias.1.b32.0 r0.x, c0.x
++
++ the SP_PS_ALIASED_COMPONENTS would be 0x00001111
++ </doc>
++
++ <bitfield name="RT0" low="0" high="3"/>
++ <bitfield name="RT1" low="4" high="7"/>
++ <bitfield name="RT2" low="8" high="11"/>
++ <bitfield name="RT3" low="12" high="15"/>
++ <bitfield name="RT4" low="16" high="19"/>
++ <bitfield name="RT5" low="20" high="23"/>
++ <bitfield name="RT6" low="24" high="27"/>
++ <bitfield name="RT7" low="28" high="31"/>
++ </reg32>
++
++ <reg32 offset="0xaaf2" name="SP_UNKNOWN_AAF2" type="uint" usage="cmd"/>
++
++ <!--
++ This enum is probably similar in purpose to SNORMMODE on a3xx,
++ minus the snorm stuff, i.e. it controls what happens with an
++ out-of-bounds isam/isamm. GL and Vulkan robustness require us to
++ return 0 on out-of-bound textureFetch().
++ -->
++ <enum name="a6xx_isam_mode">
++ <value value="0x1" name="ISAMMODE_CL"/>
++ <value value="0x2" name="ISAMMODE_GL"/>
++ </enum>
++
++ <reg32 offset="0xab00" name="SP_MODE_CONTROL" usage="rp_blit">
++ <!--
++ When set, half register loads from the constant file will
++ load a 32-bit value (so hc0.y loads the same value as c0.y)
++ and implicitly convert it to 16b (f2f16, or u2u16, based on
++ operand type). When unset, half register loads from the
++ constant file will load 16 bits from the packed constant
++ file (so hc0.y loads the top 16 bits of the value of c0.x)
++ -->
++ <bitfield name="CONSTANT_DEMOTION_ENABLE" pos="0" type="boolean"/>
++ <bitfield name="ISAMMODE" low="1" high="2" type="a6xx_isam_mode"/>
++ <bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see HLSQ_SHARED_CONSTS -->
++ </reg32>
++
++ <reg32 offset="0xab01" name="SP_UNKNOWN_AB01" variants="A7XX-" usage="cmd"/>
++ <reg32 offset="0xab02" name="SP_UNKNOWN_AB02" variants="A7XX-" usage="cmd"/>
++
++ <reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
++ <reg32 offset="0xab05" name="SP_FS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
++
++ <array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit">
++ <reg64 offset="0" name="DESCRIPTOR" variants="A6XX">
++ <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
++ <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
++ </reg64>
++ </array>
++ <array offset="0xab0a" name="SP_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="rp_blit">
++ <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-">
++ <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
++ <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
++ </reg64>
++ </array>
++
++ <!--
++ Combined IBO state for 3d pipe, used for Image and SSBO write/atomic
++ instructions VS/HS/DS/GS/FS. See SP_CS_IBO_* for compute shaders.
++ -->
++ <reg64 offset="0xab1a" name="SP_IBO" type="address" align="16" usage="cmd"/>
++ <reg32 offset="0xab20" name="SP_IBO_COUNT" low="0" high="6" type="uint" usage="cmd"/>
++
++ <reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX-" usage="cmd"/>
++
++ <bitset name="a6xx_sp_2d_dst_format" inline="yes">
++ <bitfield name="NORM" pos="0" type="boolean"/>
++ <bitfield name="SINT" pos="1" type="boolean"/>
++ <bitfield name="UINT" pos="2" type="boolean"/>
++ <!-- looks like HW only cares about the base type of this format,
++ which matches the ifmt? -->
++ <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/>
++ <!-- set when ifmt is R2D_UNORM8_SRGB -->
++ <bitfield name="SRGB" pos="11" type="boolean"/>
++ <!-- some sort of channel mask, not sure what it is for -->
++ <bitfield name="MASK" low="12" high="15"/>
++ </bitset>
++
++ <reg32 offset="0xacc0" name="SP_2D_DST_FORMAT" type="a6xx_sp_2d_dst_format" variants="A6XX" usage="rp_blit"/>
++ <reg32 offset="0xa9bf" name="SP_2D_DST_FORMAT" type="a6xx_sp_2d_dst_format" variants="A7XX-" usage="rp_blit"/>
++
++ <reg32 offset="0xae00" name="SP_DBG_ECO_CNTL" usage="cmd"/>
++ <reg32 offset="0xae01" name="SP_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
++ <reg32 offset="0xae02" name="SP_NC_MODE_CNTL">
++ <!-- TODO: valid bits 0x3c3f, see kernel -->
++ </reg32>
++ <reg32 offset="0xae03" name="SP_CHICKEN_BITS" usage="cmd"/>
++ <reg32 offset="0xae04" name="SP_FLOAT_CNTL" usage="cmd">
++ <bitfield name="F16_NO_INF" pos="3" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0xae06" name="SP_UNKNOWN_AE06" variants="A7XX-" usage="cmd"/>
++ <reg32 offset="0xae08" name="SP_UNKNOWN_AE08" variants="A7XX-" usage="cmd"/>
++ <reg32 offset="0xae09" name="SP_UNKNOWN_AE09" variants="A7XX-" usage="cmd"/>
++ <reg32 offset="0xae0a" name="SP_UNKNOWN_AE0A" variants="A7XX-" usage="cmd"/>
++
++ <reg32 offset="0xae0f" name="SP_PERFCTR_ENABLE" usage="cmd">
++ <!-- some perfcntrs are affected by a per-stage enable bit
++ (PERF_SP_ALU_WORKING_CYCLES for example)
++ TODO: verify position of HS/DS/GS bits -->
++ <bitfield name="VS" pos="0" type="boolean"/>
++ <bitfield name="HS" pos="1" type="boolean"/>
++ <bitfield name="DS" pos="2" type="boolean"/>
++ <bitfield name="GS" pos="3" type="boolean"/>
++ <bitfield name="FS" pos="4" type="boolean"/>
++ <bitfield name="CS" pos="5" type="boolean"/>
++ </reg32>
++ <array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24"/>
++ <array offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6" variants="A7XX-"/>
++ <reg32 offset="0xae6a" name="SP_UNKNOWN_AE6A" variants="A7XX-" usage="cmd"/>
++ <reg32 offset="0xae6b" name="SP_UNKNOWN_AE6B" variants="A7XX-" usage="cmd"/>
++ <reg32 offset="0xae6c" name="SP_UNKNOWN_AE6C" variants="A7XX-" usage="cmd"/>
++ <reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX-">
++ <bitfield name="LOCATION" low="18" high="19" type="a7xx_state_location"/>
++ <bitfield name="PIPE" low="16" high="17" type="a7xx_pipe"/>
++ <bitfield name="STATETYPE" low="8" high="15" type="a7xx_statetype_id"/>
++ <bitfield name="USPTP" low="4" high="7"/>
++ <bitfield name="SPTP" low="0" high="3"/>
++ </reg32>
++ <reg32 offset="0xae71" name="SP_DBG_CNTL" variants="A7XX-"/>
++ <reg32 offset="0xae73" name="SP_UNKNOWN_AE73" variants="A7XX-" usage="cmd"/>
++ <array offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36" variants="A7XX-"/>
++ <!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) -->
++ <!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range -->
++ <reg32 offset="0xbe22" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
++
++ <!--
++ The downstream kernel calls the debug cluster of registers
++ "a6xx_sp_ps_tp_cluster" but this actually specifies the border
++ color base for compute shaders.
++ -->
++ <reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128" usage="cmd"/>
++ <reg32 offset="0xb182" name="SP_UNKNOWN_B182" low="0" high="2" usage="cmd"/>
++ <reg32 offset="0xb183" name="SP_UNKNOWN_B183" low="0" high="23" usage="cmd"/>
++
++ <reg32 offset="0xb190" name="SP_UNKNOWN_B190"/>
++ <reg32 offset="0xb191" name="SP_UNKNOWN_B191"/>
++
++ <!-- could be all the stuff below here is actually TPL1?? -->
++
++ <reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL" usage="rp_blit">
++ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
++ <bitfield name="UNK2" low="2" high="3"/>
++ </reg32>
++ <reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL" usage="rp_blit">
++ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
++ <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
++ </reg32>
++
++ <!-- looks to work in the same way as a5xx: -->
++ <reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128" usage="cmd"/>
++ <reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/>
++ <reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/>
++ <reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/>
++ <reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/>
++ <reg32 offset="0xb309" name="SP_TP_MODE_CNTL" usage="cmd">
++ <bitfield name="ISAMMODE" low="0" high="1" type="a6xx_isam_mode"/>
++ <bitfield name="UNK3" low="2" high="7"/>
++ </reg32>
++ <reg32 offset="0xb310" name="SP_UNKNOWN_B310" variants="A7XX-" usage="cmd"/>
++
++ <!--
++ Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either
++ badly named or the functionality moved in a6xx. But downstream kernel
++ calls this "a6xx_sp_ps_tp_2d_cluster"
++ -->
++ <reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info" variants="A6XX" usage="rp_blit"/>
++ <reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE" variants="A6XX" usage="rp_blit">
++ <bitfield name="WIDTH" low="0" high="14" type="uint"/>
++ <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
++ </reg32>
++ <reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="address" align="16" variants="A6XX" usage="rp_blit"/>
++ <reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH" variants="A6XX" usage="rp_blit">
++ <bitfield name="UNK0" low="0" high="8"/>
++ <bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0xb2c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info" variants="A7XX-" usage="rp_blit"/>
++ <reg32 offset="0xb2c1" name="SP_PS_2D_SRC_SIZE" variants="A7XX">
++ <bitfield name="WIDTH" low="0" high="14" type="uint"/>
++ <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
++ </reg32>
++ <reg64 offset="0xb2c2" name="SP_PS_2D_SRC" type="address" align="16" variants="A7XX-" usage="rp_blit"/>
++ <reg32 offset="0xb2c4" name="SP_PS_2D_SRC_PITCH" variants="A7XX">
++ <bitfield name="UNK0" low="0" high="8"/>
++ <bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/>
++ </reg32>
++
++ <!-- planes for NV12, etc. (TODO: not tested) -->
++ <reg64 offset="0xb4c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16" variants="A6XX"/>
++ <reg32 offset="0xb4c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" variants="A6XX"/>
++ <reg64 offset="0xb4c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16" variants="A6XX"/>
++
++ <reg64 offset="0xb2c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16" variants="A7XX-"/>
++ <reg32 offset="0xb2c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" variants="A7XX-"/>
++ <reg64 offset="0xb2c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16" variants="A7XX-"/>
++
++ <reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16" variants="A6XX" usage="rp_blit"/>
++ <reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" variants="A6XX" usage="rp_blit"/>
++
++ <reg64 offset="0xb2ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16" variants="A7XX-" usage="rp_blit"/>
++ <reg32 offset="0xb2cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" variants="A7XX-" usage="rp_blit"/>
++
++ <reg32 offset="0xb4cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A6XX"/>
++ <reg32 offset="0xb4ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A6XX"/>
++ <reg32 offset="0xb4cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A6XX"/>
++ <reg32 offset="0xb4d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A6XX"/>
++ <reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A6XX" usage="rp_blit"/>
++
++ <reg32 offset="0xb2cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A7XX"/>
++ <reg32 offset="0xb2ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A7XX"/>
++ <reg32 offset="0xb2cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A7XX"/>
++ <reg32 offset="0xb2d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A7XX"/>
++ <reg32 offset="0xb2d1" name="SP_PS_2D_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX"/>
++ <reg32 offset="0xb2d2" name="SP_PS_UNKNOWN_B2D2" variants="A7XX-" usage="rp_blit"/>
++ <reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-" usage="rp_blit"/>
++
++ <!-- always 0x100000 or 0x1000000? -->
++ <reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25" usage="cmd"/>
++ <reg32 offset="0xb601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++ <reg32 offset="0xb602" name="TPL1_UNKNOWN_B602" low="0" high="7" type="uint" usage="cmd"/>
++ <reg32 offset="0xb604" name="TPL1_NC_MODE_CNTL">
++ <bitfield name="MODE" pos="0" type="boolean"/>
++ <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>
++ <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
++ <bitfield name="UPPER_BIT" pos="4" type="uint"/>
++ <bitfield name="UNK6" low="6" high="7"/>
++ </reg32>
++ <reg32 offset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint" variants="A6XX" usage="cmd"/> <!-- always 0x0 or 0x44 ? -->
++
++ <reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A6XX"/>
++ <reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A6XX"/>
++ <reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A6XX"/>
++ <reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A6XX"/>
++ <reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A6XX"/>
++
++ <reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A7XX" usage="cmd"/>
++ <reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A7XX" usage="cmd"/>
++ <reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A7XX" usage="cmd"/>
++ <reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A7XX" usage="cmd"/>
++ <reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A7XX" usage="cmd"/>
++
++ <array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="12"/>
++
++ <!-- TODO: 4 more perfcntr sel at 0xb620 ? -->
++
++ <bitset name="a6xx_hlsq_xs_cntl" inline="yes">
++ <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/>
++ <bitfield name="ENABLED" pos="8" type="boolean"/>
++ <bitfield name="READ_IMM_SHARED_CONSTS" pos="9" type="boolean" variants="A7XX-"/>
++ </bitset>
++
++ <reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>
++ <reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>
++ <reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>
++ <reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>
++
++ <reg32 offset="0xa827" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>
++ <reg32 offset="0xa83f" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>
++ <reg32 offset="0xa867" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>
++ <reg32 offset="0xa898" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>
++
++ <reg32 offset="0xa9aa" name="HLSQ_FS_UNKNOWN_A9AA" variants="A7XX-" usage="rp_blit">
++ <!-- Tentatively named, appears to disable consts being loaded via CP_LOAD_STATE6_FRAG -->
++ <bitfield name="CONSTS_LOAD_DISABLE" pos="0" type="boolean"/>
++ </reg32>
++
++ <!-- Always 0 -->
++ <reg32 offset="0xa9ac" name="HLSQ_UNKNOWN_A9AC" variants="A7XX-" usage="cmd"/>
++
++ <!-- Used in VK_KHR_fragment_shading_rate -->
++ <reg32 offset="0xa9ad" name="HLSQ_UNKNOWN_A9AD" variants="A7XX-" usage="cmd"/>
++
++ <reg32 offset="0xa9ae" name="HLSQ_UNKNOWN_A9AE" variants="A7XX-" usage="rp_blit">
++ <bitfield name="SYSVAL_REGS_COUNT" low="0" high="7" type="uint"/>
++ <!-- UNK8 is set on a730/a740 -->
++ <bitfield name="UNK8" pos="8" type="boolean"/>
++ <!-- UNK9 is set on a750 -->
++ <bitfield name="UNK9" pos="9" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0xb820" name="HLSQ_LOAD_STATE_GEOM_CMD"/>
++ <reg64 offset="0xb821" name="HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR" align="16" type="address"/>
++ <reg32 offset="0xb823" name="HLSQ_LOAD_STATE_GEOM_DATA"/>
++
++
++ <bitset name="a6xx_hlsq_fs_cntl_0" inline="yes">
++ <!-- must match SP_FS_CTRL -->
++ <bitfield name="THREADSIZE" pos="0" type="a6xx_threadsize"/>
++ <bitfield name="VARYINGS" pos="1" type="boolean"/>
++ <bitfield name="UNK2" low="2" high="11"/>
++ </bitset>
++ <bitset name="a6xx_hlsq_control_3_reg" inline="yes">
++ <!-- register loaded with position (bary.f) -->
++ <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
++ </bitset>
++ <bitset name="a6xx_hlsq_control_4_reg" inline="yes">
++ <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
++ </bitset>
++ <bitset name="a6xx_hlsq_control_5_reg" inline="yes">
++ <bitfield name="LINELENGTHREGID" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="FOVEATIONQUALITYREGID" low="8" high="15" type="a3xx_regid"/>
++ </bitset>
++
++ <reg32 offset="0xb980" type="a6xx_hlsq_fs_cntl_0" name="HLSQ_FS_CNTL_0" variants="A6XX" usage="rp_blit"/>
++ <reg32 offset="0xb981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean" variants="A6XX"/> <!-- never used by blob -->
++ <reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A6XX" usage="rp_blit">
++ <!-- Sets the maximum number of primitives allowed in one FS wave minus one, similarly to the
++ A3xx field, except that it's not necessary to set it to anything but the maximum, since
++ the hardware will simply emit smaller waves when it runs out of space. -->
++ <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/>
++ </reg32>
++ <reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG" variants="A6XX" usage="rp_blit">
++ <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
++ <!-- SAMPLEID is loaded into a half-precision register: -->
++ <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0xb984" type="a6xx_hlsq_control_3_reg" name="HLSQ_CONTROL_3_REG" variants="A6XX" usage="rp_blit"/>
++ <reg32 offset="0xb985" type="a6xx_hlsq_control_4_reg" name="HLSQ_CONTROL_4_REG" variants="A6XX" usage="rp_blit"/>
++ <reg32 offset="0xb986" type="a6xx_hlsq_control_5_reg" name="HLSQ_CONTROL_5_REG" variants="A6XX" usage="rp_blit"/>
++ <reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="cmd"/>
++ <reg32 offset="0xa9c6" type="a6xx_hlsq_fs_cntl_0" name="HLSQ_FS_CNTL_0" variants="A7XX-" usage="rp_blit"/>
++ <reg32 offset="0xa9c7" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A7XX-" usage="rp_blit">
++ <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/>
++ </reg32>
++ <reg32 offset="0xa9c8" name="HLSQ_CONTROL_2_REG" variants="A7XX-" usage="rp_blit">
++ <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
++ <!-- SAMPLEID is loaded into a half-precision register: -->
++ <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0xa9c9" type="a6xx_hlsq_control_3_reg" name="HLSQ_CONTROL_3_REG" variants="A7XX-" usage="rp_blit"/>
++ <reg32 offset="0xa9ca" type="a6xx_hlsq_control_4_reg" name="HLSQ_CONTROL_4_REG" variants="A7XX-" usage="rp_blit"/>
++ <reg32 offset="0xa9cb" type="a6xx_hlsq_control_5_reg" name="HLSQ_CONTROL_5_REG" variants="A7XX-" usage="rp_blit"/>
++ <reg32 offset="0xa9cd" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="cmd"/>
++
++ <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) -->
++ <reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0" variants="A6XX" usage="rp_blit">
++ <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
++ <!-- localsize is value minus one: -->
++ <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
++ <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
++ <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1" variants="A6XX" usage="rp_blit">
++ <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2" variants="A6XX" usage="rp_blit">
++ <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3" variants="A6XX" usage="rp_blit">
++ <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4" variants="A6XX" usage="rp_blit">
++ <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5" variants="A6XX" usage="rp_blit">
++ <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6" variants="A6XX" usage="rp_blit">
++ <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xb997" name="HLSQ_CS_CNTL_0" variants="A6XX" usage="rp_blit">
++ <!-- these are all vec3. first 3 need to be high regs
++ WGSIZECONSTID is the local size (from HLSQ_CS_NDRANGE_0)
++ WGOFFSETCONSTID is WGIDCONSTID*WGSIZECONSTID
++ -->
++ <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
++ <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/>
++ <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/>
++ <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
++ </reg32>
++ <reg32 offset="0xb998" name="HLSQ_CS_CNTL_1" variants="A6XX" usage="rp_blit">
++ <!-- gl_LocalInvocationIndex -->
++ <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
++ <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only
++ one of those 6 "SP cores" -->
++ <bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/>
++ <!-- Must match SP_CS_CTRL -->
++ <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/>
++ <!-- 1 thread per wave (ignored if bit9 set) -->
++ <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/>
++ </reg32>
++ <!--note: vulkan blob doesn't use these -->
++ <reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X" variants="A6XX" usage="rp_blit"/>
++ <reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y" variants="A6XX" usage="rp_blit"/>
++ <reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z" variants="A6XX" usage="rp_blit"/>
++
++ <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) -->
++ <reg32 offset="0xa9d4" name="HLSQ_CS_NDRANGE_0" variants="A7XX-" usage="rp_blit">
++ <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
++ <!-- localsize is value minus one: -->
++ <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
++ <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
++ <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xa9d5" name="HLSQ_CS_NDRANGE_1" variants="A7XX-" usage="rp_blit">
++ <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xa9d6" name="HLSQ_CS_NDRANGE_2" variants="A7XX-" usage="rp_blit">
++ <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xa9d7" name="HLSQ_CS_NDRANGE_3" variants="A7XX-" usage="rp_blit">
++ <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xa9d8" name="HLSQ_CS_NDRANGE_4" variants="A7XX-" usage="rp_blit">
++ <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xa9d9" name="HLSQ_CS_NDRANGE_5" variants="A7XX-" usage="rp_blit">
++ <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0xa9da" name="HLSQ_CS_NDRANGE_6" variants="A7XX-" usage="rp_blit">
++ <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
++ </reg32>
++ <!--note: vulkan blob doesn't use these -->
++ <reg32 offset="0xa9dc" name="HLSQ_CS_KERNEL_GROUP_X" variants="A7XX-" usage="rp_blit"/>
++ <reg32 offset="0xa9dd" name="HLSQ_CS_KERNEL_GROUP_Y" variants="A7XX-" usage="rp_blit"/>
++ <reg32 offset="0xa9de" name="HLSQ_CS_KERNEL_GROUP_Z" variants="A7XX-" usage="rp_blit"/>
++
++ <enum name="a7xx_cs_yalign">
++ <value name="CS_YALIGN_1" value="8"/>
++ <value name="CS_YALIGN_2" value="4"/>
++ <value name="CS_YALIGN_4" value="2"/>
++ <value name="CS_YALIGN_8" value="1"/>
++ </enum>
++
++ <reg32 offset="0xa9db" name="HLSQ_CS_CNTL_1" variants="A7XX-" usage="rp_blit">
++ <!-- gl_LocalInvocationIndex -->
++ <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
++ <!-- Must match SP_CS_CTRL -->
++ <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/>
++ <bitfield name="UNK11" pos="11" type="boolean"/>
++ <bitfield name="UNK22" pos="22" type="boolean"/>
++ <bitfield name="UNK26" pos="26" type="boolean"/>
++ <bitfield name="YALIGN" low="27" high="30" type="a7xx_cs_yalign"/>
++ </reg32>
++
++ <reg32 offset="0xa9df" name="HLSQ_CS_LOCAL_SIZE" variants="A7XX-" usage="cmd">
++ <!-- localsize is value minus one: -->
++ <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
++ <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
++ <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0xb9a0" name="HLSQ_LOAD_STATE_FRAG_CMD"/>
++ <reg64 offset="0xb9a1" name="HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR" align="16" type="address"/>
++ <reg32 offset="0xb9a3" name="HLSQ_LOAD_STATE_FRAG_DATA"/>
++
++ <!-- mirror of SP_CS_BINDLESS_BASE -->
++ <array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit">
++ <reg64 offset="0" name="DESCRIPTOR">
++ <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
++ <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
++ </reg64>
++ </array>
++
++ <!-- new in a6xx gen4, mirror of SP_CS_UNKNOWN_A9B1? -->
++ <reg32 offset="0xb9d0" name="HLSQ_CS_UNKNOWN_B9D0" variants="A6XX" usage="cmd">
++ <bitfield name="SHARED_SIZE" low="0" high="4" type="uint"/>
++ <bitfield name="UNK5" pos="5" type="boolean"/>
++ <!-- always 1 ? -->
++ <bitfield name="UNK6" pos="6" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0xbb00" name="HLSQ_DRAW_CMD">
++ <bitfield name="STATE_ID" low="0" high="7"/>
++ </reg32>
++
++ <reg32 offset="0xbb01" name="HLSQ_DISPATCH_CMD">
++ <bitfield name="STATE_ID" low="0" high="7"/>
++ </reg32>
++
++ <reg32 offset="0xbb02" name="HLSQ_EVENT_CMD">
++ <!-- I think only the low bit is actually used? -->
++ <bitfield name="STATE_ID" low="16" high="23"/>
++ <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
++ </reg32>
++
++ <reg32 offset="0xbb08" name="HLSQ_INVALIDATE_CMD" variants="A6XX" usage="cmd">
++ <doc>
++ This register clears pending loads queued up by
++ CP_LOAD_STATE6. Each bit resets a particular kind(s) of
++ CP_LOAD_STATE6.
++ </doc>
++
++ <!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->
++ <bitfield name="VS_STATE" pos="0" type="boolean"/>
++ <bitfield name="HS_STATE" pos="1" type="boolean"/>
++ <bitfield name="DS_STATE" pos="2" type="boolean"/>
++ <bitfield name="GS_STATE" pos="3" type="boolean"/>
++ <bitfield name="FS_STATE" pos="4" type="boolean"/>
++ <bitfield name="CS_STATE" pos="5" type="boolean"/>
++
++ <bitfield name="CS_IBO" pos="6" type="boolean"/>
++ <bitfield name="GFX_IBO" pos="7" type="boolean"/>
++
++ <!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 -->
++ <bitfield name="CS_SHARED_CONST" pos="19" type="boolean"/>
++ <bitfield name="GFX_SHARED_CONST" pos="8" type="boolean"/>
++
++ <!-- SS6_BINDLESS: one bit per bindless base -->
++ <bitfield name="CS_BINDLESS" low="9" high="13" type="hex"/>
++ <bitfield name="GFX_BINDLESS" low="14" high="18" type="hex"/>
++ </reg32>
++
++ <reg32 offset="0xab1f" name="HLSQ_INVALIDATE_CMD" variants="A7XX-" usage="cmd">
++ <doc>
++ This register clears pending loads queued up by
++ CP_LOAD_STATE6. Each bit resets a particular kind(s) of
++ CP_LOAD_STATE6.
++ </doc>
++
++ <!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->
++ <bitfield name="VS_STATE" pos="0" type="boolean"/>
++ <bitfield name="HS_STATE" pos="1" type="boolean"/>
++ <bitfield name="DS_STATE" pos="2" type="boolean"/>
++ <bitfield name="GS_STATE" pos="3" type="boolean"/>
++ <bitfield name="FS_STATE" pos="4" type="boolean"/>
++ <bitfield name="CS_STATE" pos="5" type="boolean"/>
++
++ <bitfield name="CS_IBO" pos="6" type="boolean"/>
++ <bitfield name="GFX_IBO" pos="7" type="boolean"/>
++
++ <!-- SS6_BINDLESS: one bit per bindless base -->
++ <bitfield name="CS_BINDLESS" low="9" high="16" type="hex"/>
++ <bitfield name="GFX_BINDLESS" low="17" high="24" type="hex"/>
++ </reg32>
++
++ <reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>
++ <reg32 offset="0xab03" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>
++
++ <array offset="0xab40" name="HLSQ_SHARED_CONSTS_IMM" stride="1" length="64" variants="A7XX-"/>
++
++ <reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS" variants="A6XX" usage="cmd">
++ <doc>
++ Shared constants are intended to be used for Vulkan push
++ constants. When enabled, 8 vec4's are reserved in the FS
++ const pool and 16 in the geometry const pool although
++ only 8 are actually used (why?) and they are mapped to
++ c504-c511 in each stage. Both VS and FS shared consts
++ are written using ST6_CONSTANTS/SB6_IBO, so that both
++ the geometry and FS shared consts can be written at once
++ by using CP_LOAD_STATE6 rather than
++ CP_LOAD_STATE6_FRAG/CP_LOAD_STATE6_GEOM. In addition
++ DST_OFF and NUM_UNIT are in units of dwords instead of
++ vec4's.
++
++ There is also a separate shared constant pool for CS,
++ which is loaded through CP_LOAD_STATE6_FRAG with
++ ST6_UBO/ST6_IBO. However the only real difference for CS
++ is the dword units.
++ </doc>
++ <bitfield name="ENABLE" pos="0" type="boolean"/>
++ </reg32>
++
++ <!-- mirror of SP_BINDLESS_BASE -->
++ <array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="cmd">
++ <reg64 offset="0" name="DESCRIPTOR">
++ <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
++ <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
++ </reg64>
++ </array>
++
++ <reg32 offset="0xbd80" name="HLSQ_2D_EVENT_CMD">
++ <bitfield name="STATE_ID" low="8" high="15"/>
++ <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
++ </reg32>
++
++ <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00" variants="A6XX" usage="cmd"/> <!-- all bits valid except bit 29 -->
++ <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01" low="4" high="6" variants="A6XX" usage="cmd"/>
++ <reg32 offset="0xbe04" name="HLSQ_DBG_ECO_CNTL" variants="A6XX" usage="cmd"/>
++ <reg32 offset="0xbe05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
++ <reg32 offset="0xbe08" name="HLSQ_UNKNOWN_BE08" low="0" high="15"/>
++ <array offset="0xbe10" name="HLSQ_PERFCTR_HLSQ_SEL" stride="1" length="6"/>
++
++ <!-- TODO: some valid registers between 0xbe20 and 0xbe33 -->
++ <reg32 offset="0xbe22" name="HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
++
++ <reg32 offset="0xc000" name="SP_AHB_READ_APERTURE" variants="A7XX-"/>
++
++ <!-- Don't know if these are SP, always 0 -->
++ <reg64 offset="0x0ce2" name="SP_UNKNOWN_0CE2" variants="A7XX-" usage="cmd"/>
++ <reg64 offset="0x0ce4" name="SP_UNKNOWN_0CE4" variants="A7XX-" usage="cmd"/>
++ <reg64 offset="0x0ce6" name="SP_UNKNOWN_0CE6" variants="A7XX-" usage="cmd"/>
++
++ <!--
++ These special registers signal the beginning/end of an event
++ sequence. The sequence used internally for an event looks like:
++ - write EVENT_CMD pipe register
++ - write CP_EVENT_START
++ - write HLSQ_EVENT_CMD with event or HLSQ_DRAW_CMD
++ - write PC_EVENT_CMD with event or PC_DRAW_CMD
++ - write HLSQ_EVENT_CMD(CONTEXT_DONE)
++ - write PC_EVENT_CMD(CONTEXT_DONE)
++ - write CP_EVENT_END
++ Writing to CP_EVENT_END seems to actually trigger the context roll
++ -->
++ <reg32 offset="0xd600" name="CP_EVENT_START">
++ <bitfield name="STATE_ID" low="0" high="7"/>
++ </reg32>
++ <reg32 offset="0xd601" name="CP_EVENT_END">
++ <bitfield name="STATE_ID" low="0" high="7"/>
++ </reg32>
++ <reg32 offset="0xd700" name="CP_2D_EVENT_START">
++ <bitfield name="STATE_ID" low="0" high="7"/>
++ </reg32>
++ <reg32 offset="0xd701" name="CP_2D_EVENT_END">
++ <bitfield name="STATE_ID" low="0" high="7"/>
++ </reg32>
++</domain>
++
++<!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
++<domain name="A6XX_TEX_SAMP" width="32">
++ <doc>Texture sampler dwords</doc>
++ <enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
++ <value name="A6XX_TEX_NEAREST" value="0"/>
++ <value name="A6XX_TEX_LINEAR" value="1"/>
++ <value name="A6XX_TEX_ANISO" value="2"/>
++ <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->
++ </enum>
++ <enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
++ <value name="A6XX_TEX_REPEAT" value="0"/>
++ <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/>
++ <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/>
++ <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/>
++ <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/>
++ </enum>
++ <enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
++ <value name="A6XX_TEX_ANISO_1" value="0"/>
++ <value name="A6XX_TEX_ANISO_2" value="1"/>
++ <value name="A6XX_TEX_ANISO_4" value="2"/>
++ <value name="A6XX_TEX_ANISO_8" value="3"/>
++ <value name="A6XX_TEX_ANISO_16" value="4"/>
++ </enum>
++ <enum name="a6xx_reduction_mode">
++ <value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/>
++ <value name="A6XX_REDUCTION_MODE_MIN" value="1"/>
++ <value name="A6XX_REDUCTION_MODE_MAX" value="2"/>
++ </enum>
++
++ <reg32 offset="0" name="0">
++ <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
++ <bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/>
++ <bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/>
++ <bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/>
++ <bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/>
++ <bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/>
++ <bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/>
++ <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="CLAMPENABLE" pos="0" type="boolean">
++ <doc>
++ clamp result to [0, 1] if the format is unorm or
++ [-1, 1] if the format is snorm, *after*
++ filtering. Has no effect for other formats.
++ </doc>
++ </bitfield>
++ <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
++ <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
++ <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
++ <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
++ <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
++ <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/>
++ <bitfield name="CHROMA_LINEAR" pos="5" type="boolean"/>
++ <bitfield name="BCOLOR" low="7" high="31"/>
++ </reg32>
++ <reg32 offset="3" name="3"/>
++</domain>
++
++<domain name="A6XX_TEX_CONST" width="32">
++ <doc>Texture constant dwords</doc>
++ <enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
++ <value name="A6XX_TEX_X" value="0"/>
++ <value name="A6XX_TEX_Y" value="1"/>
++ <value name="A6XX_TEX_Z" value="2"/>
++ <value name="A6XX_TEX_W" value="3"/>
++ <value name="A6XX_TEX_ZERO" value="4"/>
++ <value name="A6XX_TEX_ONE" value="5"/>
++ </enum>
++ <enum name="a6xx_tex_type"> <!-- same as a4xx? -->
++ <value name="A6XX_TEX_1D" value="0"/>
++ <value name="A6XX_TEX_2D" value="1"/>
++ <value name="A6XX_TEX_CUBE" value="2"/>
++ <value name="A6XX_TEX_3D" value="3"/>
++ <value name="A6XX_TEX_BUFFER" value="4"/>
++ </enum>
++ <reg32 offset="0" name="0">
++ <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
++ <bitfield name="SRGB" pos="2" type="boolean"/>
++ <bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/>
++ <bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/>
++ <bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/>
++ <bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/>
++ <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
++ <!-- overlaps with MIPLVLS -->
++ <bitfield name="CHROMA_MIDPOINT_X" pos="16" type="boolean"/>
++ <bitfield name="CHROMA_MIDPOINT_Y" pos="18" type="boolean"/>
++ <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
++ <bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
++ <!--
++ Why is the swap needed in addition to SWIZ_*? The swap
++ is performed before border color replacement, while the
++ swizzle is applied after after it.
++ -->
++ <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="WIDTH" low="0" high="14" type="uint"/>
++ <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
++ </reg32>
++ <reg32 offset="2" name="2">
++ <!--
++ These fields overlap PITCH, and are used instead of
++ PITCH/PITCHALIGN when TYPE is A6XX_TEX_BUFFER.
++ -->
++ <doc> probably for D3D structured UAVs, normally set to 1 </doc>
++ <bitfield name="STRUCTSIZETEXELS" low="4" high="15" type="uint"/>
++ <bitfield name="STARTOFFSETTEXELS" low="16" high="21" type="uint"/>
++
++ <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
++ <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
++ <doc>Pitch in bytes (so actually stride)</doc>
++ <bitfield name="PITCH" low="7" high="28" type="uint"/>
++ <bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/>
++ </reg32>
++ <reg32 offset="3" name="3">
++ <!--
++ ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
++ for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
++ layer size at the point that it stops being reduced moving to
++ higher (smaller) mipmap levels
++ -->
++ <bitfield name="ARRAY_PITCH" low="0" high="22" shr="12" type="uint"/>
++ <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
++ <!--
++ by default levels with w < 16 are linear
++ TILE_ALL makes all levels have tiling
++ seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
++ -->
++ <bitfield name="TILE_ALL" pos="27" type="boolean"/>
++ <bitfield name="FLAG" pos="28" type="boolean"/>
++ </reg32>
++ <!-- for 2-3 plane format, BASE is flag buffer address (if enabled)
++ the address of the non-flag base buffer is determined automatically,
++ and must follow the flag buffer
++ -->
++ <reg32 offset="4" name="4">
++ <bitfield name="BASE_LO" low="5" high="31" shr="5"/>
++ </reg32>
++ <reg32 offset="5" name="5">
++ <bitfield name="BASE_HI" low="0" high="16"/>
++ <bitfield name="DEPTH" low="17" high="29" type="uint"/>
++ </reg32>
++ <reg32 offset="6" name="6">
++ <!-- overlaps with PLANE_PITCH -->
++ <bitfield name="MIN_LOD_CLAMP" low="0" high="11" type="ufixed" radix="8"/>
++ <!-- pitch for plane 2 / plane 3 -->
++ <bitfield name="PLANE_PITCH" low="8" high="31" type="uint"/>
++ </reg32>
++ <!-- 7/8 is plane 2 address for planar formats -->
++ <reg32 offset="7" name="7">
++ <bitfield name="FLAG_LO" low="5" high="31" shr="5"/>
++ </reg32>
++ <reg32 offset="8" name="8">
++ <bitfield name="FLAG_HI" low="0" high="16"/>
++ </reg32>
++ <!-- 9/10 is plane 3 address for planar formats -->
++ <reg32 offset="9" name="9">
++ <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
++ </reg32>
++ <reg32 offset="10" name="10">
++ <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
++ <!-- log2 size of the first level, required for mipmapping -->
++ <bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/>
++ <bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/>
++ </reg32>
++ <reg32 offset="11" name="11"/>
++ <reg32 offset="12" name="12"/>
++ <reg32 offset="13" name="13"/>
++ <reg32 offset="14" name="14"/>
++ <reg32 offset="15" name="15"/>
++</domain>
++
++<domain name="A6XX_UBO" width="32">
++ <reg32 offset="0" name="0">
++ <bitfield name="BASE_LO" low="0" high="31"/>
++ </reg32>
++ <reg32 offset="1" name="1">
++ <bitfield name="BASE_HI" low="0" high="16"/>
++ <bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units -->
++ </reg32>
++</domain>
++
++<domain name="A6XX_PDC" width="32">
++ <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/>
++ <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/>
++ <reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/>
++ <reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/>
++ <reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/>
++ <reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/>
++ <reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/>
++ <reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/>
++ <reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/>
++ <reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/>
++ <reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/>
++ <reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/>
++ <reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/>
++ <reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/>
++ <reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/>
++ <reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/>
++ <reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/>
++ <reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/>
++ <reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/>
++ <reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/>
++ <reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/>
++ <reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/>
++ <reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/>
++ <reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/>
++ <reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/>
++ <reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/>
++</domain>
++
++<domain name="A6XX_PDC_GPU_SEQ" width="32">
++ <reg32 offset="0x0" name="MEM_0"/>
++</domain>
++
++<domain name="A6XX_CX_DBGC" width="32">
++ <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A">
++ <bitfield high="7" low="0" name="PING_INDEX"/>
++ <bitfield high="15" low="8" name="PING_BLK_SEL"/>
++ </reg32>
++ <reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/>
++ <reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/>
++ <reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/>
++ <reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT">
++ <bitfield high="5" low="0" name="TRACEEN"/>
++ <bitfield high="14" low="12" name="GRANU"/>
++ <bitfield high="31" low="28" name="SEGT"/>
++ </reg32>
++ <reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM">
++ <bitfield high="27" low="24" name="ENABLE"/>
++ </reg32>
++ <reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/>
++ <reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/>
++ <reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/>
++ <reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/>
++ <reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/>
++ <reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/>
++ <reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/>
++ <reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/>
++ <reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0">
++ <bitfield high="3" low="0" name="BYTEL0"/>
++ <bitfield high="7" low="4" name="BYTEL1"/>
++ <bitfield high="11" low="8" name="BYTEL2"/>
++ <bitfield high="15" low="12" name="BYTEL3"/>
++ <bitfield high="19" low="16" name="BYTEL4"/>
++ <bitfield high="23" low="20" name="BYTEL5"/>
++ <bitfield high="27" low="24" name="BYTEL6"/>
++ <bitfield high="31" low="28" name="BYTEL7"/>
++ </reg32>
++ <reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1">
++ <bitfield high="3" low="0" name="BYTEL8"/>
++ <bitfield high="7" low="4" name="BYTEL9"/>
++ <bitfield high="11" low="8" name="BYTEL10"/>
++ <bitfield high="15" low="12" name="BYTEL11"/>
++ <bitfield high="19" low="16" name="BYTEL12"/>
++ <bitfield high="23" low="20" name="BYTEL13"/>
++ <bitfield high="27" low="24" name="BYTEL14"/>
++ <bitfield high="31" low="28" name="BYTEL15"/>
++ </reg32>
++
++ <reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/>
++ <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>
++</domain>
++
++<domain name="A6XX_CX_MISC" width="32" prefix="variant" varset="chip">
++ <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
++ <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
++ <reg32 offset="0x0039" name="CX_MISC_TCM_RET_CNTL" variants="A7XX-"/>
++</domain>
++
++</database>
+diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
+new file mode 100644
+index 0000000000000..6531749d30f4e
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
+@@ -0,0 +1,228 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++<import file="adreno/adreno_common.xml"/>
++
++<domain name="A6XX" width="32" prefix="variant" varset="chip">
++
++ <bitset name="A6XX_GMU_GPU_IDLE_STATUS">
++ <bitfield name="BUSY_IGN_AHB" pos="23"/>
++ <bitfield name="CX_GX_CPU_BUSY_IGN_AHB" pos="30"/>
++ </bitset>
++
++ <bitset name="A6XX_GMU_OOB">
++ <bitfield name="BOOT_SLUMBER_SET_MASK" pos="22"/>
++ <bitfield name="BOOT_SLUMBER_CHECK_MASK" pos="30"/>
++ <bitfield name="BOOT_SLUMBER_CLEAR_MASK" pos="30"/>
++ <bitfield name="DCVS_SET_MASK" pos="23"/>
++ <bitfield name="DCVS_CHECK_MASK" pos="31"/>
++ <bitfield name="DCVS_CLEAR_MASK" pos="31"/>
++ <bitfield name="GPU_SET_MASK" pos="18"/>
++ <bitfield name="GPU_CHECK_MASK" pos="26"/>
++ <bitfield name="GPU_CLEAR_MASK" pos="26"/>
++ <bitfield name="PERFCNTR_SET_MASK" pos="17"/>
++ <bitfield name="PERFCNTR_CHECK_MASK" pos="25"/>
++ <bitfield name="PERFCNTR_CLEAR_MASK" pos="25"/>
++ </bitset>
++
++ <bitset name="A6XX_HFI_IRQ">
++ <bitfield name="MSGQ_MASK" pos="0" />
++ <bitfield name="DSGQ_MASK" pos="1"/>
++ <bitfield name="BLOCKED_MSG_MASK" pos="2"/>
++ <bitfield name="CM3_FAULT_MASK" pos="23"/>
++ <bitfield name="GMU_ERR_MASK" low="16" high="22"/>
++ <bitfield name="OOB_MASK" low="24" high="31"/>
++ </bitset>
++
++ <bitset name="A6XX_HFI_H2F">
++ <bitfield name="IRQ_MASK_BIT" pos="0" />
++ </bitset>
++
++ <reg32 offset="0x80" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/>
++ <reg32 offset="0x81" name="GMU_GX_SPTPRAC_POWER_CONTROL"/>
++ <reg32 offset="0xc00" name="GMU_CM3_ITCM_START"/>
++ <reg32 offset="0x1c00" name="GMU_CM3_DTCM_START"/>
++ <reg32 offset="0x23f0" name="GMU_NMI_CONTROL_STATUS"/>
++ <reg32 offset="0x23f8" name="GMU_BOOT_SLUMBER_OPTION"/>
++ <reg32 offset="0x23f9" name="GMU_GX_VOTE_IDX"/>
++ <reg32 offset="0x23fa" name="GMU_MX_VOTE_IDX"/>
++ <reg32 offset="0x23fc" name="GMU_DCVS_ACK_OPTION"/>
++ <reg32 offset="0x23fd" name="GMU_DCVS_PERF_SETTING"/>
++ <reg32 offset="0x23fe" name="GMU_DCVS_BW_SETTING"/>
++ <reg32 offset="0x23ff" name="GMU_DCVS_RETURN"/>
++ <reg32 offset="0x4c00" name="GMU_ICACHE_CONFIG"/>
++ <reg32 offset="0x4c01" name="GMU_DCACHE_CONFIG"/>
++ <reg32 offset="0x4c0f" name="GMU_SYS_BUS_CONFIG"/>
++ <reg32 offset="0x5000" name="GMU_CM3_SYSRESET"/>
++ <reg32 offset="0x5001" name="GMU_CM3_BOOT_CONFIG"/>
++ <reg32 offset="0x501a" name="GMU_CM3_FW_BUSY"/>
++ <reg32 offset="0x501c" name="GMU_CM3_FW_INIT_RESULT"/>
++ <reg32 offset="0x502d" name="GMU_CM3_CFG"/>
++ <reg32 offset="0x5040" name="GMU_CX_GMU_POWER_COUNTER_ENABLE"/>
++ <reg32 offset="0x5041" name="GMU_CX_GMU_POWER_COUNTER_SELECT_0"/>
++ <reg32 offset="0x5042" name="GMU_CX_GMU_POWER_COUNTER_SELECT_1"/>
++ <reg32 offset="0x5044" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L"/>
++ <reg32 offset="0x5045" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H"/>
++ <reg32 offset="0x5046" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L"/>
++ <reg32 offset="0x5047" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H"/>
++ <reg32 offset="0x5048" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L"/>
++ <reg32 offset="0x5049" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H"/>
++ <reg32 offset="0x504a" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L"/>
++ <reg32 offset="0x504b" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H"/>
++ <reg32 offset="0x504c" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L"/>
++ <reg32 offset="0x504d" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H"/>
++ <reg32 offset="0x504e" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L"/>
++ <reg32 offset="0x504f" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H"/>
++ <reg32 offset="0x50c0" name="GMU_PWR_COL_INTER_FRAME_CTRL">
++ <bitfield name="IFPC_ENABLE" pos="0" type="boolean"/>
++ <bitfield name="HM_POWER_COLLAPSE_ENABLE" pos="1" type="boolean"/>
++ <bitfield name="SPTPRAC_POWER_CONTROL_ENABLE" pos="2" type="boolean"/>
++ <bitfield name="NUM_PASS_SKIPS" low="10" high="13"/>
++ <bitfield name="MIN_PASS_LENGTH" low="14" high="31"/>
++ </reg32>
++ <reg32 offset="0x50c1" name="GMU_PWR_COL_INTER_FRAME_HYST"/>
++ <reg32 offset="0x50c2" name="GMU_PWR_COL_SPTPRAC_HYST"/>
++ <reg32 offset="0x50d0" name="GMU_SPTPRAC_PWR_CLK_STATUS">
++ <bitfield name="SPTPRAC_GDSC_POWERING_OFF" pos="0" type="boolean"/>
++ <bitfield name="SPTPRAC_GDSC_POWERING_ON" pos="1" type="boolean"/>
++ <bitfield name="SPTPRAC_GDSC_POWER_OFF" pos="2" type="boolean"/>
++ <bitfield name="SPTPRAC_GDSC_POWER_ON" pos="3" type="boolean"/>
++ <bitfield name="SP_CLOCK_OFF" pos="4" type="boolean"/>
++ <bitfield name="GMU_UP_POWER_STATE" pos="5" type="boolean"/>
++ <bitfield name="GX_HM_GDSC_POWER_OFF" pos="6" type="boolean"/>
++ <bitfield name="GX_HM_CLK_OFF" pos="7" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x50e4" name="GMU_GPU_NAP_CTRL">
++ <bitfield name="HW_NAP_ENABLE" pos="0"/>
++ <bitfield name="SID" low="4" high="8"/>
++ </reg32>
++ <reg32 offset="0x50e8" name="GMU_RPMH_CTRL">
++ <bitfield name="RPMH_INTERFACE_ENABLE" pos="0" type="boolean"/>
++ <bitfield name="LLC_VOTE_ENABLE" pos="4" type="boolean"/>
++ <bitfield name="DDR_VOTE_ENABLE" pos="8" type="boolean"/>
++ <bitfield name="MX_VOTE_ENABLE" pos="9" type="boolean"/>
++ <bitfield name="CX_VOTE_ENABLE" pos="10" type="boolean"/>
++ <bitfield name="GFX_VOTE_ENABLE" pos="11" type="boolean"/>
++ <bitfield name="DDR_MIN_VOTE_ENABLE" pos="12" type="boolean"/>
++ <bitfield name="MX_MIN_VOTE_ENABLE" pos="13" type="boolean"/>
++ <bitfield name="CX_MIN_VOTE_ENABLE" pos="14" type="boolean"/>
++ <bitfield name="GFX_MIN_VOTE_ENABLE" pos="15" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x50e9" name="GMU_RPMH_HYST_CTRL"/>
++ <reg32 offset="0x50ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE"/>
++ <reg32 offset="0x50f0" name="GPU_GMU_CX_GMU_CX_FAL_INTF"/>
++ <reg32 offset="0x50f1" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF"/>
++ <reg32 offset="0x5100" name="GPU_GMU_CX_GMU_PWR_COL_CP_MSG"/>
++ <reg32 offset="0x5101" name="GPU_GMU_CX_GMU_PWR_COL_CP_RESP"/>
++ <reg32 offset="0x51f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/>
++ <reg32 offset="0x5157" name="GMU_LLM_GLM_SLEEP_CTRL"/>
++ <reg32 offset="0x5158" name="GMU_LLM_GLM_SLEEP_STATUS"/>
++ <reg32 offset="0x5088" name="GMU_ALWAYS_ON_COUNTER_L"/>
++ <reg32 offset="0x5089" name="GMU_ALWAYS_ON_COUNTER_H"/>
++ <reg32 offset="0x50c3" name="GMU_GMU_PWR_COL_KEEPALIVE"/>
++ <reg32 offset="0x5180" name="GMU_HFI_CTRL_STATUS"/>
++ <reg32 offset="0x5181" name="GMU_HFI_VERSION_INFO"/>
++ <reg32 offset="0x5182" name="GMU_HFI_SFR_ADDR"/>
++ <reg32 offset="0x5183" name="GMU_HFI_MMAP_ADDR"/>
++ <reg32 offset="0x5184" name="GMU_HFI_QTBL_INFO"/>
++ <reg32 offset="0x5185" name="GMU_HFI_QTBL_ADDR"/>
++ <reg32 offset="0x5186" name="GMU_HFI_CTRL_INIT"/>
++ <reg32 offset="0x5190" name="GMU_GMU2HOST_INTR_SET"/>
++ <reg32 offset="0x5191" name="GMU_GMU2HOST_INTR_CLR"/>
++ <reg32 offset="0x5192" name="GMU_GMU2HOST_INTR_INFO">
++ <bitfield name="MSGQ" pos="0" type="boolean"/>
++ <bitfield name="CM3_FAULT" pos="23" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x5193" name="GMU_GMU2HOST_INTR_MASK"/>
++ <reg32 offset="0x5194" name="GMU_HOST2GMU_INTR_SET"/>
++ <reg32 offset="0x5195" name="GMU_HOST2GMU_INTR_CLR"/>
++ <reg32 offset="0x5196" name="GMU_HOST2GMU_INTR_RAW_INFO"/>
++ <reg32 offset="0x5197" name="GMU_HOST2GMU_INTR_EN_0"/>
++ <reg32 offset="0x5198" name="GMU_HOST2GMU_INTR_EN_1"/>
++ <reg32 offset="0x5199" name="GMU_HOST2GMU_INTR_EN_2"/>
++ <reg32 offset="0x519a" name="GMU_HOST2GMU_INTR_EN_3"/>
++ <reg32 offset="0x519b" name="GMU_HOST2GMU_INTR_INFO_0"/>
++ <reg32 offset="0x519c" name="GMU_HOST2GMU_INTR_INFO_1"/>
++ <reg32 offset="0x519d" name="GMU_HOST2GMU_INTR_INFO_2"/>
++ <reg32 offset="0x519e" name="GMU_HOST2GMU_INTR_INFO_3"/>
++ <reg32 offset="0x51c5" name="GMU_GENERAL_0"/>
++ <reg32 offset="0x51c6" name="GMU_GENERAL_1"/>
++ <reg32 offset="0x51cb" name="GMU_GENERAL_6"/>
++ <reg32 offset="0x51cc" name="GMU_GENERAL_7"/>
++ <reg32 offset="0x51cd" name="GMU_GENERAL_8" variants="A7XX"/>
++ <reg32 offset="0x51ce" name="GMU_GENERAL_9" variants="A7XX"/>
++ <reg32 offset="0x51cf" name="GMU_GENERAL_10" variants="A7XX"/>
++ <reg32 offset="0x515d" name="GMU_ISENSE_CTRL"/>
++ <reg32 offset="0x8920" name="GPU_CS_ENABLE_REG"/>
++ <reg32 offset="0x515d" name="GPU_GMU_CX_GMU_ISENSE_CTRL"/>
++ <reg32 offset="0x8578" name="GPU_CS_AMP_CALIBRATION_CONTROL3"/>
++ <reg32 offset="0x8558" name="GPU_CS_AMP_CALIBRATION_CONTROL2"/>
++ <reg32 offset="0x8580" name="GPU_CS_A_SENSOR_CTRL_0"/>
++ <reg32 offset="0x27ada" name="GPU_CS_A_SENSOR_CTRL_2"/>
++ <reg32 offset="0x881a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
++ <reg32 offset="0x8957" name="GPU_CS_AMP_CALIBRATION_CONTROL1"/>
++ <reg32 offset="0x881a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
++ <reg32 offset="0x881d" name="GPU_CS_AMP_CALIBRATION_STATUS1_0"/>
++ <reg32 offset="0x881f" name="GPU_CS_AMP_CALIBRATION_STATUS1_2"/>
++ <reg32 offset="0x8821" name="GPU_CS_AMP_CALIBRATION_STATUS1_4"/>
++ <reg32 offset="0x8965" name="GPU_CS_AMP_CALIBRATION_DONE"/>
++ <reg32 offset="0x896d" name="GPU_CS_AMP_PERIOD_CTRL"/>
++ <reg32 offset="0x8965" name="GPU_CS_AMP_CALIBRATION_DONE"/>
++ <reg32 offset="0x514d" name="GPU_GMU_CX_GMU_PWR_THRESHOLD"/>
++ <reg32 offset="0x9303" name="GMU_AO_INTERRUPT_EN"/>
++ <reg32 offset="0x9304" name="GMU_AO_HOST_INTERRUPT_CLR"/>
++ <reg32 offset="0x9305" name="GMU_AO_HOST_INTERRUPT_STATUS">
++ <bitfield name="WDOG_BITE" pos="0" type="boolean"/>
++ <bitfield name="RSCC_COMP" pos="1" type="boolean"/>
++ <bitfield name="VDROOP" pos="2" type="boolean"/>
++ <bitfield name="FENCE_ERR" pos="3" type="boolean"/>
++ <bitfield name="DBD_WAKEUP" pos="4" type="boolean"/>
++ <bitfield name="HOST_AHB_BUS_ERROR" pos="5" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x9306" name="GMU_AO_HOST_INTERRUPT_MASK"/>
++ <reg32 offset="0x9309" name="GPU_GMU_AO_GMU_CGC_MODE_CNTL"/>
++ <reg32 offset="0x930a" name="GPU_GMU_AO_GMU_CGC_DELAY_CNTL"/>
++ <reg32 offset="0x930b" name="GPU_GMU_AO_GMU_CGC_HYST_CNTL"/>
++ <reg32 offset="0x930c" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS">
++ <bitfield name = "GPUBUSYIGNAHB" pos="23" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x930d" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS2"/>
++ <reg32 offset="0x930e" name="GPU_GMU_AO_GPU_CX_BUSY_MASK"/>
++ <reg32 offset="0x9310" name="GMU_AO_AHB_FENCE_CTRL"/>
++ <reg32 offset="0x9313" name="GMU_AHB_FENCE_STATUS"/>
++ <reg32 offset="0x9314" name="GMU_AHB_FENCE_STATUS_CLR"/>
++ <reg32 offset="0x9315" name="GMU_RBBM_INT_UNMASKED_STATUS"/>
++ <reg32 offset="0x9316" name="GMU_AO_SPARE_CNTL"/>
++ <reg32 offset="0x9307" name="GMU_RSCC_CONTROL_REQ"/>
++ <reg32 offset="0x9308" name="GMU_RSCC_CONTROL_ACK"/>
++ <reg32 offset="0x9311" name="GMU_AHB_FENCE_RANGE_0"/>
++ <reg32 offset="0x9312" name="GMU_AHB_FENCE_RANGE_1"/>
++ <reg32 offset="0x9c03" name="GPU_CC_GX_GDSCR"/>
++ <reg32 offset="0x9d42" name="GPU_CC_GX_DOMAIN_MISC"/>
++ <reg32 offset="0xc001" name="GPU_CPR_FSM_CTL"/>
++
++ <!-- starts at offset 0x8c00 on most gpus -->
++ <reg32 offset="0x0004" name="GPU_RSCC_RSC_STATUS0_DRV0"/>
++ <reg32 offset="0x0008" name="RSCC_PDC_SEQ_START_ADDR"/>
++ <reg32 offset="0x0009" name="RSCC_PDC_MATCH_VALUE_LO"/>
++ <reg32 offset="0x000a" name="RSCC_PDC_MATCH_VALUE_HI"/>
++ <reg32 offset="0x000b" name="RSCC_PDC_SLAVE_ID_DRV0"/>
++ <reg32 offset="0x000d" name="RSCC_HIDDEN_TCS_CMD0_ADDR"/>
++ <reg32 offset="0x000e" name="RSCC_HIDDEN_TCS_CMD0_DATA"/>
++ <reg32 offset="0x0082" name="RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0"/>
++ <reg32 offset="0x0083" name="RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0"/>
++ <reg32 offset="0x0089" name="RSCC_TIMESTAMP_UNIT1_EN_DRV0"/>
++ <reg32 offset="0x008c" name="RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0"/>
++ <reg32 offset="0x0100" name="RSCC_OVERRIDE_START_ADDR"/>
++ <reg32 offset="0x0101" name="RSCC_SEQ_BUSY_DRV0"/>
++ <reg32 offset="0x0154" name="RSCC_SEQ_MEM_0_DRV0_A740" variants="A7XX"/>
++ <reg32 offset="0x0180" name="RSCC_SEQ_MEM_0_DRV0"/>
++ <reg32 offset="0x0346" name="RSCC_TCS0_DRV0_STATUS"/>
++ <reg32 offset="0x03ee" name="RSCC_TCS1_DRV0_STATUS"/>
++ <reg32 offset="0x0496" name="RSCC_TCS2_DRV0_STATUS"/>
++ <reg32 offset="0x053e" name="RSCC_TCS3_DRV0_STATUS"/>
++</domain>
++
++</database>
+--
+2.39.5
+
--- /dev/null
+From 0a6417c7664e2a0656c9a009deaaa9da71ba60be Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 1 Apr 2024 05:42:40 +0300
+Subject: drm/msm: import gen_header.py script from Mesa
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 5acf49119630a463b4f6daa4b96344f87453d46d ]
+
+Import the gen_headers.py script from Mesa, commit b5414e716684
+("freedreno/registers: Add license header"). This script will be used to
+generate MSM register files on the fly during compilation.
+
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Patchwork: https://patchwork.freedesktop.org/patch/585864/
+Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-10-4bdb277a85a1@linaro.org
+Stable-dep-of: 588257897058 ("drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG0 updated from driver side")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/registers/gen_header.py | 961 ++++++++++++++++++++
+ 1 file changed, 961 insertions(+)
+ create mode 100644 drivers/gpu/drm/msm/registers/gen_header.py
+
+diff --git a/drivers/gpu/drm/msm/registers/gen_header.py b/drivers/gpu/drm/msm/registers/gen_header.py
+new file mode 100644
+index 0000000000000..9b2842d4a354f
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/gen_header.py
+@@ -0,0 +1,961 @@
++#!/usr/bin/python3
++#
++# Copyright © 2019-2024 Google, Inc.
++#
++# SPDX-License-Identifier: MIT
++
++import xml.parsers.expat
++import sys
++import os
++import collections
++import argparse
++import time
++import datetime
++
++class Error(Exception):
++ def __init__(self, message):
++ self.message = message
++
++class Enum(object):
++ def __init__(self, name):
++ self.name = name
++ self.values = []
++
++ def has_name(self, name):
++ for (n, value) in self.values:
++ if n == name:
++ return True
++ return False
++
++ def names(self):
++ return [n for (n, value) in self.values]
++
++ def dump(self):
++ use_hex = False
++ for (name, value) in self.values:
++ if value > 0x1000:
++ use_hex = True
++
++ print("enum %s {" % self.name)
++ for (name, value) in self.values:
++ if use_hex:
++ print("\t%s = 0x%08x," % (name, value))
++ else:
++ print("\t%s = %d," % (name, value))
++ print("};\n")
++
++ def dump_pack_struct(self):
++ pass
++
++class Field(object):
++ def __init__(self, name, low, high, shr, type, parser):
++ self.name = name
++ self.low = low
++ self.high = high
++ self.shr = shr
++ self.type = type
++
++ builtin_types = [ None, "a3xx_regid", "boolean", "uint", "hex", "int", "fixed", "ufixed", "float", "address", "waddress" ]
++
++ maxpos = parser.current_bitsize - 1
++
++ if low < 0 or low > maxpos:
++ raise parser.error("low attribute out of range: %d" % low)
++ if high < 0 or high > maxpos:
++ raise parser.error("high attribute out of range: %d" % high)
++ if high < low:
++ raise parser.error("low is greater than high: low=%d, high=%d" % (low, high))
++ if self.type == "boolean" and not low == high:
++ raise parser.error("booleans should be 1 bit fields")
++ elif self.type == "float" and not (high - low == 31 or high - low == 15):
++ raise parser.error("floats should be 16 or 32 bit fields")
++ elif not self.type in builtin_types and not self.type in parser.enums:
++ raise parser.error("unknown type '%s'" % self.type)
++
++ def ctype(self, var_name):
++ if self.type == None:
++ type = "uint32_t"
++ val = var_name
++ elif self.type == "boolean":
++ type = "bool"
++ val = var_name
++ elif self.type == "uint" or self.type == "hex" or self.type == "a3xx_regid":
++ type = "uint32_t"
++ val = var_name
++ elif self.type == "int":
++ type = "int32_t"
++ val = var_name
++ elif self.type == "fixed":
++ type = "float"
++ val = "((int32_t)(%s * %d.0))" % (var_name, 1 << self.radix)
++ elif self.type == "ufixed":
++ type = "float"
++ val = "((uint32_t)(%s * %d.0))" % (var_name, 1 << self.radix)
++ elif self.type == "float" and self.high - self.low == 31:
++ type = "float"
++ val = "fui(%s)" % var_name
++ elif self.type == "float" and self.high - self.low == 15:
++ type = "float"
++ val = "_mesa_float_to_half(%s)" % var_name
++ elif self.type in [ "address", "waddress" ]:
++ type = "uint64_t"
++ val = var_name
++ else:
++ type = "enum %s" % self.type
++ val = var_name
++
++ if self.shr > 0:
++ val = "(%s >> %d)" % (val, self.shr)
++
++ return (type, val)
++
++def tab_to(name, value):
++ tab_count = (68 - (len(name) & ~7)) // 8
++ if tab_count <= 0:
++ tab_count = 1
++ print(name + ('\t' * tab_count) + value)
++
++def mask(low, high):
++ return ((0xffffffffffffffff >> (64 - (high + 1 - low))) << low)
++
++def field_name(reg, f):
++ if f.name:
++ name = f.name.lower()
++ else:
++ # We hit this path when a reg is defined with no bitset fields, ie.
++ # <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint"/>
++ name = reg.name.lower()
++
++ if (name in [ "double", "float", "int" ]) or not (name[0].isalpha()):
++ name = "_" + name
++
++ return name
++
++# indices - array of (ctype, stride, __offsets_NAME)
++def indices_varlist(indices):
++ return ", ".join(["i%d" % i for i in range(len(indices))])
++
++def indices_prototype(indices):
++ return ", ".join(["%s i%d" % (ctype, idx)
++ for (idx, (ctype, stride, offset)) in enumerate(indices)])
++
++def indices_strides(indices):
++ return " + ".join(["0x%x*i%d" % (stride, idx)
++ if stride else
++ "%s(i%d)" % (offset, idx)
++ for (idx, (ctype, stride, offset)) in enumerate(indices)])
++
++class Bitset(object):
++ def __init__(self, name, template):
++ self.name = name
++ self.inline = False
++ if template:
++ self.fields = template.fields[:]
++ else:
++ self.fields = []
++
++ # Get address field if there is one in the bitset, else return None:
++ def get_address_field(self):
++ for f in self.fields:
++ if f.type in [ "address", "waddress" ]:
++ return f
++ return None
++
++ def dump_regpair_builder(self, reg):
++ print("#ifndef NDEBUG")
++ known_mask = 0
++ for f in self.fields:
++ known_mask |= mask(f.low, f.high)
++ if f.type in [ "boolean", "address", "waddress" ]:
++ continue
++ type, val = f.ctype("fields.%s" % field_name(reg, f))
++ print(" assert((%-40s & 0x%08x) == 0);" % (val, 0xffffffff ^ mask(0 , f.high - f.low)))
++ print(" assert((%-40s & 0x%08x) == 0);" % ("fields.unknown", known_mask))
++ print("#endif\n")
++
++ print(" return (struct fd_reg_pair) {")
++ if reg.array:
++ print(" .reg = REG_%s(__i)," % reg.full_name)
++ else:
++ print(" .reg = REG_%s," % reg.full_name)
++
++ print(" .value =")
++ for f in self.fields:
++ if f.type in [ "address", "waddress" ]:
++ continue
++ else:
++ type, val = f.ctype("fields.%s" % field_name(reg, f))
++ print(" (%-40s << %2d) |" % (val, f.low))
++ value_name = "dword"
++ if reg.bit_size == 64:
++ value_name = "qword"
++ print(" fields.unknown | fields.%s," % (value_name,))
++
++ address = self.get_address_field()
++ if address:
++ print(" .bo = fields.bo,")
++ print(" .is_address = true,")
++ if f.type == "waddress":
++ print(" .bo_write = true,")
++ print(" .bo_offset = fields.bo_offset,")
++ print(" .bo_shift = %d," % address.shr)
++ print(" .bo_low = %d," % address.low)
++
++ print(" };")
++
++ def dump_pack_struct(self, reg=None):
++ if not reg:
++ return
++
++ prefix = reg.full_name
++
++ print("struct %s {" % prefix)
++ for f in self.fields:
++ if f.type in [ "address", "waddress" ]:
++ tab_to(" __bo_type", "bo;")
++ tab_to(" uint32_t", "bo_offset;")
++ continue
++ name = field_name(reg, f)
++
++ type, val = f.ctype("var")
++
++ tab_to(" %s" % type, "%s;" % name)
++ if reg.bit_size == 64:
++ tab_to(" uint64_t", "unknown;")
++ tab_to(" uint64_t", "qword;")
++ else:
++ tab_to(" uint32_t", "unknown;")
++ tab_to(" uint32_t", "dword;")
++ print("};\n")
++
++ if reg.array:
++ print("static inline struct fd_reg_pair\npack_%s(uint32_t __i, struct %s fields)\n{" %
++ (prefix, prefix))
++ else:
++ print("static inline struct fd_reg_pair\npack_%s(struct %s fields)\n{" %
++ (prefix, prefix))
++
++ self.dump_regpair_builder(reg)
++
++ print("\n}\n")
++
++ if self.get_address_field():
++ skip = ", { .reg = 0 }"
++ else:
++ skip = ""
++
++ if reg.array:
++ print("#define %s(__i, ...) pack_%s(__i, __struct_cast(%s) { __VA_ARGS__ })%s\n" %
++ (prefix, prefix, prefix, skip))
++ else:
++ print("#define %s(...) pack_%s(__struct_cast(%s) { __VA_ARGS__ })%s\n" %
++ (prefix, prefix, prefix, skip))
++
++
++ def dump(self, prefix=None):
++ if prefix == None:
++ prefix = self.name
++ for f in self.fields:
++ if f.name:
++ name = prefix + "_" + f.name
++ else:
++ name = prefix
++
++ if not f.name and f.low == 0 and f.shr == 0 and not f.type in ["float", "fixed", "ufixed"]:
++ pass
++ elif f.type == "boolean" or (f.type == None and f.low == f.high):
++ tab_to("#define %s" % name, "0x%08x" % (1 << f.low))
++ else:
++ tab_to("#define %s__MASK" % name, "0x%08x" % mask(f.low, f.high))
++ tab_to("#define %s__SHIFT" % name, "%d" % f.low)
++ type, val = f.ctype("val")
++
++ print("static inline uint32_t %s(%s val)\n{" % (name, type))
++ if f.shr > 0:
++ print("\tassert(!(val & 0x%x));" % mask(0, f.shr - 1))
++ print("\treturn ((%s) << %s__SHIFT) & %s__MASK;\n}" % (val, name, name))
++ print()
++
++class Array(object):
++ def __init__(self, attrs, domain, variant, parent, index_type):
++ if "name" in attrs:
++ self.local_name = attrs["name"]
++ else:
++ self.local_name = ""
++ self.domain = domain
++ self.variant = variant
++ self.parent = parent
++ if self.parent:
++ self.name = self.parent.name + "_" + self.local_name
++ else:
++ self.name = self.local_name
++ if "offsets" in attrs:
++ self.offsets = map(lambda i: "0x%08x" % int(i, 0), attrs["offsets"].split(","))
++ self.fixed_offsets = True
++ elif "doffsets" in attrs:
++ self.offsets = map(lambda s: "(%s)" % s , attrs["doffsets"].split(","))
++ self.fixed_offsets = True
++ else:
++ self.offset = int(attrs["offset"], 0)
++ self.stride = int(attrs["stride"], 0)
++ self.fixed_offsets = False
++ if "index" in attrs:
++ self.index_type = index_type
++ else:
++ self.index_type = None
++ self.length = int(attrs["length"], 0)
++ if "usage" in attrs:
++ self.usages = attrs["usage"].split(',')
++ else:
++ self.usages = None
++
++ def index_ctype(self):
++ if not self.index_type:
++ return "uint32_t"
++ else:
++ return "enum %s" % self.index_type.name
++
++ # Generate array of (ctype, stride, __offsets_NAME)
++ def indices(self):
++ if self.parent:
++ indices = self.parent.indices()
++ else:
++ indices = []
++ if self.length != 1:
++ if self.fixed_offsets:
++ indices.append((self.index_ctype(), None, f"__offset_{self.local_name}"))
++ else:
++ indices.append((self.index_ctype(), self.stride, None))
++ return indices
++
++ def total_offset(self):
++ offset = 0
++ if not self.fixed_offsets:
++ offset += self.offset
++ if self.parent:
++ offset += self.parent.total_offset()
++ return offset
++
++ def dump(self):
++ proto = indices_varlist(self.indices())
++ strides = indices_strides(self.indices())
++ array_offset = self.total_offset()
++ if self.fixed_offsets:
++ print("static inline uint32_t __offset_%s(%s idx)" % (self.local_name, self.index_ctype()))
++ print("{\n\tswitch (idx) {")
++ if self.index_type:
++ for val, offset in zip(self.index_type.names(), self.offsets):
++ print("\t\tcase %s: return %s;" % (val, offset))
++ else:
++ for idx, offset in enumerate(self.offsets):
++ print("\t\tcase %d: return %s;" % (idx, offset))
++ print("\t\tdefault: return INVALID_IDX(idx);")
++ print("\t}\n}")
++ if proto == '':
++ tab_to("#define REG_%s_%s" % (self.domain, self.name), "0x%08x\n" % array_offset)
++ else:
++ tab_to("#define REG_%s_%s(%s)" % (self.domain, self.name, proto), "(0x%08x + %s )\n" % (array_offset, strides))
++
++ def dump_pack_struct(self):
++ pass
++
++ def dump_regpair_builder(self):
++ pass
++
++class Reg(object):
++ def __init__(self, attrs, domain, array, bit_size):
++ self.name = attrs["name"]
++ self.domain = domain
++ self.array = array
++ self.offset = int(attrs["offset"], 0)
++ self.type = None
++ self.bit_size = bit_size
++ if array:
++ self.name = array.name + "_" + self.name
++ self.full_name = self.domain + "_" + self.name
++ if "stride" in attrs:
++ self.stride = int(attrs["stride"], 0)
++ self.length = int(attrs["length"], 0)
++ else:
++ self.stride = None
++ self.length = None
++
++ # Generate array of (ctype, stride, __offsets_NAME)
++ def indices(self):
++ if self.array:
++ indices = self.array.indices()
++ else:
++ indices = []
++ if self.stride:
++ indices.append(("uint32_t", self.stride, None))
++ return indices
++
++ def total_offset(self):
++ if self.array:
++ return self.array.total_offset() + self.offset
++ else:
++ return self.offset
++
++ def dump(self):
++ proto = indices_prototype(self.indices())
++ strides = indices_strides(self.indices())
++ offset = self.total_offset()
++ if proto == '':
++ tab_to("#define REG_%s" % self.full_name, "0x%08x" % offset)
++ else:
++ print("static inline uint32_t REG_%s(%s) { return 0x%08x + %s; }" % (self.full_name, proto, offset, strides))
++
++ if self.bitset.inline:
++ self.bitset.dump(self.full_name)
++
++ def dump_pack_struct(self):
++ if self.bitset.inline:
++ self.bitset.dump_pack_struct(self)
++
++ def dump_regpair_builder(self):
++ if self.bitset.inline:
++ self.bitset.dump_regpair_builder(self)
++
++ def dump_py(self):
++ print("\tREG_%s = 0x%08x" % (self.full_name, self.offset))
++
++
++class Parser(object):
++ def __init__(self):
++ self.current_array = None
++ self.current_domain = None
++ self.current_prefix = None
++ self.current_prefix_type = None
++ self.current_stripe = None
++ self.current_bitset = None
++ self.current_bitsize = 32
++ # The varset attribute on the domain specifies the enum which
++ # specifies all possible hw variants:
++ self.current_varset = None
++ # Regs that have multiple variants.. we only generated the C++
++ # template based struct-packers for these
++ self.variant_regs = {}
++ # Information in which contexts regs are used, to be used in
++ # debug options
++ self.usage_regs = collections.defaultdict(list)
++ self.bitsets = {}
++ self.enums = {}
++ self.variants = set()
++ self.file = []
++ self.xml_files = []
++ self.copyright_year = None
++ self.authors = []
++ self.license = None
++
++ def error(self, message):
++ parser, filename = self.stack[-1]
++ return Error("%s:%d:%d: %s" % (filename, parser.CurrentLineNumber, parser.CurrentColumnNumber, message))
++
++ def prefix(self, variant=None):
++ if self.current_prefix_type == "variant" and variant:
++ return variant
++ elif self.current_stripe:
++ return self.current_stripe + "_" + self.current_domain
++ elif self.current_prefix:
++ return self.current_prefix + "_" + self.current_domain
++ else:
++ return self.current_domain
++
++ def parse_field(self, name, attrs):
++ try:
++ if "pos" in attrs:
++ high = low = int(attrs["pos"], 0)
++ elif "high" in attrs and "low" in attrs:
++ high = int(attrs["high"], 0)
++ low = int(attrs["low"], 0)
++ else:
++ low = 0
++ high = self.current_bitsize - 1
++
++ if "type" in attrs:
++ type = attrs["type"]
++ else:
++ type = None
++
++ if "shr" in attrs:
++ shr = int(attrs["shr"], 0)
++ else:
++ shr = 0
++
++ b = Field(name, low, high, shr, type, self)
++
++ if type == "fixed" or type == "ufixed":
++ b.radix = int(attrs["radix"], 0)
++
++ self.current_bitset.fields.append(b)
++ except ValueError as e:
++ raise self.error(e)
++
++ def parse_varset(self, attrs):
++ # Inherit the varset from the enclosing domain if not overriden:
++ varset = self.current_varset
++ if "varset" in attrs:
++ varset = self.enums[attrs["varset"]]
++ return varset
++
++ def parse_variants(self, attrs):
++ if not "variants" in attrs:
++ return None
++ variant = attrs["variants"].split(",")[0]
++ if "-" in variant:
++ variant = variant[:variant.index("-")]
++
++ varset = self.parse_varset(attrs)
++
++ assert varset.has_name(variant)
++
++ return variant
++
++ def add_all_variants(self, reg, attrs, parent_variant):
++ # TODO this should really handle *all* variants, including dealing
++ # with open ended ranges (ie. "A2XX,A4XX-") (we have the varset
++ # enum now to make that possible)
++ variant = self.parse_variants(attrs)
++ if not variant:
++ variant = parent_variant
++
++ if reg.name not in self.variant_regs:
++ self.variant_regs[reg.name] = {}
++ else:
++ # All variants must be same size:
++ v = next(iter(self.variant_regs[reg.name]))
++ assert self.variant_regs[reg.name][v].bit_size == reg.bit_size
++
++ self.variant_regs[reg.name][variant] = reg
++
++ def add_all_usages(self, reg, usages):
++ if not usages:
++ return
++
++ for usage in usages:
++ self.usage_regs[usage].append(reg)
++
++ self.variants.add(reg.domain)
++
++ def do_validate(self, schemafile):
++ try:
++ from lxml import etree
++
++ parser, filename = self.stack[-1]
++ dirname = os.path.dirname(filename)
++
++ # we expect this to look like <namespace url> schema.xsd.. I think
++ # technically it is supposed to be just a URL, but that doesn't
++ # quite match up to what we do.. Just skip over everything up to
++ # and including the first whitespace character:
++ schemafile = schemafile[schemafile.rindex(" ")+1:]
++
++ # this is a bit cheezy, but the xml file to validate could be
++ # in a child director, ie. we don't really know where the schema
++ # file is, the way the rnn C code does. So if it doesn't exist
++ # just look one level up
++ if not os.path.exists(dirname + "/" + schemafile):
++ schemafile = "../" + schemafile
++
++ if not os.path.exists(dirname + "/" + schemafile):
++ raise self.error("Cannot find schema for: " + filename)
++
++ xmlschema_doc = etree.parse(dirname + "/" + schemafile)
++ xmlschema = etree.XMLSchema(xmlschema_doc)
++
++ xml_doc = etree.parse(filename)
++ if not xmlschema.validate(xml_doc):
++ error_str = str(xmlschema.error_log.filter_from_errors()[0])
++ raise self.error("Schema validation failed for: " + filename + "\n" + error_str)
++ except ImportError:
++ print("lxml not found, skipping validation", file=sys.stderr)
++
++ def do_parse(self, filename):
++ filepath = os.path.abspath(filename)
++ if filepath in self.xml_files:
++ return
++ self.xml_files.append(filepath)
++ file = open(filename, "rb")
++ parser = xml.parsers.expat.ParserCreate()
++ self.stack.append((parser, filename))
++ parser.StartElementHandler = self.start_element
++ parser.EndElementHandler = self.end_element
++ parser.CharacterDataHandler = self.character_data
++ parser.buffer_text = True
++ parser.ParseFile(file)
++ self.stack.pop()
++ file.close()
++
++ def parse(self, rnn_path, filename):
++ self.path = rnn_path
++ self.stack = []
++ self.do_parse(filename)
++
++ def parse_reg(self, attrs, bit_size):
++ self.current_bitsize = bit_size
++ if "type" in attrs and attrs["type"] in self.bitsets:
++ bitset = self.bitsets[attrs["type"]]
++ if bitset.inline:
++ self.current_bitset = Bitset(attrs["name"], bitset)
++ self.current_bitset.inline = True
++ else:
++ self.current_bitset = bitset
++ else:
++ self.current_bitset = Bitset(attrs["name"], None)
++ self.current_bitset.inline = True
++ if "type" in attrs:
++ self.parse_field(None, attrs)
++
++ variant = self.parse_variants(attrs)
++ if not variant and self.current_array:
++ variant = self.current_array.variant
++
++ self.current_reg = Reg(attrs, self.prefix(variant), self.current_array, bit_size)
++ self.current_reg.bitset = self.current_bitset
++
++ if len(self.stack) == 1:
++ self.file.append(self.current_reg)
++
++ if variant is not None:
++ self.add_all_variants(self.current_reg, attrs, variant)
++
++ usages = None
++ if "usage" in attrs:
++ usages = attrs["usage"].split(',')
++ elif self.current_array:
++ usages = self.current_array.usages
++
++ self.add_all_usages(self.current_reg, usages)
++
++ def start_element(self, name, attrs):
++ self.cdata = ""
++ if name == "import":
++ filename = attrs["file"]
++ self.do_parse(os.path.join(self.path, filename))
++ elif name == "domain":
++ self.current_domain = attrs["name"]
++ if "prefix" in attrs:
++ self.current_prefix = self.parse_variants(attrs)
++ self.current_prefix_type = attrs["prefix"]
++ else:
++ self.current_prefix = None
++ self.current_prefix_type = None
++ if "varset" in attrs:
++ self.current_varset = self.enums[attrs["varset"]]
++ elif name == "stripe":
++ self.current_stripe = self.parse_variants(attrs)
++ elif name == "enum":
++ self.current_enum_value = 0
++ self.current_enum = Enum(attrs["name"])
++ self.enums[attrs["name"]] = self.current_enum
++ if len(self.stack) == 1:
++ self.file.append(self.current_enum)
++ elif name == "value":
++ if "value" in attrs:
++ value = int(attrs["value"], 0)
++ else:
++ value = self.current_enum_value
++ self.current_enum.values.append((attrs["name"], value))
++ elif name == "reg32":
++ self.parse_reg(attrs, 32)
++ elif name == "reg64":
++ self.parse_reg(attrs, 64)
++ elif name == "array":
++ self.current_bitsize = 32
++ variant = self.parse_variants(attrs)
++ index_type = self.enums[attrs["index"]] if "index" in attrs else None
++ self.current_array = Array(attrs, self.prefix(variant), variant, self.current_array, index_type)
++ if len(self.stack) == 1:
++ self.file.append(self.current_array)
++ elif name == "bitset":
++ self.current_bitset = Bitset(attrs["name"], None)
++ if "inline" in attrs and attrs["inline"] == "yes":
++ self.current_bitset.inline = True
++ self.bitsets[self.current_bitset.name] = self.current_bitset
++ if len(self.stack) == 1 and not self.current_bitset.inline:
++ self.file.append(self.current_bitset)
++ elif name == "bitfield" and self.current_bitset:
++ self.parse_field(attrs["name"], attrs)
++ elif name == "database":
++ self.do_validate(attrs["xsi:schemaLocation"])
++ elif name == "copyright":
++ self.copyright_year = attrs["year"]
++ elif name == "author":
++ self.authors.append(attrs["name"] + " <" + attrs["email"] + "> " + attrs["name"])
++
++ def end_element(self, name):
++ if name == "domain":
++ self.current_domain = None
++ self.current_prefix = None
++ self.current_prefix_type = None
++ elif name == "stripe":
++ self.current_stripe = None
++ elif name == "bitset":
++ self.current_bitset = None
++ elif name == "reg32":
++ self.current_reg = None
++ elif name == "array":
++ self.current_array = self.current_array.parent
++ elif name == "enum":
++ self.current_enum = None
++ elif name == "license":
++ self.license = self.cdata
++
++ def character_data(self, data):
++ self.cdata += data
++
++ def dump_reg_usages(self):
++ d = collections.defaultdict(list)
++ for usage, regs in self.usage_regs.items():
++ for reg in regs:
++ variants = self.variant_regs.get(reg.name)
++ if variants:
++ for variant, vreg in variants.items():
++ if reg == vreg:
++ d[(usage, variant)].append(reg)
++ else:
++ for variant in self.variants:
++ d[(usage, variant)].append(reg)
++
++ print("#ifdef __cplusplus")
++
++ for usage, regs in self.usage_regs.items():
++ print("template<chip CHIP> constexpr inline uint16_t %s_REGS[] = {};" % (usage.upper()))
++
++ for (usage, variant), regs in d.items():
++ offsets = []
++
++ for reg in regs:
++ if reg.array:
++ for i in range(reg.array.length):
++ offsets.append(reg.array.offset + reg.offset + i * reg.array.stride)
++ if reg.bit_size == 64:
++ offsets.append(offsets[-1] + 1)
++ else:
++ offsets.append(reg.offset)
++ if reg.bit_size == 64:
++ offsets.append(offsets[-1] + 1)
++
++ offsets.sort()
++
++ print("template<> constexpr inline uint16_t %s_REGS<%s>[] = {" % (usage.upper(), variant))
++ for offset in offsets:
++ print("\t%s," % hex(offset))
++ print("};")
++
++ print("#endif")
++
++ def dump(self):
++ enums = []
++ bitsets = []
++ regs = []
++ for e in self.file:
++ if isinstance(e, Enum):
++ enums.append(e)
++ elif isinstance(e, Bitset):
++ bitsets.append(e)
++ else:
++ regs.append(e)
++
++ for e in enums + bitsets + regs:
++ e.dump()
++
++ self.dump_reg_usages()
++
++
++ def dump_regs_py(self):
++ regs = []
++ for e in self.file:
++ if isinstance(e, Reg):
++ regs.append(e)
++
++ for e in regs:
++ e.dump_py()
++
++
++ def dump_reg_variants(self, regname, variants):
++ # Don't bother for things that only have a single variant:
++ if len(variants) == 1:
++ return
++ print("#ifdef __cplusplus")
++ print("struct __%s {" % regname)
++ # TODO be more clever.. we should probably figure out which
++ # fields have the same type in all variants (in which they
++ # appear) and stuff everything else in a variant specific
++ # sub-structure.
++ seen_fields = []
++ bit_size = 32
++ array = False
++ address = None
++ for variant in variants.keys():
++ print(" /* %s fields: */" % variant)
++ reg = variants[variant]
++ bit_size = reg.bit_size
++ array = reg.array
++ for f in reg.bitset.fields:
++ fld_name = field_name(reg, f)
++ if fld_name in seen_fields:
++ continue
++ seen_fields.append(fld_name)
++ name = fld_name.lower()
++ if f.type in [ "address", "waddress" ]:
++ if address:
++ continue
++ address = f
++ tab_to(" __bo_type", "bo;")
++ tab_to(" uint32_t", "bo_offset;")
++ continue
++ type, val = f.ctype("var")
++ tab_to(" %s" %type, "%s;" %name)
++ print(" /* fallback fields: */")
++ if bit_size == 64:
++ tab_to(" uint64_t", "unknown;")
++ tab_to(" uint64_t", "qword;")
++ else:
++ tab_to(" uint32_t", "unknown;")
++ tab_to(" uint32_t", "dword;")
++ print("};")
++ # TODO don't hardcode the varset enum name
++ varenum = "chip"
++ print("template <%s %s>" % (varenum, varenum.upper()))
++ print("static inline struct fd_reg_pair")
++ xtra = ""
++ xtravar = ""
++ if array:
++ xtra = "int __i, "
++ xtravar = "__i, "
++ print("__%s(%sstruct __%s fields) {" % (regname, xtra, regname))
++ for variant in variants.keys():
++ print(" if (%s == %s) {" % (varenum.upper(), variant))
++ reg = variants[variant]
++ reg.dump_regpair_builder()
++ print(" } else")
++ print(" assert(!\"invalid variant\");")
++ print("}")
++
++ if bit_size == 64:
++ skip = ", { .reg = 0 }"
++ else:
++ skip = ""
++
++ print("#define %s(VARIANT, %s...) __%s<VARIANT>(%s{__VA_ARGS__})%s" % (regname, xtravar, regname, xtravar, skip))
++ print("#endif /* __cplusplus */")
++
++ def dump_structs(self):
++ for e in self.file:
++ e.dump_pack_struct()
++
++ for regname in self.variant_regs:
++ self.dump_reg_variants(regname, self.variant_regs[regname])
++
++
++def dump_c(args, guard, func):
++ p = Parser()
++
++ try:
++ p.parse(args.rnn, args.xml)
++ except Error as e:
++ print(e, file=sys.stderr)
++ exit(1)
++
++ print("#ifndef %s\n#define %s\n" % (guard, guard))
++
++ print("""/* Autogenerated file, DO NOT EDIT manually!
++
++This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
++http://gitlab.freedesktop.org/mesa/mesa/
++git clone https://gitlab.freedesktop.org/mesa/mesa.git
++
++The rules-ng-ng source files this header was generated from are:
++""")
++ maxlen = 0
++ for filepath in p.xml_files:
++ maxlen = max(maxlen, len(filepath))
++ for filepath in p.xml_files:
++ pad = " " * (maxlen - len(filepath))
++ filesize = str(os.path.getsize(filepath))
++ filesize = " " * (7 - len(filesize)) + filesize
++ filetime = time.ctime(os.path.getmtime(filepath))
++ print("- " + filepath + pad + " (" + filesize + " bytes, from " + filetime + ")")
++ if p.copyright_year:
++ current_year = str(datetime.date.today().year)
++ print()
++ print("Copyright (C) %s-%s by the following authors:" % (p.copyright_year, current_year))
++ for author in p.authors:
++ print("- " + author)
++ if p.license:
++ print(p.license)
++ print("*/")
++
++ print()
++ print("#ifdef __KERNEL__")
++ print("#include <linux/bug.h>")
++ print("#define assert(x) BUG_ON(!(x))")
++ print("#else")
++ print("#include <assert.h>")
++ print("#endif")
++ print()
++
++ print("#ifdef __cplusplus")
++ print("#define __struct_cast(X)")
++ print("#else")
++ print("#define __struct_cast(X) (struct X)")
++ print("#endif")
++ print()
++
++ func(p)
++
++ print("\n#endif /* %s */" % guard)
++
++
++def dump_c_defines(args):
++ guard = str.replace(os.path.basename(args.xml), '.', '_').upper()
++ dump_c(args, guard, lambda p: p.dump())
++
++
++def dump_c_pack_structs(args):
++ guard = str.replace(os.path.basename(args.xml), '.', '_').upper() + '_STRUCTS'
++ dump_c(args, guard, lambda p: p.dump_structs())
++
++
++def dump_py_defines(args):
++ p = Parser()
++
++ try:
++ p.parse(args.rnn, args.xml)
++ except Error as e:
++ print(e, file=sys.stderr)
++ exit(1)
++
++ file_name = os.path.splitext(os.path.basename(args.xml))[0]
++
++ print("from enum import IntEnum")
++ print("class %sRegs(IntEnum):" % file_name.upper())
++
++ os.path.basename(args.xml)
++
++ p.dump_regs_py()
++
++
++def main():
++ parser = argparse.ArgumentParser()
++ parser.add_argument('--rnn', type=str, required=True)
++ parser.add_argument('--xml', type=str, required=True)
++
++ subparsers = parser.add_subparsers(required=True)
++
++ parser_c_defines = subparsers.add_parser('c-defines')
++ parser_c_defines.set_defaults(func=dump_c_defines)
++
++ parser_c_pack_structs = subparsers.add_parser('c-pack-structs')
++ parser_c_pack_structs.set_defaults(func=dump_c_pack_structs)
++
++ parser_py_defines = subparsers.add_parser('py-defines')
++ parser_py_defines.set_defaults(func=dump_py_defines)
++
++ args = parser.parse_args()
++ args.func(args)
++
++
++if __name__ == '__main__':
++ main()
+--
+2.39.5
+
--- /dev/null
+From 55c623c17f13c43e7e9d0f3c302ecb629032edd2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 1 Apr 2024 05:42:36 +0300
+Subject: drm/msm: import XML display registers database
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 4f52f5e63b62c9db8318f435f81bcd9addcc6709 ]
+
+Import display-related registers database from the Mesa, commit
+639488f924d9 ("freedreno/registers: limit the rules schema").
+
+The msm.xml and mdp_common.xml files were adjusted to drop subdirectory paths.
+
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Patchwork: https://patchwork.freedesktop.org/patch/585852/
+Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-6-4bdb277a85a1@linaro.org
+Stable-dep-of: 588257897058 ("drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG0 updated from driver side")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/registers/.gitignore | 4 +
+ drivers/gpu/drm/msm/registers/display/dsi.xml | 390 +++++++
+ .../msm/registers/display/dsi_phy_10nm.xml | 102 ++
+ .../msm/registers/display/dsi_phy_14nm.xml | 135 +++
+ .../msm/registers/display/dsi_phy_20nm.xml | 100 ++
+ .../msm/registers/display/dsi_phy_28nm.xml | 180 +++
+ .../registers/display/dsi_phy_28nm_8960.xml | 134 +++
+ .../drm/msm/registers/display/dsi_phy_7nm.xml | 230 ++++
+ drivers/gpu/drm/msm/registers/display/edp.xml | 239 ++++
+ .../gpu/drm/msm/registers/display/hdmi.xml | 1015 +++++++++++++++++
+ .../gpu/drm/msm/registers/display/mdp4.xml | 504 ++++++++
+ .../gpu/drm/msm/registers/display/mdp5.xml | 806 +++++++++++++
+ .../drm/msm/registers/display/mdp_common.xml | 90 ++
+ drivers/gpu/drm/msm/registers/display/msm.xml | 32 +
+ .../gpu/drm/msm/registers/display/sfpb.xml | 17 +
+ .../drm/msm/registers/freedreno_copyright.xml | 40 +
+ drivers/gpu/drm/msm/registers/rules-fd.xsd | 404 +++++++
+ 17 files changed, 4422 insertions(+)
+ create mode 100644 drivers/gpu/drm/msm/registers/.gitignore
+ create mode 100644 drivers/gpu/drm/msm/registers/display/dsi.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/display/dsi_phy_10nm.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/display/dsi_phy_14nm.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/display/dsi_phy_20nm.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/display/dsi_phy_28nm.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/display/dsi_phy_28nm_8960.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/display/edp.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/display/hdmi.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/display/mdp4.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/display/mdp5.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/display/mdp_common.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/display/msm.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/display/sfpb.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/freedreno_copyright.xml
+ create mode 100644 drivers/gpu/drm/msm/registers/rules-fd.xsd
+
+diff --git a/drivers/gpu/drm/msm/registers/.gitignore b/drivers/gpu/drm/msm/registers/.gitignore
+new file mode 100644
+index 0000000000000..848e0e3efbcb2
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/.gitignore
+@@ -0,0 +1,4 @@
++# ignore XML files present at Mesa but not used by the kernel
++adreno/adreno_control_regs.xml
++adreno/adreno_pipe_regs.xml
++adreno/ocmem.xml
+diff --git a/drivers/gpu/drm/msm/registers/display/dsi.xml b/drivers/gpu/drm/msm/registers/display/dsi.xml
+new file mode 100644
+index 0000000000000..501ffc585a9f6
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/display/dsi.xml
+@@ -0,0 +1,390 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++
++<domain name="DSI" width="32">
++ <enum name="dsi_traffic_mode">
++ <value name="NON_BURST_SYNCH_PULSE" value="0"/>
++ <value name="NON_BURST_SYNCH_EVENT" value="1"/>
++ <value name="BURST_MODE" value="2"/>
++ </enum>
++ <enum name="dsi_vid_dst_format">
++ <value name="VID_DST_FORMAT_RGB565" value="0"/>
++ <value name="VID_DST_FORMAT_RGB666" value="1"/>
++ <value name="VID_DST_FORMAT_RGB666_LOOSE" value="2"/>
++ <value name="VID_DST_FORMAT_RGB888" value="3"/>
++ </enum>
++ <enum name="dsi_rgb_swap">
++ <value name="SWAP_RGB" value="0"/>
++ <value name="SWAP_RBG" value="1"/>
++ <value name="SWAP_BGR" value="2"/>
++ <value name="SWAP_BRG" value="3"/>
++ <value name="SWAP_GRB" value="4"/>
++ <value name="SWAP_GBR" value="5"/>
++ </enum>
++ <enum name="dsi_cmd_trigger">
++ <value name="TRIGGER_NONE" value="0"/>
++ <value name="TRIGGER_SEOF" value="1"/>
++ <value name="TRIGGER_TE" value="2"/>
++ <value name="TRIGGER_SW" value="4"/>
++ <value name="TRIGGER_SW_SEOF" value="5"/>
++ <value name="TRIGGER_SW_TE" value="6"/>
++ </enum>
++ <enum name="dsi_cmd_dst_format">
++ <value name="CMD_DST_FORMAT_RGB111" value="0"/>
++ <value name="CMD_DST_FORMAT_RGB332" value="3"/>
++ <value name="CMD_DST_FORMAT_RGB444" value="4"/>
++ <value name="CMD_DST_FORMAT_RGB565" value="6"/>
++ <value name="CMD_DST_FORMAT_RGB666" value="7"/>
++ <value name="CMD_DST_FORMAT_RGB888" value="8"/>
++ </enum>
++ <enum name="dsi_lane_swap">
++ <value name="LANE_SWAP_0123" value="0"/>
++ <value name="LANE_SWAP_3012" value="1"/>
++ <value name="LANE_SWAP_2301" value="2"/>
++ <value name="LANE_SWAP_1230" value="3"/>
++ <value name="LANE_SWAP_0321" value="4"/>
++ <value name="LANE_SWAP_1032" value="5"/>
++ <value name="LANE_SWAP_2103" value="6"/>
++ <value name="LANE_SWAP_3210" value="7"/>
++ </enum>
++ <enum name="video_config_bpp">
++ <value name="VIDEO_CONFIG_18BPP" value="0"/>
++ <value name="VIDEO_CONFIG_24BPP" value="1"/>
++ </enum>
++ <enum name="video_pattern_sel">
++ <value name="VID_PRBS" value="0"/>
++ <value name="VID_INCREMENTAL" value="1"/>
++ <value name="VID_FIXED" value="2"/>
++ <value name="VID_MDSS_GENERAL_PATTERN" value="3"/>
++ </enum>
++ <enum name="cmd_mdp_stream0_pattern_sel">
++ <value name="CMD_MDP_PRBS" value="0"/>
++ <value name="CMD_MDP_INCREMENTAL" value="1"/>
++ <value name="CMD_MDP_FIXED" value="2"/>
++ <value name="CMD_MDP_MDSS_GENERAL_PATTERN" value="3"/>
++ </enum>
++ <enum name="cmd_dma_pattern_sel">
++ <value name="CMD_DMA_PRBS" value="0"/>
++ <value name="CMD_DMA_INCREMENTAL" value="1"/>
++ <value name="CMD_DMA_FIXED" value="2"/>
++ <value name="CMD_DMA_CUSTOM_PATTERN_DMA_FIFO" value="3"/>
++ </enum>
++ <bitset name="DSI_IRQ">
++ <bitfield name="CMD_DMA_DONE" pos="0" type="boolean"/>
++ <bitfield name="MASK_CMD_DMA_DONE" pos="1" type="boolean"/>
++ <bitfield name="CMD_MDP_DONE" pos="8" type="boolean"/>
++ <bitfield name="MASK_CMD_MDP_DONE" pos="9" type="boolean"/>
++ <bitfield name="VIDEO_DONE" pos="16" type="boolean"/>
++ <bitfield name="MASK_VIDEO_DONE" pos="17" type="boolean"/>
++ <bitfield name="BTA_DONE" pos="20" type="boolean"/>
++ <bitfield name="MASK_BTA_DONE" pos="21" type="boolean"/>
++ <bitfield name="ERROR" pos="24" type="boolean"/>
++ <bitfield name="MASK_ERROR" pos="25" type="boolean"/>
++ </bitset>
++
++ <reg32 offset="0x00000" name="6G_HW_VERSION">
++ <bitfield name="MAJOR" low="28" high="31" type="uint"/>
++ <bitfield name="MINOR" low="16" high="27" type="uint"/>
++ <bitfield name="STEP" low="0" high="15" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x00000" name="CTRL">
++ <bitfield name="ENABLE" pos="0" type="boolean"/>
++ <bitfield name="VID_MODE_EN" pos="1" type="boolean"/>
++ <bitfield name="CMD_MODE_EN" pos="2" type="boolean"/>
++ <bitfield name="LANE0" pos="4" type="boolean"/>
++ <bitfield name="LANE1" pos="5" type="boolean"/>
++ <bitfield name="LANE2" pos="6" type="boolean"/>
++ <bitfield name="LANE3" pos="7" type="boolean"/>
++ <bitfield name="CLK_EN" pos="8" type="boolean"/>
++ <bitfield name="ECC_CHECK" pos="20" type="boolean"/>
++ <bitfield name="CRC_CHECK" pos="24" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x00004" name="STATUS0">
++ <bitfield name="CMD_MODE_ENGINE_BUSY" pos="0" type="boolean"/>
++ <bitfield name="CMD_MODE_DMA_BUSY" pos="1" type="boolean"/>
++ <bitfield name="CMD_MODE_MDP_BUSY" pos="2" type="boolean"/>
++ <bitfield name="VIDEO_MODE_ENGINE_BUSY" pos="3" type="boolean"/>
++ <bitfield name="DSI_BUSY" pos="4" type="boolean"/> <!-- see mipi_dsi_cmd_bta_sw_trigger() -->
++ <bitfield name="INTERLEAVE_OP_CONTENTION" pos="31" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x00008" name="FIFO_STATUS">
++ <bitfield name="VIDEO_MDP_FIFO_OVERFLOW" pos="0" type="boolean"/>
++ <bitfield name="VIDEO_MDP_FIFO_UNDERFLOW" pos="3" type="boolean"/>
++ <bitfield name="CMD_MDP_FIFO_UNDERFLOW" pos="7" type="boolean"/>
++ <bitfield name="CMD_DMA_FIFO_RD_WATERMARK_REACH" pos="8" type="boolean"/>
++ <bitfield name="CMD_DMA_FIFO_WR_WATERMARK_REACH" pos="9" type="boolean"/>
++ <bitfield name="CMD_DMA_FIFO_UNDERFLOW" pos="10" type="boolean"/>
++ <bitfield name="DLN0_LP_FIFO_EMPTY" pos="12" type="boolean"/>
++ <bitfield name="DLN0_LP_FIFO_FULL" pos="13" type="boolean"/>
++ <bitfield name="DLN0_LP_FIFO_OVERFLOW" pos="14" type="boolean"/>
++ <bitfield name="DLN0_HS_FIFO_EMPTY" pos="16" type="boolean"/>
++ <bitfield name="DLN0_HS_FIFO_FULL" pos="17" type="boolean"/>
++ <bitfield name="DLN0_HS_FIFO_OVERFLOW" pos="18" type="boolean"/>
++ <bitfield name="DLN0_HS_FIFO_UNDERFLOW" pos="19" type="boolean"/>
++ <bitfield name="DLN1_HS_FIFO_EMPTY" pos="20" type="boolean"/>
++ <bitfield name="DLN1_HS_FIFO_FULL" pos="21" type="boolean"/>
++ <bitfield name="DLN1_HS_FIFO_OVERFLOW" pos="22" type="boolean"/>
++ <bitfield name="DLN1_HS_FIFO_UNDERFLOW" pos="23" type="boolean"/>
++ <bitfield name="DLN2_HS_FIFO_EMPTY" pos="24" type="boolean"/>
++ <bitfield name="DLN2_HS_FIFO_FULL" pos="25" type="boolean"/>
++ <bitfield name="DLN2_HS_FIFO_OVERFLOW" pos="26" type="boolean"/>
++ <bitfield name="DLN2_HS_FIFO_UNDERFLOW" pos="27" type="boolean"/>
++ <bitfield name="DLN3_HS_FIFO_EMPTY" pos="28" type="boolean"/>
++ <bitfield name="DLN3_HS_FIFO_FULL" pos="29" type="boolean"/>
++ <bitfield name="DLN3_HS_FIFO_OVERFLOW" pos="30" type="boolean"/>
++ <bitfield name="DLN3_HS_FIFO_UNDERFLOW" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0000c" name="VID_CFG0">
++ <bitfield name="VIRT_CHANNEL" low="0" high="1" type="uint"/> <!-- always zero? -->
++ <bitfield name="DST_FORMAT" low="4" high="5" type="dsi_vid_dst_format"/>
++ <bitfield name="TRAFFIC_MODE" low="8" high="9" type="dsi_traffic_mode"/>
++ <bitfield name="BLLP_POWER_STOP" pos="12" type="boolean"/>
++ <bitfield name="EOF_BLLP_POWER_STOP" pos="15" type="boolean"/>
++ <bitfield name="HSA_POWER_STOP" pos="16" type="boolean"/>
++ <bitfield name="HBP_POWER_STOP" pos="20" type="boolean"/>
++ <bitfield name="HFP_POWER_STOP" pos="24" type="boolean"/>
++ <bitfield name="DATABUS_WIDEN" pos="25" type="boolean"/>
++ <bitfield name="PULSE_MODE_HSA_HE" pos="28" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0001c" name="VID_CFG1">
++ <bitfield name="R_SEL" pos="0" type="boolean"/>
++ <bitfield name="G_SEL" pos="4" type="boolean"/>
++ <bitfield name="B_SEL" pos="8" type="boolean"/>
++ <bitfield name="RGB_SWAP" low="12" high="14" type="dsi_rgb_swap"/>
++ </reg32>
++ <reg32 offset="0x00020" name="ACTIVE_H">
++ <bitfield name="START" low="0" high="11" type="uint"/>
++ <bitfield name="END" low="16" high="27" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00024" name="ACTIVE_V">
++ <bitfield name="START" low="0" high="11" type="uint"/>
++ <bitfield name="END" low="16" high="27" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00028" name="TOTAL">
++ <bitfield name="H_TOTAL" low="0" high="11" type="uint"/>
++ <bitfield name="V_TOTAL" low="16" high="27" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0002c" name="ACTIVE_HSYNC">
++ <bitfield name="START" low="0" high="11" type="uint"/>
++ <bitfield name="END" low="16" high="27" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00030" name="ACTIVE_VSYNC_HPOS">
++ <bitfield name="START" low="0" high="11" type="uint"/>
++ <bitfield name="END" low="16" high="27" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00034" name="ACTIVE_VSYNC_VPOS">
++ <bitfield name="START" low="0" high="11" type="uint"/>
++ <bitfield name="END" low="16" high="27" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x00038" name="CMD_DMA_CTRL">
++ <bitfield name="BROADCAST_EN" pos="31" type="boolean"/>
++ <bitfield name="FROM_FRAME_BUFFER" pos="28" type="boolean"/>
++ <bitfield name="LOW_POWER" pos="26" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0003c" name="CMD_CFG0">
++ <bitfield name="DST_FORMAT" low="0" high="3" type="dsi_cmd_dst_format"/>
++ <bitfield name="R_SEL" pos="4" type="boolean"/>
++ <bitfield name="G_SEL" pos="8" type="boolean"/>
++ <bitfield name="B_SEL" pos="12" type="boolean"/>
++ <bitfield name="INTERLEAVE_MAX" low="20" high="23" type="uint"/>
++ <bitfield name="RGB_SWAP" low="16" high="18" type="dsi_rgb_swap"/>
++ </reg32>
++ <reg32 offset="0x00040" name="CMD_CFG1">
++ <bitfield name="WR_MEM_START" low="0" high="7" type="uint"/>
++ <bitfield name="WR_MEM_CONTINUE" low="8" high="15" type="uint"/>
++ <bitfield name="INSERT_DCS_COMMAND" pos="16" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00044" name="DMA_BASE"/>
++ <reg32 offset="0x00048" name="DMA_LEN"/>
++ <reg32 offset="0x00054" name="CMD_MDP_STREAM0_CTRL">
++ <bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
++ <bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/>
++ <bitfield name="WORD_COUNT" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00058" name="CMD_MDP_STREAM0_TOTAL">
++ <bitfield name="H_TOTAL" low="0" high="11" type="uint"/>
++ <bitfield name="V_TOTAL" low="16" high="27" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0005c" name="CMD_MDP_STREAM1_CTRL">
++ <bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
++ <bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/>
++ <bitfield name="WORD_COUNT" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00060" name="CMD_MDP_STREAM1_TOTAL">
++ <bitfield name="H_TOTAL" low="0" high="15" type="uint"/>
++ <bitfield name="V_TOTAL" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00064" name="ACK_ERR_STATUS"/>
++ <array offset="0x00068" name="RDBK" length="4" stride="4">
++ <reg32 offset="0x0" name="DATA"/>
++ </array>
++ <reg32 offset="0x00080" name="TRIG_CTRL">
++ <bitfield name="DMA_TRIGGER" low="0" high="2" type="dsi_cmd_trigger"/>
++ <bitfield name="MDP_TRIGGER" low="4" high="6" type="dsi_cmd_trigger"/>
++ <bitfield name="STREAM" low="8" high="9" type="uint"/>
++ <bitfield name="BLOCK_DMA_WITHIN_FRAME" pos="12" type="boolean"/>
++ <bitfield name="TE" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0008c" name="TRIG_DMA"/>
++ <reg32 offset="0x000b0" name="DLN0_PHY_ERR">
++ <bitfield name="DLN0_ERR_ESC" pos="0" type="boolean"/>
++ <bitfield name="DLN0_ERR_SYNC_ESC" pos="4" type="boolean"/>
++ <bitfield name="DLN0_ERR_CONTROL" pos="8" type="boolean"/>
++ <bitfield name="DLN0_ERR_CONTENTION_LP0" pos="12" type="boolean"/>
++ <bitfield name="DLN0_ERR_CONTENTION_LP1" pos="16" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x000b4" name="LP_TIMER_CTRL">
++ <bitfield name="LP_RX_TO" low="0" high="15" type="uint"/>
++ <bitfield name="BTA_TO" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x000b8" name="HS_TIMER_CTRL">
++ <bitfield name="HS_TX_TO" low="0" high="15" type="uint"/>
++ <bitfield name="TIMER_RESOLUTION" low="16" high="19" type="uint"/>
++ <bitfield name="HS_TX_TO_STOP_EN" pos="28" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x000bc" name="TIMEOUT_STATUS"/>
++ <reg32 offset="0x000c0" name="CLKOUT_TIMING_CTRL">
++ <bitfield name="T_CLK_PRE" low="0" high="5" type="uint"/>
++ <bitfield name="T_CLK_POST" low="8" high="13" type="uint"/>
++ </reg32>
++ <reg32 offset="0x000c8" name="EOT_PACKET_CTRL">
++ <bitfield name="TX_EOT_APPEND" pos="0" type="boolean"/>
++ <bitfield name="RX_EOT_IGNORE" pos="4" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x000a4" name="LANE_STATUS">
++ <bitfield name="DLN0_STOPSTATE" pos="0" type="boolean"/>
++ <bitfield name="DLN1_STOPSTATE" pos="1" type="boolean"/>
++ <bitfield name="DLN2_STOPSTATE" pos="2" type="boolean"/>
++ <bitfield name="DLN3_STOPSTATE" pos="3" type="boolean"/>
++ <bitfield name="CLKLN_STOPSTATE" pos="4" type="boolean"/>
++ <bitfield name="DLN0_ULPS_ACTIVE_NOT" pos="8" type="boolean"/>
++ <bitfield name="DLN1_ULPS_ACTIVE_NOT" pos="9" type="boolean"/>
++ <bitfield name="DLN2_ULPS_ACTIVE_NOT" pos="10" type="boolean"/>
++ <bitfield name="DLN3_ULPS_ACTIVE_NOT" pos="11" type="boolean"/>
++ <bitfield name="CLKLN_ULPS_ACTIVE_NOT" pos="12" type="boolean"/>
++ <bitfield name="DLN0_DIRECTION" pos="16" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x000a8" name="LANE_CTRL">
++ <bitfield name="HS_REQ_SEL_PHY" pos="24" type="boolean"/>
++ <bitfield name="CLKLN_HS_FORCE_REQUEST" pos="28" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x000ac" name="LANE_SWAP_CTRL">
++ <bitfield name="DLN_SWAP_SEL" low="0" high="2" type="dsi_lane_swap"/>
++ </reg32>
++ <reg32 offset="0x00108" name="ERR_INT_MASK0"/>
++ <reg32 offset="0x0010c" name="INTR_CTRL" type="DSI_IRQ"/>
++ <reg32 offset="0x00114" name="RESET"/>
++ <reg32 offset="0x00118" name="CLK_CTRL">
++ <bitfield name="AHBS_HCLK_ON" pos="0" type="boolean"/>
++ <bitfield name="AHBM_SCLK_ON" pos="1" type="boolean"/>
++ <bitfield name="PCLK_ON" pos="2" type="boolean"/>
++ <bitfield name="DSICLK_ON" pos="3" type="boolean"/>
++ <bitfield name="BYTECLK_ON" pos="4" type="boolean"/>
++ <bitfield name="ESCCLK_ON" pos="5" type="boolean"/>
++ <bitfield name="FORCE_ON_DYN_AHBM_HCLK" pos="9" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0011c" name="CLK_STATUS">
++ <bitfield name="DSI_AON_AHBM_HCLK_ACTIVE" pos="0" type="boolean"/>
++ <bitfield name="DSI_DYN_AHBM_HCLK_ACTIVE" pos="1" type="boolean"/>
++ <bitfield name="DSI_AON_AHBS_HCLK_ACTIVE" pos="2" type="boolean"/>
++ <bitfield name="DSI_DYN_AHBS_HCLK_ACTIVE" pos="3" type="boolean"/>
++ <bitfield name="DSI_AON_DSICLK_ACTIVE" pos="4" type="boolean"/>
++ <bitfield name="DSI_DYN_DSICLK_ACTIVE" pos="5" type="boolean"/>
++ <bitfield name="DSI_AON_BYTECLK_ACTIVE" pos="6" type="boolean"/>
++ <bitfield name="DSI_DYN_BYTECLK_ACTIVE" pos="7" type="boolean"/>
++ <bitfield name="DSI_AON_ESCCLK_ACTIVE" pos="8" type="boolean"/>
++ <bitfield name="DSI_AON_PCLK_ACTIVE" pos="9" type="boolean"/>
++ <bitfield name="DSI_DYN_PCLK_ACTIVE" pos="10" type="boolean"/>
++ <bitfield name="DSI_DYN_CMD_PCLK_ACTIVE" pos="12" type="boolean"/>
++ <bitfield name="DSI_CMD_PCLK_ACTIVE" pos="13" type="boolean"/>
++ <bitfield name="DSI_VID_PCLK_ACTIVE" pos="14" type="boolean"/>
++ <bitfield name="DSI_CAM_BIST_PCLK_ACT" pos="15" type="boolean"/>
++ <bitfield name="PLL_UNLOCKED" pos="16" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00128" name="PHY_RESET">
++ <bitfield name="RESET" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00160" name="TEST_PATTERN_GEN_VIDEO_INIT_VAL"/>
++ <reg32 offset="0x00198" name="TPG_MAIN_CONTROL">
++ <bitfield name="CHECKERED_RECTANGLE_PATTERN" pos="8" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x001a0" name="TPG_VIDEO_CONFIG">
++ <bitfield name="BPP" low="0" high="1" type="video_config_bpp"/>
++ <bitfield name="RGB" pos="2" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00158" name="TEST_PATTERN_GEN_CTRL">
++ <bitfield name="CMD_DMA_PATTERN_SEL" low="16" high="17" type="cmd_dma_pattern_sel"/>
++ <bitfield name="CMD_MDP_STREAM0_PATTERN_SEL" low="8" high="9" type="cmd_mdp_stream0_pattern_sel"/>
++ <bitfield name="VIDEO_PATTERN_SEL" low="4" high="5" type="video_pattern_sel"/>
++ <bitfield name="TPG_DMA_FIFO_MODE" pos="2" type="boolean"/>
++ <bitfield name="CMD_DMA_TPG_EN" pos="1" type="boolean"/>
++ <bitfield name="EN" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00168" name="TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0"/>
++ <reg32 offset="0x00180" name="TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER">
++ <bitfield name="SW_TRIGGER" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0019c" name="TPG_MAIN_CONTROL2">
++ <bitfield name="CMD_MDP0_CHECKERED_RECTANGLE_PATTERN" pos="7" type="boolean"/>
++ <bitfield name="CMD_MDP1_CHECKERED_RECTANGLE_PATTERN" pos="16" type="boolean"/>
++ <bitfield name="CMD_MDP2_CHECKERED_RECTANGLE_PATTERN" pos="25" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0017c" name="T_CLK_PRE_EXTEND">
++ <bitfield name="INC_BY_2_BYTECLK" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x001b4" name="CMD_MODE_MDP_CTRL2">
++ <bitfield name="DST_FORMAT2" low="0" high="3" type="dsi_cmd_dst_format"/>
++ <bitfield name="R_SEL" pos="4" type="boolean"/>
++ <bitfield name="G_SEL" pos="5" type="boolean"/>
++ <bitfield name="B_SEL" pos="6" type="boolean"/>
++ <bitfield name="BYTE_MSB_LSB_FLIP" pos="7" type="boolean"/>
++ <bitfield name="RGB_SWAP" low="8" high="10" type="dsi_rgb_swap"/>
++ <bitfield name="INPUT_RGB_SWAP" low="12" high="14" type="dsi_rgb_swap"/>
++ <bitfield name="BURST_MODE" pos="16" type="boolean"/>
++ <bitfield name="DATABUS_WIDEN" pos="20" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x001b8" name="CMD_MODE_MDP_STREAM2_CTRL">
++ <bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
++ <bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/>
++ <bitfield name="WORD_COUNT" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x001d0" name="RDBK_DATA_CTRL">
++ <bitfield name="COUNT" low="16" high="23" type="uint"/>
++ <bitfield name="CLR" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x001f0" name="VERSION">
++ <bitfield name="MAJOR" low="24" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x002d4" name="CPHY_MODE_CTRL"/>
++ <reg32 offset="0x0029c" name="VIDEO_COMPRESSION_MODE_CTRL">
++ <bitfield name="WC" low="16" high="31" type="uint"/>
++ <bitfield name="DATATYPE" low="8" high="13" type="uint"/>
++ <bitfield name="PKT_PER_LINE" low="6" high="7" type="uint"/>
++ <bitfield name="EOL_BYTE_NUM" low="4" high="5" type="uint"/>
++ <bitfield name="EN" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x002a4" name="COMMAND_COMPRESSION_MODE_CTRL">
++ <bitfield name="STREAM1_DATATYPE" low="24" high="29" type="uint"/>
++ <bitfield name="STREAM1_PKT_PER_LINE" low="22" high="23" type="uint"/>
++ <bitfield name="STREAM1_EOL_BYTE_NUM" low="20" high="21" type="uint"/>
++ <bitfield name="STREAM1_EN" pos="16" type="boolean"/>
++ <bitfield name="STREAM0_DATATYPE" low="8" high="13" type="uint"/>
++ <bitfield name="STREAM0_PKT_PER_LINE" low="6" high="7" type="uint"/>
++ <bitfield name="STREAM0_EOL_BYTE_NUM" low="4" high="5" type="uint"/>
++ <bitfield name="STREAM0_EN" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x002a8" name="COMMAND_COMPRESSION_MODE_CTRL2">
++ <bitfield name="STREAM1_SLICE_WIDTH" low="16" high="31" type="uint"/>
++ <bitfield name="STREAM0_SLICE_WIDTH" low="0" high="15" type="uint"/>
++ </reg32>
++
++</domain>
++
++</database>
+diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_10nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_10nm.xml
+new file mode 100644
+index 0000000000000..874c3db3e1261
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_10nm.xml
+@@ -0,0 +1,102 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++
++<domain name="DSI_10nm_PHY_CMN" width="32">
++ <reg32 offset="0x00000" name="REVISION_ID0"/>
++ <reg32 offset="0x00004" name="REVISION_ID1"/>
++ <reg32 offset="0x00008" name="REVISION_ID2"/>
++ <reg32 offset="0x0000c" name="REVISION_ID3"/>
++ <reg32 offset="0x00010" name="CLK_CFG0"/>
++ <reg32 offset="0x00014" name="CLK_CFG1"/>
++ <reg32 offset="0x00018" name="GLBL_CTRL"/>
++ <reg32 offset="0x0001c" name="RBUF_CTRL"/>
++ <reg32 offset="0x00020" name="VREG_CTRL"/>
++ <reg32 offset="0x00024" name="CTRL_0"/>
++ <reg32 offset="0x00028" name="CTRL_1"/>
++ <reg32 offset="0x0002c" name="CTRL_2"/>
++ <reg32 offset="0x00030" name="LANE_CFG0"/>
++ <reg32 offset="0x00034" name="LANE_CFG1"/>
++ <reg32 offset="0x00038" name="PLL_CNTRL"/>
++ <reg32 offset="0x00098" name="LANE_CTRL0"/>
++ <reg32 offset="0x0009c" name="LANE_CTRL1"/>
++ <reg32 offset="0x000a0" name="LANE_CTRL2"/>
++ <reg32 offset="0x000a4" name="LANE_CTRL3"/>
++ <reg32 offset="0x000a8" name="LANE_CTRL4"/>
++ <reg32 offset="0x000ac" name="TIMING_CTRL_0"/>
++ <reg32 offset="0x000b0" name="TIMING_CTRL_1"/>
++ <reg32 offset="0x000b4" name="TIMING_CTRL_2"/>
++ <reg32 offset="0x000b8" name="TIMING_CTRL_3"/>
++ <reg32 offset="0x000bc" name="TIMING_CTRL_4"/>
++ <reg32 offset="0x000c0" name="TIMING_CTRL_5"/>
++ <reg32 offset="0x000c4" name="TIMING_CTRL_6"/>
++ <reg32 offset="0x000c8" name="TIMING_CTRL_7"/>
++ <reg32 offset="0x000cc" name="TIMING_CTRL_8"/>
++ <reg32 offset="0x000d0" name="TIMING_CTRL_9"/>
++ <reg32 offset="0x000d4" name="TIMING_CTRL_10"/>
++ <reg32 offset="0x000d8" name="TIMING_CTRL_11"/>
++ <reg32 offset="0x000ec" name="PHY_STATUS"/>
++ <reg32 offset="0x000f4" name="LANE_STATUS0"/>
++ <reg32 offset="0x000f8" name="LANE_STATUS1"/>
++</domain>
++
++<domain name="DSI_10nm_PHY" width="32">
++ <array offset="0x00000" name="LN" length="5" stride="0x80">
++ <reg32 offset="0x00" name="CFG0"/>
++ <reg32 offset="0x04" name="CFG1"/>
++ <reg32 offset="0x08" name="CFG2"/>
++ <reg32 offset="0x0c" name="CFG3"/>
++ <reg32 offset="0x10" name="TEST_DATAPATH"/>
++ <reg32 offset="0x14" name="PIN_SWAP"/>
++ <reg32 offset="0x18" name="HSTX_STR_CTRL"/>
++ <reg32 offset="0x1c" name="OFFSET_TOP_CTRL"/>
++ <reg32 offset="0x20" name="OFFSET_BOT_CTRL"/>
++ <reg32 offset="0x24" name="LPTX_STR_CTRL"/>
++ <reg32 offset="0x28" name="LPRX_CTRL"/>
++ <reg32 offset="0x2c" name="TX_DCTRL"/>
++ </array>
++</domain>
++
++<domain name="DSI_10nm_PHY_PLL" width="32">
++ <reg32 offset="0x0000" name="ANALOG_CONTROLS_ONE"/>
++ <reg32 offset="0x0004" name="ANALOG_CONTROLS_TWO"/>
++ <reg32 offset="0x0010" name="ANALOG_CONTROLS_THREE"/>
++ <reg32 offset="0x001c" name="DSM_DIVIDER"/>
++ <reg32 offset="0x0020" name="FEEDBACK_DIVIDER"/>
++ <reg32 offset="0x0024" name="SYSTEM_MUXES"/>
++ <reg32 offset="0x002c" name="CMODE"/>
++ <reg32 offset="0x0030" name="CALIBRATION_SETTINGS"/>
++ <reg32 offset="0x0054" name="BAND_SEL_CAL_SETTINGS_THREE"/>
++ <reg32 offset="0x0064" name="FREQ_DETECT_SETTINGS_ONE"/>
++ <reg32 offset="0x007c" name="PFILT"/>
++ <reg32 offset="0x0080" name="IFILT"/>
++ <reg32 offset="0x0094" name="OUTDIV"/>
++ <reg32 offset="0x00a4" name="CORE_OVERRIDE"/>
++ <reg32 offset="0x00a8" name="CORE_INPUT_OVERRIDE"/>
++ <reg32 offset="0x00b4" name="PLL_DIGITAL_TIMERS_TWO"/>
++ <reg32 offset="0x00cc" name="DECIMAL_DIV_START_1"/>
++ <reg32 offset="0x00d0" name="FRAC_DIV_START_LOW_1"/>
++ <reg32 offset="0x00d4" name="FRAC_DIV_START_MID_1"/>
++ <reg32 offset="0x00d8" name="FRAC_DIV_START_HIGH_1"/>
++ <reg32 offset="0x010c" name="SSC_STEPSIZE_LOW_1"/>
++ <reg32 offset="0x0110" name="SSC_STEPSIZE_HIGH_1"/>
++ <reg32 offset="0x0114" name="SSC_DIV_PER_LOW_1"/>
++ <reg32 offset="0x0118" name="SSC_DIV_PER_HIGH_1"/>
++ <reg32 offset="0x011c" name="SSC_DIV_ADJPER_LOW_1"/>
++ <reg32 offset="0x0120" name="SSC_DIV_ADJPER_HIGH_1"/>
++ <reg32 offset="0x013c" name="SSC_CONTROL"/>
++ <reg32 offset="0x0140" name="PLL_OUTDIV_RATE"/>
++ <reg32 offset="0x0144" name="PLL_LOCKDET_RATE_1"/>
++ <reg32 offset="0x014c" name="PLL_PROP_GAIN_RATE_1"/>
++ <reg32 offset="0x0154" name="PLL_BAND_SET_RATE_1"/>
++ <reg32 offset="0x015c" name="PLL_INT_GAIN_IFILT_BAND_1"/>
++ <reg32 offset="0x0164" name="PLL_FL_INT_GAIN_PFILT_BAND_1"/>
++ <reg32 offset="0x0180" name="PLL_LOCK_OVERRIDE"/>
++ <reg32 offset="0x0184" name="PLL_LOCK_DELAY"/>
++ <reg32 offset="0x018c" name="CLOCK_INVERTERS"/>
++ <reg32 offset="0x01a0" name="COMMON_STATUS_ONE"/>
++</domain>
++
++</database>
+diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_14nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_14nm.xml
+new file mode 100644
+index 0000000000000..314b74489d49a
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_14nm.xml
+@@ -0,0 +1,135 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++
++<domain name="DSI_14nm_PHY_CMN" width="32">
++ <reg32 offset="0x00000" name="REVISION_ID0"/>
++ <reg32 offset="0x00004" name="REVISION_ID1"/>
++ <reg32 offset="0x00008" name="REVISION_ID2"/>
++ <reg32 offset="0x0000c" name="REVISION_ID3"/>
++ <reg32 offset="0x00010" name="CLK_CFG0">
++ <bitfield name="DIV_CTRL_3_0" low="4" high="7" type="uint"/>
++ <bitfield name="DIV_CTRL_7_4" low="4" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00014" name="CLK_CFG1">
++ <bitfield name="DSICLK_SEL" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00018" name="GLBL_TEST_CTRL">
++ <bitfield name="BITCLK_HS_SEL" pos="2" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0001C" name="CTRL_0"/>
++ <reg32 offset="0x00020" name="CTRL_1">
++ </reg32>
++ <reg32 offset="0x00024" name="HW_TRIGGER"/>
++ <reg32 offset="0x00028" name="SW_CFG0"/>
++ <reg32 offset="0x0002C" name="SW_CFG1"/>
++ <reg32 offset="0x00030" name="SW_CFG2"/>
++ <reg32 offset="0x00034" name="HW_CFG0"/>
++ <reg32 offset="0x00038" name="HW_CFG1"/>
++ <reg32 offset="0x0003C" name="HW_CFG2"/>
++ <reg32 offset="0x00040" name="HW_CFG3"/>
++ <reg32 offset="0x00044" name="HW_CFG4"/>
++ <reg32 offset="0x00048" name="PLL_CNTRL">
++ <bitfield name="PLL_START" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0004C" name="LDO_CNTRL">
++ <bitfield name="VREG_CTRL" low="0" high="5" type="uint"/>
++ </reg32>
++</domain>
++
++<domain name="DSI_14nm_PHY" width="32">
++ <array offset="0x00000" name="LN" length="5" stride="0x80">
++ <reg32 offset="0x00" name="CFG0">
++ <bitfield name="PREPARE_DLY" low="6" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x04" name="CFG1">
++ <bitfield name="HALFBYTECLK_EN" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x08" name="CFG2"/>
++ <reg32 offset="0x0c" name="CFG3"/>
++ <reg32 offset="0x10" name="TEST_DATAPATH"/>
++ <reg32 offset="0x14" name="TEST_STR"/>
++ <reg32 offset="0x18" name="TIMING_CTRL_4">
++ <bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x1c" name="TIMING_CTRL_5">
++ <bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x20" name="TIMING_CTRL_6">
++ <bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x24" name="TIMING_CTRL_7">
++ <bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x28" name="TIMING_CTRL_8">
++ <bitfield name="HS_RQST" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x2c" name="TIMING_CTRL_9">
++ <bitfield name="TA_GO" low="0" high="2" type="uint"/>
++ <bitfield name="TA_SURE" low="4" high="6" type="uint"/>
++ </reg32>
++ <reg32 offset="0x30" name="TIMING_CTRL_10">
++ <bitfield name="TA_GET" low="0" high="2" type="uint"/>
++ </reg32>
++ <reg32 offset="0x34" name="TIMING_CTRL_11">
++ <bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x38" name="STRENGTH_CTRL_0"/>
++ <reg32 offset="0x3c" name="STRENGTH_CTRL_1"/>
++ <reg32 offset="0x64" name="VREG_CNTRL"/>
++ </array>
++</domain>
++
++<domain name="DSI_14nm_PHY_PLL" width="32">
++ <reg32 offset="0x000" name="IE_TRIM"/>
++ <reg32 offset="0x004" name="IP_TRIM"/>
++ <reg32 offset="0x010" name="IPTAT_TRIM"/>
++ <reg32 offset="0x01c" name="CLKBUFLR_EN"/>
++ <reg32 offset="0x028" name="SYSCLK_EN_RESET"/>
++ <reg32 offset="0x02c" name="RESETSM_CNTRL"/>
++ <reg32 offset="0x030" name="RESETSM_CNTRL2"/>
++ <reg32 offset="0x034" name="RESETSM_CNTRL3"/>
++ <reg32 offset="0x038" name="RESETSM_CNTRL4"/>
++ <reg32 offset="0x03c" name="RESETSM_CNTRL5"/>
++ <reg32 offset="0x040" name="KVCO_DIV_REF1"/>
++ <reg32 offset="0x044" name="KVCO_DIV_REF2"/>
++ <reg32 offset="0x048" name="KVCO_COUNT1"/>
++ <reg32 offset="0x04c" name="KVCO_COUNT2"/>
++ <reg32 offset="0x05c" name="VREF_CFG1"/>
++ <reg32 offset="0x058" name="KVCO_CODE"/>
++ <reg32 offset="0x06c" name="VCO_DIV_REF1"/>
++ <reg32 offset="0x070" name="VCO_DIV_REF2"/>
++ <reg32 offset="0x074" name="VCO_COUNT1"/>
++ <reg32 offset="0x078" name="VCO_COUNT2"/>
++ <reg32 offset="0x07c" name="PLLLOCK_CMP1"/>
++ <reg32 offset="0x080" name="PLLLOCK_CMP2"/>
++ <reg32 offset="0x084" name="PLLLOCK_CMP3"/>
++ <reg32 offset="0x088" name="PLLLOCK_CMP_EN"/>
++ <reg32 offset="0x08c" name="PLL_VCO_TUNE"/>
++ <reg32 offset="0x090" name="DEC_START"/>
++ <reg32 offset="0x094" name="SSC_EN_CENTER"/>
++ <reg32 offset="0x098" name="SSC_ADJ_PER1"/>
++ <reg32 offset="0x09c" name="SSC_ADJ_PER2"/>
++ <reg32 offset="0x0a0" name="SSC_PER1"/>
++ <reg32 offset="0x0a4" name="SSC_PER2"/>
++ <reg32 offset="0x0a8" name="SSC_STEP_SIZE1"/>
++ <reg32 offset="0x0ac" name="SSC_STEP_SIZE2"/>
++ <reg32 offset="0x0b4" name="DIV_FRAC_START1"/>
++ <reg32 offset="0x0b8" name="DIV_FRAC_START2"/>
++ <reg32 offset="0x0bc" name="DIV_FRAC_START3"/>
++ <reg32 offset="0x0c0" name="TXCLK_EN"/>
++ <reg32 offset="0x0c4" name="PLL_CRCTRL"/>
++ <reg32 offset="0x0cc" name="RESET_SM_READY_STATUS"/>
++ <reg32 offset="0x0e8" name="PLL_MISC1"/>
++ <reg32 offset="0x0f0" name="CP_SET_CUR"/>
++ <reg32 offset="0x0f4" name="PLL_ICPMSET"/>
++ <reg32 offset="0x0f8" name="PLL_ICPCSET"/>
++ <reg32 offset="0x0fc" name="PLL_ICP_SET"/>
++ <reg32 offset="0x100" name="PLL_LPF1"/>
++ <reg32 offset="0x104" name="PLL_LPF2_POSTDIV"/>
++ <reg32 offset="0x108" name="PLL_BANDGAP"/>
++</domain>
++
++</database>
+diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_20nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_20nm.xml
+new file mode 100644
+index 0000000000000..99e9deb361b6e
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_20nm.xml
+@@ -0,0 +1,100 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++
++<domain name="DSI_20nm_PHY" width="32">
++ <array offset="0x00000" name="LN" length="4" stride="0x40">
++ <reg32 offset="0x00" name="CFG_0"/>
++ <reg32 offset="0x04" name="CFG_1"/>
++ <reg32 offset="0x08" name="CFG_2"/>
++ <reg32 offset="0x0c" name="CFG_3"/>
++ <reg32 offset="0x10" name="CFG_4"/>
++ <reg32 offset="0x14" name="TEST_DATAPATH"/>
++ <reg32 offset="0x18" name="DEBUG_SEL"/>
++ <reg32 offset="0x1c" name="TEST_STR_0"/>
++ <reg32 offset="0x20" name="TEST_STR_1"/>
++ </array>
++
++ <reg32 offset="0x00100" name="LNCK_CFG_0"/>
++ <reg32 offset="0x00104" name="LNCK_CFG_1"/>
++ <reg32 offset="0x00108" name="LNCK_CFG_2"/>
++ <reg32 offset="0x0010c" name="LNCK_CFG_3"/>
++ <reg32 offset="0x00110" name="LNCK_CFG_4"/>
++ <reg32 offset="0x00114" name="LNCK_TEST_DATAPATH"/>
++ <reg32 offset="0x00118" name="LNCK_DEBUG_SEL"/>
++ <reg32 offset="0x0011c" name="LNCK_TEST_STR0"/>
++ <reg32 offset="0x00120" name="LNCK_TEST_STR1"/>
++
++ <reg32 offset="0x00140" name="TIMING_CTRL_0">
++ <bitfield name="CLK_ZERO" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00144" name="TIMING_CTRL_1">
++ <bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00148" name="TIMING_CTRL_2">
++ <bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0014c" name="TIMING_CTRL_3">
++ <bitfield name="CLK_ZERO_8" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00150" name="TIMING_CTRL_4">
++ <bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00154" name="TIMING_CTRL_5">
++ <bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00158" name="TIMING_CTRL_6">
++ <bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0015c" name="TIMING_CTRL_7">
++ <bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00160" name="TIMING_CTRL_8">
++ <bitfield name="HS_RQST" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00164" name="TIMING_CTRL_9">
++ <bitfield name="TA_GO" low="0" high="2" type="uint"/>
++ <bitfield name="TA_SURE" low="4" high="6" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00168" name="TIMING_CTRL_10">
++ <bitfield name="TA_GET" low="0" high="2" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0016c" name="TIMING_CTRL_11">
++ <bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x00170" name="CTRL_0"/>
++ <reg32 offset="0x00174" name="CTRL_1"/>
++ <reg32 offset="0x00178" name="CTRL_2"/>
++ <reg32 offset="0x0017c" name="CTRL_3"/>
++ <reg32 offset="0x00180" name="CTRL_4"/>
++
++ <reg32 offset="0x00184" name="STRENGTH_0"/>
++ <reg32 offset="0x00188" name="STRENGTH_1"/>
++
++ <reg32 offset="0x001b4" name="BIST_CTRL_0"/>
++ <reg32 offset="0x001b8" name="BIST_CTRL_1"/>
++ <reg32 offset="0x001bc" name="BIST_CTRL_2"/>
++ <reg32 offset="0x001c0" name="BIST_CTRL_3"/>
++ <reg32 offset="0x001c4" name="BIST_CTRL_4"/>
++ <reg32 offset="0x001c8" name="BIST_CTRL_5"/>
++
++ <reg32 offset="0x001d4" name="GLBL_TEST_CTRL">
++ <bitfield name="BITCLK_HS_SEL" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x001dc" name="LDO_CNTRL"/>
++</domain>
++
++<domain name="DSI_20nm_PHY_REGULATOR" width="32">
++ <reg32 offset="0x00000" name="CTRL_0"/>
++ <reg32 offset="0x00004" name="CTRL_1"/>
++ <reg32 offset="0x00008" name="CTRL_2"/>
++ <reg32 offset="0x0000c" name="CTRL_3"/>
++ <reg32 offset="0x00010" name="CTRL_4"/>
++ <reg32 offset="0x00014" name="CTRL_5"/>
++ <reg32 offset="0x00018" name="CAL_PWR_CFG"/>
++</domain>
++
++</database>
+diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_28nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_28nm.xml
+new file mode 100644
+index 0000000000000..81d5b96f18c44
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_28nm.xml
+@@ -0,0 +1,180 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++
++<domain name="DSI_28nm_PHY" width="32">
++ <array offset="0x00000" name="LN" length="4" stride="0x40">
++ <reg32 offset="0x00" name="CFG_0"/>
++ <reg32 offset="0x04" name="CFG_1"/>
++ <reg32 offset="0x08" name="CFG_2"/>
++ <reg32 offset="0x0c" name="CFG_3"/>
++ <reg32 offset="0x10" name="CFG_4"/>
++ <reg32 offset="0x14" name="TEST_DATAPATH"/>
++ <reg32 offset="0x18" name="DEBUG_SEL"/>
++ <reg32 offset="0x1c" name="TEST_STR_0"/>
++ <reg32 offset="0x20" name="TEST_STR_1"/>
++ </array>
++
++ <reg32 offset="0x00100" name="LNCK_CFG_0"/>
++ <reg32 offset="0x00104" name="LNCK_CFG_1"/>
++ <reg32 offset="0x00108" name="LNCK_CFG_2"/>
++ <reg32 offset="0x0010c" name="LNCK_CFG_3"/>
++ <reg32 offset="0x00110" name="LNCK_CFG_4"/>
++ <reg32 offset="0x00114" name="LNCK_TEST_DATAPATH"/>
++ <reg32 offset="0x00118" name="LNCK_DEBUG_SEL"/>
++ <reg32 offset="0x0011c" name="LNCK_TEST_STR0"/>
++ <reg32 offset="0x00120" name="LNCK_TEST_STR1"/>
++
++ <reg32 offset="0x00140" name="TIMING_CTRL_0">
++ <bitfield name="CLK_ZERO" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00144" name="TIMING_CTRL_1">
++ <bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00148" name="TIMING_CTRL_2">
++ <bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0014c" name="TIMING_CTRL_3">
++ <bitfield name="CLK_ZERO_8" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00150" name="TIMING_CTRL_4">
++ <bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00154" name="TIMING_CTRL_5">
++ <bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00158" name="TIMING_CTRL_6">
++ <bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0015c" name="TIMING_CTRL_7">
++ <bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00160" name="TIMING_CTRL_8">
++ <bitfield name="HS_RQST" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00164" name="TIMING_CTRL_9">
++ <bitfield name="TA_GO" low="0" high="2" type="uint"/>
++ <bitfield name="TA_SURE" low="4" high="6" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00168" name="TIMING_CTRL_10">
++ <bitfield name="TA_GET" low="0" high="2" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0016c" name="TIMING_CTRL_11">
++ <bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x00170" name="CTRL_0"/>
++ <reg32 offset="0x00174" name="CTRL_1"/>
++ <reg32 offset="0x00178" name="CTRL_2"/>
++ <reg32 offset="0x0017c" name="CTRL_3"/>
++ <reg32 offset="0x00180" name="CTRL_4"/>
++
++ <reg32 offset="0x00184" name="STRENGTH_0"/>
++ <reg32 offset="0x00188" name="STRENGTH_1"/>
++
++ <reg32 offset="0x001b4" name="BIST_CTRL_0"/>
++ <reg32 offset="0x001b8" name="BIST_CTRL_1"/>
++ <reg32 offset="0x001bc" name="BIST_CTRL_2"/>
++ <reg32 offset="0x001c0" name="BIST_CTRL_3"/>
++ <reg32 offset="0x001c4" name="BIST_CTRL_4"/>
++ <reg32 offset="0x001c8" name="BIST_CTRL_5"/>
++
++ <reg32 offset="0x001d4" name="GLBL_TEST_CTRL">
++ <bitfield name="BITCLK_HS_SEL" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x001dc" name="LDO_CNTRL"/>
++</domain>
++
++<domain name="DSI_28nm_PHY_REGULATOR" width="32">
++ <reg32 offset="0x00000" name="CTRL_0"/>
++ <reg32 offset="0x00004" name="CTRL_1"/>
++ <reg32 offset="0x00008" name="CTRL_2"/>
++ <reg32 offset="0x0000c" name="CTRL_3"/>
++ <reg32 offset="0x00010" name="CTRL_4"/>
++ <reg32 offset="0x00014" name="CTRL_5"/>
++ <reg32 offset="0x00018" name="CAL_PWR_CFG"/>
++</domain>
++
++<domain name="DSI_28nm_PHY_PLL" width="32">
++ <reg32 offset="0x00000" name="REFCLK_CFG">
++ <bitfield name="DBLR" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00004" name="POSTDIV1_CFG"/>
++ <reg32 offset="0x00008" name="CHGPUMP_CFG"/>
++ <reg32 offset="0x0000C" name="VCOLPF_CFG"/>
++ <reg32 offset="0x00010" name="VREG_CFG">
++ <bitfield name="POSTDIV1_BYPASS_B" pos="1" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00014" name="PWRGEN_CFG"/>
++ <reg32 offset="0x00018" name="DMUX_CFG"/>
++ <reg32 offset="0x0001C" name="AMUX_CFG"/>
++ <reg32 offset="0x00020" name="GLB_CFG">
++ <bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/>
++ <bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/>
++ <bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/>
++ <bitfield name="PLL_ENABLE" pos="3" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00024" name="POSTDIV2_CFG"/>
++ <reg32 offset="0x00028" name="POSTDIV3_CFG"/>
++ <reg32 offset="0x0002C" name="LPFR_CFG"/>
++ <reg32 offset="0x00030" name="LPFC1_CFG"/>
++ <reg32 offset="0x00034" name="LPFC2_CFG"/>
++ <reg32 offset="0x00038" name="SDM_CFG0">
++ <bitfield name="BYP_DIV" low="0" high="5" type="uint"/>
++ <bitfield name="BYP" pos="6" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0003C" name="SDM_CFG1">
++ <bitfield name="DC_OFFSET" low="0" high="5" type="uint"/>
++ <bitfield name="DITHER_EN" pos="6" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00040" name="SDM_CFG2">
++ <bitfield name="FREQ_SEED_7_0" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00044" name="SDM_CFG3">
++ <bitfield name="FREQ_SEED_15_8" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00048" name="SDM_CFG4"/>
++ <reg32 offset="0x0004C" name="SSC_CFG0"/>
++ <reg32 offset="0x00050" name="SSC_CFG1"/>
++ <reg32 offset="0x00054" name="SSC_CFG2"/>
++ <reg32 offset="0x00058" name="SSC_CFG3"/>
++ <reg32 offset="0x0005C" name="LKDET_CFG0"/>
++ <reg32 offset="0x00060" name="LKDET_CFG1"/>
++ <reg32 offset="0x00064" name="LKDET_CFG2"/>
++ <reg32 offset="0x00068" name="TEST_CFG">
++ <bitfield name="PLL_SW_RESET" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0006C" name="CAL_CFG0"/>
++ <reg32 offset="0x00070" name="CAL_CFG1"/>
++ <reg32 offset="0x00074" name="CAL_CFG2"/>
++ <reg32 offset="0x00078" name="CAL_CFG3"/>
++ <reg32 offset="0x0007C" name="CAL_CFG4"/>
++ <reg32 offset="0x00080" name="CAL_CFG5"/>
++ <reg32 offset="0x00084" name="CAL_CFG6"/>
++ <reg32 offset="0x00088" name="CAL_CFG7"/>
++ <reg32 offset="0x0008C" name="CAL_CFG8"/>
++ <reg32 offset="0x00090" name="CAL_CFG9"/>
++ <reg32 offset="0x00094" name="CAL_CFG10"/>
++ <reg32 offset="0x00098" name="CAL_CFG11"/>
++ <reg32 offset="0x0009C" name="EFUSE_CFG"/>
++ <reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/>
++ <reg32 offset="0x000A4" name="CTRL_42"/>
++ <reg32 offset="0x000A8" name="CTRL_43"/>
++ <reg32 offset="0x000AC" name="CTRL_44"/>
++ <reg32 offset="0x000B0" name="CTRL_45"/>
++ <reg32 offset="0x000B4" name="CTRL_46"/>
++ <reg32 offset="0x000B8" name="CTRL_47"/>
++ <reg32 offset="0x000BC" name="CTRL_48"/>
++ <reg32 offset="0x000C0" name="STATUS">
++ <bitfield name="PLL_RDY" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x000C4" name="DEBUG_BUS0"/>
++ <reg32 offset="0x000C8" name="DEBUG_BUS1"/>
++ <reg32 offset="0x000CC" name="DEBUG_BUS2"/>
++ <reg32 offset="0x000D0" name="DEBUG_BUS3"/>
++ <reg32 offset="0x000D4" name="CTRL_54"/>
++</domain>
++
++</database>
+diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_28nm_8960.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_28nm_8960.xml
+new file mode 100644
+index 0000000000000..4c4de4dda6408
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_28nm_8960.xml
+@@ -0,0 +1,134 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++
++<domain name="DSI_28nm_8960_PHY" width="32">
++
++ <array offset="0x00000" name="LN" length="4" stride="0x40">
++ <reg32 offset="0x00" name="CFG_0"/>
++ <reg32 offset="0x04" name="CFG_1"/>
++ <reg32 offset="0x08" name="CFG_2"/>
++ <reg32 offset="0x0c" name="TEST_DATAPATH"/>
++ <reg32 offset="0x14" name="TEST_STR_0"/>
++ <reg32 offset="0x18" name="TEST_STR_1"/>
++ </array>
++
++ <reg32 offset="0x00100" name="LNCK_CFG_0"/>
++ <reg32 offset="0x00104" name="LNCK_CFG_1"/>
++ <reg32 offset="0x00108" name="LNCK_CFG_2"/>
++
++ <reg32 offset="0x0010c" name="LNCK_TEST_DATAPATH"/>
++ <reg32 offset="0x00114" name="LNCK_TEST_STR0"/>
++ <reg32 offset="0x00118" name="LNCK_TEST_STR1"/>
++
++ <reg32 offset="0x00140" name="TIMING_CTRL_0">
++ <bitfield name="CLK_ZERO" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00144" name="TIMING_CTRL_1">
++ <bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00148" name="TIMING_CTRL_2">
++ <bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x0014c" name="TIMING_CTRL_3"/>
++
++ <reg32 offset="0x00150" name="TIMING_CTRL_4">
++ <bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00154" name="TIMING_CTRL_5">
++ <bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00158" name="TIMING_CTRL_6">
++ <bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0015c" name="TIMING_CTRL_7">
++ <bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00160" name="TIMING_CTRL_8">
++ <bitfield name="HS_RQST" low="0" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00164" name="TIMING_CTRL_9">
++ <bitfield name="TA_GO" low="0" high="2" type="uint"/>
++ <bitfield name="TA_SURE" low="4" high="6" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00168" name="TIMING_CTRL_10">
++ <bitfield name="TA_GET" low="0" high="2" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0016c" name="TIMING_CTRL_11">
++ <bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x00170" name="CTRL_0"/>
++ <reg32 offset="0x00174" name="CTRL_1"/>
++ <reg32 offset="0x00178" name="CTRL_2"/>
++ <reg32 offset="0x0017c" name="CTRL_3"/>
++
++ <reg32 offset="0x00180" name="STRENGTH_0"/>
++ <reg32 offset="0x00184" name="STRENGTH_1"/>
++ <reg32 offset="0x00188" name="STRENGTH_2"/>
++
++ <reg32 offset="0x0018c" name="BIST_CTRL_0"/>
++ <reg32 offset="0x00190" name="BIST_CTRL_1"/>
++ <reg32 offset="0x00194" name="BIST_CTRL_2"/>
++ <reg32 offset="0x00198" name="BIST_CTRL_3"/>
++ <reg32 offset="0x0019c" name="BIST_CTRL_4"/>
++
++ <reg32 offset="0x001b0" name="LDO_CTRL"/>
++</domain>
++
++<domain name="DSI_28nm_8960_PHY_MISC" width="32">
++ <reg32 offset="0x00000" name="REGULATOR_CTRL_0"/>
++ <reg32 offset="0x00004" name="REGULATOR_CTRL_1"/>
++ <reg32 offset="0x00008" name="REGULATOR_CTRL_2"/>
++ <reg32 offset="0x0000c" name="REGULATOR_CTRL_3"/>
++ <reg32 offset="0x00010" name="REGULATOR_CTRL_4"/>
++ <reg32 offset="0x00014" name="REGULATOR_CTRL_5"/>
++ <reg32 offset="0x00018" name="REGULATOR_CAL_PWR_CFG"/>
++ <reg32 offset="0x00028" name="CAL_HW_TRIGGER"/>
++ <reg32 offset="0x0002c" name="CAL_SW_CFG_0"/>
++ <reg32 offset="0x00030" name="CAL_SW_CFG_1"/>
++ <reg32 offset="0x00034" name="CAL_SW_CFG_2"/>
++ <reg32 offset="0x00038" name="CAL_HW_CFG_0"/>
++ <reg32 offset="0x0003c" name="CAL_HW_CFG_1"/>
++ <reg32 offset="0x00040" name="CAL_HW_CFG_2"/>
++ <reg32 offset="0x00044" name="CAL_HW_CFG_3"/>
++ <reg32 offset="0x00048" name="CAL_HW_CFG_4"/>
++ <reg32 offset="0x00050" name="CAL_STATUS">
++ <bitfield name="CAL_BUSY" pos="4" type="boolean"/>
++ </reg32>
++</domain>
++
++<domain name="DSI_28nm_8960_PHY_PLL" width="32">
++ <reg32 offset="0x00000" name="CTRL_0">
++ <bitfield name="ENABLE" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00004" name="CTRL_1"/>
++ <reg32 offset="0x00008" name="CTRL_2"/>
++ <reg32 offset="0x0000c" name="CTRL_3"/>
++ <reg32 offset="0x00010" name="CTRL_4"/>
++ <reg32 offset="0x00014" name="CTRL_5"/>
++ <reg32 offset="0x00018" name="CTRL_6"/>
++ <reg32 offset="0x0001c" name="CTRL_7"/>
++ <reg32 offset="0x00020" name="CTRL_8"/>
++ <reg32 offset="0x00024" name="CTRL_9"/>
++ <reg32 offset="0x00028" name="CTRL_10"/>
++ <reg32 offset="0x0002c" name="CTRL_11"/>
++ <reg32 offset="0x00030" name="CTRL_12"/>
++ <reg32 offset="0x00034" name="CTRL_13"/>
++ <reg32 offset="0x00038" name="CTRL_14"/>
++ <reg32 offset="0x0003c" name="CTRL_15"/>
++ <reg32 offset="0x00040" name="CTRL_16"/>
++ <reg32 offset="0x00044" name="CTRL_17"/>
++ <reg32 offset="0x00048" name="CTRL_18"/>
++ <reg32 offset="0x0004c" name="CTRL_19"/>
++ <reg32 offset="0x00050" name="CTRL_20"/>
++
++ <reg32 offset="0x00080" name="RDY">
++ <bitfield name="PLL_RDY" pos="0" type="boolean"/>
++ </reg32>
++</domain>
++
++</database>
+diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
+new file mode 100644
+index 0000000000000..d54b72f924493
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
+@@ -0,0 +1,230 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++
++<domain name="DSI_7nm_PHY_CMN" width="32">
++ <reg32 offset="0x00000" name="REVISION_ID0"/>
++ <reg32 offset="0x00004" name="REVISION_ID1"/>
++ <reg32 offset="0x00008" name="REVISION_ID2"/>
++ <reg32 offset="0x0000c" name="REVISION_ID3"/>
++ <reg32 offset="0x00010" name="CLK_CFG0"/>
++ <reg32 offset="0x00014" name="CLK_CFG1"/>
++ <reg32 offset="0x00018" name="GLBL_CTRL"/>
++ <reg32 offset="0x0001c" name="RBUF_CTRL"/>
++ <reg32 offset="0x00020" name="VREG_CTRL_0"/>
++ <reg32 offset="0x00024" name="CTRL_0"/>
++ <reg32 offset="0x00028" name="CTRL_1"/>
++ <reg32 offset="0x0002c" name="CTRL_2"/>
++ <reg32 offset="0x00030" name="CTRL_3"/>
++ <reg32 offset="0x00034" name="LANE_CFG0"/>
++ <reg32 offset="0x00038" name="LANE_CFG1"/>
++ <reg32 offset="0x0003c" name="PLL_CNTRL"/>
++ <reg32 offset="0x00040" name="DPHY_SOT"/>
++ <reg32 offset="0x000a0" name="LANE_CTRL0"/>
++ <reg32 offset="0x000a4" name="LANE_CTRL1"/>
++ <reg32 offset="0x000a8" name="LANE_CTRL2"/>
++ <reg32 offset="0x000ac" name="LANE_CTRL3"/>
++ <reg32 offset="0x000b0" name="LANE_CTRL4"/>
++ <reg32 offset="0x000b4" name="TIMING_CTRL_0"/>
++ <reg32 offset="0x000b8" name="TIMING_CTRL_1"/>
++ <reg32 offset="0x000bc" name="TIMING_CTRL_2"/>
++ <reg32 offset="0x000c0" name="TIMING_CTRL_3"/>
++ <reg32 offset="0x000c4" name="TIMING_CTRL_4"/>
++ <reg32 offset="0x000c8" name="TIMING_CTRL_5"/>
++ <reg32 offset="0x000cc" name="TIMING_CTRL_6"/>
++ <reg32 offset="0x000d0" name="TIMING_CTRL_7"/>
++ <reg32 offset="0x000d4" name="TIMING_CTRL_8"/>
++ <reg32 offset="0x000d8" name="TIMING_CTRL_9"/>
++ <reg32 offset="0x000dc" name="TIMING_CTRL_10"/>
++ <reg32 offset="0x000e0" name="TIMING_CTRL_11"/>
++ <reg32 offset="0x000e4" name="TIMING_CTRL_12"/>
++ <reg32 offset="0x000e8" name="TIMING_CTRL_13"/>
++ <reg32 offset="0x000ec" name="GLBL_HSTX_STR_CTRL_0"/>
++ <reg32 offset="0x000f0" name="GLBL_HSTX_STR_CTRL_1"/>
++ <reg32 offset="0x000f4" name="GLBL_RESCODE_OFFSET_TOP_CTRL"/>
++ <reg32 offset="0x000f8" name="GLBL_RESCODE_OFFSET_BOT_CTRL"/>
++ <reg32 offset="0x000fc" name="GLBL_RESCODE_OFFSET_MID_CTRL"/>
++ <reg32 offset="0x00100" name="GLBL_LPTX_STR_CTRL"/>
++ <reg32 offset="0x00104" name="GLBL_PEMPH_CTRL_0"/>
++ <reg32 offset="0x00108" name="GLBL_PEMPH_CTRL_1"/>
++ <reg32 offset="0x0010c" name="GLBL_STR_SWI_CAL_SEL_CTRL"/>
++ <reg32 offset="0x00110" name="VREG_CTRL_1"/>
++ <reg32 offset="0x00114" name="CTRL_4"/>
++ <reg32 offset="0x00128" name="GLBL_DIGTOP_SPARE4"/>
++ <reg32 offset="0x00140" name="PHY_STATUS"/>
++ <reg32 offset="0x00148" name="LANE_STATUS0"/>
++ <reg32 offset="0x0014c" name="LANE_STATUS1"/>
++ <reg32 offset="0x001ac" name="GLBL_DIGTOP_SPARE10"/>
++</domain>
++
++<domain name="DSI_7nm_PHY" width="32">
++ <array offset="0x00000" name="LN" length="5" stride="0x80">
++ <reg32 offset="0x00" name="CFG0"/>
++ <reg32 offset="0x04" name="CFG1"/>
++ <reg32 offset="0x08" name="CFG2"/>
++ <reg32 offset="0x0c" name="TEST_DATAPATH"/>
++ <reg32 offset="0x10" name="PIN_SWAP"/>
++ <reg32 offset="0x14" name="LPRX_CTRL"/>
++ <reg32 offset="0x18" name="TX_DCTRL"/>
++ </array>
++</domain>
++
++<domain name="DSI_7nm_PHY_PLL" width="32">
++ <reg32 offset="0x0000" name="ANALOG_CONTROLS_ONE"/>
++ <reg32 offset="0x0004" name="ANALOG_CONTROLS_TWO"/>
++ <reg32 offset="0x0008" name="INT_LOOP_SETTINGS"/>
++ <reg32 offset="0x000c" name="INT_LOOP_SETTINGS_TWO"/>
++ <reg32 offset="0x0010" name="ANALOG_CONTROLS_THREE"/>
++ <reg32 offset="0x0014" name="ANALOG_CONTROLS_FOUR"/>
++ <reg32 offset="0x0018" name="ANALOG_CONTROLS_FIVE"/>
++ <reg32 offset="0x001c" name="INT_LOOP_CONTROLS"/>
++ <reg32 offset="0x0020" name="DSM_DIVIDER"/>
++ <reg32 offset="0x0024" name="FEEDBACK_DIVIDER"/>
++ <reg32 offset="0x0028" name="SYSTEM_MUXES"/>
++ <reg32 offset="0x002c" name="FREQ_UPDATE_CONTROL_OVERRIDES"/>
++ <reg32 offset="0x0030" name="CMODE"/>
++ <reg32 offset="0x0034" name="PSM_CTRL"/>
++ <reg32 offset="0x0038" name="RSM_CTRL"/>
++ <reg32 offset="0x003c" name="VCO_TUNE_MAP"/>
++ <reg32 offset="0x0040" name="PLL_CNTRL"/>
++ <reg32 offset="0x0044" name="CALIBRATION_SETTINGS"/>
++ <reg32 offset="0x0048" name="BAND_SEL_CAL_TIMER_LOW"/>
++ <reg32 offset="0x004c" name="BAND_SEL_CAL_TIMER_HIGH"/>
++ <reg32 offset="0x0050" name="BAND_SEL_CAL_SETTINGS"/>
++ <reg32 offset="0x0054" name="BAND_SEL_MIN"/>
++ <reg32 offset="0x0058" name="BAND_SEL_MAX"/>
++ <reg32 offset="0x005c" name="BAND_SEL_PFILT"/>
++ <reg32 offset="0x0060" name="BAND_SEL_IFILT"/>
++ <reg32 offset="0x0064" name="BAND_SEL_CAL_SETTINGS_TWO"/>
++ <reg32 offset="0x0068" name="BAND_SEL_CAL_SETTINGS_THREE"/>
++ <reg32 offset="0x006c" name="BAND_SEL_CAL_SETTINGS_FOUR"/>
++ <reg32 offset="0x0070" name="BAND_SEL_ICODE_HIGH"/>
++ <reg32 offset="0x0074" name="BAND_SEL_ICODE_LOW"/>
++ <reg32 offset="0x0078" name="FREQ_DETECT_SETTINGS_ONE"/>
++ <reg32 offset="0x007c" name="FREQ_DETECT_THRESH"/>
++ <reg32 offset="0x0080" name="FREQ_DET_REFCLK_HIGH"/>
++ <reg32 offset="0x0084" name="FREQ_DET_REFCLK_LOW"/>
++ <reg32 offset="0x0088" name="FREQ_DET_PLLCLK_HIGH"/>
++ <reg32 offset="0x008c" name="FREQ_DET_PLLCLK_LOW"/>
++ <reg32 offset="0x0090" name="PFILT"/>
++ <reg32 offset="0x0094" name="IFILT"/>
++ <reg32 offset="0x0098" name="PLL_GAIN"/>
++ <reg32 offset="0x009c" name="ICODE_LOW"/>
++ <reg32 offset="0x00a0" name="ICODE_HIGH"/>
++ <reg32 offset="0x00a4" name="LOCKDET"/>
++ <reg32 offset="0x00a8" name="OUTDIV"/>
++ <reg32 offset="0x00ac" name="FASTLOCK_CONTROL"/>
++ <reg32 offset="0x00b0" name="PASS_OUT_OVERRIDE_ONE"/>
++ <reg32 offset="0x00b4" name="PASS_OUT_OVERRIDE_TWO"/>
++ <reg32 offset="0x00b8" name="CORE_OVERRIDE"/>
++ <reg32 offset="0x00bc" name="CORE_INPUT_OVERRIDE"/>
++ <reg32 offset="0x00c0" name="RATE_CHANGE"/>
++ <reg32 offset="0x00c4" name="PLL_DIGITAL_TIMERS"/>
++ <reg32 offset="0x00c8" name="PLL_DIGITAL_TIMERS_TWO"/>
++ <reg32 offset="0x00cc" name="DECIMAL_DIV_START"/>
++ <reg32 offset="0x00d0" name="FRAC_DIV_START_LOW"/>
++ <reg32 offset="0x00d4" name="FRAC_DIV_START_MID"/>
++ <reg32 offset="0x00d8" name="FRAC_DIV_START_HIGH"/>
++ <reg32 offset="0x00dc" name="DEC_FRAC_MUXES"/>
++ <reg32 offset="0x00e0" name="DECIMAL_DIV_START_1"/>
++ <reg32 offset="0x00e4" name="FRAC_DIV_START_LOW_1"/>
++ <reg32 offset="0x00e8" name="FRAC_DIV_START_MID_1"/>
++ <reg32 offset="0x00ec" name="FRAC_DIV_START_HIGH_1"/>
++ <reg32 offset="0x00f0" name="DECIMAL_DIV_START_2"/>
++ <reg32 offset="0x00f4" name="FRAC_DIV_START_LOW_2"/>
++ <reg32 offset="0x00f8" name="FRAC_DIV_START_MID_2"/>
++ <reg32 offset="0x00fc" name="FRAC_DIV_START_HIGH_2"/>
++ <reg32 offset="0x0100" name="MASH_CONTROL"/>
++ <reg32 offset="0x0104" name="SSC_STEPSIZE_LOW"/>
++ <reg32 offset="0x0108" name="SSC_STEPSIZE_HIGH"/>
++ <reg32 offset="0x010c" name="SSC_DIV_PER_LOW"/>
++ <reg32 offset="0x0110" name="SSC_DIV_PER_HIGH"/>
++ <reg32 offset="0x0114" name="SSC_ADJPER_LOW"/>
++ <reg32 offset="0x0118" name="SSC_ADJPER_HIGH"/>
++ <reg32 offset="0x011c" name="SSC_MUX_CONTROL"/>
++ <reg32 offset="0x0120" name="SSC_STEPSIZE_LOW_1"/>
++ <reg32 offset="0x0124" name="SSC_STEPSIZE_HIGH_1"/>
++ <reg32 offset="0x0128" name="SSC_DIV_PER_LOW_1"/>
++ <reg32 offset="0x012c" name="SSC_DIV_PER_HIGH_1"/>
++ <reg32 offset="0x0130" name="SSC_ADJPER_LOW_1"/>
++ <reg32 offset="0x0134" name="SSC_ADJPER_HIGH_1"/>
++ <reg32 offset="0x0138" name="SSC_STEPSIZE_LOW_2"/>
++ <reg32 offset="0x013c" name="SSC_STEPSIZE_HIGH_2"/>
++ <reg32 offset="0x0140" name="SSC_DIV_PER_LOW_2"/>
++ <reg32 offset="0x0144" name="SSC_DIV_PER_HIGH_2"/>
++ <reg32 offset="0x0148" name="SSC_ADJPER_LOW_2"/>
++ <reg32 offset="0x014c" name="SSC_ADJPER_HIGH_2"/>
++ <reg32 offset="0x0150" name="SSC_CONTROL"/>
++ <reg32 offset="0x0154" name="PLL_OUTDIV_RATE"/>
++ <reg32 offset="0x0158" name="PLL_LOCKDET_RATE_1"/>
++ <reg32 offset="0x015c" name="PLL_LOCKDET_RATE_2"/>
++ <reg32 offset="0x0160" name="PLL_PROP_GAIN_RATE_1"/>
++ <reg32 offset="0x0164" name="PLL_PROP_GAIN_RATE_2"/>
++ <reg32 offset="0x0168" name="PLL_BAND_SEL_RATE_1"/>
++ <reg32 offset="0x016c" name="PLL_BAND_SEL_RATE_2"/>
++ <reg32 offset="0x0170" name="PLL_INT_GAIN_IFILT_BAND_1"/>
++ <reg32 offset="0x0174" name="PLL_INT_GAIN_IFILT_BAND_2"/>
++ <reg32 offset="0x0178" name="PLL_FL_INT_GAIN_PFILT_BAND_1"/>
++ <reg32 offset="0x017c" name="PLL_FL_INT_GAIN_PFILT_BAND_2"/>
++ <reg32 offset="0x0180" name="PLL_FASTLOCK_EN_BAND"/>
++ <reg32 offset="0x0184" name="FREQ_TUNE_ACCUM_INIT_MID"/>
++ <reg32 offset="0x0188" name="FREQ_TUNE_ACCUM_INIT_HIGH"/>
++ <reg32 offset="0x018c" name="FREQ_TUNE_ACCUM_INIT_MUX"/>
++ <reg32 offset="0x0190" name="PLL_LOCK_OVERRIDE"/>
++ <reg32 offset="0x0194" name="PLL_LOCK_DELAY"/>
++ <reg32 offset="0x0198" name="PLL_LOCK_MIN_DELAY"/>
++ <reg32 offset="0x019c" name="CLOCK_INVERTERS"/>
++ <reg32 offset="0x01a0" name="SPARE_AND_JPC_OVERRIDES"/>
++ <reg32 offset="0x01a4" name="BIAS_CONTROL_1"/>
++ <reg32 offset="0x01a8" name="BIAS_CONTROL_2"/>
++ <reg32 offset="0x01ac" name="ALOG_OBSV_BUS_CTRL_1"/>
++ <reg32 offset="0x01b0" name="COMMON_STATUS_ONE"/>
++ <reg32 offset="0x01b4" name="COMMON_STATUS_TWO"/>
++ <reg32 offset="0x01b8" name="BAND_SEL_CAL"/>
++ <reg32 offset="0x01bc" name="ICODE_ACCUM_STATUS_LOW"/>
++ <reg32 offset="0x01c0" name="ICODE_ACCUM_STATUS_HIGH"/>
++ <reg32 offset="0x01c4" name="FD_OUT_LOW"/>
++ <reg32 offset="0x01c8" name="FD_OUT_HIGH"/>
++ <reg32 offset="0x01cc" name="ALOG_OBSV_BUS_STATUS_1"/>
++ <reg32 offset="0x01d0" name="PLL_MISC_CONFIG"/>
++ <reg32 offset="0x01d4" name="FLL_CONFIG"/>
++ <reg32 offset="0x01d8" name="FLL_FREQ_ACQ_TIME"/>
++ <reg32 offset="0x01dc" name="FLL_CODE0"/>
++ <reg32 offset="0x01e0" name="FLL_CODE1"/>
++ <reg32 offset="0x01e4" name="FLL_GAIN0"/>
++ <reg32 offset="0x01e8" name="FLL_GAIN1"/>
++ <reg32 offset="0x01ec" name="SW_RESET"/>
++ <reg32 offset="0x01f0" name="FAST_PWRUP"/>
++ <reg32 offset="0x01f4" name="LOCKTIME0"/>
++ <reg32 offset="0x01f8" name="LOCKTIME1"/>
++ <reg32 offset="0x01fc" name="DEBUG_BUS_SEL"/>
++ <reg32 offset="0x0200" name="DEBUG_BUS0"/>
++ <reg32 offset="0x0204" name="DEBUG_BUS1"/>
++ <reg32 offset="0x0208" name="DEBUG_BUS2"/>
++ <reg32 offset="0x020c" name="DEBUG_BUS3"/>
++ <reg32 offset="0x0210" name="ANALOG_FLL_CONTROL_OVERRIDES"/>
++ <reg32 offset="0x0214" name="VCO_CONFIG"/>
++ <reg32 offset="0x0218" name="VCO_CAL_CODE1_MODE0_STATUS"/>
++ <reg32 offset="0x021c" name="VCO_CAL_CODE1_MODE1_STATUS"/>
++ <reg32 offset="0x0220" name="RESET_SM_STATUS"/>
++ <reg32 offset="0x0224" name="TDC_OFFSET"/>
++ <reg32 offset="0x0228" name="PS3_PWRDOWN_CONTROLS"/>
++ <reg32 offset="0x022c" name="PS4_PWRDOWN_CONTROLS"/>
++ <reg32 offset="0x0230" name="PLL_RST_CONTROLS"/>
++ <reg32 offset="0x0234" name="GEAR_BAND_SELECT_CONTROLS"/>
++ <reg32 offset="0x0238" name="PSM_CLK_CONTROLS"/>
++ <reg32 offset="0x023c" name="SYSTEM_MUXES_2"/>
++ <reg32 offset="0x0240" name="VCO_CONFIG_1"/>
++ <reg32 offset="0x0244" name="VCO_CONFIG_2"/>
++ <reg32 offset="0x0248" name="CLOCK_INVERTERS_1"/>
++ <reg32 offset="0x024c" name="CLOCK_INVERTERS_2"/>
++ <reg32 offset="0x0250" name="CMODE_1"/>
++ <reg32 offset="0x0254" name="CMODE_2"/>
++ <reg32 offset="0x0258" name="ANALOG_CONTROLS_FIVE_1"/>
++ <reg32 offset="0x025c" name="ANALOG_CONTROLS_FIVE_2"/>
++ <reg32 offset="0x0260" name="PERF_OPTIMIZE"/>
++</domain>
++
++</database>
+diff --git a/drivers/gpu/drm/msm/registers/display/edp.xml b/drivers/gpu/drm/msm/registers/display/edp.xml
+new file mode 100644
+index 0000000000000..354f90eb6de52
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/display/edp.xml
+@@ -0,0 +1,239 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++
++<domain name="EDP" width="32">
++ <enum name="edp_color_depth">
++ <value name="EDP_6BIT" value="0"/>
++ <value name="EDP_8BIT" value="1"/>
++ <value name="EDP_10BIT" value="2"/>
++ <value name="EDP_12BIT" value="3"/>
++ <value name="EDP_16BIT" value="4"/>
++ </enum>
++
++ <enum name="edp_component_format">
++ <value name="EDP_RGB" value="0"/>
++ <value name="EDP_YUV422" value="1"/>
++ <value name="EDP_YUV444" value="2"/>
++ </enum>
++
++ <reg32 offset="0x0004" name="MAINLINK_CTRL">
++ <bitfield name="ENABLE" pos="0" type="boolean"/>
++ <bitfield name="RESET" pos="1" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x0008" name="STATE_CTRL">
++ <bitfield name="TRAIN_PATTERN_1" pos="0" type="boolean"/>
++ <bitfield name="TRAIN_PATTERN_2" pos="1" type="boolean"/>
++ <bitfield name="TRAIN_PATTERN_3" pos="2" type="boolean"/>
++ <bitfield name="SYMBOL_ERR_RATE_MEAS" pos="3" type="boolean"/>
++ <bitfield name="PRBS7" pos="4" type="boolean"/>
++ <bitfield name="CUSTOM_80_BIT_PATTERN" pos="5" type="boolean"/>
++ <bitfield name="SEND_VIDEO" pos="6" type="boolean"/>
++ <bitfield name="PUSH_IDLE" pos="7" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x000c" name="CONFIGURATION_CTRL">
++ <!-- next two may be swapped? -->
++ <bitfield name="SYNC_CLK" pos="0" type="boolean"/>
++ <bitfield name="STATIC_MVID" pos="1" type="boolean"/>
++ <bitfield name="PROGRESSIVE" pos="2" type="boolean"/>
++ <!-- # of lanes minus one: -->
++ <bitfield name="LANES" low="4" high="5" type="uint"/>
++ <bitfield name="ENHANCED_FRAMING" pos="6" type="boolean"/>
++ <!--
++ NOTE: only 6bit and 8bit valid
++ -->
++ <bitfield name="COLOR" pos="8" type="edp_color_depth"/>
++ </reg32>
++
++ <reg32 offset="0x0014" name="SOFTWARE_MVID" type="uint"/>
++ <reg32 offset="0x0018" name="SOFTWARE_NVID" type="uint"/>
++
++ <reg32 offset="0x001c" name="TOTAL_HOR_VER">
++ <bitfield name="HORIZ" low="0" high="15" type="uint"/>
++ <bitfield name="VERT" low="16" high="31" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x0020" name="START_HOR_VER_FROM_SYNC">
++ <bitfield name="HORIZ" low="0" high="15" type="uint"/>
++ <bitfield name="VERT" low="16" high="31" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x0024" name="HSYNC_VSYNC_WIDTH_POLARITY">
++ <bitfield name="HORIZ" low="0" high="14" type="uint"/>
++ <bitfield name="NHSYNC" pos="15" type="boolean"/>
++ <bitfield name="VERT" low="16" high="30" type="uint"/>
++ <bitfield name="NVSYNC" pos="31" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x0028" name="ACTIVE_HOR_VER">
++ <bitfield name="HORIZ" low="0" high="15" type="uint"/>
++ <bitfield name="VERT" low="16" high="31" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x002c" name="MISC1_MISC0">
++ <!-- MISC0 from DisplayPort v1.2 spec: -->
++ <bitfield name="MISC0" low="0" high="7"/>
++ <!-- aliased MISC0 bitfields: -->
++ <bitfield name="SYNC" pos="0" type="boolean"/>
++ <bitfield name="COMPONENT_FORMAT" low="1" high="2" type="edp_component_format"/>
++ <!-- CEA (vs VESA) color range: -->
++ <bitfield name="CEA" pos="3" type="boolean"/>
++ <!-- YCbCr Colorimetry ITU-R BT709-5 (vs ITU-R BT601-5): -->
++ <bitfield name="BT709_5" pos="4" type="boolean"/>
++ <bitfield name="COLOR" low="5" high="7" type="edp_color_depth"/>
++
++ <!-- MISC1 from DisplayPort v1.2 spec: -->
++ <bitfield name="MISC1" low="8" high="15"/>
++ <!-- aliased MISC1 bitfields: -->
++ <bitfield name="INTERLACED_ODD" pos="8" type="boolean"/>
++ <bitfield name="STEREO" low="9" high="10" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x0074" name="PHY_CTRL">
++ <bitfield name="SW_RESET_PLL" pos="0" type="boolean"/>
++ <bitfield name="SW_RESET" pos="2" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0084" name="MAINLINK_READY">
++ <bitfield name="TRAIN_PATTERN_1_READY" pos="3" type="boolean"/>
++ <bitfield name="TRAIN_PATTERN_2_READY" pos="4" type="boolean"/>
++ <bitfield name="TRAIN_PATTERN_3_READY" pos="5" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x0300" name="AUX_CTRL">
++ <bitfield name="ENABLE" pos="0" type="boolean"/>
++ <bitfield name="RESET" pos="1" type="boolean"/>
++ </reg32>
++
++ <!-- interrupt registers come in sets of 3 bits, status/ack/en -->
++ <reg32 offset="0x0308" name="INTERRUPT_REG_1">
++ <bitfield name="HPD" pos="0" type="boolean"/>
++ <bitfield name="HPD_ACK" pos="1" type="boolean"/>
++ <bitfield name="HPD_EN" pos="2" type="boolean"/>
++ <bitfield name="AUX_I2C_DONE" pos="3" type="boolean"/>
++ <bitfield name="AUX_I2C_DONE_ACK" pos="4" type="boolean"/>
++ <bitfield name="AUX_I2C_DONE_EN" pos="5" type="boolean"/>
++ <bitfield name="WRONG_ADDR" pos="6" type="boolean"/>
++ <bitfield name="WRONG_ADDR_ACK" pos="7" type="boolean"/>
++ <bitfield name="WRONG_ADDR_EN" pos="8" type="boolean"/>
++ <bitfield name="TIMEOUT" pos="9" type="boolean"/>
++ <bitfield name="TIMEOUT_ACK" pos="10" type="boolean"/>
++ <bitfield name="TIMEOUT_EN" pos="11" type="boolean"/>
++ <bitfield name="NACK_DEFER" pos="12" type="boolean"/>
++ <bitfield name="NACK_DEFER_ACK" pos="13" type="boolean"/>
++ <bitfield name="NACK_DEFER_EN" pos="14" type="boolean"/>
++ <bitfield name="WRONG_DATA_CNT" pos="15" type="boolean"/>
++ <bitfield name="WRONG_DATA_CNT_ACK" pos="16" type="boolean"/>
++ <bitfield name="WRONG_DATA_CNT_EN" pos="17" type="boolean"/>
++ <bitfield name="I2C_NACK" pos="18" type="boolean"/>
++ <bitfield name="I2C_NACK_ACK" pos="19" type="boolean"/>
++ <bitfield name="I2C_NACK_EN" pos="20" type="boolean"/>
++ <bitfield name="I2C_DEFER" pos="21" type="boolean"/>
++ <bitfield name="I2C_DEFER_ACK" pos="22" type="boolean"/>
++ <bitfield name="I2C_DEFER_EN" pos="23" type="boolean"/>
++ <bitfield name="PLL_UNLOCK" pos="24" type="boolean"/>
++ <bitfield name="PLL_UNLOCK_ACK" pos="25" type="boolean"/>
++ <bitfield name="PLL_UNLOCK_EN" pos="26" type="boolean"/>
++ <bitfield name="AUX_ERROR" pos="27" type="boolean"/>
++ <bitfield name="AUX_ERROR_ACK" pos="28" type="boolean"/>
++ <bitfield name="AUX_ERROR_EN" pos="29" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x030c" name="INTERRUPT_REG_2">
++ <bitfield name="READY_FOR_VIDEO" pos="0" type="boolean"/>
++ <bitfield name="READY_FOR_VIDEO_ACK" pos="1" type="boolean"/>
++ <bitfield name="READY_FOR_VIDEO_EN" pos="2" type="boolean"/>
++ <bitfield name="IDLE_PATTERNs_SENT" pos="3" type="boolean"/>
++ <bitfield name="IDLE_PATTERNs_SENT_ACK" pos="4" type="boolean"/>
++ <bitfield name="IDLE_PATTERNs_SENT_EN" pos="5" type="boolean"/>
++ <bitfield name="FRAME_END" pos="9" type="boolean"/>
++ <bitfield name="FRAME_END_ACK" pos="7" type="boolean"/>
++ <bitfield name="FRAME_END_EN" pos="8" type="boolean"/>
++ <bitfield name="CRC_UPDATED" pos="9" type="boolean"/>
++ <bitfield name="CRC_UPDATED_ACK" pos="10" type="boolean"/>
++ <bitfield name="CRC_UPDATED_EN" pos="11" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x0310" name="INTERRUPT_TRANS_NUM"/>
++ <reg32 offset="0x0314" name="AUX_DATA">
++ <bitfield name="READ" pos="0" type="boolean"/>
++ <bitfield name="DATA" low="8" high="15"/>
++ <bitfield name="INDEX" low="16" high="23"/>
++ <bitfield name="INDEX_WRITE" pos="31" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x0318" name="AUX_TRANS_CTRL">
++ <bitfield name="I2C" pos="8" type="boolean"/>
++ <bitfield name="GO" pos="9" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x0324" name="AUX_STATUS"/>
++</domain>
++
++<domain name="EDP_PHY" width="32">
++ <array offset="0x0400" name="LN" length="4" stride="0x40">
++ <reg32 offset="0x04" name="PD_CTL"/>
++ </array>
++ <reg32 offset="0x0510" name="GLB_VM_CFG0"/>
++ <reg32 offset="0x0514" name="GLB_VM_CFG1"/>
++ <reg32 offset="0x0518" name="GLB_MISC9"/>
++ <reg32 offset="0x0528" name="GLB_CFG"/>
++ <reg32 offset="0x052c" name="GLB_PD_CTL"/>
++ <reg32 offset="0x0598" name="GLB_PHY_STATUS"/>
++</domain>
++
++<domain name="EDP_28nm_PHY_PLL" width="32">
++ <reg32 offset="0x00000" name="REFCLK_CFG"/>
++ <reg32 offset="0x00004" name="POSTDIV1_CFG"/>
++ <reg32 offset="0x00008" name="CHGPUMP_CFG"/>
++ <reg32 offset="0x0000C" name="VCOLPF_CFG"/>
++ <reg32 offset="0x00010" name="VREG_CFG"/>
++ <reg32 offset="0x00014" name="PWRGEN_CFG"/>
++ <reg32 offset="0x00018" name="DMUX_CFG"/>
++ <reg32 offset="0x0001C" name="AMUX_CFG"/>
++ <reg32 offset="0x00020" name="GLB_CFG">
++ <bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/>
++ <bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/>
++ <bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/>
++ <bitfield name="PLL_ENABLE" pos="3" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00024" name="POSTDIV2_CFG"/>
++ <reg32 offset="0x00028" name="POSTDIV3_CFG"/>
++ <reg32 offset="0x0002C" name="LPFR_CFG"/>
++ <reg32 offset="0x00030" name="LPFC1_CFG"/>
++ <reg32 offset="0x00034" name="LPFC2_CFG"/>
++ <reg32 offset="0x00038" name="SDM_CFG0"/>
++ <reg32 offset="0x0003C" name="SDM_CFG1"/>
++ <reg32 offset="0x00040" name="SDM_CFG2"/>
++ <reg32 offset="0x00044" name="SDM_CFG3"/>
++ <reg32 offset="0x00048" name="SDM_CFG4"/>
++ <reg32 offset="0x0004C" name="SSC_CFG0"/>
++ <reg32 offset="0x00050" name="SSC_CFG1"/>
++ <reg32 offset="0x00054" name="SSC_CFG2"/>
++ <reg32 offset="0x00058" name="SSC_CFG3"/>
++ <reg32 offset="0x0005C" name="LKDET_CFG0"/>
++ <reg32 offset="0x00060" name="LKDET_CFG1"/>
++ <reg32 offset="0x00064" name="LKDET_CFG2"/>
++ <reg32 offset="0x00068" name="TEST_CFG">
++ <bitfield name="PLL_SW_RESET" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0006C" name="CAL_CFG0"/>
++ <reg32 offset="0x00070" name="CAL_CFG1"/>
++ <reg32 offset="0x00074" name="CAL_CFG2"/>
++ <reg32 offset="0x00078" name="CAL_CFG3"/>
++ <reg32 offset="0x0007C" name="CAL_CFG4"/>
++ <reg32 offset="0x00080" name="CAL_CFG5"/>
++ <reg32 offset="0x00084" name="CAL_CFG6"/>
++ <reg32 offset="0x00088" name="CAL_CFG7"/>
++ <reg32 offset="0x0008C" name="CAL_CFG8"/>
++ <reg32 offset="0x00090" name="CAL_CFG9"/>
++ <reg32 offset="0x00094" name="CAL_CFG10"/>
++ <reg32 offset="0x00098" name="CAL_CFG11"/>
++ <reg32 offset="0x0009C" name="EFUSE_CFG"/>
++ <reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/>
++</domain>
++
++</database>
+diff --git a/drivers/gpu/drm/msm/registers/display/hdmi.xml b/drivers/gpu/drm/msm/registers/display/hdmi.xml
+new file mode 100644
+index 0000000000000..6c81581016c78
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/display/hdmi.xml
+@@ -0,0 +1,1015 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++
++<!--
++ NOTE: also see mdss_hdmi_util.h.. newer devices using MDSS appear
++ to have the same HDMI block (or maybe a newer version?) but for
++ some reason duplicate the code under drivers/video/msm/mdss
++ -->
++
++<domain name="HDMI" width="32">
++ <enum name="hdmi_hdcp_key_state">
++ <value name="HDCP_KEYS_STATE_NO_KEYS" value="0"/>
++ <value name="HDCP_KEYS_STATE_NOT_CHECKED" value="1"/>
++ <value name="HDCP_KEYS_STATE_CHECKING" value="2"/>
++ <value name="HDCP_KEYS_STATE_VALID" value="3"/>
++ <value name="HDCP_KEYS_STATE_AKSV_NOT_VALID" value="4"/>
++ <value name="HDCP_KEYS_STATE_CHKSUM_MISMATCH" value="5"/>
++ <value name="HDCP_KEYS_STATE_PROD_AKSV" value="6"/>
++ <value name="HDCP_KEYS_STATE_RESERVED" value="7"/>
++ </enum>
++ <enum name="hdmi_ddc_read_write">
++ <value name="DDC_WRITE" value="0"/>
++ <value name="DDC_READ" value="1"/>
++ </enum>
++ <enum name="hdmi_acr_cts">
++ <value name="ACR_NONE" value="0"/>
++ <value name="ACR_32" value="1"/>
++ <value name="ACR_44" value="2"/>
++ <value name="ACR_48" value="3"/>
++ </enum>
++
++ <enum name="hdmi_cec_tx_status">
++ <value name="CEC_TX_OK" value="0"/>
++ <value name="CEC_TX_NACK" value="1"/>
++ <value name="CEC_TX_ARB_LOSS" value="2"/>
++ <value name="CEC_TX_MAX_RETRIES" value="3"/>
++ </enum>
++
++ <reg32 offset="0x00000" name="CTRL">
++ <bitfield name="ENABLE" pos="0" type="boolean"/>
++ <bitfield name="HDMI" pos="1" type="boolean"/>
++ <bitfield name="ENCRYPTED" pos="2" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00020" name="AUDIO_PKT_CTRL1">
++ <bitfield name="AUDIO_SAMPLE_SEND" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00024" name="ACR_PKT_CTRL">
++ <!--
++ Guessing on order of bitfields from these comments:
++ /* AUDIO_PRIORITY | SOURCE */
++ acr_pck_ctrl_reg |= 0x80000100;
++ /* N_MULTIPLE(multiplier) */
++ acr_pck_ctrl_reg |= (multiplier & 7) << 16;
++ /* SEND | CONT */
++ acr_pck_ctrl_reg |= 0x00000003;
++ -->
++ <bitfield name="CONT" pos="0" type="boolean"/>
++ <bitfield name="SEND" pos="1" type="boolean"/>
++ <bitfield name="SELECT" low="4" high="5" type="hdmi_acr_cts"/>
++ <bitfield name="SOURCE" pos="8" type="boolean"/>
++ <bitfield name="N_MULTIPLIER" low="16" high="18" type="uint"/>
++ <bitfield name="AUDIO_PRIORITY" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0028" name="VBI_PKT_CTRL">
++ <!--
++ Guessing on the order of bits from:
++ /* GC packet enable (every frame) */
++ /* HDMI_VBI_PKT_CTRL[0x0028] */
++ hdmi_msm_rmw32or(0x0028, 3 << 4);
++ /* HDMI_VBI_PKT_CTRL[0x0028] */
++ /* ISRC Send + Continuous */
++ hdmi_msm_rmw32or(0x0028, 3 << 8);
++ /* HDMI_VBI_PKT_CTRL[0x0028] */
++ /* ACP send, s/w source */
++ hdmi_msm_rmw32or(0x0028, 3 << 12);
++ -->
++ <bitfield name="GC_ENABLE" pos="4" type="boolean"/>
++ <bitfield name="GC_EVERY_FRAME" pos="5" type="boolean"/>
++ <bitfield name="ISRC_SEND" pos="8" type="boolean"/>
++ <bitfield name="ISRC_CONTINUOUS" pos="9" type="boolean"/>
++ <bitfield name="ACP_SEND" pos="12" type="boolean"/>
++ <bitfield name="ACP_SRC_SW" pos="13" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0002c" name="INFOFRAME_CTRL0">
++ <!--
++ Guessing on the order of these flags, from this comment:
++ /* Set these flags */
++ /* AUDIO_INFO_UPDATE | AUDIO_INFO_SOURCE | AUDIO_INFO_CONT
++ | AUDIO_INFO_SEND */
++ audio_info_ctrl_reg |= 0x000000F0;
++ /* 0x3 for AVI InfFrame enable (every frame) */
++ HDMI_OUTP(0x002C, HDMI_INP(0x002C) | 0x00000003L);
++ -->
++ <bitfield name="AVI_SEND" pos="0" type="boolean"/>
++ <bitfield name="AVI_CONT" pos="1" type="boolean"/> <!-- every frame -->
++ <bitfield name="AUDIO_INFO_SEND" pos="4" type="boolean"/>
++ <bitfield name="AUDIO_INFO_CONT" pos="5" type="boolean"/> <!-- every frame -->
++ <bitfield name="AUDIO_INFO_SOURCE" pos="6" type="boolean"/>
++ <bitfield name="AUDIO_INFO_UPDATE" pos="7" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00030" name="INFOFRAME_CTRL1">
++ <bitfield name="AVI_INFO_LINE" low="0" high="5" type="uint"/>
++ <bitfield name="AUDIO_INFO_LINE" low="8" high="13" type="uint"/>
++ <bitfield name="MPEG_INFO_LINE" low="16" high="21" type="uint"/>
++ <bitfield name="VENSPEC_INFO_LINE" low="24" high="29" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00034" name="GEN_PKT_CTRL">
++ <!--
++ 0x0034 GEN_PKT_CTRL
++ GENERIC0_SEND 0 0 = Disable Generic0 Packet Transmission
++ 1 = Enable Generic0 Packet Transmission
++ GENERIC0_CONT 1 0 = Send Generic0 Packet on next frame only
++ 1 = Send Generic0 Packet on every frame
++ GENERIC0_UPDATE 2 NUM
++ GENERIC1_SEND 4 0 = Disable Generic1 Packet Transmission
++ 1 = Enable Generic1 Packet Transmission
++ GENERIC1_CONT 5 0 = Send Generic1 Packet on next frame only
++ 1 = Send Generic1 Packet on every frame
++ GENERIC0_LINE 21:16 NUM
++ GENERIC1_LINE 29:24 NUM
++
++ GENERIC0_LINE | GENERIC0_UPDATE | GENERIC0_CONT | GENERIC0_SEND
++ Setup HDMI TX generic packet control
++ Enable this packet to transmit every frame
++ Enable this packet to transmit every frame
++ Enable HDMI TX engine to transmit Generic packet 0
++ HDMI_OUTP(0x0034, (1 << 16) | (1 << 2) | BIT(1) | BIT(0));
++ -->
++ <bitfield name="GENERIC0_SEND" pos="0" type="boolean"/>
++ <bitfield name="GENERIC0_CONT" pos="1" type="boolean"/>
++ <bitfield name="GENERIC0_UPDATE" low="2" high="3" type="uint"/> <!-- ??? -->
++ <bitfield name="GENERIC1_SEND" pos="4" type="boolean"/>
++ <bitfield name="GENERIC1_CONT" pos="5" type="boolean"/>
++ <bitfield name="GENERIC0_LINE" low="16" high="21" type="uint"/>
++ <bitfield name="GENERIC1_LINE" low="24" high="29" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00040" name="GC">
++ <bitfield name="MUTE" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00044" name="AUDIO_PKT_CTRL2">
++ <bitfield name="OVERRIDE" pos="0" type="boolean"/>
++ <bitfield name="LAYOUT" pos="1" type="boolean"/> <!-- 1 for >2 channels -->
++ </reg32>
++
++ <!--
++ AVI_INFO appears to be the infoframe in a slightly weird order..
++ starts with PB0 (checksum), and ends with version..
++ -->
++ <reg32 offset="0x0006c" name="AVI_INFO" stride="4" length="4"/>
++
++ <reg32 offset="0x00084" name="GENERIC0_HDR"/>
++ <reg32 offset="0x00088" name="GENERIC0" stride="4" length="7"/>
++
++ <reg32 offset="0x000a4" name="GENERIC1_HDR"/>
++ <reg32 offset="0x000a8" name="GENERIC1" stride="4" length="7"/>
++
++ <!--
++ TODO add a way to show symbolic offsets into array: hdmi_acr_cts-1
++ -->
++ <array offset="0x00c4" name="ACR" length="3" stride="8" index="hdmi_acr_cts">
++ <reg32 offset="0" name="0">
++ <bitfield name="CTS" low="12" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="4" name="1">
++ <!-- not sure the actual # of bits.. -->
++ <bitfield name="N" low="0" high="31" type="uint"/>
++ </reg32>
++ </array>
++
++ <reg32 offset="0x000e4" name="AUDIO_INFO0">
++ <bitfield name="CHECKSUM" low="0" high="7"/>
++ <bitfield name="CC" low="8" high="10" type="uint"/> <!-- channel count -->
++ </reg32>
++ <reg32 offset="0x000e8" name="AUDIO_INFO1">
++ <bitfield name="CA" low="0" high="7"/> <!-- Channel Allocation -->
++ <bitfield name="LSV" low="11" high="14"/> <!-- Level Shift -->
++ <bitfield name="DM_INH" pos="15" type="boolean"/> <!-- down-mix inhibit flag -->
++ </reg32>
++ <reg32 offset="0x00110" name="HDCP_CTRL">
++ <bitfield name="ENABLE" pos="0" type="boolean"/>
++ <bitfield name="ENCRYPTION_ENABLE" pos="8" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00114" name="HDCP_DEBUG_CTRL">
++ <bitfield name="RNG_CIPHER" pos="2" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00118" name="HDCP_INT_CTRL">
++ <bitfield name="AUTH_SUCCESS_INT" pos="0" type="boolean"/>
++ <bitfield name="AUTH_SUCCESS_ACK" pos="1" type="boolean"/>
++ <bitfield name="AUTH_SUCCESS_MASK" pos="2" type="boolean"/>
++ <bitfield name="AUTH_FAIL_INT" pos="4" type="boolean"/>
++ <bitfield name="AUTH_FAIL_ACK" pos="5" type="boolean"/>
++ <bitfield name="AUTH_FAIL_MASK" pos="6" type="boolean"/>
++ <bitfield name="AUTH_FAIL_INFO_ACK" pos="7" type="boolean"/>
++ <bitfield name="AUTH_XFER_REQ_INT" pos="8" type="boolean"/>
++ <bitfield name="AUTH_XFER_REQ_ACK" pos="9" type="boolean"/>
++ <bitfield name="AUTH_XFER_REQ_MASK" pos="10" type="boolean"/>
++ <bitfield name="AUTH_XFER_DONE_INT" pos="12" type="boolean"/>
++ <bitfield name="AUTH_XFER_DONE_ACK" pos="13" type="boolean"/>
++ <bitfield name="AUTH_XFER_DONE_MASK" pos="14" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0011c" name="HDCP_LINK0_STATUS">
++ <bitfield name="AN_0_READY" pos="8" type="boolean"/>
++ <bitfield name="AN_1_READY" pos="9" type="boolean"/>
++ <bitfield name="RI_MATCHES" pos="12" type="boolean"/>
++ <bitfield name="V_MATCHES" pos="20" type="boolean"/>
++ <bitfield name="KEY_STATE" low="28" high="30" type="hdmi_hdcp_key_state"/>
++ </reg32>
++ <reg32 offset="0x00120" name="HDCP_DDC_CTRL_0">
++ <bitfield name="DISABLE" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00124" name="HDCP_DDC_CTRL_1">
++ <bitfield name="FAILED_ACK" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00128" name="HDCP_DDC_STATUS">
++ <bitfield name="XFER_REQ" pos="4" type="boolean"/>
++ <bitfield name="XFER_DONE" pos="10" type="boolean"/>
++ <bitfield name="ABORTED" pos="12" type="boolean"/>
++ <bitfield name="TIMEOUT" pos="13" type="boolean"/>
++ <bitfield name="NACK0" pos="14" type="boolean"/>
++ <bitfield name="NACK1" pos="15" type="boolean"/>
++ <bitfield name="FAILED" pos="16" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x0012c" name="HDCP_ENTROPY_CTRL0"/>
++ <reg32 offset="0x0025c" name="HDCP_ENTROPY_CTRL1"/>
++
++ <reg32 offset="0x00130" name="HDCP_RESET">
++ <bitfield name="LINK0_DEAUTHENTICATE" pos="0" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x00134" name="HDCP_RCVPORT_DATA0"/>
++ <reg32 offset="0x00138" name="HDCP_RCVPORT_DATA1"/>
++ <reg32 offset="0x0013C" name="HDCP_RCVPORT_DATA2_0"/>
++ <reg32 offset="0x00140" name="HDCP_RCVPORT_DATA2_1"/>
++ <reg32 offset="0x00144" name="HDCP_RCVPORT_DATA3"/>
++ <reg32 offset="0x00148" name="HDCP_RCVPORT_DATA4"/>
++ <reg32 offset="0x0014c" name="HDCP_RCVPORT_DATA5"/>
++ <reg32 offset="0x00150" name="HDCP_RCVPORT_DATA6"/>
++ <reg32 offset="0x00154" name="HDCP_RCVPORT_DATA7"/>
++ <reg32 offset="0x00158" name="HDCP_RCVPORT_DATA8"/>
++ <reg32 offset="0x0015c" name="HDCP_RCVPORT_DATA9"/>
++ <reg32 offset="0x00160" name="HDCP_RCVPORT_DATA10"/>
++ <reg32 offset="0x00164" name="HDCP_RCVPORT_DATA11"/>
++ <reg32 offset="0x00168" name="HDCP_RCVPORT_DATA12"/>
++
++ <reg32 offset="0x0016c" name="VENSPEC_INFO0"/>
++ <reg32 offset="0x00170" name="VENSPEC_INFO1"/>
++ <reg32 offset="0x00174" name="VENSPEC_INFO2"/>
++ <reg32 offset="0x00178" name="VENSPEC_INFO3"/>
++ <reg32 offset="0x0017c" name="VENSPEC_INFO4"/>
++ <reg32 offset="0x00180" name="VENSPEC_INFO5"/>
++ <reg32 offset="0x00184" name="VENSPEC_INFO6"/>
++
++ <reg32 offset="0x001d0" name="AUDIO_CFG">
++ <bitfield name="ENGINE_ENABLE" pos="0" type="boolean"/>
++ <bitfield name="FIFO_WATERMARK" low="4" high="7" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x00208" name="USEC_REFTIMER"/>
++ <reg32 offset="0x0020c" name="DDC_CTRL">
++ <!--
++ 0x020C HDMI_DDC_CTRL
++ [21:20] TRANSACTION_CNT
++ Number of transactions to be done in current transfer.
++ * 0x0: transaction0 only
++ * 0x1: transaction0, transaction1
++ * 0x2: transaction0, transaction1, transaction2
++ * 0x3: transaction0, transaction1, transaction2, transaction3
++ [3] SW_STATUS_RESET
++ Write 1 to reset HDMI_DDC_SW_STATUS flags, will reset SW_DONE,
++ ABORTED, TIMEOUT, SW_INTERRUPTED, BUFFER_OVERFLOW,
++ STOPPED_ON_NACK, NACK0, NACK1, NACK2, NACK3
++ [2] SEND_RESET Set to 1 to send reset sequence (9 clocks with no
++ data) at start of transfer. This sequence is sent after GO is
++ written to 1, before the first transaction only.
++ [1] SOFT_RESET Write 1 to reset DDC controller
++ [0] GO WRITE ONLY. Write 1 to start DDC transfer.
++ -->
++ <bitfield name="GO" pos="0" type="boolean"/>
++ <bitfield name="SOFT_RESET" pos="1" type="boolean"/>
++ <bitfield name="SEND_RESET" pos="2" type="boolean"/>
++ <bitfield name="SW_STATUS_RESET" pos="3" type="boolean"/>
++ <bitfield name="TRANSACTION_CNT" low="20" high="21" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00210" name="DDC_ARBITRATION">
++ <bitfield name="HW_ARBITRATION" pos="4" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00214" name="DDC_INT_CTRL">
++ <!--
++ HDMI_DDC_INT_CTRL[0x0214]
++ [2] SW_DONE_MK Mask bit for SW_DONE_INT. Set to 1 to enable
++ interrupt.
++ [1] SW_DONE_ACK WRITE ONLY. Acknowledge bit for SW_DONE_INT.
++ Write 1 to clear interrupt.
++ [0] SW_DONE_INT READ ONLY. SW_DONE interrupt status */
++ -->
++ <bitfield name="SW_DONE_INT" pos="0" type="boolean"/>
++ <bitfield name="SW_DONE_ACK" pos="1" type="boolean"/>
++ <bitfield name="SW_DONE_MASK" pos="2" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00218" name="DDC_SW_STATUS">
++ <bitfield name="NACK0" pos="12" type="boolean"/>
++ <bitfield name="NACK1" pos="13" type="boolean"/>
++ <bitfield name="NACK2" pos="14" type="boolean"/>
++ <bitfield name="NACK3" pos="15" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0021c" name="DDC_HW_STATUS">
++ <bitfield name="DONE" pos="3" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00220" name="DDC_SPEED">
++ <!--
++ 0x0220 HDMI_DDC_SPEED
++ [31:16] PRESCALE prescale = (m * xtal_frequency) /
++ (desired_i2c_speed), where m is multiply
++ factor, default: m = 1
++ [1:0] THRESHOLD Select threshold to use to determine whether value
++ sampled on SDA is a 1 or 0. Specified in terms of the ratio
++ between the number of sampled ones and the total number of times
++ SDA is sampled.
++ * 0x0: >0
++ * 0x1: 1/4 of total samples
++ * 0x2: 1/2 of total samples
++ * 0x3: 3/4 of total samples */
++ -->
++ <bitfield name="THRESHOLD" low="0" high="1" type="uint"/>
++ <bitfield name="PRESCALE" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00224" name="DDC_SETUP">
++ <!--
++ * 0x0224 HDMI_DDC_SETUP
++ * Setting 31:24 bits : Time units to wait before timeout
++ * when clock is being stalled by external sink device
++ -->
++ <bitfield name="TIMEOUT" low="24" high="31" type="uint"/>
++ </reg32>
++ <!-- Guessing length is 4, as elsewhere the are references to trans0 thru trans3 -->
++ <array offset="0x00228" name="I2C_TRANSACTION" length="4" stride="4">
++ <reg32 offset="0" name="REG">
++ <!--
++ 0x0228 HDMI_DDC_TRANS0
++ [23:16] CNT0 Byte count for first transaction (excluding the first
++ byte, which is usually the address).
++ [13] STOP0 Determines whether a stop bit will be sent after the first
++ transaction
++ * 0: NO STOP
++ * 1: STOP
++ [12] START0 Determines whether a start bit will be sent before the
++ first transaction
++ * 0: NO START
++ * 1: START
++ [8] STOP_ON_NACK0 Determines whether the current transfer will stop
++ if a NACK is received during the first transaction (current
++ transaction always stops).
++ * 0: STOP CURRENT TRANSACTION, GO TO NEXT TRANSACTION
++ * 1: STOP ALL TRANSACTIONS, SEND STOP BIT
++ [0] RW0 Read/write indicator for first transaction - set to 0 for
++ write, 1 for read. This bit only controls HDMI_DDC behaviour -
++ the R/W bit in the transaction is programmed into the DDC buffer
++ as the LSB of the address byte.
++ * 0: WRITE
++ * 1: READ
++ -->
++ <bitfield name="RW" pos="0" type="hdmi_ddc_read_write"/>
++ <bitfield name="STOP_ON_NACK" pos="8" type="boolean"/>
++ <bitfield name="START" pos="12" type="boolean"/>
++ <bitfield name="STOP" pos="13" type="boolean"/>
++ <bitfield name="CNT" low="16" high="23" type="uint"/>
++ </reg32>
++ </array>
++ <reg32 offset="0x00238" name="DDC_DATA">
++ <!--
++ 0x0238 HDMI_DDC_DATA
++ [31] INDEX_WRITE WRITE ONLY. To write index field, set this bit to
++ 1 while writing HDMI_DDC_DATA.
++ [23:16] INDEX Use to set index into DDC buffer for next read or
++ current write, or to read index of current read or next write.
++ Writable only when INDEX_WRITE=1.
++ [15:8] DATA Use to fill or read the DDC buffer
++ [0] DATA_RW Select whether buffer access will be a read or write.
++ For writes, address auto-increments on write to HDMI_DDC_DATA.
++ For reads, address autoincrements on reads to HDMI_DDC_DATA.
++ * 0: Write
++ * 1: Read
++ -->
++ <bitfield name="DATA_RW" pos="0" type="hdmi_ddc_read_write"/>
++ <bitfield name="DATA" low="8" high="15" type="uint"/>
++ <bitfield name="INDEX" low="16" high="23" type="uint"/>
++ <bitfield name="INDEX_WRITE" pos="31" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x0023c" name="HDCP_SHA_CTRL"/>
++ <reg32 offset="0x00240" name="HDCP_SHA_STATUS">
++ <bitfield name="BLOCK_DONE" pos="0" type="boolean"/>
++ <bitfield name="COMP_DONE" pos="4" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00244" name="HDCP_SHA_DATA">
++ <bitfield name="DONE" pos="0" type="boolean"/>
++ </reg32>
++
++ <reg32 offset="0x00250" name="HPD_INT_STATUS">
++ <bitfield name="INT" pos="0" type="boolean"/> <!-- an irq has occurred -->
++ <bitfield name="CABLE_DETECTED" pos="1" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00254" name="HPD_INT_CTRL">
++ <!-- (this useful comment was removed in df6b645.. git archaeology is fun)
++ HPD_INT_CTRL[0x0254]
++ 31:10 Reserved
++ 9 RCV_PLUGIN_DET_MASK receiver plug in interrupt mask.
++ When programmed to 1,
++ RCV_PLUGIN_DET_INT will toggle
++ the interrupt line
++ 8:6 Reserved
++ 5 RX_INT_EN Panel RX interrupt enable
++ 0: Disable
++ 1: Enable
++ 4 RX_INT_ACK WRITE ONLY. Panel RX interrupt
++ ack
++ 3 Reserved
++ 2 INT_EN Panel interrupt control
++ 0: Disable
++ 1: Enable
++ 1 INT_POLARITY Panel interrupt polarity
++ 0: generate interrupt on disconnect
++ 1: generate interrupt on connect
++ 0 INT_ACK WRITE ONLY. Panel interrupt ack
++ -->
++ <bitfield name="INT_ACK" pos="0" type="boolean"/>
++ <bitfield name="INT_CONNECT" pos="1" type="boolean"/>
++ <bitfield name="INT_EN" pos="2" type="boolean"/>
++ <bitfield name="RX_INT_ACK" pos="4" type="boolean"/>
++ <bitfield name="RX_INT_EN" pos="5" type="boolean"/>
++ <bitfield name="RCV_PLUGIN_DET_MASK" pos="9" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00258" name="HPD_CTRL">
++ <bitfield name="TIMEOUT" low="0" high="12" type="uint"/>
++ <bitfield name="ENABLE" pos="28" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0027c" name="DDC_REF">
++ <!--
++ 0x027C HDMI_DDC_REF
++ [16] REFTIMER_ENABLE Enable the timer
++ * 0: Disable
++ * 1: Enable
++ [15:0] REFTIMER Value to set the register in order to generate
++ DDC strobe. This register counts on HDCP application clock
++
++ /* Enable reference timer
++ * 27 micro-seconds */
++ HDMI_OUTP_ND(0x027C, (1 << 16) | (27 << 0));
++ -->
++ <bitfield name="REFTIMER_ENABLE" pos="16" type="boolean"/>
++ <bitfield name="REFTIMER" low="0" high="15" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x00284" name="HDCP_SW_UPPER_AKSV"/>
++ <reg32 offset="0x00288" name="HDCP_SW_LOWER_AKSV"/>
++
++ <reg32 offset="0x0028c" name="CEC_CTRL">
++ <bitfield name="ENABLE" pos="0" type="boolean"/>
++ <bitfield name="SEND_TRIGGER" pos="1" type="boolean"/>
++ <bitfield name="FRAME_SIZE" low="4" high="8" type="uint"/>
++ <bitfield name="LINE_OE" pos="9" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00290" name="CEC_WR_DATA">
++ <bitfield name="BROADCAST" pos="0" type="boolean"/>
++ <bitfield name="DATA" low="8" high="15" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00294" name="CEC_RETRANSMIT">
++ <bitfield name="ENABLE" pos="0" type="boolean"/>
++ <bitfield name="COUNT" low="1" high="7" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00298" name="CEC_STATUS">
++ <bitfield name="BUSY" pos="0" type="boolean"/>
++ <bitfield name="TX_FRAME_DONE" pos="3" type="boolean"/>
++ <bitfield name="TX_STATUS" low="4" high="7" type="hdmi_cec_tx_status"/>
++ </reg32>
++ <reg32 offset="0x0029c" name="CEC_INT">
++ <bitfield name="TX_DONE" pos="0" type="boolean"/>
++ <bitfield name="TX_DONE_MASK" pos="1" type="boolean"/>
++ <bitfield name="TX_ERROR" pos="2" type="boolean"/>
++ <bitfield name="TX_ERROR_MASK" pos="3" type="boolean"/>
++ <bitfield name="MONITOR" pos="4" type="boolean"/>
++ <bitfield name="MONITOR_MASK" pos="5" type="boolean"/>
++ <bitfield name="RX_DONE" pos="6" type="boolean"/>
++ <bitfield name="RX_DONE_MASK" pos="7" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x002a0" name="CEC_ADDR"/>
++ <reg32 offset="0x002a4" name="CEC_TIME">
++ <bitfield name="ENABLE" pos="0" type="boolean"/>
++ <bitfield name="SIGNAL_FREE_TIME" low="7" high="15" type="uint"/>
++ </reg32>
++ <reg32 offset="0x002a8" name="CEC_REFTIMER">
++ <bitfield name="REFTIMER" low="0" high="15" type="uint"/>
++ <bitfield name="ENABLE" pos="16" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x002ac" name="CEC_RD_DATA">
++ <bitfield name="DATA" low="0" high="7" type="uint"/>
++ <bitfield name="SIZE" low="8" high="12" type="uint"/>
++ </reg32>
++ <reg32 offset="0x002b0" name="CEC_RD_FILTER"/>
++
++ <reg32 offset="0x002b4" name="ACTIVE_HSYNC">
++ <bitfield name="START" low="0" high="12" type="uint"/>
++ <bitfield name="END" low="16" high="27" type="uint"/>
++ </reg32>
++ <reg32 offset="0x002b8" name="ACTIVE_VSYNC">
++ <bitfield name="START" low="0" high="12" type="uint"/>
++ <bitfield name="END" low="16" high="28" type="uint"/>
++ </reg32>
++ <reg32 offset="0x002bc" name="VSYNC_ACTIVE_F2">
++ <!-- interlaced, frame 2 -->
++ <bitfield name="START" low="0" high="12" type="uint"/>
++ <bitfield name="END" low="16" high="28" type="uint"/>
++ </reg32>
++ <reg32 offset="0x002c0" name="TOTAL">
++ <bitfield name="H_TOTAL" low="0" high="12" type="uint"/>
++ <bitfield name="V_TOTAL" low="16" high="28" type="uint"/>
++ </reg32>
++ <reg32 offset="0x002c4" name="VSYNC_TOTAL_F2">
++ <!-- interlaced, frame 2 -->
++ <bitfield name="V_TOTAL" low="0" high="12" type="uint"/>
++ </reg32>
++ <reg32 offset="0x002c8" name="FRAME_CTRL">
++ <bitfield name="RGB_MUX_SEL_BGR" pos="12" type="boolean"/>
++ <bitfield name="VSYNC_LOW" pos="28" type="boolean"/>
++ <bitfield name="HSYNC_LOW" pos="29" type="boolean"/>
++ <bitfield name="INTERLACED_EN" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x002cc" name="AUD_INT">
++ <!--
++ HDMI_AUD_INT[0x02CC]
++ [3] AUD_SAM_DROP_MASK [R/W]
++ [2] AUD_SAM_DROP_ACK [W], AUD_SAM_DROP_INT [R]
++ [1] AUD_FIFO_URUN_MASK [R/W]
++ [0] AUD_FIFO_URUN_ACK [W], AUD_FIFO_URUN_INT [R]
++ -->
++ <bitfield name="AUD_FIFO_URUN_INT" pos="0" type="boolean"/> <!-- write to ack irq -->
++ <bitfield name="AUD_FIFO_URAN_MASK" pos="1" type="boolean"/> <!-- r/w, enables irq -->
++ <bitfield name="AUD_SAM_DROP_INT" pos="2" type="boolean"/> <!-- write to ack irq -->
++ <bitfield name="AUD_SAM_DROP_MASK" pos="3" type="boolean"/> <!-- r/w, enables irq -->
++ </reg32>
++ <reg32 offset="0x002d4" name="PHY_CTRL">
++ <!--
++ in hdmi_phy_reset() it appears to be toggling SW_RESET/
++ SW_RESET_PLL based on the value of the bit above, so
++ I'm guessing the bit above is a polarit bit
++ -->
++ <bitfield name="SW_RESET_PLL" pos="0" type="boolean"/>
++ <bitfield name="SW_RESET_PLL_LOW" pos="1" type="boolean"/>
++ <bitfield name="SW_RESET" pos="2" type="boolean"/>
++ <bitfield name="SW_RESET_LOW" pos="3" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x002dc" name="CEC_WR_RANGE"/>
++ <reg32 offset="0x002e0" name="CEC_RD_RANGE"/>
++ <reg32 offset="0x002e4" name="VERSION"/>
++ <reg32 offset="0x00360" name="CEC_COMPL_CTL"/>
++ <reg32 offset="0x00364" name="CEC_RD_START_RANGE"/>
++ <reg32 offset="0x00368" name="CEC_RD_TOTAL_RANGE"/>
++ <reg32 offset="0x0036c" name="CEC_RD_ERR_RESP_LO"/>
++ <reg32 offset="0x00370" name="CEC_WR_CHECK_CONFIG"/>
++
++</domain>
++
++<domain name="HDMI_8x60" width="32">
++ <reg32 offset="0x00000" name="PHY_REG0">
++ <bitfield name="DESER_DEL_CTRL" low="2" high="4" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00004" name="PHY_REG1">
++ <bitfield name="DTEST_MUX_SEL" low="4" high="7" type="uint"/>
++ <bitfield name="OUTVOL_SWING_CTRL" low="0" high="3" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00008" name="PHY_REG2">
++ <bitfield name="PD_DESER" pos="0" type="boolean"/>
++ <bitfield name="PD_DRIVE_1" pos="1" type="boolean"/>
++ <bitfield name="PD_DRIVE_2" pos="2" type="boolean"/>
++ <bitfield name="PD_DRIVE_3" pos="3" type="boolean"/>
++ <bitfield name="PD_DRIVE_4" pos="4" type="boolean"/>
++ <bitfield name="PD_PLL" pos="5" type="boolean"/>
++ <bitfield name="PD_PWRGEN" pos="6" type="boolean"/>
++ <bitfield name="RCV_SENSE_EN" pos="7" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0000c" name="PHY_REG3">
++ <bitfield name="PLL_ENABLE" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00010" name="PHY_REG4"/>
++ <reg32 offset="0x00014" name="PHY_REG5"/>
++ <reg32 offset="0x00018" name="PHY_REG6"/>
++ <reg32 offset="0x0001c" name="PHY_REG7"/>
++ <reg32 offset="0x00020" name="PHY_REG8"/>
++ <reg32 offset="0x00024" name="PHY_REG9"/>
++ <reg32 offset="0x00028" name="PHY_REG10"/>
++ <reg32 offset="0x0002c" name="PHY_REG11"/>
++ <reg32 offset="0x00030" name="PHY_REG12">
++ <bitfield name="RETIMING_EN" pos="0" type="boolean"/>
++ <bitfield name="PLL_LOCK_DETECT_EN" pos="1" type="boolean"/>
++ <bitfield name="FORCE_LOCK" pos="4" type="boolean"/>
++ </reg32>
++</domain>
++
++<domain name="HDMI_8960" width="32">
++ <!--
++ some of the bitfields may be same as 8x60.. but no helpful comments
++ in msm_dss_io_8960.c
++ -->
++ <reg32 offset="0x00000" name="PHY_REG0"/>
++ <reg32 offset="0x00004" name="PHY_REG1"/>
++ <reg32 offset="0x00008" name="PHY_REG2"/>
++ <reg32 offset="0x0000c" name="PHY_REG3"/>
++ <reg32 offset="0x00010" name="PHY_REG4"/>
++ <reg32 offset="0x00014" name="PHY_REG5"/>
++ <reg32 offset="0x00018" name="PHY_REG6"/>
++ <reg32 offset="0x0001c" name="PHY_REG7"/>
++ <reg32 offset="0x00020" name="PHY_REG8"/>
++ <reg32 offset="0x00024" name="PHY_REG9"/>
++ <reg32 offset="0x00028" name="PHY_REG10"/>
++ <reg32 offset="0x0002c" name="PHY_REG11"/>
++ <reg32 offset="0x00030" name="PHY_REG12">
++ <bitfield name="SW_RESET" pos="5" type="boolean"/>
++ <bitfield name="PWRDN_B" pos="7" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00034" name="PHY_REG_BIST_CFG"/>
++ <reg32 offset="0x00038" name="PHY_DEBUG_BUS_SEL"/>
++ <reg32 offset="0x0003c" name="PHY_REG_MISC0"/>
++ <reg32 offset="0x00040" name="PHY_REG13"/>
++ <reg32 offset="0x00044" name="PHY_REG14"/>
++ <reg32 offset="0x00048" name="PHY_REG15"/>
++</domain>
++
++<domain name="HDMI_8960_PHY_PLL" width="32">
++ <reg32 offset="0x00000" name="REFCLK_CFG"/>
++ <reg32 offset="0x00004" name="CHRG_PUMP_CFG"/>
++ <reg32 offset="0x00008" name="LOOP_FLT_CFG0"/>
++ <reg32 offset="0x0000c" name="LOOP_FLT_CFG1"/>
++ <reg32 offset="0x00010" name="IDAC_ADJ_CFG"/>
++ <reg32 offset="0x00014" name="I_VI_KVCO_CFG"/>
++ <reg32 offset="0x00018" name="PWRDN_B">
++ <bitfield name="PD_PLL" pos="1" type="boolean"/>
++ <bitfield name="PLL_PWRDN_B" pos="3" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0001c" name="SDM_CFG0"/>
++ <reg32 offset="0x00020" name="SDM_CFG1"/>
++ <reg32 offset="0x00024" name="SDM_CFG2"/>
++ <reg32 offset="0x00028" name="SDM_CFG3"/>
++ <reg32 offset="0x0002c" name="SDM_CFG4"/>
++ <reg32 offset="0x00030" name="SSC_CFG0"/>
++ <reg32 offset="0x00034" name="SSC_CFG1"/>
++ <reg32 offset="0x00038" name="SSC_CFG2"/>
++ <reg32 offset="0x0003c" name="SSC_CFG3"/>
++ <reg32 offset="0x00040" name="LOCKDET_CFG0"/>
++ <reg32 offset="0x00044" name="LOCKDET_CFG1"/>
++ <reg32 offset="0x00048" name="LOCKDET_CFG2"/>
++ <reg32 offset="0x0004c" name="VCOCAL_CFG0"/>
++ <reg32 offset="0x00050" name="VCOCAL_CFG1"/>
++ <reg32 offset="0x00054" name="VCOCAL_CFG2"/>
++ <reg32 offset="0x00058" name="VCOCAL_CFG3"/>
++ <reg32 offset="0x0005c" name="VCOCAL_CFG4"/>
++ <reg32 offset="0x00060" name="VCOCAL_CFG5"/>
++ <reg32 offset="0x00064" name="VCOCAL_CFG6"/>
++ <reg32 offset="0x00068" name="VCOCAL_CFG7"/>
++ <reg32 offset="0x0006c" name="DEBUG_SEL"/>
++ <reg32 offset="0x00070" name="MISC0"/>
++ <reg32 offset="0x00074" name="MISC1"/>
++ <reg32 offset="0x00078" name="MISC2"/>
++ <reg32 offset="0x0007c" name="MISC3"/>
++ <reg32 offset="0x00080" name="MISC4"/>
++ <reg32 offset="0x00084" name="MISC5"/>
++ <reg32 offset="0x00088" name="MISC6"/>
++ <reg32 offset="0x0008c" name="DEBUG_BUS0"/>
++ <reg32 offset="0x00090" name="DEBUG_BUS1"/>
++ <reg32 offset="0x00094" name="DEBUG_BUS2"/>
++ <reg32 offset="0x00098" name="STATUS0">
++ <bitfield name="PLL_LOCK" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0009c" name="STATUS1"/>
++</domain>
++
++<domain name="HDMI_8x74" width="32">
++ <!--
++ seems to be all mdp5+ have same?
++ -->
++ <reg32 offset="0x00000" name="ANA_CFG0"/>
++ <reg32 offset="0x00004" name="ANA_CFG1"/>
++ <reg32 offset="0x00008" name="ANA_CFG2"/>
++ <reg32 offset="0x0000c" name="ANA_CFG3"/>
++ <reg32 offset="0x00010" name="PD_CTRL0"/>
++ <reg32 offset="0x00014" name="PD_CTRL1"/>
++ <reg32 offset="0x00018" name="GLB_CFG"/>
++ <reg32 offset="0x0001c" name="DCC_CFG0"/>
++ <reg32 offset="0x00020" name="DCC_CFG1"/>
++ <reg32 offset="0x00024" name="TXCAL_CFG0"/>
++ <reg32 offset="0x00028" name="TXCAL_CFG1"/>
++ <reg32 offset="0x0002c" name="TXCAL_CFG2"/>
++ <reg32 offset="0x00030" name="TXCAL_CFG3"/>
++ <reg32 offset="0x00034" name="BIST_CFG0"/>
++ <reg32 offset="0x0003c" name="BIST_PATN0"/>
++ <reg32 offset="0x00040" name="BIST_PATN1"/>
++ <reg32 offset="0x00044" name="BIST_PATN2"/>
++ <reg32 offset="0x00048" name="BIST_PATN3"/>
++ <reg32 offset="0x0005c" name="STATUS"/>
++</domain>
++
++<domain name="HDMI_28nm_PHY_PLL" width="32">
++ <reg32 offset="0x00000" name="REFCLK_CFG"/>
++ <reg32 offset="0x00004" name="POSTDIV1_CFG"/>
++ <reg32 offset="0x00008" name="CHGPUMP_CFG"/>
++ <reg32 offset="0x0000C" name="VCOLPF_CFG"/>
++ <reg32 offset="0x00010" name="VREG_CFG"/>
++ <reg32 offset="0x00014" name="PWRGEN_CFG"/>
++ <reg32 offset="0x00018" name="DMUX_CFG"/>
++ <reg32 offset="0x0001C" name="AMUX_CFG"/>
++ <reg32 offset="0x00020" name="GLB_CFG">
++ <bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/>
++ <bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/>
++ <bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/>
++ <bitfield name="PLL_ENABLE" pos="3" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x00024" name="POSTDIV2_CFG"/>
++ <reg32 offset="0x00028" name="POSTDIV3_CFG"/>
++ <reg32 offset="0x0002C" name="LPFR_CFG"/>
++ <reg32 offset="0x00030" name="LPFC1_CFG"/>
++ <reg32 offset="0x00034" name="LPFC2_CFG"/>
++ <reg32 offset="0x00038" name="SDM_CFG0"/>
++ <reg32 offset="0x0003C" name="SDM_CFG1"/>
++ <reg32 offset="0x00040" name="SDM_CFG2"/>
++ <reg32 offset="0x00044" name="SDM_CFG3"/>
++ <reg32 offset="0x00048" name="SDM_CFG4"/>
++ <reg32 offset="0x0004C" name="SSC_CFG0"/>
++ <reg32 offset="0x00050" name="SSC_CFG1"/>
++ <reg32 offset="0x00054" name="SSC_CFG2"/>
++ <reg32 offset="0x00058" name="SSC_CFG3"/>
++ <reg32 offset="0x0005C" name="LKDET_CFG0"/>
++ <reg32 offset="0x00060" name="LKDET_CFG1"/>
++ <reg32 offset="0x00064" name="LKDET_CFG2"/>
++ <reg32 offset="0x00068" name="TEST_CFG">
++ <bitfield name="PLL_SW_RESET" pos="0" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0006C" name="CAL_CFG0"/>
++ <reg32 offset="0x00070" name="CAL_CFG1"/>
++ <reg32 offset="0x00074" name="CAL_CFG2"/>
++ <reg32 offset="0x00078" name="CAL_CFG3"/>
++ <reg32 offset="0x0007C" name="CAL_CFG4"/>
++ <reg32 offset="0x00080" name="CAL_CFG5"/>
++ <reg32 offset="0x00084" name="CAL_CFG6"/>
++ <reg32 offset="0x00088" name="CAL_CFG7"/>
++ <reg32 offset="0x0008C" name="CAL_CFG8"/>
++ <reg32 offset="0x00090" name="CAL_CFG9"/>
++ <reg32 offset="0x00094" name="CAL_CFG10"/>
++ <reg32 offset="0x00098" name="CAL_CFG11"/>
++ <reg32 offset="0x0009C" name="EFUSE_CFG"/>
++ <reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/>
++ <reg32 offset="0x000C0" name="STATUS"/>
++</domain>
++
++<domain name="HDMI_8996_PHY" width="32">
++ <reg32 offset="0x00000" name="CFG"/>
++ <reg32 offset="0x00004" name="PD_CTL"/>
++ <reg32 offset="0x00008" name="MODE"/>
++ <reg32 offset="0x0000C" name="MISR_CLEAR"/>
++ <reg32 offset="0x00010" name="TX0_TX1_BIST_CFG0"/>
++ <reg32 offset="0x00014" name="TX0_TX1_BIST_CFG1"/>
++ <reg32 offset="0x00018" name="TX0_TX1_PRBS_SEED_BYTE0"/>
++ <reg32 offset="0x0001C" name="TX0_TX1_PRBS_SEED_BYTE1"/>
++ <reg32 offset="0x00020" name="TX0_TX1_BIST_PATTERN0"/>
++ <reg32 offset="0x00024" name="TX0_TX1_BIST_PATTERN1"/>
++ <reg32 offset="0x00028" name="TX2_TX3_BIST_CFG0"/>
++ <reg32 offset="0x0002C" name="TX2_TX3_BIST_CFG1"/>
++ <reg32 offset="0x00030" name="TX2_TX3_PRBS_SEED_BYTE0"/>
++ <reg32 offset="0x00034" name="TX2_TX3_PRBS_SEED_BYTE1"/>
++ <reg32 offset="0x00038" name="TX2_TX3_BIST_PATTERN0"/>
++ <reg32 offset="0x0003C" name="TX2_TX3_BIST_PATTERN1"/>
++ <reg32 offset="0x00040" name="DEBUG_BUS_SEL"/>
++ <reg32 offset="0x00044" name="TXCAL_CFG0"/>
++ <reg32 offset="0x00048" name="TXCAL_CFG1"/>
++ <reg32 offset="0x0004C" name="TX0_TX1_LANE_CTL"/>
++ <reg32 offset="0x00050" name="TX2_TX3_LANE_CTL"/>
++ <reg32 offset="0x00054" name="LANE_BIST_CONFIG"/>
++ <reg32 offset="0x00058" name="CLOCK"/>
++ <reg32 offset="0x0005C" name="MISC1"/>
++ <reg32 offset="0x00060" name="MISC2"/>
++ <reg32 offset="0x00064" name="TX0_TX1_BIST_STATUS0"/>
++ <reg32 offset="0x00068" name="TX0_TX1_BIST_STATUS1"/>
++ <reg32 offset="0x0006C" name="TX0_TX1_BIST_STATUS2"/>
++ <reg32 offset="0x00070" name="TX2_TX3_BIST_STATUS0"/>
++ <reg32 offset="0x00074" name="TX2_TX3_BIST_STATUS1"/>
++ <reg32 offset="0x00078" name="TX2_TX3_BIST_STATUS2"/>
++ <reg32 offset="0x0007C" name="PRE_MISR_STATUS0"/>
++ <reg32 offset="0x00080" name="PRE_MISR_STATUS1"/>
++ <reg32 offset="0x00084" name="PRE_MISR_STATUS2"/>
++ <reg32 offset="0x00088" name="PRE_MISR_STATUS3"/>
++ <reg32 offset="0x0008C" name="POST_MISR_STATUS0"/>
++ <reg32 offset="0x00090" name="POST_MISR_STATUS1"/>
++ <reg32 offset="0x00094" name="POST_MISR_STATUS2"/>
++ <reg32 offset="0x00098" name="POST_MISR_STATUS3"/>
++ <reg32 offset="0x0009C" name="STATUS"/>
++ <reg32 offset="0x000A0" name="MISC3_STATUS"/>
++ <reg32 offset="0x000A4" name="MISC4_STATUS"/>
++ <reg32 offset="0x000A8" name="DEBUG_BUS0"/>
++ <reg32 offset="0x000AC" name="DEBUG_BUS1"/>
++ <reg32 offset="0x000B0" name="DEBUG_BUS2"/>
++ <reg32 offset="0x000B4" name="DEBUG_BUS3"/>
++ <reg32 offset="0x000B8" name="PHY_REVISION_ID0"/>
++ <reg32 offset="0x000BC" name="PHY_REVISION_ID1"/>
++ <reg32 offset="0x000C0" name="PHY_REVISION_ID2"/>
++ <reg32 offset="0x000C4" name="PHY_REVISION_ID3"/>
++</domain>
++
++<domain name="HDMI_PHY_QSERDES_COM" width="32">
++ <reg32 offset="0x00000" name="ATB_SEL1"/>
++ <reg32 offset="0x00004" name="ATB_SEL2"/>
++ <reg32 offset="0x00008" name="FREQ_UPDATE"/>
++ <reg32 offset="0x0000C" name="BG_TIMER"/>
++ <reg32 offset="0x00010" name="SSC_EN_CENTER"/>
++ <reg32 offset="0x00014" name="SSC_ADJ_PER1"/>
++ <reg32 offset="0x00018" name="SSC_ADJ_PER2"/>
++ <reg32 offset="0x0001C" name="SSC_PER1"/>
++ <reg32 offset="0x00020" name="SSC_PER2"/>
++ <reg32 offset="0x00024" name="SSC_STEP_SIZE1"/>
++ <reg32 offset="0x00028" name="SSC_STEP_SIZE2"/>
++ <reg32 offset="0x0002C" name="POST_DIV"/>
++ <reg32 offset="0x00030" name="POST_DIV_MUX"/>
++ <reg32 offset="0x00034" name="BIAS_EN_CLKBUFLR_EN"/>
++ <reg32 offset="0x00038" name="CLK_ENABLE1"/>
++ <reg32 offset="0x0003C" name="SYS_CLK_CTRL"/>
++ <reg32 offset="0x00040" name="SYSCLK_BUF_ENABLE"/>
++ <reg32 offset="0x00044" name="PLL_EN"/>
++ <reg32 offset="0x00048" name="PLL_IVCO"/>
++ <reg32 offset="0x0004C" name="LOCK_CMP1_MODE0"/>
++ <reg32 offset="0x00050" name="LOCK_CMP2_MODE0"/>
++ <reg32 offset="0x00054" name="LOCK_CMP3_MODE0"/>
++ <reg32 offset="0x00058" name="LOCK_CMP1_MODE1"/>
++ <reg32 offset="0x0005C" name="LOCK_CMP2_MODE1"/>
++ <reg32 offset="0x00060" name="LOCK_CMP3_MODE1"/>
++ <reg32 offset="0x00064" name="LOCK_CMP1_MODE2"/>
++ <reg32 offset="0x00064" name="CMN_RSVD0"/>
++ <reg32 offset="0x00068" name="LOCK_CMP2_MODE2"/>
++ <reg32 offset="0x00068" name="EP_CLOCK_DETECT_CTRL"/>
++ <reg32 offset="0x0006C" name="LOCK_CMP3_MODE2"/>
++ <reg32 offset="0x0006C" name="SYSCLK_DET_COMP_STATUS"/>
++ <reg32 offset="0x00070" name="BG_TRIM"/>
++ <reg32 offset="0x00074" name="CLK_EP_DIV"/>
++ <reg32 offset="0x00078" name="CP_CTRL_MODE0"/>
++ <reg32 offset="0x0007C" name="CP_CTRL_MODE1"/>
++ <reg32 offset="0x00080" name="CP_CTRL_MODE2"/>
++ <reg32 offset="0x00080" name="CMN_RSVD1"/>
++ <reg32 offset="0x00084" name="PLL_RCTRL_MODE0"/>
++ <reg32 offset="0x00088" name="PLL_RCTRL_MODE1"/>
++ <reg32 offset="0x0008C" name="PLL_RCTRL_MODE2"/>
++ <reg32 offset="0x0008C" name="CMN_RSVD2"/>
++ <reg32 offset="0x00090" name="PLL_CCTRL_MODE0"/>
++ <reg32 offset="0x00094" name="PLL_CCTRL_MODE1"/>
++ <reg32 offset="0x00098" name="PLL_CCTRL_MODE2"/>
++ <reg32 offset="0x00098" name="CMN_RSVD3"/>
++ <reg32 offset="0x0009C" name="PLL_CNTRL"/>
++ <reg32 offset="0x000A0" name="PHASE_SEL_CTRL"/>
++ <reg32 offset="0x000A4" name="PHASE_SEL_DC"/>
++ <reg32 offset="0x000A8" name="CORE_CLK_IN_SYNC_SEL"/>
++ <reg32 offset="0x000A8" name="BIAS_EN_CTRL_BY_PSM"/>
++ <reg32 offset="0x000AC" name="SYSCLK_EN_SEL"/>
++ <reg32 offset="0x000B0" name="CML_SYSCLK_SEL"/>
++ <reg32 offset="0x000B4" name="RESETSM_CNTRL"/>
++ <reg32 offset="0x000B8" name="RESETSM_CNTRL2"/>
++ <reg32 offset="0x000BC" name="RESTRIM_CTRL"/>
++ <reg32 offset="0x000C0" name="RESTRIM_CTRL2"/>
++ <reg32 offset="0x000C4" name="RESCODE_DIV_NUM"/>
++ <reg32 offset="0x000C8" name="LOCK_CMP_EN"/>
++ <reg32 offset="0x000CC" name="LOCK_CMP_CFG"/>
++ <reg32 offset="0x000D0" name="DEC_START_MODE0"/>
++ <reg32 offset="0x000D4" name="DEC_START_MODE1"/>
++ <reg32 offset="0x000D8" name="DEC_START_MODE2"/>
++ <reg32 offset="0x000D8" name="VCOCAL_DEADMAN_CTRL"/>
++ <reg32 offset="0x000DC" name="DIV_FRAC_START1_MODE0"/>
++ <reg32 offset="0x000E0" name="DIV_FRAC_START2_MODE0"/>
++ <reg32 offset="0x000E4" name="DIV_FRAC_START3_MODE0"/>
++ <reg32 offset="0x000E8" name="DIV_FRAC_START1_MODE1"/>
++ <reg32 offset="0x000EC" name="DIV_FRAC_START2_MODE1"/>
++ <reg32 offset="0x000F0" name="DIV_FRAC_START3_MODE1"/>
++ <reg32 offset="0x000F4" name="DIV_FRAC_START1_MODE2"/>
++ <reg32 offset="0x000F4" name="VCO_TUNE_MINVAL1"/>
++ <reg32 offset="0x000F8" name="DIV_FRAC_START2_MODE2"/>
++ <reg32 offset="0x000F8" name="VCO_TUNE_MINVAL2"/>
++ <reg32 offset="0x000FC" name="DIV_FRAC_START3_MODE2"/>
++ <reg32 offset="0x000FC" name="CMN_RSVD4"/>
++ <reg32 offset="0x00100" name="INTEGLOOP_INITVAL"/>
++ <reg32 offset="0x00104" name="INTEGLOOP_EN"/>
++ <reg32 offset="0x00108" name="INTEGLOOP_GAIN0_MODE0"/>
++ <reg32 offset="0x0010C" name="INTEGLOOP_GAIN1_MODE0"/>
++ <reg32 offset="0x00110" name="INTEGLOOP_GAIN0_MODE1"/>
++ <reg32 offset="0x00114" name="INTEGLOOP_GAIN1_MODE1"/>
++ <reg32 offset="0x00118" name="INTEGLOOP_GAIN0_MODE2"/>
++ <reg32 offset="0x00118" name="VCO_TUNE_MAXVAL1"/>
++ <reg32 offset="0x0011C" name="INTEGLOOP_GAIN1_MODE2"/>
++ <reg32 offset="0x0011C" name="VCO_TUNE_MAXVAL2"/>
++ <reg32 offset="0x00120" name="RES_TRIM_CONTROL2"/>
++ <reg32 offset="0x00124" name="VCO_TUNE_CTRL"/>
++ <reg32 offset="0x00128" name="VCO_TUNE_MAP"/>
++ <reg32 offset="0x0012C" name="VCO_TUNE1_MODE0"/>
++ <reg32 offset="0x00130" name="VCO_TUNE2_MODE0"/>
++ <reg32 offset="0x00134" name="VCO_TUNE1_MODE1"/>
++ <reg32 offset="0x00138" name="VCO_TUNE2_MODE1"/>
++ <reg32 offset="0x0013C" name="VCO_TUNE1_MODE2"/>
++ <reg32 offset="0x0013C" name="VCO_TUNE_INITVAL1"/>
++ <reg32 offset="0x00140" name="VCO_TUNE2_MODE2"/>
++ <reg32 offset="0x00140" name="VCO_TUNE_INITVAL2"/>
++ <reg32 offset="0x00144" name="VCO_TUNE_TIMER1"/>
++ <reg32 offset="0x00148" name="VCO_TUNE_TIMER2"/>
++ <reg32 offset="0x0014C" name="SAR"/>
++ <reg32 offset="0x00150" name="SAR_CLK"/>
++ <reg32 offset="0x00154" name="SAR_CODE_OUT_STATUS"/>
++ <reg32 offset="0x00158" name="SAR_CODE_READY_STATUS"/>
++ <reg32 offset="0x0015C" name="CMN_STATUS"/>
++ <reg32 offset="0x00160" name="RESET_SM_STATUS"/>
++ <reg32 offset="0x00164" name="RESTRIM_CODE_STATUS"/>
++ <reg32 offset="0x00168" name="PLLCAL_CODE1_STATUS"/>
++ <reg32 offset="0x0016C" name="PLLCAL_CODE2_STATUS"/>
++ <reg32 offset="0x00170" name="BG_CTRL"/>
++ <reg32 offset="0x00174" name="CLK_SELECT"/>
++ <reg32 offset="0x00178" name="HSCLK_SEL"/>
++ <reg32 offset="0x0017C" name="INTEGLOOP_BINCODE_STATUS"/>
++ <reg32 offset="0x00180" name="PLL_ANALOG"/>
++ <reg32 offset="0x00184" name="CORECLK_DIV"/>
++ <reg32 offset="0x00188" name="SW_RESET"/>
++ <reg32 offset="0x0018C" name="CORE_CLK_EN"/>
++ <reg32 offset="0x00190" name="C_READY_STATUS"/>
++ <reg32 offset="0x00194" name="CMN_CONFIG"/>
++ <reg32 offset="0x00198" name="CMN_RATE_OVERRIDE"/>
++ <reg32 offset="0x0019C" name="SVS_MODE_CLK_SEL"/>
++ <reg32 offset="0x001A0" name="DEBUG_BUS0"/>
++ <reg32 offset="0x001A4" name="DEBUG_BUS1"/>
++ <reg32 offset="0x001A8" name="DEBUG_BUS2"/>
++ <reg32 offset="0x001AC" name="DEBUG_BUS3"/>
++ <reg32 offset="0x001B0" name="DEBUG_BUS_SEL"/>
++ <reg32 offset="0x001B4" name="CMN_MISC1"/>
++ <reg32 offset="0x001B8" name="CMN_MISC2"/>
++ <reg32 offset="0x001BC" name="CORECLK_DIV_MODE1"/>
++ <reg32 offset="0x001C0" name="CORECLK_DIV_MODE2"/>
++ <reg32 offset="0x001C4" name="CMN_RSVD5"/>
++</domain>
++
++
++<domain name="HDMI_PHY_QSERDES_TX_LX" width="32">
++ <reg32 offset="0x00000" name="BIST_MODE_LANENO"/>
++ <reg32 offset="0x00004" name="BIST_INVERT"/>
++ <reg32 offset="0x00008" name="CLKBUF_ENABLE"/>
++ <reg32 offset="0x0000C" name="CMN_CONTROL_ONE"/>
++ <reg32 offset="0x00010" name="CMN_CONTROL_TWO"/>
++ <reg32 offset="0x00014" name="CMN_CONTROL_THREE"/>
++ <reg32 offset="0x00018" name="TX_EMP_POST1_LVL"/>
++ <reg32 offset="0x0001C" name="TX_POST2_EMPH"/>
++ <reg32 offset="0x00020" name="TX_BOOST_LVL_UP_DN"/>
++ <reg32 offset="0x00024" name="HP_PD_ENABLES"/>
++ <reg32 offset="0x00028" name="TX_IDLE_LVL_LARGE_AMP"/>
++ <reg32 offset="0x0002C" name="TX_DRV_LVL"/>
++ <reg32 offset="0x00030" name="TX_DRV_LVL_OFFSET"/>
++ <reg32 offset="0x00034" name="RESET_TSYNC_EN"/>
++ <reg32 offset="0x00038" name="PRE_STALL_LDO_BOOST_EN"/>
++ <reg32 offset="0x0003C" name="TX_BAND"/>
++ <reg32 offset="0x00040" name="SLEW_CNTL"/>
++ <reg32 offset="0x00044" name="INTERFACE_SELECT"/>
++ <reg32 offset="0x00048" name="LPB_EN"/>
++ <reg32 offset="0x0004C" name="RES_CODE_LANE_TX"/>
++ <reg32 offset="0x00050" name="RES_CODE_LANE_RX"/>
++ <reg32 offset="0x00054" name="RES_CODE_LANE_OFFSET"/>
++ <reg32 offset="0x00058" name="PERL_LENGTH1"/>
++ <reg32 offset="0x0005C" name="PERL_LENGTH2"/>
++ <reg32 offset="0x00060" name="SERDES_BYP_EN_OUT"/>
++ <reg32 offset="0x00064" name="DEBUG_BUS_SEL"/>
++ <reg32 offset="0x00068" name="HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN"/>
++ <reg32 offset="0x0006C" name="TX_POL_INV"/>
++ <reg32 offset="0x00070" name="PARRATE_REC_DETECT_IDLE_EN"/>
++ <reg32 offset="0x00074" name="BIST_PATTERN1"/>
++ <reg32 offset="0x00078" name="BIST_PATTERN2"/>
++ <reg32 offset="0x0007C" name="BIST_PATTERN3"/>
++ <reg32 offset="0x00080" name="BIST_PATTERN4"/>
++ <reg32 offset="0x00084" name="BIST_PATTERN5"/>
++ <reg32 offset="0x00088" name="BIST_PATTERN6"/>
++ <reg32 offset="0x0008C" name="BIST_PATTERN7"/>
++ <reg32 offset="0x00090" name="BIST_PATTERN8"/>
++ <reg32 offset="0x00094" name="LANE_MODE"/>
++ <reg32 offset="0x00098" name="IDAC_CAL_LANE_MODE"/>
++ <reg32 offset="0x0009C" name="IDAC_CAL_LANE_MODE_CONFIGURATION"/>
++ <reg32 offset="0x000A0" name="ATB_SEL1"/>
++ <reg32 offset="0x000A4" name="ATB_SEL2"/>
++ <reg32 offset="0x000A8" name="RCV_DETECT_LVL"/>
++ <reg32 offset="0x000AC" name="RCV_DETECT_LVL_2"/>
++ <reg32 offset="0x000B0" name="PRBS_SEED1"/>
++ <reg32 offset="0x000B4" name="PRBS_SEED2"/>
++ <reg32 offset="0x000B8" name="PRBS_SEED3"/>
++ <reg32 offset="0x000BC" name="PRBS_SEED4"/>
++ <reg32 offset="0x000C0" name="RESET_GEN"/>
++ <reg32 offset="0x000C4" name="RESET_GEN_MUXES"/>
++ <reg32 offset="0x000C8" name="TRAN_DRVR_EMP_EN"/>
++ <reg32 offset="0x000CC" name="TX_INTERFACE_MODE"/>
++ <reg32 offset="0x000D0" name="PWM_CTRL"/>
++ <reg32 offset="0x000D4" name="PWM_ENCODED_OR_DATA"/>
++ <reg32 offset="0x000D8" name="PWM_GEAR_1_DIVIDER_BAND2"/>
++ <reg32 offset="0x000DC" name="PWM_GEAR_2_DIVIDER_BAND2"/>
++ <reg32 offset="0x000E0" name="PWM_GEAR_3_DIVIDER_BAND2"/>
++ <reg32 offset="0x000E4" name="PWM_GEAR_4_DIVIDER_BAND2"/>
++ <reg32 offset="0x000E8" name="PWM_GEAR_1_DIVIDER_BAND0_1"/>
++ <reg32 offset="0x000EC" name="PWM_GEAR_2_DIVIDER_BAND0_1"/>
++ <reg32 offset="0x000F0" name="PWM_GEAR_3_DIVIDER_BAND0_1"/>
++ <reg32 offset="0x000F4" name="PWM_GEAR_4_DIVIDER_BAND0_1"/>
++ <reg32 offset="0x000F8" name="VMODE_CTRL1"/>
++ <reg32 offset="0x000FC" name="VMODE_CTRL2"/>
++ <reg32 offset="0x00100" name="TX_ALOG_INTF_OBSV_CNTL"/>
++ <reg32 offset="0x00104" name="BIST_STATUS"/>
++ <reg32 offset="0x00108" name="BIST_ERROR_COUNT1"/>
++ <reg32 offset="0x0010C" name="BIST_ERROR_COUNT2"/>
++ <reg32 offset="0x00110" name="TX_ALOG_INTF_OBSV"/>
++</domain>
++
++</database>
+diff --git a/drivers/gpu/drm/msm/registers/display/mdp4.xml b/drivers/gpu/drm/msm/registers/display/mdp4.xml
+new file mode 100644
+index 0000000000000..6abb4a3c04da9
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/display/mdp4.xml
+@@ -0,0 +1,504 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++<import file="display/mdp_common.xml"/>
++
++<domain name="MDP4" width="32">
++ <enum name="mdp4_pipe">
++ <brief>pipe names, index into PIPE[]</brief>
++ <value name="VG1" value="0"/>
++ <value name="VG2" value="1"/>
++ <value name="RGB1" value="2"/>
++ <value name="RGB2" value="3"/>
++ <value name="RGB3" value="4"/>
++ <value name="VG3" value="5"/>
++ <value name="VG4" value="6"/>
++ </enum>
++
++ <enum name="mdp4_mixer">
++ <value name="MIXER0" value="0"/>
++ <value name="MIXER1" value="1"/>
++ <value name="MIXER2" value="2"/>
++ </enum>
++
++ <enum name="mdp4_intf">
++ <!--
++ A bit confusing the enums for interface selection:
++ enum {
++ LCDC_RGB_INTF, /* 0 */
++ DTV_INTF = LCDC_RGB_INTF, /* 0 */
++ MDDI_LCDC_INTF, /* 1 */
++ MDDI_INTF, /* 2 */
++ EBI2_INTF, /* 3 */
++ TV_INTF = EBI2_INTF, /* 3 */
++ DSI_VIDEO_INTF,
++ DSI_CMD_INTF
++ };
++ there is some overlap, and not all the values end up getting
++ written to hw (mdp4_display_intf_sel() remaps the last two
++ values to MDDI_LCDC_INTF/MDDI_INTF with extra bits set).. so
++ taking some liberties in guessing the actual meanings/names:
++ -->
++ <value name="INTF_LCDC_DTV" value="0"/> <!-- LCDC RGB or DTV (external) -->
++ <value name="INTF_DSI_VIDEO" value="1"/>
++ <value name="INTF_DSI_CMD" value="2"/>
++ <value name="INTF_EBI2_TV" value="3"/> <!-- EBI2 or TV (external) -->
++ </enum>
++ <enum name="mdp4_cursor_format">
++ <value name="CURSOR_ARGB" value="1"/>
++ <value name="CURSOR_XRGB" value="2"/>
++ </enum>
++ <enum name="mdp4_frame_format">
++ <value name="FRAME_LINEAR" value="0"/>
++ <value name="FRAME_TILE_ARGB_4X4" value="1"/>
++ <value name="FRAME_TILE_YCBCR_420" value="2"/>
++ </enum>
++ <enum name="mdp4_scale_unit">
++ <value name="SCALE_FIR" value="0"/>
++ <value name="SCALE_MN_PHASE" value="1"/>
++ <value name="SCALE_PIXEL_RPT" value="2"/>
++ </enum>
++
++ <bitset name="mdp4_layermixer_in_cfg" inline="yes">
++ <brief>appears to map pipe to mixer stage</brief>
++ <bitfield name="PIPE0" low="0" high="2" type="mdp_mixer_stage_id"/>
++ <bitfield name="PIPE0_MIXER1" pos="3" type="boolean"/>
++ <bitfield name="PIPE1" low="4" high="6" type="mdp_mixer_stage_id"/>
++ <bitfield name="PIPE1_MIXER1" pos="7" type="boolean"/>
++ <bitfield name="PIPE2" low="8" high="10" type="mdp_mixer_stage_id"/>
++ <bitfield name="PIPE2_MIXER1" pos="11" type="boolean"/>
++ <bitfield name="PIPE3" low="12" high="14" type="mdp_mixer_stage_id"/>
++ <bitfield name="PIPE3_MIXER1" pos="15" type="boolean"/>
++ <bitfield name="PIPE4" low="16" high="18" type="mdp_mixer_stage_id"/>
++ <bitfield name="PIPE4_MIXER1" pos="19" type="boolean"/>
++ <bitfield name="PIPE5" low="20" high="22" type="mdp_mixer_stage_id"/>
++ <bitfield name="PIPE5_MIXER1" pos="23" type="boolean"/>
++ <bitfield name="PIPE6" low="24" high="26" type="mdp_mixer_stage_id"/>
++ <bitfield name="PIPE6_MIXER1" pos="27" type="boolean"/>
++ <bitfield name="PIPE7" low="28" high="30" type="mdp_mixer_stage_id"/>
++ <bitfield name="PIPE7_MIXER1" pos="31" type="boolean"/>
++ </bitset>
++
++ <bitset name="MDP4_IRQ">
++ <bitfield name="OVERLAY0_DONE" pos="0" type="boolean"/>
++ <bitfield name="OVERLAY1_DONE" pos="1" type="boolean"/>
++ <bitfield name="DMA_S_DONE" pos="2" type="boolean"/>
++ <bitfield name="DMA_E_DONE" pos="3" type="boolean"/>
++ <bitfield name="DMA_P_DONE" pos="4" type="boolean"/>
++ <bitfield name="VG1_HISTOGRAM" pos="5" type="boolean"/>
++ <bitfield name="VG2_HISTOGRAM" pos="6" type="boolean"/>
++ <bitfield name="PRIMARY_VSYNC" pos="7" type="boolean"/>
++ <bitfield name="PRIMARY_INTF_UDERRUN" pos="8" type="boolean"/>
++ <bitfield name="EXTERNAL_VSYNC" pos="9" type="boolean"/>
++ <bitfield name="EXTERNAL_INTF_UDERRUN" pos="10" type="boolean"/>
++ <bitfield name="PRIMARY_RDPTR" pos="11" type="boolean"/> <!-- read pointer -->
++ <bitfield name="DMA_P_HISTOGRAM" pos="17" type="boolean"/>
++ <bitfield name="DMA_S_HISTOGRAM" pos="26" type="boolean"/>
++ <bitfield name="OVERLAY2_DONE" pos="30" type="boolean"/>
++ </bitset>
++
++ <reg32 offset="0x00000" name="VERSION">
++ <!--
++ from mdp_probe() we can see minor rev starts at 16.. assume
++ major is above that.. not sure the rest of bits but doesn't
++ really seem to matter
++ -->
++ <bitfield name="MINOR" low="16" high="23" type="uint"/>
++ <bitfield name="MAJOR" low="24" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00004" name="OVLP0_KICK"/>
++ <reg32 offset="0x00008" name="OVLP1_KICK"/>
++ <reg32 offset="0x000d0" name="OVLP2_KICK"/>
++ <reg32 offset="0x0000c" name="DMA_P_KICK"/>
++ <reg32 offset="0x00010" name="DMA_S_KICK"/>
++ <reg32 offset="0x00014" name="DMA_E_KICK"/>
++ <reg32 offset="0x00018" name="DISP_STATUS"/>
++
++ <reg32 offset="0x00038" name="DISP_INTF_SEL">
++ <bitfield name="PRIM" low="0" high="1" type="mdp4_intf"/>
++ <bitfield name="SEC" low="2" high="3" type="mdp4_intf"/>
++ <bitfield name="EXT" low="4" high="5" type="mdp4_intf"/>
++ <bitfield name="DSI_VIDEO" pos="6" type="boolean"/>
++ <bitfield name="DSI_CMD" pos="7" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0003c" name="RESET_STATUS"/> <!-- only mdp4 >v2.1 -->
++ <reg32 offset="0x0004c" name="READ_CNFG"/> <!-- something about # of pending requests.. -->
++ <reg32 offset="0x00050" name="INTR_ENABLE" type="MDP4_IRQ"/>
++ <reg32 offset="0x00054" name="INTR_STATUS" type="MDP4_IRQ"/>
++ <reg32 offset="0x00058" name="INTR_CLEAR" type="MDP4_IRQ"/>
++ <reg32 offset="0x00060" name="EBI2_LCD0"/>
++ <reg32 offset="0x00064" name="EBI2_LCD1"/>
++ <reg32 offset="0x00070" name="PORTMAP_MODE"/>
++
++ <!-- mdp chip-select controller: -->
++ <reg32 offset="0x000c0" name="CS_CONTROLLER0"/>
++ <reg32 offset="0x000c4" name="CS_CONTROLLER1"/>
++
++ <reg32 offset="0x100f0" name="LAYERMIXER2_IN_CFG" type="mdp4_layermixer_in_cfg"/>
++ <reg32 offset="0x100fc" name="LAYERMIXER_IN_CFG_UPDATE_METHOD"/>
++ <reg32 offset="0x10100" name="LAYERMIXER_IN_CFG" type="mdp4_layermixer_in_cfg"/>
++
++ <reg32 offset="0x30050" name="VG2_SRC_FORMAT"/>
++ <reg32 offset="0x31008" name="VG2_CONST_COLOR"/>
++
++ <reg32 offset="0x18000" name="OVERLAY_FLUSH">
++ <bitfield name="OVLP0" pos="0" type="boolean"/>
++ <bitfield name="OVLP1" pos="1" type="boolean"/>
++ <bitfield name="VG1" pos="2" type="boolean"/>
++ <bitfield name="VG2" pos="3" type="boolean"/>
++ <bitfield name="RGB1" pos="4" type="boolean"/>
++ <bitfield name="RGB2" pos="5" type="boolean"/>
++ </reg32>
++
++ <array offsets="0x10000,0x18000,0x88000" name="OVLP" length="3" stride="0x8000">
++ <reg32 offset="0x0004" name="CFG"/>
++ <reg32 offset="0x0008" name="SIZE" type="reg_wh"/>
++ <reg32 offset="0x000c" name="BASE"/>
++ <reg32 offset="0x0010" name="STRIDE" type="uint"/>
++ <reg32 offset="0x0014" name="OPMODE"/>
++
++ <array offsets="0x0104,0x0124,0x0144,0x0160" name="STAGE" length="4" stride="0x1c">
++ <reg32 offset="0x00" name="OP">
++ <bitfield name="FG_ALPHA" low="0" high="1" type="mdp_alpha_type"/>
++ <bitfield name="FG_INV_ALPHA" pos="2" type="boolean"/>
++ <bitfield name="FG_MOD_ALPHA" pos="3" type="boolean"/>
++ <bitfield name="BG_ALPHA" low="4" high="5" type="mdp_alpha_type"/>
++ <bitfield name="BG_INV_ALPHA" pos="6" type="boolean"/>
++ <bitfield name="BG_MOD_ALPHA" pos="7" type="boolean"/>
++ <bitfield name="FG_TRANSP" pos="8" type="boolean"/>
++ <bitfield name="BG_TRANSP" pos="9" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x04" name="FG_ALPHA"/>
++ <reg32 offset="0x08" name="BG_ALPHA"/>
++ <reg32 offset="0x0c" name="TRANSP_LOW0"/>
++ <reg32 offset="0x10" name="TRANSP_LOW1"/>
++ <reg32 offset="0x14" name="TRANSP_HIGH0"/>
++ <reg32 offset="0x18" name="TRANSP_HIGH1"/>
++ </array>
++
++ <array offsets="0x1004,0x1404,0x1804,0x1b84" name="STAGE_CO3" length="4" stride="4">
++ <reg32 offset="0" name="SEL">
++ <bitfield name="FG_ALPHA" pos="0" type="boolean"/> <!-- otherwise bg alpha -->
++ </reg32>
++ </array>
++
++ <reg32 offset="0x0180" name="TRANSP_LOW0"/>
++ <reg32 offset="0x0184" name="TRANSP_LOW1"/>
++ <reg32 offset="0x0188" name="TRANSP_HIGH0"/>
++ <reg32 offset="0x018c" name="TRANSP_HIGH1"/>
++
++ <reg32 offset="0x0200" name="CSC_CONFIG"/>
++
++ <array offset="0x2000" name="CSC" length="1" stride="0x700">
++ <array offset="0x400" name="MV" length="9" stride="4">
++ <reg32 offset="0" name="VAL"/>
++ </array>
++ <array offset="0x500" name="PRE_BV" length="3" stride="4">
++ <reg32 offset="0" name="VAL"/>
++ </array>
++ <array offset="0x580" name="POST_BV" length="3" stride="4">
++ <reg32 offset="0" name="VAL"/>
++ </array>
++ <array offset="0x600" name="PRE_LV" length="6" stride="4">
++ <reg32 offset="0" name="VAL"/>
++ </array>
++ <array offset="0x680" name="POST_LV" length="6" stride="4">
++ <reg32 offset="0" name="VAL"/>
++ </array>
++ </array>
++ </array>
++
++ <enum name="mdp4_dma">
++ <value name="DMA_P" value="0"/>
++ <value name="DMA_S" value="1"/>
++ <value name="DMA_E" value="2"/>
++ </enum>
++ <reg32 offset="0x90070" name="DMA_P_OP_MODE"/>
++ <array offset="0x94800" name="LUTN" length="2" stride="0x400">
++ <array offset="0" name="LUT" length="0x100" stride="4">
++ <reg32 offset="0" name="VAL"/>
++ </array>
++ </array>
++ <reg32 offset="0xa0028" name="DMA_S_OP_MODE"/>
++ <!-- I guess if DMA_S has an OP_MODE, it must have a LUT too.. -->
++ <reg32 offset="0xb0070" name="DMA_E_QUANT" length="3" stride="4"/>
++ <array offsets="0x90000,0xa0000,0xb0000" name="DMA" length="3" stride="0x10000" index="mdp4_dma">
++ <reg32 offset="0x0000" name="CONFIG">
++ <bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/>
++ <bitfield name="B_BPC" low="2" high="3" type="mdp_bpc"/>
++ <bitfield name="R_BPC" low="4" high="5" type="mdp_bpc"/>
++ <bitfield name="PACK_ALIGN_MSB" pos="7" type="boolean"/>
++ <bitfield name="PACK" low="8" high="15"/>
++ <!-- bit 24 is DITHER_EN on DMA_P, DEFLKR_EN on DMA_E -->
++ <bitfield name="DEFLKR_EN" pos="24" type="boolean"/>
++ <bitfield name="DITHER_EN" pos="24" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0004" name="SRC_SIZE" type="reg_wh"/>
++ <reg32 offset="0x0008" name="SRC_BASE"/>
++ <reg32 offset="0x000c" name="SRC_STRIDE" type="uint"/>
++ <reg32 offset="0x0010" name="DST_SIZE" type="reg_wh"/>
++
++ <reg32 offset="0x0044" name="CURSOR_SIZE">
++ <!-- seems the limit is 64x64: -->
++ <bitfield name="WIDTH" low="0" high="6" type="uint"/>
++ <bitfield name="HEIGHT" low="16" high="22" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0048" name="CURSOR_BASE"/>
++ <reg32 offset="0x004c" name="CURSOR_POS">
++ <bitfield name="X" low="0" high="15" type="uint"/>
++ <bitfield name="Y" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0060" name="CURSOR_BLEND_CONFIG">
++ <bitfield name="CURSOR_EN" pos="0" type="boolean"/>
++ <bitfield name="FORMAT" low="1" high="2" type="mdp4_cursor_format"/>
++ <bitfield name="TRANSP_EN" pos="3" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0064" name="CURSOR_BLEND_PARAM"/>
++ <reg32 offset="0x0068" name="BLEND_TRANS_LOW"/>
++ <reg32 offset="0x006c" name="BLEND_TRANS_HIGH"/>
++
++ <reg32 offset="0x1004" name="FETCH_CONFIG"/>
++ <array offset="0x3000" name="CSC" length="1" stride="0x700">
++ <array offset="0x400" name="MV" length="9" stride="4">
++ <reg32 offset="0" name="VAL"/>
++ </array>
++ <array offset="0x500" name="PRE_BV" length="3" stride="4">
++ <reg32 offset="0" name="VAL"/>
++ </array>
++ <array offset="0x580" name="POST_BV" length="3" stride="4">
++ <reg32 offset="0" name="VAL"/>
++ </array>
++ <array offset="0x600" name="PRE_LV" length="6" stride="4">
++ <reg32 offset="0" name="VAL"/>
++ </array>
++ <array offset="0x680" name="POST_LV" length="6" stride="4">
++ <reg32 offset="0" name="VAL"/>
++ </array>
++ </array>
++ </array>
++
++ <!--
++ TODO length should be 7, but that would collide w/ OVLP2..!?!
++ this register map is a bit strange..
++ -->
++ <array offset="0x20000" name="PIPE" length="6" stride="0x10000" index="mdp4_pipe">
++ <reg32 offset="0x0000" name="SRC_SIZE" type="reg_wh"/>
++ <reg32 offset="0x0004" name="SRC_XY" type="reg_xy"/>
++ <reg32 offset="0x0008" name="DST_SIZE" type="reg_wh"/>
++ <reg32 offset="0x000c" name="DST_XY" type="reg_xy"/>
++ <reg32 offset="0x0010" name="SRCP0_BASE"/>
++ <reg32 offset="0x0014" name="SRCP1_BASE"/>
++ <reg32 offset="0x0018" name="SRCP2_BASE"/>
++ <reg32 offset="0x001c" name="SRCP3_BASE"/>
++ <reg32 offset="0x0040" name="SRC_STRIDE_A">
++ <bitfield name="P0" low="0" high="15" type="uint"/>
++ <bitfield name="P1" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0044" name="SRC_STRIDE_B">
++ <bitfield name="P2" low="0" high="15" type="uint"/>
++ <bitfield name="P3" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0048" name="SSTILE_FRAME_SIZE" type="reg_wh"/>
++ <reg32 offset="0x0050" name="SRC_FORMAT">
++ <bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/>
++ <bitfield name="B_BPC" low="2" high="3" type="mdp_bpc"/>
++ <bitfield name="R_BPC" low="4" high="5" type="mdp_bpc"/>
++ <bitfield name="A_BPC" low="6" high="7" type="mdp_bpc_alpha"/>
++ <bitfield name="ALPHA_ENABLE" pos="8" type="boolean"/>
++ <bitfield name="CPP" low="9" high="10" type="uint">
++ <brief>8bit characters per pixel minus 1</brief>
++ </bitfield>
++ <bitfield name="ROTATED_90" pos="12" type="boolean"/>
++ <bitfield name="UNPACK_COUNT" low="13" high="14" type="uint"/>
++ <bitfield name="UNPACK_TIGHT" pos="17" type="boolean"/>
++ <bitfield name="UNPACK_ALIGN_MSB" pos="18" type="boolean"/>
++ <bitfield name="FETCH_PLANES" low="19" high="20" type="uint"/>
++ <bitfield name="SOLID_FILL" pos="22" type="boolean"/>
++ <bitfield name="CHROMA_SAMP" low="26" high="27" type="mdp_chroma_samp_type"/>
++ <bitfield name="FRAME_FORMAT" low="29" high="30" type="mdp4_frame_format"/>
++ </reg32>
++ <reg32 offset="0x0054" name="SRC_UNPACK" type="mdp_unpack_pattern"/>
++ <reg32 offset="0x0058" name="OP_MODE">
++ <bitfield name="SCALEX_EN" pos="0" type="boolean"/>
++ <bitfield name="SCALEY_EN" pos="1" type="boolean"/>
++ <bitfield name="SCALEX_UNIT_SEL" low="2" high="3" type="mdp4_scale_unit"/>
++ <bitfield name="SCALEY_UNIT_SEL" low="4" high="5" type="mdp4_scale_unit"/>
++ <bitfield name="SRC_YCBCR" pos="9" type="boolean"/>
++ <bitfield name="DST_YCBCR" pos="10" type="boolean"/>
++ <bitfield name="CSC_EN" pos="11" type="boolean"/>
++ <bitfield name="FLIP_LR" pos="13" type="boolean"/>
++ <bitfield name="FLIP_UD" pos="14" type="boolean"/>
++ <bitfield name="DITHER_EN" pos="15" type="boolean"/>
++ <bitfield name="IGC_LUT_EN" pos="16" type="boolean"/>
++ <bitfield name="DEINT_EN" pos="18" type="boolean"/>
++ <bitfield name="DEINT_ODD_REF" pos="19" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x005c" name="PHASEX_STEP"/>
++ <reg32 offset="0x0060" name="PHASEY_STEP"/>
++ <reg32 offset="0x1004" name="FETCH_CONFIG"/>
++ <reg32 offset="0x1008" name="SOLID_COLOR"/>
++
++ <array offset="0x4000" name="CSC" length="1" stride="0x700">
++ <array offset="0x400" name="MV" length="9" stride="4">
++ <reg32 offset="0" name="VAL"/>
++ </array>
++ <array offset="0x500" name="PRE_BV" length="3" stride="4">
++ <reg32 offset="0" name="VAL"/>
++ </array>
++ <array offset="0x580" name="POST_BV" length="3" stride="4">
++ <reg32 offset="0" name="VAL"/>
++ </array>
++ <array offset="0x600" name="PRE_LV" length="6" stride="4">
++ <reg32 offset="0" name="VAL"/>
++ </array>
++ <array offset="0x680" name="POST_LV" length="6" stride="4">
++ <reg32 offset="0" name="VAL"/>
++ </array>
++ </array>
++ </array>
++
++ <!--
++ ENCODERS
++ LCDC and DSI seem the same, DTV is just slightly different..
++ -->
++
++ <bitset name="mdp4_ctrl_polarity" inline="yes">
++ <!-- not entirely sure if these bits mean hi or low.. -->
++ <bitfield name="HSYNC_LOW" pos="0" type="boolean"/>
++ <bitfield name="VSYNC_LOW" pos="1" type="boolean"/>
++ <bitfield name="DATA_EN_LOW" pos="2" type="boolean"/>
++ </bitset>
++
++ <bitset name="mdp4_active_hctl" inline="yes">
++ <bitfield name="START" low="0" high="14" type="uint"/>
++ <bitfield name="END" low="16" high="30" type="uint"/>
++ <bitfield name="ACTIVE_START_X" pos="31" type="boolean"/>
++ </bitset>
++
++ <bitset name="mdp4_display_hctl" inline="yes">
++ <bitfield name="START" low="0" high="15" type="uint"/>
++ <bitfield name="END" low="16" high="31" type="uint"/>
++ </bitset>
++
++ <bitset name="mdp4_hsync_ctrl" inline="yes">
++ <bitfield name="PULSEW" low="0" high="15" type="uint"/>
++ <bitfield name="PERIOD" low="16" high="31" type="uint"/>
++ </bitset>
++
++ <bitset name="mdp4_underflow_clr" inline="yes">
++ <bitfield name="COLOR" low="0" high="23"/>
++ <bitfield name="ENABLE_RECOVERY" pos="31" type="boolean"/>
++ </bitset>
++
++ <!-- offset is 0xe0000 on !mdp4.. -->
++ <array offset="0xc0000" name="LCDC" length="1" stride="0x1000">
++ <reg32 offset="0x0000" name="ENABLE"/>
++ <reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/>
++ <reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/>
++ <reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/>
++ <reg32 offset="0x0010" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/>
++ <reg32 offset="0x0014" name="DISPLAY_VSTART" type="uint"/>
++ <reg32 offset="0x0018" name="DISPLAY_VEND" type="uint"/>
++ <reg32 offset="0x001c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/>
++ <reg32 offset="0x0020" name="ACTIVE_VSTART" type="uint"/>
++ <reg32 offset="0x0024" name="ACTIVE_VEND" type="uint"/>
++ <reg32 offset="0x0028" name="BORDER_CLR"/>
++ <reg32 offset="0x002c" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/>
++ <reg32 offset="0x0030" name="HSYNC_SKEW"/>
++ <reg32 offset="0x0034" name="TEST_CNTL"/>
++ <reg32 offset="0x0038" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/>
++ </array>
++
++ <reg32 offset="0xc2000" name="LCDC_LVDS_INTF_CTL">
++ <bitfield name="MODE_SEL" pos="2" type="boolean"/>
++ <bitfield name="RGB_OUT" pos="3" type="boolean"/>
++ <bitfield name="CH_SWAP" pos="4" type="boolean"/>
++ <bitfield name="CH1_RES_BIT" pos="5" type="boolean"/>
++ <bitfield name="CH2_RES_BIT" pos="6" type="boolean"/>
++ <bitfield name="ENABLE" pos="7" type="boolean"/>
++ <bitfield name="CH1_DATA_LANE0_EN" pos="8" type="boolean"/>
++ <bitfield name="CH1_DATA_LANE1_EN" pos="9" type="boolean"/>
++ <bitfield name="CH1_DATA_LANE2_EN" pos="10" type="boolean"/>
++ <bitfield name="CH1_DATA_LANE3_EN" pos="11" type="boolean"/>
++ <bitfield name="CH2_DATA_LANE0_EN" pos="12" type="boolean"/>
++ <bitfield name="CH2_DATA_LANE1_EN" pos="13" type="boolean"/>
++ <bitfield name="CH2_DATA_LANE2_EN" pos="14" type="boolean"/>
++ <bitfield name="CH2_DATA_LANE3_EN" pos="15" type="boolean"/>
++ <bitfield name="CH1_CLK_LANE_EN" pos="16" type="boolean"/>
++ <bitfield name="CH2_CLK_LANE_EN" pos="17" type="boolean"/>
++ </reg32>
++
++ <array offset="0xc2014" name="LCDC_LVDS_MUX_CTL" length="4" stride="0x8">
++ <reg32 offset="0x0" name="3_TO_0">
++ <bitfield name="BIT0" low="0" high="7"/>
++ <bitfield name="BIT1" low="8" high="15"/>
++ <bitfield name="BIT2" low="16" high="23"/>
++ <bitfield name="BIT3" low="24" high="31"/>
++ </reg32>
++ <reg32 offset="0x4" name="6_TO_4">
++ <bitfield name="BIT4" low="0" high="7"/>
++ <bitfield name="BIT5" low="8" high="15"/>
++ <bitfield name="BIT6" low="16" high="23"/>
++ </reg32>
++ </array>
++
++ <reg32 offset="0xc2034" name="LCDC_LVDS_PHY_RESET"/>
++
++ <reg32 offset="0xc3000" name="LVDS_PHY_PLL_CTRL_0"/>
++ <reg32 offset="0xc3004" name="LVDS_PHY_PLL_CTRL_1"/>
++ <reg32 offset="0xc3008" name="LVDS_PHY_PLL_CTRL_2"/>
++ <reg32 offset="0xc300c" name="LVDS_PHY_PLL_CTRL_3"/>
++ <reg32 offset="0xc3014" name="LVDS_PHY_PLL_CTRL_5"/>
++ <reg32 offset="0xc3018" name="LVDS_PHY_PLL_CTRL_6"/>
++ <reg32 offset="0xc301c" name="LVDS_PHY_PLL_CTRL_7"/>
++ <reg32 offset="0xc3020" name="LVDS_PHY_PLL_CTRL_8"/>
++ <reg32 offset="0xc3024" name="LVDS_PHY_PLL_CTRL_9"/>
++ <reg32 offset="0xc3080" name="LVDS_PHY_PLL_LOCKED"/>
++ <reg32 offset="0xc3108" name="LVDS_PHY_CFG2"/>
++
++ <reg32 offset="0xc3100" name="LVDS_PHY_CFG0">
++ <bitfield name="SERIALIZATION_ENBLE" pos="4" type="boolean"/>
++ <bitfield name="CHANNEL0" pos="6" type="boolean"/>
++ <bitfield name="CHANNEL1" pos="7" type="boolean"/>
++ </reg32>
++
++ <array offset="0xd0000" name="DTV" length="1" stride="0x1000">
++ <reg32 offset="0x0000" name="ENABLE"/>
++ <reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/>
++ <reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/>
++ <reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/>
++ <reg32 offset="0x0018" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/>
++ <reg32 offset="0x001c" name="DISPLAY_VSTART" type="uint"/>
++ <reg32 offset="0x0020" name="DISPLAY_VEND" type="uint"/>
++ <reg32 offset="0x002c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/>
++ <reg32 offset="0x0030" name="ACTIVE_VSTART" type="uint"/>
++ <reg32 offset="0x0038" name="ACTIVE_VEND" type="uint"/>
++ <reg32 offset="0x0040" name="BORDER_CLR"/>
++ <reg32 offset="0x0044" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/>
++ <reg32 offset="0x0048" name="HSYNC_SKEW"/>
++ <reg32 offset="0x004c" name="TEST_CNTL"/>
++ <reg32 offset="0x0050" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/>
++ </array>
++
++ <array offset="0xe0000" name="DSI" length="1" stride="0x1000">
++ <reg32 offset="0x0000" name="ENABLE"/>
++ <reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/>
++ <reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/>
++ <reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/>
++ <reg32 offset="0x0010" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/>
++ <reg32 offset="0x0014" name="DISPLAY_VSTART" type="uint"/>
++ <reg32 offset="0x0018" name="DISPLAY_VEND" type="uint"/>
++ <reg32 offset="0x001c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/>
++ <reg32 offset="0x0020" name="ACTIVE_VSTART" type="uint"/>
++ <reg32 offset="0x0024" name="ACTIVE_VEND" type="uint"/>
++ <reg32 offset="0x0028" name="BORDER_CLR"/>
++ <reg32 offset="0x002c" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/>
++ <reg32 offset="0x0030" name="HSYNC_SKEW"/>
++ <reg32 offset="0x0034" name="TEST_CNTL"/>
++ <reg32 offset="0x0038" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/>
++ </array>
++</domain>
++
++</database>
+diff --git a/drivers/gpu/drm/msm/registers/display/mdp5.xml b/drivers/gpu/drm/msm/registers/display/mdp5.xml
+new file mode 100644
+index 0000000000000..92f3263af1701
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/display/mdp5.xml
+@@ -0,0 +1,806 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++<import file="display/mdp_common.xml"/>
++
++<!-- where does this belong? -->
++<domain name="VBIF" width="32">
++</domain>
++
++<domain name="MDSS" width="32">
++ <reg32 offset="0x00000" name="HW_VERSION">
++ <bitfield name="STEP" low="0" high="15" type="uint"/>
++ <bitfield name="MINOR" low="16" high="27" type="uint"/>
++ <bitfield name="MAJOR" low="28" high="31" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x00010" name="HW_INTR_STATUS">
++ <bitfield name="INTR_MDP" pos="0" type="boolean"/>
++ <bitfield name="INTR_DSI0" pos="4" type="boolean"/>
++ <bitfield name="INTR_DSI1" pos="5" type="boolean"/>
++ <bitfield name="INTR_HDMI" pos="8" type="boolean"/>
++ <bitfield name="INTR_EDP" pos="12" type="boolean"/>
++ </reg32>
++</domain>
++
++<domain name="MDP5" width="32">
++
++ <enum name="mdp5_intf_type">
++ <value name="INTF_DISABLED" value="0x0"/>
++ <value name="INTF_DSI" value="0x1"/>
++ <value name="INTF_HDMI" value="0x3"/>
++ <value name="INTF_LCDC" value="0x5"/>
++ <value name="INTF_eDP" value="0x9"/>
++ <value name="INTF_VIRTUAL" value="0x64"/>
++ <!-- non-display interfaces are listed below: -->
++ <value name="INTF_WB" value="0x65"/>
++ </enum>
++
++ <enum name="mdp5_intfnum">
++ <value name="NO_INTF" value="0"/>
++ <value name="INTF0" value="1"/>
++ <value name="INTF1" value="2"/>
++ <value name="INTF2" value="3"/>
++ <value name="INTF3" value="4"/>
++ </enum>
++
++ <enum name="mdp5_pipe">
++ <value name="SSPP_NONE" value="0"/>
++ <value name="SSPP_VIG0" value="1"/>
++ <value name="SSPP_VIG1" value="2"/>
++ <value name="SSPP_VIG2" value="3"/>
++ <value name="SSPP_RGB0" value="4"/>
++ <value name="SSPP_RGB1" value="5"/>
++ <value name="SSPP_RGB2" value="6"/>
++ <value name="SSPP_DMA0" value="7"/>
++ <value name="SSPP_DMA1" value="8"/>
++ <value name="SSPP_VIG3" value="9"/>
++ <value name="SSPP_RGB3" value="10"/>
++ <value name="SSPP_CURSOR0" value="11"/>
++ <value name="SSPP_CURSOR1" value="12"/>
++ </enum>
++
++ <enum name="mdp5_format">
++ <!-- TODO -->
++ <value name="DUMMY" value="0"/>
++ </enum>
++
++ <enum name="mdp5_ctl_mode">
++ <value name="MODE_NONE" value="0"/>
++ <value name="MODE_WB_0_BLOCK" value="1"/>
++ <value name="MODE_WB_1_BLOCK" value="2"/>
++ <value name="MODE_WB_0_LINE" value="3"/>
++ <value name="MODE_WB_1_LINE" value="4"/>
++ <value name="MODE_WB_2_LINE" value="5"/>
++ </enum>
++
++ <enum name="mdp5_pack_3d">
++ <value name="PACK_3D_FRAME_INT" value="0"/>
++ <value name="PACK_3D_H_ROW_INT" value="1"/>
++ <value name="PACK_3D_V_ROW_INT" value="2"/>
++ <value name="PACK_3D_COL_INT" value="3"/>
++ </enum>
++
++ <enum name="mdp5_scale_filter">
++ <value name="SCALE_FILTER_NEAREST" value="0"/>
++ <value name="SCALE_FILTER_BIL" value="1"/>
++ <value name="SCALE_FILTER_PCMN" value="2"/>
++ <value name="SCALE_FILTER_CA" value="3"/>
++ </enum>
++
++ <enum name="mdp5_pipe_bwc">
++ <value name="BWC_LOSSLESS" value="0"/>
++ <value name="BWC_Q_HIGH" value="1"/>
++ <value name="BWC_Q_MED" value="2"/>
++ </enum>
++
++ <enum name="mdp5_cursor_format">
++ <value name="CURSOR_FMT_ARGB8888" value="0"/>
++ <value name="CURSOR_FMT_ARGB1555" value="2"/>
++ <value name="CURSOR_FMT_ARGB4444" value="4"/>
++ </enum>
++
++ <enum name="mdp5_cursor_alpha">
++ <value name="CURSOR_ALPHA_CONST" value="0"/>
++ <value name="CURSOR_ALPHA_PER_PIXEL" value="2"/>
++ </enum>
++
++ <bitset name="MDP5_IRQ">
++ <bitfield name="WB_0_DONE" pos="0" type="boolean"/>
++ <bitfield name="WB_1_DONE" pos="1" type="boolean"/>
++ <bitfield name="WB_2_DONE" pos="4" type="boolean"/>
++ <bitfield name="PING_PONG_0_DONE" pos="8" type="boolean"/>
++ <bitfield name="PING_PONG_1_DONE" pos="9" type="boolean"/>
++ <bitfield name="PING_PONG_2_DONE" pos="10" type="boolean"/>
++ <bitfield name="PING_PONG_3_DONE" pos="11" type="boolean"/>
++ <bitfield name="PING_PONG_0_RD_PTR" pos="12" type="boolean"/>
++ <bitfield name="PING_PONG_1_RD_PTR" pos="13" type="boolean"/>
++ <bitfield name="PING_PONG_2_RD_PTR" pos="14" type="boolean"/>
++ <bitfield name="PING_PONG_3_RD_PTR" pos="15" type="boolean"/>
++ <bitfield name="PING_PONG_0_WR_PTR" pos="16" type="boolean"/>
++ <bitfield name="PING_PONG_1_WR_PTR" pos="17" type="boolean"/>
++ <bitfield name="PING_PONG_2_WR_PTR" pos="18" type="boolean"/>
++ <bitfield name="PING_PONG_3_WR_PTR" pos="19" type="boolean"/>
++ <bitfield name="PING_PONG_0_AUTO_REF" pos="20" type="boolean"/>
++ <bitfield name="PING_PONG_1_AUTO_REF" pos="21" type="boolean"/>
++ <bitfield name="PING_PONG_2_AUTO_REF" pos="22" type="boolean"/>
++ <bitfield name="PING_PONG_3_AUTO_REF" pos="23" type="boolean"/>
++ <bitfield name="INTF0_UNDER_RUN" pos="24" type="boolean"/>
++ <bitfield name="INTF0_VSYNC" pos="25" type="boolean"/>
++ <bitfield name="INTF1_UNDER_RUN" pos="26" type="boolean"/>
++ <bitfield name="INTF1_VSYNC" pos="27" type="boolean"/>
++ <bitfield name="INTF2_UNDER_RUN" pos="28" type="boolean"/>
++ <bitfield name="INTF2_VSYNC" pos="29" type="boolean"/>
++ <bitfield name="INTF3_UNDER_RUN" pos="30" type="boolean"/>
++ <bitfield name="INTF3_VSYNC" pos="31" type="boolean"/>
++ </bitset>
++
++ <bitset name="mdp5_smp_alloc" inline="yes">
++ <!-- Use "mdp5_cfg->mdp.smp.clients[enum mdp5_pipe]" instead -->
++ <bitfield name="CLIENT0" low="0" high="7" type="uint"/>
++ <bitfield name="CLIENT1" low="8" high="15" type="uint"/>
++ <bitfield name="CLIENT2" low="16" high="23" type="uint"/>
++ </bitset>
++
++ <reg32 offset="0x00000" name="HW_VERSION">
++ <bitfield name="STEP" low="0" high="15" type="uint"/>
++ <bitfield name="MINOR" low="16" high="27" type="uint"/>
++ <bitfield name="MAJOR" low="28" high="31" type="uint"/>
++ </reg32>
++
++ <reg32 offset="0x00004" name="DISP_INTF_SEL">
++ <bitfield name="INTF0" low="0" high="7" type="mdp5_intf_type"/>
++ <bitfield name="INTF1" low="8" high="15" type="mdp5_intf_type"/>
++ <bitfield name="INTF2" low="16" high="23" type="mdp5_intf_type"/>
++ <bitfield name="INTF3" low="24" high="31" type="mdp5_intf_type"/>
++ </reg32>
++ <reg32 offset="0x00010" name="INTR_EN" type="MDP5_IRQ"/>
++ <reg32 offset="0x00014" name="INTR_STATUS" type="MDP5_IRQ"/>
++ <reg32 offset="0x00018" name="INTR_CLEAR" type="MDP5_IRQ"/>
++ <reg32 offset="0x0001C" name="HIST_INTR_EN"/>
++ <reg32 offset="0x00020" name="HIST_INTR_STATUS"/>
++ <reg32 offset="0x00024" name="HIST_INTR_CLEAR"/>
++ <reg32 offset="0x00028" name="SPARE_0">
++ <bitfield name="SPLIT_DPL_SINGLE_FLUSH_EN" pos="0"/>
++ </reg32>
++
++ <array offset="0x00080" name="SMP_ALLOC_W" length="8" stride="4">
++ <reg32 offset="0" name="REG" type="mdp5_smp_alloc"/>
++ </array>
++ <array offset="0x00130" name="SMP_ALLOC_R" length="8" stride="4">
++ <reg32 offset="0" name="REG" type="mdp5_smp_alloc"/>
++ </array>
++
++ <enum name="mdp5_igc_type">
++ <value name="IGC_VIG" value="0"/> <!-- 0x200 -->
++ <value name="IGC_RGB" value="1"/> <!-- 0x210 -->
++ <value name="IGC_DMA" value="2"/> <!-- 0x220 -->
++ <value name="IGC_DSPP" value="3"/> <!-- 0x300 -->
++ </enum>
++ <array offsets="0x00200,0x00210,0x00220,0x00300" name="IGC" length="3" stride="0x10" index="mdp5_igc_type">
++ <array offset="0x00" name="LUT" length="3" stride="4">
++ <reg32 offset="0" name="REG">
++ <bitfield name="VAL" low="0" high="11"/>
++ <bitfield name="INDEX_UPDATE" pos="25" type="boolean"/>
++ <!--
++ not sure about these:
++ /* INDEX_UPDATE */
++ data = (1 << 25) | (((~(1 << blk_idx)) & 0x7) << 28);
++ MDSS_MDP_REG_WRITE(offset, (cfg->c0_c1_data[0] & 0xFFF) | data);
++ -->
++ <bitfield name="DISABLE_PIPE_0" pos="28" type="boolean"/>
++ <bitfield name="DISABLE_PIPE_1" pos="29" type="boolean"/>
++ <bitfield name="DISABLE_PIPE_2" pos="30" type="boolean"/>
++ </reg32>
++ </array>
++ </array>
++ <reg32 offset="0x002f4" name="SPLIT_DPL_EN"/>
++ <reg32 offset="0x002f8" name="SPLIT_DPL_UPPER">
++ <bitfield name="SMART_PANEL" pos="1" type="boolean"/>
++ <bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
++ <bitfield name="INTF1_SW_TRG_MUX" pos="4" type="boolean"/>
++ <bitfield name="INTF2_SW_TRG_MUX" pos="8" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x003f0" name="SPLIT_DPL_LOWER">
++ <bitfield name="SMART_PANEL" pos="1" type="boolean"/>
++ <bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
++ <bitfield name="INTF1_TG_SYNC" pos="4" type="boolean"/>
++ <bitfield name="INTF2_TG_SYNC" pos="8" type="boolean"/>
++ </reg32>
++
++<!-- check length/index.. -->
++ <array doffsets="mdp5_cfg->ctl.base[0],mdp5_cfg->ctl.base[1],mdp5_cfg->ctl.base[2],mdp5_cfg->ctl.base[3],mdp5_cfg->ctl.base[4]" name="CTL" length="5" stride="0x400">
++ <array offsets="0x000,0x004,0x008,0x00C,0x010,0x024" name="LAYER" length="6" stride="4">
++ <!--
++ NOTE: for backwards compat (from when there were fewer stages),
++ this register has the low three bits of mdp_mixer_stage_id, with
++ the high bit coming from LAYER_EXT
++ -->
++ <reg32 offset="0" name="REG">
++ <bitfield name="VIG0" low="0" high="2" type="uint"/>
++ <bitfield name="VIG1" low="3" high="5" type="uint"/>
++ <bitfield name="VIG2" low="6" high="8" type="uint"/>
++ <bitfield name="RGB0" low="9" high="11" type="uint"/>
++ <bitfield name="RGB1" low="12" high="14" type="uint"/>
++ <bitfield name="RGB2" low="15" high="17" type="uint"/>
++ <bitfield name="DMA0" low="18" high="20" type="uint"/>
++ <bitfield name="DMA1" low="21" high="23" type="uint"/>
++ <bitfield name="BORDER_COLOR" pos="24" type="boolean"/>
++ <bitfield name="CURSOR_OUT" pos="25" type="boolean"/>
++ <bitfield name="VIG3" low="26" high="28" type="uint"/>
++ <bitfield name="RGB3" low="29" high="31" type="uint"/>
++ </reg32>
++ </array>
++ <reg32 offset="0x014" name="OP">
++ <bitfield name="MODE" low="0" high="3" type="mdp5_ctl_mode"/>
++ <bitfield name="INTF_NUM" low="4" high="6" type="mdp5_intfnum"/>
++ <bitfield name="CMD_MODE" pos="17" type="boolean"/>
++ <bitfield name="PACK_3D_ENABLE" pos="19" type="boolean"/>
++ <bitfield name="PACK_3D" low="20" high="21" type="mdp5_pack_3d"/>
++ </reg32>
++ <reg32 offset="0x018" name="FLUSH">
++ <bitfield name="VIG0" pos="0" type="boolean"/>
++ <bitfield name="VIG1" pos="1" type="boolean"/>
++ <bitfield name="VIG2" pos="2" type="boolean"/>
++ <bitfield name="RGB0" pos="3" type="boolean"/>
++ <bitfield name="RGB1" pos="4" type="boolean"/>
++ <bitfield name="RGB2" pos="5" type="boolean"/>
++ <bitfield name="LM0" pos="6" type="boolean"/>
++ <bitfield name="LM1" pos="7" type="boolean"/>
++ <bitfield name="LM2" pos="8" type="boolean"/>
++ <bitfield name="LM3" pos="9" type="boolean"/>
++ <bitfield name="LM4" pos="10" type="boolean"/>
++ <bitfield name="DMA0" pos="11" type="boolean"/>
++ <bitfield name="DMA1" pos="12" type="boolean"/>
++ <bitfield name="DSPP0" pos="13" type="boolean"/>
++ <bitfield name="DSPP1" pos="14" type="boolean"/>
++ <bitfield name="DSPP2" pos="15" type="boolean"/>
++ <bitfield name="WB" pos="16" type="boolean"/>
++ <bitfield name="CTL" pos="17" type="boolean"/>
++ <bitfield name="VIG3" pos="18" type="boolean"/>
++ <bitfield name="RGB3" pos="19" type="boolean"/>
++ <bitfield name="LM5" pos="20" type="boolean"/>
++ <bitfield name="DSPP3" pos="21" type="boolean"/>
++ <bitfield name="CURSOR_0" pos="22" type="boolean"/>
++ <bitfield name="CURSOR_1" pos="23" type="boolean"/>
++ <bitfield name="CHROMADOWN_0" pos="26" type="boolean"/>
++ <bitfield name="TIMING_3" pos="28" type="boolean"/>
++ <bitfield name="TIMING_2" pos="29" type="boolean"/>
++ <bitfield name="TIMING_1" pos="30" type="boolean"/>
++ <bitfield name="TIMING_0" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x01C" name="START"/>
++ <reg32 offset="0x020" name="PACK_3D"/>
++ <array offsets="0x040,0x044,0x048,0x04C,0x050,0x054" name="LAYER_EXT" length="6" stride="4">
++ <reg32 offset="0" name="REG">
++ <bitfield name="VIG0_BIT3" pos="0" type="boolean"/>
++ <bitfield name="VIG1_BIT3" pos="2" type="boolean"/>
++ <bitfield name="VIG2_BIT3" pos="4" type="boolean"/>
++ <bitfield name="VIG3_BIT3" pos="6" type="boolean"/>
++ <bitfield name="RGB0_BIT3" pos="8" type="boolean"/>
++ <bitfield name="RGB1_BIT3" pos="10" type="boolean"/>
++ <bitfield name="RGB2_BIT3" pos="12" type="boolean"/>
++ <bitfield name="RGB3_BIT3" pos="14" type="boolean"/>
++ <bitfield name="DMA0_BIT3" pos="16" type="boolean"/>
++ <bitfield name="DMA1_BIT3" pos="18" type="boolean"/>
++ <bitfield name="CURSOR0" low="20" high="23" type="mdp_mixer_stage_id"/>
++ <bitfield name="CURSOR1" low="26" high="29" type="mdp_mixer_stage_id"/>
++ </reg32>
++ </array>
++ </array>
++
++ <enum name="mdp5_data_format">
++ <value name="DATA_FORMAT_RGB" value="0"/>
++ <value name="DATA_FORMAT_YUV" value="1"/>
++ </enum>
++
++ <array doffsets="INVALID_IDX(idx),mdp5_cfg->pipe_vig.base[0],mdp5_cfg->pipe_vig.base[1],mdp5_cfg->pipe_vig.base[2],mdp5_cfg->pipe_rgb.base[0],mdp5_cfg->pipe_rgb.base[1],mdp5_cfg->pipe_rgb.base[2],mdp5_cfg->pipe_dma.base[0],mdp5_cfg->pipe_dma.base[1],mdp5_cfg->pipe_vig.base[3],mdp5_cfg->pipe_rgb.base[3],mdp5_cfg->pipe_cursor.base[0],mdp5_cfg->pipe_cursor.base[1]" name="PIPE" length="10" stride="0x400" index="mdp5_pipe">
++ <reg32 offset="0x200" name="OP_MODE">
++ <bitfield name="CSC_DST_DATA_FORMAT" pos="19" type="mdp5_data_format"/>
++ <bitfield name="CSC_SRC_DATA_FORMAT" pos="18" type="mdp5_data_format"/>
++ <bitfield name="CSC_1_EN" pos="17" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x2C4" name="HIST_CTL_BASE"/>
++ <reg32 offset="0x2F0" name="HIST_LUT_BASE"/>
++ <reg32 offset="0x300" name="HIST_LUT_SWAP"/>
++ <reg32 offset="0x320" name="CSC_1_MATRIX_COEFF_0">
++ <bitfield name="COEFF_11" low="0" high="12" type="uint"/>
++ <bitfield name="COEFF_12" low="16" high="28" type="uint"/>
++ </reg32>
++ <reg32 offset="0x324" name="CSC_1_MATRIX_COEFF_1">
++ <bitfield name="COEFF_13" low="0" high="12" type="uint"/>
++ <bitfield name="COEFF_21" low="16" high="28" type="uint"/>
++ </reg32>
++ <reg32 offset="0x328" name="CSC_1_MATRIX_COEFF_2">
++ <bitfield name="COEFF_22" low="0" high="12" type="uint"/>
++ <bitfield name="COEFF_23" low="16" high="28" type="uint"/>
++ </reg32>
++ <reg32 offset="0x32c" name="CSC_1_MATRIX_COEFF_3">
++ <bitfield name="COEFF_31" low="0" high="12" type="uint"/>
++ <bitfield name="COEFF_32" low="16" high="28" type="uint"/>
++ </reg32>
++ <reg32 offset="0x330" name="CSC_1_MATRIX_COEFF_4">
++ <bitfield name="COEFF_33" low="0" high="12" type="uint"/>
++ </reg32>
++ <array offset="0x334" name="CSC_1_PRE_CLAMP" length="3" stride="4">
++ <reg32 offset="0" name="REG">
++ <bitfield name="HIGH" low="0" high="7" type="uint"/>
++ <bitfield name="LOW" low="8" high="15" type="uint"/>
++ </reg32>
++ </array>
++ <array offset="0x340" name="CSC_1_POST_CLAMP" length="3" stride="4">
++ <reg32 offset="0" name="REG">
++ <bitfield name="HIGH" low="0" high="7" type="uint"/>
++ <bitfield name="LOW" low="8" high="15" type="uint"/>
++ </reg32>
++ </array>
++ <array offset="0x34c" name="CSC_1_PRE_BIAS" length="3" stride="4">
++ <reg32 offset="0" name="REG">
++ <bitfield name="VALUE" low="0" high="8" type="uint"/>
++ </reg32>
++ </array>
++ <array offset="0x358" name="CSC_1_POST_BIAS" length="3" stride="4">
++ <reg32 offset="0" name="REG">
++ <bitfield name="VALUE" low="0" high="8" type="uint"/>
++ </reg32>
++ </array>
++ <!-- SSPP: -->
++ <reg32 offset="0x000" name="SRC_SIZE" type="reg_wh"/>
++ <reg32 offset="0x004" name="SRC_IMG_SIZE" type="reg_wh"/>
++ <reg32 offset="0x008" name="SRC_XY" type="reg_xy"/>
++ <reg32 offset="0x00C" name="OUT_SIZE" type="reg_wh"/>
++ <reg32 offset="0x010" name="OUT_XY" type="reg_xy"/>
++ <reg32 offset="0x014" name="SRC0_ADDR"/>
++ <reg32 offset="0x018" name="SRC1_ADDR"/>
++ <reg32 offset="0x01C" name="SRC2_ADDR"/>
++ <reg32 offset="0x020" name="SRC3_ADDR"/>
++ <reg32 offset="0x024" name="SRC_STRIDE_A">
++ <bitfield name="P0" low="0" high="15" type="uint"/>
++ <bitfield name="P1" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x028" name="SRC_STRIDE_B">
++ <bitfield name="P2" low="0" high="15" type="uint"/>
++ <bitfield name="P3" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x02C" name="STILE_FRAME_SIZE"/>
++ <reg32 offset="0x030" name="SRC_FORMAT">
++ <bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/>
++ <bitfield name="B_BPC" low="2" high="3" type="mdp_bpc"/>
++ <bitfield name="R_BPC" low="4" high="5" type="mdp_bpc"/>
++ <bitfield name="A_BPC" low="6" high="7" type="mdp_bpc_alpha"/>
++ <bitfield name="ALPHA_ENABLE" pos="8" type="boolean"/>
++ <bitfield name="CPP" low="9" high="10" type="uint">
++ <brief>8bit characters per pixel minus 1</brief>
++ </bitfield>
++ <bitfield name="ROT90" pos="11" type="boolean"/>
++ <bitfield name="UNPACK_COUNT" low="12" high="13" type="uint"/>
++ <bitfield name="UNPACK_TIGHT" pos="17" type="boolean"/>
++ <bitfield name="UNPACK_ALIGN_MSB" pos="18" type="boolean"/>
++ <bitfield name="FETCH_TYPE" low="19" high="20" type="mdp_fetch_type"/>
++ <bitfield name="CHROMA_SAMP" low="23" high="24" type="mdp_chroma_samp_type"/>
++ </reg32>
++ <reg32 offset="0x034" name="SRC_UNPACK" type="mdp_unpack_pattern"/>
++ <reg32 offset="0x038" name="SRC_OP_MODE">
++ <bitfield name="BWC_EN" pos="0" type="boolean"/>
++ <bitfield name="BWC" low="1" high="2" type="mdp5_pipe_bwc"/>
++ <bitfield name="FLIP_LR" pos="13" type="boolean"/>
++ <bitfield name="FLIP_UD" pos="14" type="boolean"/>
++ <bitfield name="IGC_EN" pos="16" type="boolean"/>
++ <bitfield name="IGC_ROM_0" pos="17" type="boolean"/>
++ <bitfield name="IGC_ROM_1" pos="18" type="boolean"/>
++ <bitfield name="DEINTERLACE" pos="22" type="boolean"/>
++ <bitfield name="DEINTERLACE_ODD" pos="23" type="boolean"/>
++ <bitfield name="SW_PIX_EXT_OVERRIDE" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x03c" name="SRC_CONSTANT_COLOR"/>
++ <reg32 offset="0x048" name="FETCH_CONFIG"/>
++ <reg32 offset="0x04c" name="VC1_RANGE"/>
++ <reg32 offset="0x050" name="REQPRIO_FIFO_WM_0"/>
++ <reg32 offset="0x054" name="REQPRIO_FIFO_WM_1"/>
++ <reg32 offset="0x058" name="REQPRIO_FIFO_WM_2"/>
++ <reg32 offset="0x070" name="SRC_ADDR_SW_STATUS"/>
++ <reg32 offset="0x0a4" name="CURRENT_SRC0_ADDR"/>
++ <reg32 offset="0x0a8" name="CURRENT_SRC1_ADDR"/>
++ <reg32 offset="0x0ac" name="CURRENT_SRC2_ADDR"/>
++ <reg32 offset="0x0b0" name="CURRENT_SRC3_ADDR"/>
++ <reg32 offset="0x0b4" name="DECIMATION">
++ <bitfield name="VERT" low="0" high="7" type="uint"/>
++ <bitfield name="HORZ" low="8" high="15" type="uint"/>
++ </reg32>
++ <array offsets="0x100,0x110,0x120" name="SW_PIX_EXT" length="3" stride="0x10" index="mdp_component_type">
++ <!--
++ Notes:
++ o These value only take effect if SW_PIX_EXT_OVERRIDE is set in SRC_OP_MODE register
++ o For signed values (int): + indicates overfetch, - indicates line drop
++ -->
++ <reg32 offset="0x00" name="LR">
++ <bitfield name="LEFT_RPT" low="0" high="7" type="uint"/>
++ <bitfield name="LEFT_OVF" low="8" high="15" type="int"/>
++ <bitfield name="RIGHT_RPT" low="16" high="23" type="uint"/>
++ <bitfield name="RIGHT_OVF" low="24" high="31" type="int"/>
++ </reg32>
++ <reg32 offset="0x04" name="TB">
++ <bitfield name="TOP_RPT" low="0" high="7" type="uint"/>
++ <bitfield name="TOP_OVF" low="8" high="15" type="int"/>
++ <bitfield name="BOTTOM_RPT" low="16" high="23" type="uint"/>
++ <bitfield name="BOTTOM_OVF" low="24" high="31" type="int"/>
++ </reg32>
++ <reg32 offset="0x08" name="REQ_PIXELS">
++ <bitfield name="LEFT_RIGHT" low="0" high="15" type="uint"/>
++ <bitfield name="TOP_BOTTOM" low="16" high="31" type="uint"/>
++ </reg32>
++ </array>
++ <reg32 offset="0x204" name="SCALE_CONFIG">
++ <bitfield name="SCALEX_EN" pos="0" type="boolean"/>
++ <bitfield name="SCALEY_EN" pos="1" type="boolean"/>
++ <bitfield name="SCALEX_FILTER_COMP_0" low="8" high="9" type="mdp5_scale_filter"/>
++ <bitfield name="SCALEY_FILTER_COMP_0" low="10" high="11" type="mdp5_scale_filter"/>
++ <bitfield name="SCALEX_FILTER_COMP_1_2" low="12" high="13" type="mdp5_scale_filter"/>
++ <bitfield name="SCALEY_FILTER_COMP_1_2" low="14" high="15" type="mdp5_scale_filter"/>
++ <bitfield name="SCALEX_FILTER_COMP_3" low="16" high="17" type="mdp5_scale_filter"/>
++ <bitfield name="SCALEY_FILTER_COMP_3" low="18" high="19" type="mdp5_scale_filter"/>
++ </reg32>
++ <reg32 offset="0x210" name="SCALE_PHASE_STEP_X"/>
++ <reg32 offset="0x214" name="SCALE_PHASE_STEP_Y"/>
++ <reg32 offset="0x218" name="SCALE_CR_PHASE_STEP_X"/>
++ <reg32 offset="0x21c" name="SCALE_CR_PHASE_STEP_Y"/>
++ <reg32 offset="0x220" name="SCALE_INIT_PHASE_X"/>
++ <reg32 offset="0x224" name="SCALE_INIT_PHASE_Y"/>
++ </array>
++
++ <array doffsets="mdp5_cfg->lm.base[0],mdp5_cfg->lm.base[1],mdp5_cfg->lm.base[2],mdp5_cfg->lm.base[3],mdp5_cfg->lm.base[4],mdp5_cfg->lm.base[5]" name="LM" length="6" stride="0x400">
++ <reg32 offset="0x000" name="BLEND_COLOR_OUT">
++ <bitfield name="STAGE0_FG_ALPHA" pos="1" type="boolean"/>
++ <bitfield name="STAGE1_FG_ALPHA" pos="2" type="boolean"/>
++ <bitfield name="STAGE2_FG_ALPHA" pos="3" type="boolean"/>
++ <bitfield name="STAGE3_FG_ALPHA" pos="4" type="boolean"/>
++ <bitfield name="STAGE4_FG_ALPHA" pos="5" type="boolean"/>
++ <bitfield name="STAGE5_FG_ALPHA" pos="6" type="boolean"/>
++ <bitfield name="STAGE6_FG_ALPHA" pos="7" type="boolean"/>
++ <bitfield name="SPLIT_LEFT_RIGHT" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x004" name="OUT_SIZE" type="reg_wh"/>
++ <reg32 offset="0x008" name="BORDER_COLOR_0"/>
++ <reg32 offset="0x010" name="BORDER_COLOR_1"/>
++ <array offsets="0x020,0x050,0x080,0x0B0,0x230,0x260,0x290" name="BLEND" length="7" stride="0x30">
++ <reg32 offset="0x00" name="OP_MODE">
++ <bitfield name="FG_ALPHA" low="0" high="1" type="mdp_alpha_type"/>
++ <bitfield name="FG_INV_ALPHA" pos="2" type="boolean"/>
++ <bitfield name="FG_MOD_ALPHA" pos="3" type="boolean"/>
++ <bitfield name="FG_INV_MOD_ALPHA" pos="4" type="boolean"/>
++ <bitfield name="FG_TRANSP_EN" pos="5" type="boolean"/>
++ <bitfield name="BG_ALPHA" low="8" high="9" type="mdp_alpha_type"/>
++ <bitfield name="BG_INV_ALPHA" pos="10" type="boolean"/>
++ <bitfield name="BG_MOD_ALPHA" pos="11" type="boolean"/>
++ <bitfield name="BG_INV_MOD_ALPHA" pos="12" type="boolean"/>
++ <bitfield name="BG_TRANSP_EN" pos="13" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x04" name="FG_ALPHA"/>
++ <reg32 offset="0x08" name="BG_ALPHA"/>
++ <reg32 offset="0x0c" name="FG_TRANSP_LOW0"/>
++ <reg32 offset="0x10" name="FG_TRANSP_LOW1"/>
++ <reg32 offset="0x14" name="FG_TRANSP_HIGH0"/>
++ <reg32 offset="0x18" name="FG_TRANSP_HIGH1"/>
++ <reg32 offset="0x1c" name="BG_TRANSP_LOW0"/>
++ <reg32 offset="0x20" name="BG_TRANSP_LOW1"/>
++ <reg32 offset="0x24" name="BG_TRANSP_HIGH0"/>
++ <reg32 offset="0x28" name="BG_TRANSP_HIGH1"/>
++ </array>
++ <reg32 offset="0x0e0" name="CURSOR_IMG_SIZE">
++ <bitfield name="SRC_W" low="0" high="15" type="uint"/>
++ <bitfield name="SRC_H" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0e4" name="CURSOR_SIZE">
++ <bitfield name="ROI_W" low="0" high="15" type="uint"/>
++ <bitfield name="ROI_H" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0e8" name="CURSOR_XY">
++ <bitfield name="SRC_X" low="0" high="15" type="uint"/>
++ <bitfield name="SRC_Y" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0dc" name="CURSOR_STRIDE">
++ <bitfield name="STRIDE" low="0" high="15" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0ec" name="CURSOR_FORMAT">
++ <bitfield name="FORMAT" low="0" high="2" type="mdp5_cursor_format"/>
++ </reg32>
++ <reg32 offset="0x0f0" name="CURSOR_BASE_ADDR"/>
++ <reg32 offset="0x0f4" name="CURSOR_START_XY">
++ <bitfield name="X_START" low="0" high="15" type="uint"/>
++ <bitfield name="Y_START" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x0f8" name="CURSOR_BLEND_CONFIG">
++ <bitfield name="BLEND_EN" pos="0" type="boolean"/>
++ <bitfield name="BLEND_ALPHA_SEL" low="1" high="2" type="mdp5_cursor_alpha"/>
++ <bitfield name="BLEND_TRANSP_EN" pos="3" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x0fc" name="CURSOR_BLEND_PARAM"/>
++ <reg32 offset="0x100" name="CURSOR_BLEND_TRANSP_LOW0"/>
++ <reg32 offset="0x104" name="CURSOR_BLEND_TRANSP_LOW1"/>
++ <reg32 offset="0x108" name="CURSOR_BLEND_TRANSP_HIGH0"/>
++ <reg32 offset="0x10c" name="CURSOR_BLEND_TRANSP_HIGH1"/>
++ <reg32 offset="0x110" name="GC_LUT_BASE"/>
++ </array>
++
++ <array doffsets="mdp5_cfg->dspp.base[0],mdp5_cfg->dspp.base[1],mdp5_cfg->dspp.base[2],mdp5_cfg->dspp.base[3]" name="DSPP" length="4" stride="0x400">
++ <reg32 offset="0x000" name="OP_MODE">
++ <bitfield name="IGC_LUT_EN" pos="0" type="boolean"/>
++ <bitfield name="IGC_TBL_IDX" low="1" high="3" type="uint"/>
++ <bitfield name="PCC_EN" pos="4" type="boolean"/>
++ <bitfield name="DITHER_EN" pos="8" type="boolean"/>
++ <bitfield name="HIST_EN" pos="16" type="boolean"/>
++ <bitfield name="AUTO_CLEAR" pos="17" type="boolean"/>
++ <bitfield name="HIST_LUT_EN" pos="19" type="boolean"/>
++ <bitfield name="PA_EN" pos="20" type="boolean"/>
++ <bitfield name="GAMUT_EN" pos="23" type="boolean"/>
++ <bitfield name="GAMUT_ORDER" pos="24" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x030" name="PCC_BASE"/>
++ <reg32 offset="0x150" name="DITHER_DEPTH"/>
++ <reg32 offset="0x210" name="HIST_CTL_BASE"/>
++ <reg32 offset="0x230" name="HIST_LUT_BASE"/>
++ <reg32 offset="0x234" name="HIST_LUT_SWAP"/>
++ <reg32 offset="0x238" name="PA_BASE"/>
++ <reg32 offset="0x2dc" name="GAMUT_BASE"/>
++ <reg32 offset="0x2b0" name="GC_BASE"/>
++ </array>
++
++ <array doffsets="mdp5_cfg->pp.base[0],mdp5_cfg->pp.base[1],mdp5_cfg->pp.base[2],mdp5_cfg->pp.base[3]" name="PP" length="4" stride="0x100">
++ <reg32 offset="0x000" name="TEAR_CHECK_EN"/>
++ <reg32 offset="0x004" name="SYNC_CONFIG_VSYNC">
++ <bitfield name="COUNT" low="0" high="18" type="uint"/>
++ <bitfield name="COUNTER_EN" pos="19" type="boolean"/>
++ <bitfield name="IN_EN" pos="20" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x008" name="SYNC_CONFIG_HEIGHT"/>
++ <reg32 offset="0x00c" name="SYNC_WRCOUNT">
++ <bitfield name="LINE_COUNT" low="0" high="15" type="uint"/>
++ <bitfield name="FRAME_COUNT" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x010" name="VSYNC_INIT_VAL"/>
++ <reg32 offset="0x014" name="INT_COUNT_VAL">
++ <bitfield name="LINE_COUNT" low="0" high="15" type="uint"/>
++ <bitfield name="FRAME_COUNT" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x018" name="SYNC_THRESH">
++ <bitfield name="START" low="0" high="15" type="uint"/>
++ <bitfield name="CONTINUE" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x01c" name="START_POS"/>
++ <reg32 offset="0x020" name="RD_PTR_IRQ"/>
++ <reg32 offset="0x024" name="WR_PTR_IRQ"/>
++ <reg32 offset="0x028" name="OUT_LINE_COUNT"/>
++ <reg32 offset="0x02c" name="PP_LINE_COUNT"/>
++ <reg32 offset="0x030" name="AUTOREFRESH_CONFIG"/>
++ <reg32 offset="0x034" name="FBC_MODE"/>
++ <reg32 offset="0x038" name="FBC_BUDGET_CTL"/>
++ <reg32 offset="0x03c" name="FBC_LOSSY_MODE"/>
++ </array>
++
++ <enum name="mdp5_block_size">
++ <value name="BLOCK_SIZE_64" value="0"/>
++ <value name="BLOCK_SIZE_128" value="1"/>
++ </enum>
++
++ <enum name="mdp5_rotate_mode">
++ <value name="ROTATE_0" value="0"/>
++ <value name="ROTATE_90" value="1"/>
++ </enum>
++
++ <enum name="mdp5_chroma_downsample_method">
++ <value name="DS_MTHD_NO_PIXEL_DROP" value="0"/>
++ <value name="DS_MTHD_PIXEL_DROP" value="1"/>
++ </enum>
++
++ <array doffsets="mdp5_cfg->wb.base[0],mdp5_cfg->wb.base[1],mdp5_cfg->wb.base[2],mdp5_cfg->wb.base[3],mdp5_cfg->wb.base[4]" name="WB" length="5" stride="0x400">
++ <reg32 offset="0x000" name="DST_FORMAT">
++ <bitfield name="DSTC0_OUT" low="0" high="1" type="uint"/>
++ <bitfield name="DSTC1_OUT" low="2" high="3" type="uint"/>
++ <bitfield name="DSTC2_OUT" low="4" high="5" type="uint"/>
++ <bitfield name="DSTC3_OUT" low="6" high="7" type="uint"/>
++ <bitfield name="DSTC3_EN" pos="8" type="boolean"/>
++ <bitfield name="DST_BPP" low="9" high="10" type="uint"/>
++ <bitfield name="PACK_COUNT" low="12" high="13" type="uint"/>
++ <bitfield name="DST_ALPHA_X" pos="14" type="boolean"/>
++ <bitfield name="PACK_TIGHT" pos="17" type="boolean"/>
++ <bitfield name="PACK_ALIGN_MSB" pos="18" type="boolean"/>
++ <bitfield name="WRITE_PLANES" low="19" high="20" type="uint"/>
++ <bitfield name="DST_DITHER_EN" pos="22" type="boolean"/>
++ <bitfield name="DST_CHROMA_SAMP" low="23" high="25" type="uint"/>
++ <bitfield name="DST_CHROMA_SITE" low="26" high="29" type="uint"/>
++ <bitfield name="FRAME_FORMAT" low="30" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x004" name="DST_OP_MODE">
++ <bitfield name="BWC_ENC_EN" pos="0" type="boolean"/>
++ <bitfield name="BWC_ENC_OP" low="1" high="2" type="uint"/>
++ <bitfield name="BLOCK_SIZE" low="4" high="4" type="uint"/>
++ <bitfield name="ROT_MODE" low="5" high="5" type="uint"/>
++ <bitfield name="ROT_EN" pos="6" type="boolean"/>
++ <bitfield name="CSC_EN" pos="8" type="boolean"/>
++ <bitfield name="CSC_SRC_DATA_FORMAT" low="9" high="9" type="uint"/>
++ <bitfield name="CSC_DST_DATA_FORMAT" low="10" high="10" type="uint"/>
++ <bitfield name="CHROMA_DWN_SAMPLE_EN" pos="11" type="boolean"/>
++ <bitfield name="CHROMA_DWN_SAMPLE_FORMAT" low="12" high="12" type="uint"/>
++ <bitfield name="CHROMA_DWN_SAMPLE_H_MTHD" low="13" high="13" type="uint"/>
++ <bitfield name="CHROMA_DWN_SAMPLE_V_MTHD" low="14" high="14" type="uint"/>
++ </reg32>
++ <reg32 offset="0x008" name="DST_PACK_PATTERN">
++ <bitfield name="ELEMENT0" low="0" high="1" type="uint"/>
++ <bitfield name="ELEMENT1" low="8" high="9" type="uint"/>
++ <bitfield name="ELEMENT2" low="16" high="17" type="uint"/>
++ <bitfield name="ELEMENT3" low="24" high="25" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00c" name="DST0_ADDR"/>
++ <reg32 offset="0x010" name="DST1_ADDR"/>
++ <reg32 offset="0x014" name="DST2_ADDR"/>
++ <reg32 offset="0x018" name="DST3_ADDR"/>
++ <reg32 offset="0x01c" name="DST_YSTRIDE0">
++ <bitfield name="DST0_YSTRIDE" low="0" high="15" type="uint"/>
++ <bitfield name="DST1_YSTRIDE" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x020" name="DST_YSTRIDE1">
++ <bitfield name="DST2_YSTRIDE" low="0" high="15" type="uint"/>
++ <bitfield name="DST3_YSTRIDE" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x024" name="DST_DITHER_BITDEPTH"/>
++ <reg32 offset="0x030" name="DITHER_MATRIX_ROW0"/>
++ <reg32 offset="0x034" name="DITHER_MATRIX_ROW1"/>
++ <reg32 offset="0x038" name="DITHER_MATRIX_ROW2"/>
++ <reg32 offset="0x03c" name="DITHER_MATRIX_ROW3"/>
++ <reg32 offset="0x048" name="DST_WRITE_CONFIG"/>
++ <reg32 offset="0x050" name="ROTATION_DNSCALER"/>
++ <reg32 offset="0x060" name="N16_INIT_PHASE_X_0_3"/>
++ <reg32 offset="0x064" name="N16_INIT_PHASE_X_1_2"/>
++ <reg32 offset="0x068" name="N16_INIT_PHASE_Y_0_3"/>
++ <reg32 offset="0x06c" name="N16_INIT_PHASE_Y_1_2"/>
++ <reg32 offset="0x074" name="OUT_SIZE">
++ <bitfield name="DST_W" low="0" high="15" type="uint"/>
++ <bitfield name="DST_H" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x078" name="ALPHA_X_VALUE"/>
++ <reg32 offset="0x260" name="CSC_MATRIX_COEFF_0">
++ <bitfield name="COEFF_11" low="0" high="12" type="uint"/>
++ <bitfield name="COEFF_12" low="16" high="28" type="uint"/>
++ </reg32>
++ <reg32 offset="0x264" name="CSC_MATRIX_COEFF_1">
++ <bitfield name="COEFF_13" low="0" high="12" type="uint"/>
++ <bitfield name="COEFF_21" low="16" high="28" type="uint"/>
++ </reg32>
++ <reg32 offset="0x268" name="CSC_MATRIX_COEFF_2">
++ <bitfield name="COEFF_22" low="0" high="12" type="uint"/>
++ <bitfield name="COEFF_23" low="16" high="28" type="uint"/>
++ </reg32>
++ <reg32 offset="0x26c" name="CSC_MATRIX_COEFF_3">
++ <bitfield name="COEFF_31" low="0" high="12" type="uint"/>
++ <bitfield name="COEFF_32" low="16" high="28" type="uint"/>
++ </reg32>
++ <reg32 offset="0x270" name="CSC_MATRIX_COEFF_4">
++ <bitfield name="COEFF_33" low="0" high="12" type="uint"/>
++ </reg32>
++ <array offset="0x274" name="CSC_COMP_PRECLAMP" length="3" stride="4">
++ <reg32 offset="0" name="REG">
++ <bitfield name="HIGH" low="0" high="7" type="uint"/>
++ <bitfield name="LOW" low="8" high="15" type="uint"/>
++ </reg32>
++ </array>
++ <array offset="0x280" name="CSC_COMP_POSTCLAMP" length="3" stride="4">
++ <reg32 offset="0" name="REG">
++ <bitfield name="HIGH" low="0" high="7" type="uint"/>
++ <bitfield name="LOW" low="8" high="15" type="uint"/>
++ </reg32>
++ </array>
++ <array offset="0x28c" name="CSC_COMP_PREBIAS" length="3" stride="4">
++ <reg32 offset="0" name="REG">
++ <bitfield name="VALUE" low="0" high="8" type="uint"/>
++ </reg32>
++ </array>
++ <array offset="0x298" name="CSC_COMP_POSTBIAS" length="3" stride="4">
++ <reg32 offset="0" name="REG">
++ <bitfield name="VALUE" low="0" high="8" type="uint"/>
++ </reg32>
++ </array>
++ </array>
++
++ <array doffsets="mdp5_cfg->intf.base[0],mdp5_cfg->intf.base[1],mdp5_cfg->intf.base[2],mdp5_cfg->intf.base[3],mdp5_cfg->intf.base[4]" name="INTF" length="5" stride="0x200">
++ <reg32 offset="0x000" name="TIMING_ENGINE_EN"/>
++ <reg32 offset="0x004" name="CONFIG"/>
++ <reg32 offset="0x008" name="HSYNC_CTL">
++ <bitfield name="PULSEW" low="0" high="15" type="uint"/>
++ <bitfield name="PERIOD" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x00c" name="VSYNC_PERIOD_F0" type="uint"/>
++ <reg32 offset="0x010" name="VSYNC_PERIOD_F1" type="uint"/>
++ <reg32 offset="0x014" name="VSYNC_LEN_F0" type="uint"/>
++ <reg32 offset="0x018" name="VSYNC_LEN_F1" type="uint"/>
++ <reg32 offset="0x01c" name="DISPLAY_VSTART_F0" type="uint"/>
++ <reg32 offset="0x020" name="DISPLAY_VSTART_F1" type="uint"/>
++ <reg32 offset="0x024" name="DISPLAY_VEND_F0" type="uint"/>
++ <reg32 offset="0x028" name="DISPLAY_VEND_F1" type="uint"/>
++ <reg32 offset="0x02c" name="ACTIVE_VSTART_F0">
++ <bitfield name="VAL" low="0" high="30" type="uint"/>
++ <bitfield name="ACTIVE_V_ENABLE" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x030" name="ACTIVE_VSTART_F1">
++ <bitfield name="VAL" low="0" high="30" type="uint"/>
++ </reg32>
++ <reg32 offset="0x034" name="ACTIVE_VEND_F0" type="uint"/>
++ <reg32 offset="0x038" name="ACTIVE_VEND_F1" type="uint"/>
++ <reg32 offset="0x03c" name="DISPLAY_HCTL">
++ <bitfield name="START" low="0" high="15" type="uint"/>
++ <bitfield name="END" low="16" high="31" type="uint"/>
++ </reg32>
++ <reg32 offset="0x040" name="ACTIVE_HCTL">
++ <bitfield name="START" low="0" high="14" type="uint"/>
++ <bitfield name="END" low="16" high="30" type="uint"/>
++ <bitfield name="ACTIVE_H_ENABLE" pos="31" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x044" name="BORDER_COLOR"/>
++ <reg32 offset="0x048" name="UNDERFLOW_COLOR"/>
++ <reg32 offset="0x04c" name="HSYNC_SKEW"/>
++ <reg32 offset="0x050" name="POLARITY_CTL">
++ <bitfield name="HSYNC_LOW" pos="0" type="boolean"/>
++ <bitfield name="VSYNC_LOW" pos="1" type="boolean"/>
++ <bitfield name="DATA_EN_LOW" pos="2" type="boolean"/>
++ </reg32>
++ <reg32 offset="0x054" name="TEST_CTL"/>
++ <reg32 offset="0x058" name="TP_COLOR0"/>
++ <reg32 offset="0x05c" name="TP_COLOR1"/>
++ <reg32 offset="0x084" name="DSI_CMD_MODE_TRIGGER_EN"/>
++ <reg32 offset="0x090" name="PANEL_FORMAT" type="mdp5_format"/>
++ <reg32 offset="0x0a8" name="FRAME_LINE_COUNT_EN"/>
++ <reg32 offset="0x0ac" name="FRAME_COUNT"/>
++ <reg32 offset="0x0b0" name="LINE_COUNT"/>
++ <reg32 offset="0x0f0" name="DEFLICKER_CONFIG"/>
++ <reg32 offset="0x0f4" name="DEFLICKER_STRNG_COEFF"/>
++ <reg32 offset="0x0f8" name="DEFLICKER_WEAK_COEFF"/>
++ <reg32 offset="0x100" name="TPG_ENABLE"/>
++ <reg32 offset="0x104" name="TPG_MAIN_CONTROL"/>
++ <reg32 offset="0x108" name="TPG_VIDEO_CONFIG"/>
++ <reg32 offset="0x10c" name="TPG_COMPONENT_LIMITS"/>
++ <reg32 offset="0x110" name="TPG_RECTANGLE"/>
++ <reg32 offset="0x114" name="TPG_INITIAL_VALUE"/>
++ <reg32 offset="0x118" name="TPG_BLK_WHITE_PATTERN_FRAME"/>
++ <reg32 offset="0x11c" name="TPG_RGB_MAPPING"/>
++ </array>
++
++ <array doffsets="mdp5_cfg->ad.base[0],mdp5_cfg->ad.base[1]" name="AD" length="2" stride="0x200">
++ <reg32 offset="0x000" name="BYPASS"/>
++ <reg32 offset="0x004" name="CTRL_0"/>
++ <reg32 offset="0x008" name="CTRL_1"/>
++ <reg32 offset="0x00c" name="FRAME_SIZE"/>
++ <reg32 offset="0x010" name="CON_CTRL_0"/>
++ <reg32 offset="0x014" name="CON_CTRL_1"/>
++ <reg32 offset="0x018" name="STR_MAN"/>
++ <reg32 offset="0x01c" name="VAR"/>
++ <reg32 offset="0x020" name="DITH"/>
++ <reg32 offset="0x024" name="DITH_CTRL"/>
++ <reg32 offset="0x028" name="AMP_LIM"/>
++ <reg32 offset="0x02c" name="SLOPE"/>
++ <reg32 offset="0x030" name="BW_LVL"/>
++ <reg32 offset="0x034" name="LOGO_POS"/>
++ <reg32 offset="0x038" name="LUT_FI"/>
++ <reg32 offset="0x07c" name="LUT_CC"/>
++ <reg32 offset="0x0c8" name="STR_LIM"/>
++ <reg32 offset="0x0cc" name="CALIB_AB"/>
++ <reg32 offset="0x0d0" name="CALIB_CD"/>
++ <reg32 offset="0x0d4" name="MODE_SEL"/>
++ <reg32 offset="0x0d8" name="TFILT_CTRL"/>
++ <reg32 offset="0x0dc" name="BL_MINMAX"/>
++ <reg32 offset="0x0e0" name="BL"/>
++ <reg32 offset="0x0e8" name="BL_MAX"/>
++ <reg32 offset="0x0ec" name="AL"/>
++ <reg32 offset="0x0f0" name="AL_MIN"/>
++ <reg32 offset="0x0f4" name="AL_FILT"/>
++ <reg32 offset="0x0f8" name="CFG_BUF"/>
++ <reg32 offset="0x100" name="LUT_AL"/>
++ <reg32 offset="0x144" name="TARG_STR"/>
++ <reg32 offset="0x148" name="START_CALC"/>
++ <reg32 offset="0x14c" name="STR_OUT"/>
++ <reg32 offset="0x154" name="BL_OUT"/>
++ <reg32 offset="0x158" name="CALC_DONE"/>
++ </array>
++</domain>
++
++</database>
+diff --git a/drivers/gpu/drm/msm/registers/display/mdp_common.xml b/drivers/gpu/drm/msm/registers/display/mdp_common.xml
+new file mode 100644
+index 0000000000000..f1b6345c13235
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/display/mdp_common.xml
+@@ -0,0 +1,90 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++
++
++<!-- random bits that seem same between mdp4 and mdp5 (ie. not much) -->
++
++<enum name="mdp_chroma_samp_type">
++ <value name="CHROMA_FULL" value="0"/>
++ <value name="CHROMA_H2V1" value="1"/>
++ <value name="CHROMA_H1V2" value="2"/>
++ <value name="CHROMA_420" value="3"/>
++</enum>
++
++<enum name="mdp_fetch_type">
++ <value name="MDP_PLANE_INTERLEAVED" value="0"/>
++ <value name="MDP_PLANE_PLANAR" value="1"/>
++ <value name="MDP_PLANE_PSEUDO_PLANAR" value="2"/>
++</enum>
++
++<enum name="mdp_mixer_stage_id">
++ <value name="STAGE_UNUSED" value="0"/>
++ <value name="STAGE_BASE" value="1"/>
++ <value name="STAGE0" value="2"/> <!-- zorder 0 -->
++ <value name="STAGE1" value="3"/> <!-- zorder 1 -->
++ <value name="STAGE2" value="4"/> <!-- zorder 2 -->
++ <value name="STAGE3" value="5"/> <!-- zorder 3 -->
++ <value name="STAGE4" value="6"/> <!-- zorder 4 -->
++ <value name="STAGE5" value="7"/> <!-- zorder 5 -->
++ <value name="STAGE6" value="8"/> <!-- zorder 6 -->
++ <value name="STAGE_MAX" value="8"/> <!-- maximum zorder -->
++</enum>
++
++<enum name="mdp_alpha_type">
++ <value name="FG_CONST" value="0"/>
++ <value name="BG_CONST" value="1"/>
++ <value name="FG_PIXEL" value="2"/>
++ <value name="BG_PIXEL" value="3"/>
++</enum>
++
++<enum name="mdp_component_type">
++ <value name="COMP_0" value="0"/> <!-- Y component -->
++ <value name="COMP_1_2" value="1"/> <!-- Cb/Cr comp. -->
++ <value name="COMP_3" value="2"/> <!-- Trans comp. -->
++ <value name="COMP_MAX" value="3"/>
++</enum>
++
++<enum name="mdp_bpc">
++ <brief>bits per component (non-alpha channel)</brief>
++ <value name="BPC4" value="0"/> <!-- 4 bits -->
++ <value name="BPC5" value="1"/> <!-- 5 bits -->
++ <value name="BPC6" value="2"/> <!-- 6 bits -->
++ <value name="BPC8" value="3"/> <!-- 8 bits -->
++</enum>
++
++<enum name="mdp_bpc_alpha">
++ <brief>bits per component (alpha channel)</brief>
++ <value name="BPC1A" value="0"/> <!-- 1 bit -->
++ <value name="BPC4A" value="1"/> <!-- 4 bits -->
++ <value name="BPC6A" value="2"/> <!-- 6 bits -->
++ <value name="BPC8A" value="3"/> <!-- 8 bits -->
++</enum>
++
++<enum name="mdp_fetch_mode">
++ <value name="MDP_FETCH_LINEAR" value="0"/>
++ <value name="MDP_FETCH_TILE" value="1"/>
++ <value name="MDP_FETCH_UBWC" value="2"/>
++</enum>
++
++<bitset name="reg_wh" inline="yes">
++ <bitfield name="HEIGHT" low="16" high="31" type="uint"/>
++ <bitfield name="WIDTH" low="0" high="15" type="uint"/>
++</bitset>
++
++<bitset name="reg_xy" inline="yes">
++ <bitfield name="Y" low="16" high="31" type="uint"/>
++ <bitfield name="X" low="0" high="15" type="uint"/>
++</bitset>
++
++<bitset name="mdp_unpack_pattern" inline="yes">
++ <bitfield name="ELEM0" low="0" high="7"/>
++ <bitfield name="ELEM1" low="8" high="15"/>
++ <bitfield name="ELEM2" low="16" high="23"/>
++ <bitfield name="ELEM3" low="24" high="31"/>
++</bitset>
++
++</database>
++
+diff --git a/drivers/gpu/drm/msm/registers/display/msm.xml b/drivers/gpu/drm/msm/registers/display/msm.xml
+new file mode 100644
+index 0000000000000..429c35b73bad6
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/display/msm.xml
+@@ -0,0 +1,32 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
++<import file="freedreno_copyright.xml"/>
++
++<doc>
++ Register definitions for the display related hw blocks on
++ msm/snapdragon
++</doc>
++
++<!--
++<enum name="chipset">
++ <value name="MDP40"/>
++ <value name="MDP50"/>
++</enum>
++-->
++
++<import file="mdp4.xml"/>
++<import file="mdp5.xml"/>
++<import file="dsi.xml"/>
++<import file="dsi_phy_28nm_8960.xml"/>
++<import file="dsi_phy_28nm.xml"/>
++<import file="dsi_phy_20nm.xml"/>
++<import file="dsi_phy_14nm.xml"/>
++<import file="dsi_phy_10nm.xml"/>
++<import file="dsi_phy_7nm.xml"/>
++<import file="sfpb.xml"/>
++<import file="hdmi.xml"/>
++<import file="edp.xml"/>
++
++</database>
+diff --git a/drivers/gpu/drm/msm/registers/display/sfpb.xml b/drivers/gpu/drm/msm/registers/display/sfpb.xml
+new file mode 100644
+index 0000000000000..de1cf43c131f4
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/display/sfpb.xml
+@@ -0,0 +1,17 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++<import file="freedreno_copyright.xml"/>
++
++<domain name="SFPB" width="32">
++ <enum name="sfpb_ahb_arb_master_port_en">
++ <value name="SFPB_MASTER_PORT_ENABLE" value="3"/>
++ <value name="SFPB_MASTER_PORT_DISABLE" value="0"/>
++ </enum>
++ <reg32 offset="0x0058" name="GPREG">
++ <bitfield name="MASTER_PORT_EN" low="11" high="12" type="sfpb_ahb_arb_master_port_en"/>
++ </reg32>
++</domain>
++
++</database>
+diff --git a/drivers/gpu/drm/msm/registers/freedreno_copyright.xml b/drivers/gpu/drm/msm/registers/freedreno_copyright.xml
+new file mode 100644
+index 0000000000000..854efdd2e5fc0
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/freedreno_copyright.xml
+@@ -0,0 +1,40 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<database xmlns="http://nouveau.freedesktop.org/"
++xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
++xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
++
++<copyright year="2013">
++
++<author name="Rob Clark" email="robdclark@gmail.com"><nick name="robclark"/>
++Initial Author.
++</author>
++
++<author name="Ilia Mirkin" email="imirkin@alum.mit.edu"><nick name="imirkin"/>
++many a3xx/a4xx contributions
++</author>
++
++<license>
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice (including the
++next paragraph) shall be included in all copies or substantial
++portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
++IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++</license>
++
++</copyright>
++</database>
++
+diff --git a/drivers/gpu/drm/msm/registers/rules-fd.xsd b/drivers/gpu/drm/msm/registers/rules-fd.xsd
+new file mode 100644
+index 0000000000000..2eedb099a4eb5
+--- /dev/null
++++ b/drivers/gpu/drm/msm/registers/rules-fd.xsd
+@@ -0,0 +1,404 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<schema xmlns="http://www.w3.org/2001/XMLSchema"
++ targetNamespace="http://nouveau.freedesktop.org/"
++ xmlns:rng="http://nouveau.freedesktop.org/"
++ elementFormDefault="qualified">
++
++ <annotation>
++ <documentation>
++ An updated version of the old rules.xml file from the
++ RivaTV project. Specifications by Pekka Paalanen,
++ preliminary attempt by KoalaBR,
++ first working version by Jakob Bornecrantz.
++ For specifications, see the file rules-ng-format.txt
++ in Nouveau CVS module 'rules-ng'.
++ </documentation>
++ <documentation>Version 0.1</documentation>
++ </annotation>
++
++
++ <!-- Elements -->
++
++ <element name="database" type="rng:databaseType" />
++ <element name="import" type="rng:importType" />
++ <element name="copyright" type="rng:copyrightType" />
++ <element name="domain" type="rng:domainType" />
++ <element name="array" type="rng:arrayType" />
++ <element name="stripe" type="rng:stripeType" />
++ <element name="reg64" type="rng:registerType" />
++ <element name="reg32" type="rng:registerType" />
++ <element name="bitset" type="rng:bitsetType" />
++ <element name="bitfield" type="rng:bitfieldType" />
++ <element name="enum" type="rng:enumType" />
++ <element name="value" type="rng:valueType" />
++
++ <!-- Copyright elements -->
++ <element name="author" type="rng:authorType" />
++ <element name="nick" type="rng:nickType" />
++ <element name="license" type="rng:docType" />
++
++ <!-- Documentation elements -->
++
++ <!-- FIXME: allowed only one per parent element -->
++ <element name="brief" type="rng:briefType" />
++
++ <element name="doc" type="rng:docType" />
++ <element name="b" type="rng:textformatType" />
++ <element name="i" type="rng:textformatType" />
++ <element name="u" type="rng:textformatType" />
++ <element name="code" type="rng:textcodeType" />
++ <element name="ul" type="rng:listType" />
++ <element name="ol" type="rng:listType" />
++ <element name="li" type="rng:listitemType" />
++
++ <!-- Copyright element types -->
++
++ <complexType name="authorType" mixed="true">
++ <annotation>
++ <documentation>
++ register database author
++ </documentation>
++ </annotation>
++ <choice minOccurs="0" maxOccurs="unbounded">
++ <element ref="rng:nick" />
++ </choice>
++ <attribute name="name" type="string" use="required" />
++ <attribute name="email" type="string" use="required" />
++ </complexType>
++
++ <complexType name="nickType">
++ <annotation>
++ <documentation>nickType</documentation>
++ </annotation>
++ <attribute name="name" type="string" use="required" />
++ </complexType>
++
++ <!-- Database element types -->
++
++ <complexType name="databaseType">
++ <annotation>
++ <documentation>databaseType</documentation>
++ </annotation>
++ <choice minOccurs="0" maxOccurs="unbounded">
++ <group ref="rng:docGroup" />
++ <group ref="rng:topGroup" />
++ </choice>
++ </complexType>
++
++ <complexType name="importType">
++ <annotation>
++ <documentation>importType</documentation>
++ </annotation>
++ <attribute name="file" type="string" use="required" />
++ </complexType>
++
++ <complexType name="copyrightType">
++ <annotation>
++ <documentation>copyrightType</documentation>
++ </annotation>
++ <choice minOccurs="0" maxOccurs="unbounded">
++ <group ref="rng:docGroup" />
++ <group ref="rng:topGroup" />
++ <element ref="rng:author" />
++ <element ref="rng:license" />
++ </choice>
++ <attribute name="year" type="nonNegativeInteger" use="optional" />
++ </complexType>
++
++ <complexType name="domainType">
++ <annotation>
++ <documentation>domainType</documentation>
++ </annotation>
++ <choice minOccurs="0" maxOccurs="unbounded">
++ <group ref="rng:docGroup" />
++ <group ref="rng:topGroup" />
++ <group ref="rng:regarrayGroup" />
++ </choice>
++ <attribute name="name" type="NMTOKEN" use="required" />
++ <attribute name="prefix" type="NMTOKENS" use="optional" />
++ <attribute name="width" type="rng:DomainWidth" use="optional" />
++ <attribute name="varset" type="NMTOKEN" use="optional" />
++ <attribute name="variants" type="string" use="optional" />
++ </complexType>
++
++ <complexType name="arrayType">
++ <annotation>
++ <documentation>arrayType</documentation>
++ </annotation>
++ <choice minOccurs="0" maxOccurs="unbounded">
++ <group ref="rng:docGroup" />
++ <group ref="rng:topGroup" />
++ <group ref="rng:regarrayGroup" />
++ </choice>
++ <attribute name="name" type="NMTOKEN" use="optional" />
++ <attribute name="offset" type="rng:HexOrNumber" use="optional" />
++ <attribute name="offsets" type="string" use="optional"/>
++ <attribute name="doffsets" type="string" use="optional"/>
++ <attribute name="index" type="NMTOKENS" use="optional"/>
++ <attribute name="stride" type="rng:HexOrNumber" use="required" />
++ <attribute name="length" type="rng:HexOrNumber" use="required" />
++ <attribute name="varset" type="NMTOKEN" use="optional" />
++ <attribute name="variants" type="string" use="optional" />
++ <attribute name="usage" type="string" use="optional" />
++ </complexType>
++
++ <complexType name="stripeType">
++ <annotation>
++ <documentation>stripeType</documentation>
++ </annotation>
++ <choice minOccurs="0" maxOccurs="unbounded">
++ <group ref="rng:docGroup" />
++ <group ref="rng:topGroup" />
++ <group ref="rng:regarrayGroup" minOccurs="0" />
++ </choice>
++ <attribute name="varset" type="NMTOKEN" use="optional" />
++ <attribute name="variants" type="string" use="optional" />
++ <attribute name="prefix" type="NMTOKENS" use="optional" />
++ </complexType>
++
++ <complexType name="registerType">
++ <annotation>
++ <documentation>
++ registerType used by reg32, reg64
++ </documentation>
++ </annotation>
++ <choice minOccurs="0" maxOccurs="unbounded">
++ <group ref="rng:docGroup" />
++ <group ref="rng:topGroup" />
++ <element ref="rng:value" />
++ <element ref="rng:bitfield" />
++ </choice>
++ <attribute name="name" type="NMTOKEN" use="required" />
++ <attribute name="offset" type="rng:HexOrNumber" use="required" />
++ <attribute name="type" type="NMTOKENS" use="optional" />
++ <attribute name="shr" type="nonNegativeInteger" use="optional" />
++ <attribute name="varset" type="NMTOKEN" use="optional" />
++ <attribute name="variants" type="string" use="optional" />
++ <attribute name="stride" type="rng:HexOrNumber" use="optional" />
++ <attribute name="length" type="rng:HexOrNumber" use="optional" />
++ <attribute name="high" type="nonNegativeInteger" use="optional" />
++ <attribute name="low" type="nonNegativeInteger" use="optional" />
++ <attribute name="pos" type="nonNegativeInteger" use="optional" />
++ <attribute name="align" type="nonNegativeInteger" use="optional" />
++ <attribute name="radix" type="nonNegativeInteger" use="optional" />
++ <attribute name="usage" type="string" use="optional" />
++ </complexType>
++
++ <complexType name="bitsetType">
++ <annotation>
++ <documentation>bitsetType</documentation>
++ </annotation>
++ <choice maxOccurs="unbounded">
++ <element ref="rng:bitfield" />
++ <group ref="rng:docGroup" />
++ <group ref="rng:topGroup" />
++ </choice>
++ <attribute name="name" type="NMTOKEN" use="required" />
++ <attribute name="inline" type="rng:Boolean" use="optional" />
++ <attribute name="varset" type="NMTOKEN" use="optional" />
++ </complexType>
++
++ <complexType name="bitfieldType">
++ <annotation>
++ <documentation>bitfieldType</documentation>
++ </annotation>
++ <choice minOccurs="0" maxOccurs="unbounded">
++ <element ref="rng:value" maxOccurs="unbounded" />
++ <group ref="rng:docGroup" />
++ <group ref="rng:topGroup" />
++ </choice>
++ <attribute name="name" type="NMTOKEN" use="required" />
++ <attribute name="high" type="nonNegativeInteger" use="optional" />
++ <attribute name="low" type="nonNegativeInteger" use="optional" />
++ <attribute name="pos" type="nonNegativeInteger" use="optional" />
++ <attribute name="radix" type="nonNegativeInteger" use="optional" />
++ <attribute name="type" type="NMTOKENS" use="optional" />
++ <attribute name="varset" type="NMTOKEN" use="optional" />
++ <attribute name="variants" type="string" use="optional" />
++ <attribute name="addvariant" type="rng:Boolean" use="optional" />
++ <attribute name="shr" type="nonNegativeInteger" use="optional" />
++ </complexType>
++
++ <complexType name="enumType">
++ <annotation>
++ <documentation>enumType</documentation>
++ </annotation>
++ <choice maxOccurs="unbounded">
++ <element ref="rng:value" />
++ <group ref="rng:docGroup" />
++ <group ref="rng:topGroup" />
++ </choice>
++ <attribute name="name" type="NMTOKEN" use="required" />
++ <attribute name="bare" type="rng:Boolean" use="optional" />
++ <attribute name="prefix" type="NMTOKENS" use="optional" />
++ <attribute name="varset" type="NMTOKEN" use="optional" />
++ </complexType>
++
++ <complexType name="valueType">
++ <annotation>
++ <documentation>valueType</documentation>
++ </annotation>
++ <choice minOccurs="0" maxOccurs="unbounded">
++ <group ref="rng:docGroup" />
++ <group ref="rng:topGroup" />
++ </choice>
++ <attribute name="name" type="NMTOKEN" use="required" />
++ <attribute name="value" type="string" use="optional" />
++ <attribute name="varset" type="NMTOKEN" use="optional" />
++ <attribute name="variants" type="string" use="optional" />
++ </complexType>
++
++ <!-- Documentation element types -->
++
++ <complexType name="briefType">
++ <annotation>
++ <documentation>
++ brief documentation, no markup
++ </documentation>
++ </annotation>
++ <simpleContent>
++ <extension base="string" />
++ </simpleContent>
++ </complexType>
++
++ <complexType name="docType" mixed="true">
++ <annotation>
++ <documentation>
++ root element of documentation sub-tree
++ </documentation>
++ </annotation>
++ <choice minOccurs="0" maxOccurs="unbounded">
++ <group ref="rng:textformatGroup" />
++ <group ref="rng:listGroup" />
++ <element ref="rng:code" />
++ </choice>
++ </complexType>
++
++ <complexType name="textformatType" mixed="true">
++ <annotation>
++ <documentation>
++ for bold, underline, italics
++ </documentation>
++ </annotation>
++ <choice minOccurs="0" maxOccurs="unbounded">
++ <group ref="rng:textformatGroup" />
++ </choice>
++ </complexType>
++
++ <complexType name="textcodeType">
++ <simpleContent>
++ <extension base="string">
++ <attribute name="title" type="string" />
++ </extension>
++ </simpleContent>
++ </complexType>
++
++ <complexType name="listType">
++ <annotation>
++ <documentation>
++ definition of a list, ordered or unordered
++ </documentation>
++ </annotation>
++ <choice minOccurs="0" maxOccurs="unbounded">
++ <element ref="rng:li" />
++ </choice>
++ </complexType>
++
++ <complexType name="listitemType" mixed="true">
++ <annotation>
++ <documentation>
++ items of a list
++ </documentation>
++ </annotation>
++ <choice minOccurs="0" maxOccurs="unbounded">
++ <group ref="rng:textformatGroup" />
++ <group ref="rng:listGroup" />
++ <element ref="rng:code" />
++ </choice>
++ </complexType>
++
++
++
++ <!-- Attribute value types -->
++
++ <simpleType name="Hexadecimal">
++ <restriction base="string">
++ <pattern value="0x[0-9a-f]+" />
++ <pattern value="0x[0-9A-F]+" />
++ <pattern value="[0-9]" />
++ </restriction>
++ </simpleType>
++
++ <simpleType name="HexOrNumber">
++ <annotation>
++ <documentation>HexOrNumber</documentation>
++ </annotation>
++ <union memberTypes="rng:Hexadecimal nonNegativeInteger" />
++ </simpleType>
++
++ <simpleType name="Boolean">
++ <restriction base="string">
++ <enumeration value="true" />
++ <enumeration value="1" />
++ <enumeration value="yes" />
++ <enumeration value="false" />
++ <enumeration value="0" />
++ <enumeration value="no" />
++ </restriction>
++ </simpleType>
++
++ <simpleType name="DomainWidth">
++ <annotation>
++ <documentation>DomainWidth</documentation>
++ </annotation>
++ <restriction base="string">
++ <enumeration value="32" />
++ </restriction>
++ </simpleType>
++
++
++
++ <!-- Element groups -->
++
++ <group name="topGroup">
++ <choice>
++ <element ref="rng:copyright" />
++ <element ref="rng:domain" />
++ <element ref="rng:enum" />
++ <element ref="rng:bitset" />
++ <element ref="rng:import" />
++ </choice>
++ </group>
++
++ <group name="regarrayGroup">
++ <choice>
++ <element ref="rng:reg64" />
++ <element ref="rng:reg32" />
++ <element ref="rng:array" />
++ <element ref="rng:stripe" />
++ </choice>
++ </group>
++
++ <group name="docGroup">
++ <choice>
++ <element ref="rng:brief" />
++ <element ref="rng:doc" />
++ </choice>
++ </group>
++
++ <group name="textformatGroup">
++ <choice>
++ <element ref="rng:b" />
++ <element ref="rng:i" />
++ <element ref="rng:u" />
++ </choice>
++ </group>
++
++ <group name="listGroup">
++ <choice>
++ <element ref="rng:ul" />
++ <element ref="rng:ol" />
++ </choice>
++ </group>
++
++</schema>
+--
+2.39.5
+
--- /dev/null
+From 850cb9a0741b8eaa2a6a5e8b7b7372ae3f8a45cd Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 18 Feb 2025 03:28:03 -0600
+Subject: drm/nouveau/pmu: Fix gp10b firmware guard
+
+From: Aaron Kling <webgeek1234@gmail.com>
+
+[ Upstream commit 3dbc0215e3c502a9f3221576da0fdc9847fb9721 ]
+
+Most kernel configs enable multiple Tegra SoC generations, causing this
+typo to go unnoticed. But in the case where a kernel config is strictly
+for Tegra186, this is a problem.
+
+Fixes: 989863d7cbe5 ("drm/nouveau/pmu: select implementation based on available firmware")
+Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
+Signed-off-by: Danilo Krummrich <dakr@kernel.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20250218-nouveau-gm10b-guard-v2-1-a4de71500d48@gmail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c
+index a6f410ba60bc9..d393bc540f862 100644
+--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c
++++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c
+@@ -75,7 +75,7 @@ gp10b_pmu_acr = {
+ .bootstrap_multiple_falcons = gp10b_pmu_acr_bootstrap_multiple_falcons,
+ };
+
+-#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
++#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
+ MODULE_FIRMWARE("nvidia/gp10b/pmu/desc.bin");
+ MODULE_FIRMWARE("nvidia/gp10b/pmu/image.bin");
+ MODULE_FIRMWARE("nvidia/gp10b/pmu/sig.bin");
+--
+2.39.5
+
--- /dev/null
+From 39d8a7c79dee1027fa28f16329eb13153ce7faac Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 9 Nov 2023 09:38:00 +0200
+Subject: drm/tidss: Add simple K2G manual reset
+
+From: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
+
+[ Upstream commit 576d96c5c896221b5bc8feae473739469a92e144 ]
+
+K2G display controller does not support soft reset, but we can do the
+most important steps manually: mask the IRQs and disable the VPs.
+
+Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com>
+Link: https://lore.kernel.org/r/20231109-tidss-probe-v2-7-ac91b5ea35c0@ideasonboard.com
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
+Stable-dep-of: a9a73f2661e6 ("drm/tidss: Fix race condition while handling interrupt registers")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/tidss/tidss_dispc.c | 18 ++++++++++++++++--
+ 1 file changed, 16 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
+index ee3531bbccd7d..4327e1203c565 100644
+--- a/drivers/gpu/drm/tidss/tidss_dispc.c
++++ b/drivers/gpu/drm/tidss/tidss_dispc.c
+@@ -2704,14 +2704,28 @@ static void dispc_init_errata(struct dispc_device *dispc)
+ }
+ }
+
++/*
++ * K2G display controller does not support soft reset, so we do a basic manual
++ * reset here: make sure the IRQs are masked and VPs are disabled.
++ */
++static void dispc_softreset_k2g(struct dispc_device *dispc)
++{
++ dispc_set_irqenable(dispc, 0);
++ dispc_read_and_clear_irqstatus(dispc);
++
++ for (unsigned int vp_idx = 0; vp_idx < dispc->feat->num_vps; ++vp_idx)
++ VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, 0, 0);
++}
++
+ static int dispc_softreset(struct dispc_device *dispc)
+ {
+ u32 val;
+ int ret = 0;
+
+- /* K2G display controller does not support soft reset */
+- if (dispc->feat->subrev == DISPC_K2G)
++ if (dispc->feat->subrev == DISPC_K2G) {
++ dispc_softreset_k2g(dispc);
+ return 0;
++ }
+
+ /* Soft reset */
+ REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1);
+--
+2.39.5
+
--- /dev/null
+From dc7892e2e275525d63cf388e51b98804682e92f5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 21 Oct 2024 17:07:50 +0300
+Subject: drm/tidss: Fix race condition while handling interrupt registers
+
+From: Devarsh Thakkar <devarsht@ti.com>
+
+[ Upstream commit a9a73f2661e6f625d306c9b0ef082e4593f45a21 ]
+
+The driver has a spinlock for protecting the irq_masks field and irq
+enable registers. However, the driver misses protecting the irq status
+registers which can lead to races.
+
+Take the spinlock when accessing irqstatus too.
+
+Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform Display SubSystem")
+Cc: stable@vger.kernel.org
+Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
+[Tomi: updated the desc]
+Reviewed-by: Jonathan Cormier <jcormier@criticallink.com>
+Tested-by: Jonathan Cormier <jcormier@criticallink.com>
+Reviewed-by: Aradhya Bhatia <aradhya.bhatia@linux.dev>
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20241021-tidss-irq-fix-v1-6-82ddaec94e4a@ideasonboard.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/tidss/tidss_dispc.c | 4 ++++
+ drivers/gpu/drm/tidss/tidss_irq.c | 2 ++
+ 2 files changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
+index 4327e1203c565..355c64bafb82b 100644
+--- a/drivers/gpu/drm/tidss/tidss_dispc.c
++++ b/drivers/gpu/drm/tidss/tidss_dispc.c
+@@ -2710,8 +2710,12 @@ static void dispc_init_errata(struct dispc_device *dispc)
+ */
+ static void dispc_softreset_k2g(struct dispc_device *dispc)
+ {
++ unsigned long flags;
++
++ spin_lock_irqsave(&dispc->tidss->wait_lock, flags);
+ dispc_set_irqenable(dispc, 0);
+ dispc_read_and_clear_irqstatus(dispc);
++ spin_unlock_irqrestore(&dispc->tidss->wait_lock, flags);
+
+ for (unsigned int vp_idx = 0; vp_idx < dispc->feat->num_vps; ++vp_idx)
+ VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, 0, 0);
+diff --git a/drivers/gpu/drm/tidss/tidss_irq.c b/drivers/gpu/drm/tidss/tidss_irq.c
+index 0c681c7600bcb..f13c7e434f8ed 100644
+--- a/drivers/gpu/drm/tidss/tidss_irq.c
++++ b/drivers/gpu/drm/tidss/tidss_irq.c
+@@ -60,7 +60,9 @@ static irqreturn_t tidss_irq_handler(int irq, void *arg)
+ unsigned int id;
+ dispc_irq_t irqstatus;
+
++ spin_lock(&tidss->wait_lock);
+ irqstatus = dispc_read_and_clear_irqstatus(tidss->dispc);
++ spin_unlock(&tidss->wait_lock);
+
+ for (id = 0; id < tidss->num_crtcs; id++) {
+ struct drm_crtc *crtc = tidss->crtcs[id];
+--
+2.39.5
+
--- /dev/null
+From d4f87a74627a959f917dbd8faa8f274d6d8f75ba Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 24 Jan 2025 19:15:23 +0100
+Subject: nouveau/svm: fix missing folio unlock + put after
+ make_device_exclusive_range()
+
+From: David Hildenbrand <david@redhat.com>
+
+[ Upstream commit b3fefbb30a1691533cb905006b69b2a474660744 ]
+
+In case we have to retry the loop, we are missing to unlock+put the
+folio. In that case, we will keep failing make_device_exclusive_range()
+because we cannot grab the folio lock, and even return from the function
+with the folio locked and referenced, effectively never succeeding the
+make_device_exclusive_range().
+
+While at it, convert the other unlock+put to use a folio as well.
+
+This was found by code inspection.
+
+Fixes: 8f187163eb89 ("nouveau/svm: implement atomic SVM access")
+Signed-off-by: David Hildenbrand <david@redhat.com>
+Reviewed-by: Alistair Popple <apopple@nvidia.com>
+Tested-by: Alistair Popple <apopple@nvidia.com>
+Signed-off-by: Danilo Krummrich <dakr@kernel.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20250124181524.3584236-2-david@redhat.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/nouveau/nouveau_svm.c | 9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/nouveau/nouveau_svm.c b/drivers/gpu/drm/nouveau/nouveau_svm.c
+index ec9f307370fa8..6c71f6738ca51 100644
+--- a/drivers/gpu/drm/nouveau/nouveau_svm.c
++++ b/drivers/gpu/drm/nouveau/nouveau_svm.c
+@@ -593,6 +593,7 @@ static int nouveau_atomic_range_fault(struct nouveau_svmm *svmm,
+ unsigned long timeout =
+ jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
+ struct mm_struct *mm = svmm->notifier.mm;
++ struct folio *folio;
+ struct page *page;
+ unsigned long start = args->p.addr;
+ unsigned long notifier_seq;
+@@ -619,12 +620,16 @@ static int nouveau_atomic_range_fault(struct nouveau_svmm *svmm,
+ ret = -EINVAL;
+ goto out;
+ }
++ folio = page_folio(page);
+
+ mutex_lock(&svmm->mutex);
+ if (!mmu_interval_read_retry(¬ifier->notifier,
+ notifier_seq))
+ break;
+ mutex_unlock(&svmm->mutex);
++
++ folio_unlock(folio);
++ folio_put(folio);
+ }
+
+ /* Map the page on the GPU. */
+@@ -640,8 +645,8 @@ static int nouveau_atomic_range_fault(struct nouveau_svmm *svmm,
+ ret = nvif_object_ioctl(&svmm->vmm->vmm.object, args, size, NULL);
+ mutex_unlock(&svmm->mutex);
+
+- unlock_page(page);
+- put_page(page);
++ folio_unlock(folio);
++ folio_put(folio);
+
+ out:
+ mmu_interval_notifier_remove(¬ifier->notifier);
+--
+2.39.5
+
--- /dev/null
+From 69f01f80255ec2a2f5184edea982ca817d5f2a1e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 13 Feb 2025 10:05:14 -0700
+Subject: nvme/ioctl: add missing space in err message
+
+From: Caleb Sander Mateos <csander@purestorage.com>
+
+[ Upstream commit 487a3ea7b1b8ba2ca7d2c2bb3c3594dc360d6261 ]
+
+nvme_validate_passthru_nsid() logs an err message whose format string is
+split over 2 lines. There is a missing space between the two pieces,
+resulting in log lines like "... does not match nsid (1)of namespace".
+Add the missing space between ")" and "of". Also combine the format
+string pieces onto a single line to make the err message easier to grep.
+
+Fixes: e7d4b5493a2d ("nvme: factor out a nvme_validate_passthru_nsid helper")
+Signed-off-by: Caleb Sander Mateos <csander@purestorage.com>
+Reviewed-by: Christoph Hellwig <hch@lst.de>
+Signed-off-by: Keith Busch <kbusch@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/nvme/host/ioctl.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/nvme/host/ioctl.c b/drivers/nvme/host/ioctl.c
+index 19a7f0160618d..4ce31f9f06947 100644
+--- a/drivers/nvme/host/ioctl.c
++++ b/drivers/nvme/host/ioctl.c
+@@ -336,8 +336,7 @@ static bool nvme_validate_passthru_nsid(struct nvme_ctrl *ctrl,
+ {
+ if (ns && nsid != ns->head->ns_id) {
+ dev_err(ctrl->device,
+- "%s: nsid (%u) in cmd does not match nsid (%u)"
+- "of namespace\n",
++ "%s: nsid (%u) in cmd does not match nsid (%u) of namespace\n",
+ current->comm, nsid, ns->head->ns_id);
+ return false;
+ }
+--
+2.39.5
+
--- /dev/null
+From ee6ce52a6a2d18e57f39ad478a7a65bee7d68cc8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 30 Jan 2025 09:00:34 +0000
+Subject: power: supply: da9150-fg: fix potential overflow
+
+From: Andrey Vatoropin <a.vatoropin@crpt.ru>
+
+[ Upstream commit 3fb3cb4350befc4f901c54e0cb4a2a47b1302e08 ]
+
+Size of variable sd_gain equals four bytes - DA9150_QIF_SD_GAIN_SIZE.
+Size of variable shunt_val equals two bytes - DA9150_QIF_SHUNT_VAL_SIZE.
+
+The expression sd_gain * shunt_val is currently being evaluated using
+32-bit arithmetic. So during the multiplication an overflow may occur.
+
+As the value of type 'u64' is used as storage for the eventual result, put
+ULL variable at the first position of each expression in order to give the
+compiler complete information about the proper arithmetic to use. According
+to C99 the guaranteed width for a variable of type 'unsigned long long' >=
+64 bits.
+
+Remove the explicit cast to u64 as it is meaningless.
+
+Just for the sake of consistency, perform the similar trick with another
+expression concerning 'iavg'.
+
+Found by Linux Verification Center (linuxtesting.org) with SVACE.
+
+Fixes: a419b4fd9138 ("power: Add support for DA9150 Fuel-Gauge")
+Signed-off-by: Andrey Vatoropin <a.vatoropin@crpt.ru>
+Link: https://lore.kernel.org/r/20250130090030.53422-1-a.vatoropin@crpt.ru
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/power/supply/da9150-fg.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/power/supply/da9150-fg.c b/drivers/power/supply/da9150-fg.c
+index 652c1f213af1c..4f28ef1bba1a3 100644
+--- a/drivers/power/supply/da9150-fg.c
++++ b/drivers/power/supply/da9150-fg.c
+@@ -247,9 +247,9 @@ static int da9150_fg_current_avg(struct da9150_fg *fg,
+ DA9150_QIF_SD_GAIN_SIZE);
+ da9150_fg_read_sync_end(fg);
+
+- div = (u64) (sd_gain * shunt_val * 65536ULL);
++ div = 65536ULL * sd_gain * shunt_val;
+ do_div(div, 1000000);
+- res = (u64) (iavg * 1000000ULL);
++ res = 1000000ULL * iavg;
+ do_div(res, div);
+
+ val->intval = (int) res;
+--
+2.39.5
+
arp-switch-to-dev_getbyhwaddr-in-arp_req_set_public.patch
net-axienet-set-mac_managed_pm.patch
tcp-drop-secpath-at-the-same-time-as-we-currently-dr.patch
+drm-tidss-add-simple-k2g-manual-reset.patch
+drm-tidss-fix-race-condition-while-handling-interrup.patch
+drm-msm-gem-demote-userspace-errors-to-drm_ut_driver.patch
+drm-msm-gem-prevent-integer-overflow-in-msm_ioctl_ge.patch
+bpf-test_run-fix-use-after-free-issue-in-eth_skb_pkt.patch
+bpf-unify-vm_write-vs-vm_maywrite-use-in-bpf-map-mma.patch
+bpf-avoid-holding-freeze_mutex-during-mmap-operation.patch
+strparser-add-read_sock-callback.patch
+bpf-fix-wrong-copied_seq-calculation.patch
+bpf-disable-non-stream-socket-for-strparser.patch
+bpf-fix-deadlock-when-freeing-cgroup-storage.patch
+power-supply-da9150-fg-fix-potential-overflow.patch
+nouveau-svm-fix-missing-folio-unlock-put-after-make_.patch
+drm-msm-avoid-rounding-up-to-one-jiffy.patch
+drm-msm-dpu-rename-dpu_hw_setup_vsync_source-functio.patch
+drm-msm-dpu-skip-watchdog-timer-programming-through-.patch
+drm-msm-dpu-don-t-leak-bits_per_component-into-rando.patch
+drm-msm-import-xml-display-registers-database.patch
+drm-msm-import-a2xx-a4xx-xml-display-registers-datab.patch
+drm-msm-import-a5xx-xml-display-registers-database.patch
+drm-msm-import-a6xx-xml-display-registers-database.patch
+drm-msm-import-gen_header.py-script-from-mesa.patch
+drm-msm-generate-headers-on-the-fly.patch
+drm-msm-drop-msm_read-writel.patch
+drm-msm-dsi-remove-dsi_phy_read-write.patch
+drm-msm-dsi-phy-protect-phy_cmn_clk_cfg0-updated-fro.patch
+drm-msm-dsi-phy-protect-phy_cmn_clk_cfg1-against-clo.patch
+drm-msm-dsi-phy-do-not-overwite-phy_cmn_clk_cfg1-whe.patch
+nvme-ioctl-add-missing-space-in-err-message.patch
+bpf-skip-non-exist-keys-in-generic_map_lookup_batch.patch
+drm-nouveau-pmu-fix-gp10b-firmware-guard.patch
+arm64-dts-mediatek-mt8183-disable-dsi-display-output.patch
--- /dev/null
+From d81331403ca3f232bd3bebe5663067e57b04584c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 22 Jan 2025 18:09:13 +0800
+Subject: strparser: Add read_sock callback
+
+From: Jiayuan Chen <mrpre@163.com>
+
+[ Upstream commit 0532a79efd68a4d9686b0385e4993af4b130ff82 ]
+
+Added a new read_sock handler, allowing users to customize read operations
+instead of relying on the native socket's read_sock.
+
+Signed-off-by: Jiayuan Chen <mrpre@163.com>
+Signed-off-by: Martin KaFai Lau <martin.lau@kernel.org>
+Reviewed-by: Jakub Sitnicki <jakub@cloudflare.com>
+Acked-by: John Fastabend <john.fastabend@gmail.com>
+Link: https://patch.msgid.link/20250122100917.49845-2-mrpre@163.com
+Stable-dep-of: 36b62df5683c ("bpf: Fix wrong copied_seq calculation")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ Documentation/networking/strparser.rst | 9 ++++++++-
+ include/net/strparser.h | 2 ++
+ net/strparser/strparser.c | 11 +++++++++--
+ 3 files changed, 19 insertions(+), 3 deletions(-)
+
+diff --git a/Documentation/networking/strparser.rst b/Documentation/networking/strparser.rst
+index 6cab1f74ae05a..7f623d1db72aa 100644
+--- a/Documentation/networking/strparser.rst
++++ b/Documentation/networking/strparser.rst
+@@ -112,7 +112,7 @@ Functions
+ Callbacks
+ =========
+
+-There are six callbacks:
++There are seven callbacks:
+
+ ::
+
+@@ -182,6 +182,13 @@ There are six callbacks:
+ the length of the message. skb->len - offset may be greater
+ then full_len since strparser does not trim the skb.
+
++ ::
++
++ int (*read_sock)(struct strparser *strp, read_descriptor_t *desc,
++ sk_read_actor_t recv_actor);
++
++ The read_sock callback is used by strparser instead of
++ sock->ops->read_sock, if provided.
+ ::
+
+ int (*read_sock_done)(struct strparser *strp, int err);
+diff --git a/include/net/strparser.h b/include/net/strparser.h
+index 41e2ce9e9e10f..0a83010b3a64a 100644
+--- a/include/net/strparser.h
++++ b/include/net/strparser.h
+@@ -43,6 +43,8 @@ struct strparser;
+ struct strp_callbacks {
+ int (*parse_msg)(struct strparser *strp, struct sk_buff *skb);
+ void (*rcv_msg)(struct strparser *strp, struct sk_buff *skb);
++ int (*read_sock)(struct strparser *strp, read_descriptor_t *desc,
++ sk_read_actor_t recv_actor);
+ int (*read_sock_done)(struct strparser *strp, int err);
+ void (*abort_parser)(struct strparser *strp, int err);
+ void (*lock)(struct strparser *strp);
+diff --git a/net/strparser/strparser.c b/net/strparser/strparser.c
+index 8299ceb3e3739..95696f42647ec 100644
+--- a/net/strparser/strparser.c
++++ b/net/strparser/strparser.c
+@@ -347,7 +347,10 @@ static int strp_read_sock(struct strparser *strp)
+ struct socket *sock = strp->sk->sk_socket;
+ read_descriptor_t desc;
+
+- if (unlikely(!sock || !sock->ops || !sock->ops->read_sock))
++ if (unlikely(!sock || !sock->ops))
++ return -EBUSY;
++
++ if (unlikely(!strp->cb.read_sock && !sock->ops->read_sock))
+ return -EBUSY;
+
+ desc.arg.data = strp;
+@@ -355,7 +358,10 @@ static int strp_read_sock(struct strparser *strp)
+ desc.count = 1; /* give more than one skb per call */
+
+ /* sk should be locked here, so okay to do read_sock */
+- sock->ops->read_sock(strp->sk, &desc, strp_recv);
++ if (strp->cb.read_sock)
++ strp->cb.read_sock(strp, &desc, strp_recv);
++ else
++ sock->ops->read_sock(strp->sk, &desc, strp_recv);
+
+ desc.error = strp->cb.read_sock_done(strp, desc.error);
+
+@@ -468,6 +474,7 @@ int strp_init(struct strparser *strp, struct sock *sk,
+ strp->cb.unlock = cb->unlock ? : strp_sock_unlock;
+ strp->cb.rcv_msg = cb->rcv_msg;
+ strp->cb.parse_msg = cb->parse_msg;
++ strp->cb.read_sock = cb->read_sock;
+ strp->cb.read_sock_done = cb->read_sock_done ? : default_read_sock_done;
+ strp->cb.abort_parser = cb->abort_parser ? : strp_abort_strp;
+
+--
+2.39.5
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
