phy: qcom: qmp-pcie: drop bogus x1e80100 qref supplies

The PCIe PHYs on x1e80100 do not a have a qref supply so stop requesting
one. This also avoids the follow warning at boot:

	qcom-qmp-pcie-phy 1bfc000.phy: supply vdda-qref not found, using dummy regulator

Fixes: 9dab00ee9544 ("phy: qcom: qmp-pcie: Add Gen4 4-lanes mode for X1E80100")
Fixes: 606060ce8fd0 ("phy: qcom-qmp-pcie: Add support for X1E80100 g3x2 and g4x2 PCIE")
Cc: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241015121406.15033-1-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index f71787fb4d7e91a48e3fceb447bc707e956f8f18..36aaac34e6c6c3869e737fcd8915652092b7d077 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -3661,8 +3661,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = {
 
        .reset_list             = sdm845_pciephy_reset_l,
        .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
-       .vreg_list              = sm8550_qmp_phy_vreg_l,
-       .num_vregs              = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
+       .vreg_list              = qmp_phy_vreg_l,
+       .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
        .regs                   = pciephy_v6_regs_layout,
 
        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
@@ -3695,8 +3695,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = {
 
        .reset_list             = sdm845_pciephy_reset_l,
        .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
-       .vreg_list              = sm8550_qmp_phy_vreg_l,
-       .num_vregs              = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
+       .vreg_list              = qmp_phy_vreg_l,
+       .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
        .regs                   = pciephy_v6_regs_layout,
 
        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,