--- /dev/null
+From 350ab15bb2ffe7103bc6bf6c634f3c5b286eaf2a Mon Sep 17 00:00:00 2001
+From: Jaccon Bastiaansen <jaccon.bastiaansen@gmail.com>
+Date: Mon, 30 Apr 2012 11:53:43 +0200
+Subject: ARM i.MX imx21ads: Fix overlapping static i/o mappings
+
+From: Jaccon Bastiaansen <jaccon.bastiaansen@gmail.com>
+
+commit 350ab15bb2ffe7103bc6bf6c634f3c5b286eaf2a upstream.
+
+The statically defined I/O memory regions for the i.MX21 on chip
+peripherals and the on board I/O peripherals of the i.MX21ADS board
+overlap. This results in a kernel crash during startup. This is fixed
+by reducing the memory range for the on board I/O peripherals to the
+actually required range.
+
+Signed-off-by: Jaccon Bastiaansen <jaccon.bastiaansen@gmail.com>
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-imx/mach-mx21ads.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/mach-imx/mach-mx21ads.c
++++ b/arch/arm/mach-imx/mach-mx21ads.c
+@@ -32,7 +32,7 @@
+ * Memory-mapped I/O on MX21ADS base board
+ */
+ #define MX21ADS_MMIO_BASE_ADDR 0xf5000000
+-#define MX21ADS_MMIO_SIZE SZ_16M
++#define MX21ADS_MMIO_SIZE 0xc00000
+
+ #define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \
+ (MX21ADS_MMIO_BASE_ADDR + (offset))
--- /dev/null
+From cdd781ab1906d039c2a93078385645d2d5af8491 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Mon, 4 Jun 2012 14:58:07 +0200
+Subject: ARM i.MX53: Fix PLL4 base address
+
+From: Sascha Hauer <s.hauer@pengutronix.de>
+
+commit cdd781ab1906d039c2a93078385645d2d5af8491 upstream.
+
+MX53_DPLL4_BASE accidently returned the base address of PLL3.
+Fix this.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-imx/crm-regs-imx5.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/mach-imx/crm-regs-imx5.h
++++ b/arch/arm/mach-imx/crm-regs-imx5.h
+@@ -23,7 +23,7 @@
+ #define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
+ #define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
+ #define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
+-#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
++#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR)
+
+ /* PLL Register Offsets */
+ #define MXC_PLL_DP_CTL 0x00
--- /dev/null
+From 602bf40971d7f9a1ec0b7ba2b7e6427849828651 Mon Sep 17 00:00:00 2001
+From: Shawn Guo <shawn.guo@linaro.org>
+Date: Tue, 22 May 2012 22:13:46 +0800
+Subject: ARM: imx6: exit coherency when shutting down a cpu
+
+From: Shawn Guo <shawn.guo@linaro.org>
+
+commit 602bf40971d7f9a1ec0b7ba2b7e6427849828651 upstream.
+
+There is a system hang issue on imx6q which can easily be seen with
+running a cpu hotplug stress testing (hotplug secondary cores from
+user space via sysfs interface for thousands iterations).
+
+It turns out that the issue is caused by coherency of the cpu that
+is being shut down. When shutting down a cpu, we need to have the
+cpu exit coherency to prevent it from receiving cache, TLB, or BTB
+maintenance operations broadcast by other CPUs in the cluster.
+
+Copy cpu_enter_lowpower() and cpu_leave_lowpower() from mach-vexpress
+to have coherency properly handled in platform_cpu_die(), thus fix
+the issue.
+
+Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-imx/hotplug.c | 42 +++++++++++++++++++++++++++++++++++++++++-
+ 1 file changed, 41 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/mach-imx/hotplug.c
++++ b/arch/arm/mach-imx/hotplug.c
+@@ -12,6 +12,7 @@
+
+ #include <linux/errno.h>
+ #include <asm/cacheflush.h>
++#include <asm/cp15.h>
+ #include <mach/common.h>
+
+ int platform_cpu_kill(unsigned int cpu)
+@@ -19,6 +20,44 @@ int platform_cpu_kill(unsigned int cpu)
+ return 1;
+ }
+
++static inline void cpu_enter_lowpower(void)
++{
++ unsigned int v;
++
++ flush_cache_all();
++ asm volatile(
++ "mcr p15, 0, %1, c7, c5, 0\n"
++ " mcr p15, 0, %1, c7, c10, 4\n"
++ /*
++ * Turn off coherency
++ */
++ " mrc p15, 0, %0, c1, c0, 1\n"
++ " bic %0, %0, %3\n"
++ " mcr p15, 0, %0, c1, c0, 1\n"
++ " mrc p15, 0, %0, c1, c0, 0\n"
++ " bic %0, %0, %2\n"
++ " mcr p15, 0, %0, c1, c0, 0\n"
++ : "=&r" (v)
++ : "r" (0), "Ir" (CR_C), "Ir" (0x40)
++ : "cc");
++}
++
++static inline void cpu_leave_lowpower(void)
++{
++ unsigned int v;
++
++ asm volatile(
++ "mrc p15, 0, %0, c1, c0, 0\n"
++ " orr %0, %0, %1\n"
++ " mcr p15, 0, %0, c1, c0, 0\n"
++ " mrc p15, 0, %0, c1, c0, 1\n"
++ " orr %0, %0, %2\n"
++ " mcr p15, 0, %0, c1, c0, 1\n"
++ : "=&r" (v)
++ : "Ir" (CR_C), "Ir" (0x40)
++ : "cc");
++}
++
+ /*
+ * platform-specific code to shutdown a CPU
+ *
+@@ -26,9 +65,10 @@ int platform_cpu_kill(unsigned int cpu)
+ */
+ void platform_cpu_die(unsigned int cpu)
+ {
+- flush_cache_all();
++ cpu_enter_lowpower();
+ imx_enable_cpu(cpu, false);
+ cpu_do_idle();
++ cpu_leave_lowpower();
+
+ /* We should never return from idle */
+ panic("cpu %d unexpectedly exit from shutdown\n", cpu);
projects / thirdparty / kernel / stable-queue.git / commitdiff
