Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d0c013e5045aaf6a0886c5981ea9a9a05fa2be96..6a8792ab77ccd263fcf684bec41f09a9e7ef96e9 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,75 @@
+2025-09-07  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+
+       PR tree-optimization/121841
+       * tree-ssa-forwprop.cc (optimize_agr_copyprop_1): Allow
+       two different decls as bases as non-overlapping bases.
+
+2025-09-07  Jeff Law  <jlaw@ventanamicro.com>
+
+       * dep-fusion.cc: Mark clone, gate and execute methods as final.
+
+2025-09-07  Kuan-Lin Chen  <rufus@andestech.com>
+
+       * config/riscv/andes-vector-builtins-bases.cc (nds_vd4dot): New class.
+       (class nds_vd4dotsu): New class.
+       * config/riscv/andes-vector-builtins-bases.h: New def.
+       * config/riscv/andes-vector-builtins-functions.def (nds_vd4dots): Ditto.
+       (nds_vd4dotsu): Ditto.
+       (nds_vd4dotu): Ditto.
+       * config/riscv/andes-vector.md
+       (@pred_nds_vd4dot<su><mode>): New pattern.
+       (@pred_nds_vd4dotsu<mode>): New pattern.
+       * config/riscv/genrvv-type-indexer.cc (main): Modify sew of QUAD_FIX,
+       QUAD_FIX_SIGNED and QUAD_FIX_UNSIGNED.
+       * config/riscv/riscv-vector-builtins.cc
+       (qexti_vvvv_ops): New operand information.
+       (qexti_su_vvvv_ops): New operand information.
+       (qextu_vvvv_ops): New operand information.
+       * config/riscv/riscv-vector-builtins.h (XANDESVDOT_EXT): New def.
+       (required_ext_to_isa_name): Add case XANDESVDOT_EXT.
+       (required_extensions_specified): Ditto.
+       (struct function_group_info): Ditto.
+       * config/riscv/vector-iterators.md (NDS_QUAD_FIX): New iterator.
+
+2025-09-07  Jeff Law  <jlaw@ventanamicro.com>
+
+       * config/riscv/riscv-opts.h (riscv_microarchitecture_type): Fix ordering.
+
+2025-09-07  Kuan-Lin Chen  <rufus@andestech.com>
+
+       * common/config/riscv/riscv-common.cc:
+       Turn on VECTOR_ELEN_FP_16 for XAndesvpackfph.
+       * config/riscv/andes-vector-builtins-bases.cc (nds_vfpmad): New class.
+       * config/riscv/andes-vector-builtins-bases.h: New def.
+       * config/riscv/andes-vector-builtins-functions.def (nds_vfpmadt): Ditto.
+       (nds_vfpmadb): Ditto.
+       (nds_vfpmadt_frm): Ditto.
+       (nds_vfpmadb_frm): Ditto.
+       * config/riscv/andes-vector.md (@pred_nds_vfpmad<nds_tb><mode>):
+       New pattern.
+       * config/riscv/riscv-vector-builtins-types.def
+       (DEF_RVV_F16_OPS): New def.
+       * config/riscv/riscv-vector-builtins.cc (f16_ops): Ditto
+       * config/riscv/riscv-vector-builtins.def (float32_type_node): Ditto.
+       * config/riscv/riscv-vector-builtins.h (XANDESVPACKFPH_EXT): Ditto.
+       (required_ext_to_isa_name): Add case XANDESVPACKFPH_EXT.
+       (required_extensions_specified): Ditto.
+       * config/riscv/vector-iterators.md (VHF): New iterator.
+
+2025-09-07  Georg-Johann Lay  <avr@gjlay.de>
+
+       PR target/121794
+       * config/avr/avr.md (cmpqi3): Use cpi R,0 if possible.
+
+2025-09-07  Pan Li  <pan2.li@intel.com>
+
+       * config/riscv/autovec-opt.md (*vnmsac_vx_<mode>): Rename from.
+       (*mul_minus_vx_<mode>): Rename to and add nmsub support.
+       * config/riscv/vector.md (@pred_vnmsac_vx_<mode>): Rename from.
+       (@pred_mul_minus_vx_<mode>): Rename to and add nmsub support.
+       (*pred_nmsac_<mode>_scalar_undef): Rename from.
+       (*pred_mul_minus_vx<mode>_undef): Rename to and add nmsub support.
+
 2025-09-06  Sam James  <sam@gentoo.org>
 
        * doc/generic.texi (TYPE_CANONICAL): Don't mention long-removed

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 69422b8747cb9d9cabe50dbc52efb63520c6721e..535d724e1543cf25d5e768f15e0378b8a3a611ea 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20250907
+20250908

diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 6e61dffc258624f3f75a3bf15353917cc1c2f5db..28a80d0edc22df022641092760652635c9c52650 100644 (file)
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,14 @@
+2025-09-07  H.J. Lu  <hjl.tools@gmail.com>
+
+       PR c++/107393
+       * decl.cc (grokvardecl): Set a tentative TLS model which will be
+       updated by cplus_decl_attributes later.
+       * decl2.cc (cplus_decl_attributes): Update TLS model with the
+       default TLS access model if the default TLS access model is
+       stronger.
+       * pt.cc (tsubst_decl): Set TLS model only after processing a
+       variable.
+
 2025-09-06  Nathaniel Shead  <nathanieloshead@gmail.com>
 
        PR c++/121702

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index db469031de4cf6eb3f75084adc3129497c92c188..965d93b3f6aed8df5cca13f7fd8dbd0635cab23f 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,85 @@
+2025-09-07  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+
+       PR tree-optimization/121841
+       * gcc.dg/tree-ssa/copy-prop-aggregate-struct-1.c: New test.
+
+2025-09-07  Kuan-Lin Chen  <rufus@andestech.com>
+
+       * gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vd4dots.c: New test.
+       * gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vd4dotsu.c: New test.
+       * gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vd4dotu.c: New test.
+       * gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vd4dots.c: New test.
+       * gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vd4dotsu.c: New test.
+       * gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vd4dotu.c: New test.
+       * gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vd4dots.c: New test.
+       * gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vd4dotsu.c: New test.
+       * gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vd4dotu.c: New test.
+       * gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vd4dots.c: New test.
+       * gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vd4dotsu.c: New test.
+       * gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vd4dotu.c: New test.
+
+2025-09-07  Kuan-Lin Chen  <rufus@andestech.com>
+
+       * gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfpmadb.c: New test.
+       * gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfpmadt.c: New test.
+       * gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfpmadb.c: New test.
+       * gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfpmadt.c: New test.
+       * gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfpmadb.c: New test.
+       * gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfpmadt.c: New test.
+       * gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfpmadb.c: New test.
+       * gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfpmadt.c: New test.
+       * gcc.target/riscv/rvv/autovec/vls/J: New file.
+
+2025-09-07  H.J. Lu  <hjl.tools@gmail.com>
+
+       PR c++/107393
+       * g++.dg/tls/pr107393-1.C: New test.
+       * g++.dg/tls/pr107393-2.C: Likewise.
+
+2025-09-07  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check
+       for vnmsub.vx.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u16.c: New test.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u32.c: New test.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u64.c: New test.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u8.c: New test.
+
+2025-09-07  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check
+       for vnmsub.vx.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h: Add test
+       helper macros.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h: Add test
+       data for run test.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i16.c: New test.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i32.c: New test.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i64.c: New test.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i8.c: New test.
+
 2025-09-06  Kuan-Lin Chen  <rufus@andestech.com>
 
        * gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vln8.c: New test.

diff --git a/libphobos/ChangeLog b/libphobos/ChangeLog
index 442d80bf935dbb05d9dab64debf9c2cc9ec3f461..cabed28bb5d24864646a34aeab96b82fb6b24d56 100644 (file)
--- a/libphobos/ChangeLog
+++ b/libphobos/ChangeLog
@@ -1,3 +1,12 @@
+2025-09-07  Sam James  <sam@gentoo.org>
+
+       * configure.tgt: Add hppa[12]*-*-linux* as a supported target.
+
+2025-09-07  Matthias Klose  <doko@ubuntu.com>
+
+       * configure.tgt: Add powerpc64le-linux-gnu as a supported target
+       when configured with --with-long-double-format=ieee.
+
 2025-09-02  Iain Sandoe  <iain@sandoe.co.uk>
 
        * libdruntime/core/thread/osthread.d: Use PPC_THREAD_STATE