+2025-05-21 Stephanos Ioannidis <root@stephanos.io>
+
+ * configure.ac: Always add pre-installed heades to search path.
+ * configure: Regenerate.
+
2025-05-16 Spencer Abson <spencer.abson@arm.com>
* MAINTAINERS: Add myself to write after approval.
+2025-05-22 Pengxuan Zheng <quic_pzheng@quicinc.com>
+
+ * config/aarch64/aarch64.cc (aarch64_evpc_reencode): Copy zero_op0_p and
+ zero_op1_p from d to newd.
+
+2025-05-21 Andrew Pinski <quic_apinski@quicinc.com>
+
+ PR rtl-optimization/120090
+ * combine.cc (gen_lowpart_for_combine_no_emit): New function.
+ (RTL_HOOKS_GEN_LOWPART_NO_EMIT): Set to gen_lowpart_for_combine_no_emit.
+
+2025-05-21 Jeff Law <jlaw@ventanamicro.com>
+
+ * config/riscv/riscv.md ((x << C1) + C2): Tighten split condition
+ and generate more efficient code when splitting.
+
+2025-05-21 Jeff Law <jlaw@ventanamicro.com>
+
+ PR target/120368
+ * config/riscv/riscv.md (shift with masked shift count): Fix
+ opcode when generating an SImode shift on rv64.
+
+2025-05-21 Pan Li <pan2.li@intel.com>
+
+ * config/riscv/riscv-v.cc (expand_vx_binary_vec_dup_vec): Add new
+ case for rtx code AND.
+ (expand_vx_binary_vec_vec_dup): Ditto.
+ * config/riscv/riscv.cc (riscv_rtx_costs): Ditto.
+ * config/riscv/vector-iterators.md: Add new op and to no_shift_vx_ops.
+
+2025-05-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * gensupport.h (needs_barrier_p): Delete.
+ * gensupport.cc (needs_barrier_p): Likewise.
+ * rtl.h (always_void_p): Return true for PC, RETURN and SIMPLE_RETURN.
+ (expand_opcode): New enum class.
+ (expand_rtx, complete_seq): Declare.
+ * emit-rtl.cc (rtx_expander): New class.
+ (expand_rtx, complete_seq): New functions.
+ * gengenrtl.cc (special_rtx, excluded_rtx): Add a cross-reference
+ comment.
+ * genemit.cc (FIRST_CODE): New constant.
+ (print_code): Delete.
+ (generator::file, generator::used, generator::sequence_type): Delete.
+ (generator::bytes): New member variable.
+ (generator::generator): Update accordingly.
+ (generator::gen_rtx_scratch): Delete.
+ (generator::add_uint, generator::add_opcode, generator::add_code)
+ (generator::add_match_operator, generator::add_exp)
+ (generator::add_vec, generator::gen_table): New member functions.
+ (generator::gen_exp): Rewrite to use a bytecode expansion.
+ (generator::gen_emit_seq): Likewise.
+ (start_gen_insn): Return the C++ expression for the operands array.
+ (gen_insn, gen_expand, gen_split): Update callers accordingly.
+ (emit_c_code): Remove use of _val.
+
+2025-05-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * genemit.cc (clobber_pat::code): Delete.
+ (maybe_queue_insn): Don't set clobber_pat::code.
+ (output_add_clobbers): Remove info argument and output the two
+ REG and SCRATCH cases directly.
+ (main): Update call accordingly.
+
+2025-05-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * genemit.cc (generator::gen_exp): Report an error for 's' operands.
+
+2025-05-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * genemit.cc (generator::gen_exp): Raise an error if we see
+ an 'L' operand.
+
+2025-05-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * genemit.cc (generator::used): Update comment.
+ (generator::gen_exp): Remove handling of null unused arrays.
+ (gen_insn, gen_expand): Always pass a used array.
+ (output_add_clobbers): Note why the used array is null here.
+
+2025-05-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * genemit.cc (generator): New structure.
+ (gen_rtx_scratch, gen_exp, gen_emit_seq): Turn into member
+ functions of generator.
+ (gen_insn, gen_expand, gen_split, output_add_clobbers): Update
+ users accordingly.
+
+2025-05-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * genemit.cc (gen_rtx_scratch, gen_exp): Use operands[%d] rather than
+ operand%d.
+ (start_gen_insn): Mark the incoming arguments as const and store
+ them to an operands array.
+ (gen_expand, gen_split): Remove copies into and out of the operands
+ array.
+
+2025-05-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * genemit.cc (start_gen_insn): New function, split out from...
+ (gen_insn, gen_expand): ...here.
+
+2025-05-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * genemit.cc (queue): New static variable.
+ (maybe_queue_insn): New function, split out from...
+ (gen_insn): ...here.
+ (queue_expand): New function, split out from...
+ (gen_expand): ...here.
+ (gen_split): New function, split out from...
+ (queue_split): ...here.
+ (main): Queue definitions for later processing rather than
+ emitting them on the fly.
+
+2025-05-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * genemit.cc (gen_exp): Make the info argument a constant reference.
+ (gen_emit_seq, gen_insn, gen_expand, gen_split): Likewise.
+ (output_add_clobbers): Likewise.
+ (main): Update calls accordingly.
+
+2025-05-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/sparc/sparc.md (zero_extendhisi2, zero_extendhidi2)
+ (extendhisi2, extendqihi2, extendqisi2, extendqidi2)
+ (extendhidi2): Use operands[0] and operands[1] instead of
+ operand0 and operand1.
+
+2025-05-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/stormy16/stormy16.md (negsi2): Remove unused assignment.
+
+2025-05-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR target/100837
+ * config/nds32/nds32-intrinsic.md (unspec_get_pending_int): Use
+ a local variable instead of operands[2].
+
+2025-05-21 Andrew Pinski <quic_apinski@quicinc.com>
+
+ PR middle-end/120369
+ * tree-complex.cc (gimple_expand_builtin_cabs): Return early
+ if the LHS of cabs is null.
+
+2025-05-21 Co-Authored-By: Jeff Law <jlaw@ventanamicro.com>
+
+ * config/riscv/riscv-protos.h (synthesize_and): Prototype.
+ * config/riscv/riscv.cc (synthesize_and): New function.
+ * config/riscv/riscv.md (and<mode>3): Use it.
+
+2025-05-21 liuhongt <hongtao.liu@intel.com>
+
+ PR middle-end/118994
+ * match.pd ((a >> 1) + (b >> 1) + ((a | b) & 1) to
+ .AVG_CEIL (a, b)): New pattern.
+ ((a | b) - ((a ^ b) >> 1) to .AVG_CEIL (a, b)): Ditto.
+
2025-05-20 Andrew Pinski <quic_apinski@quicinc.com>
* Makefile.in (gimple-match-exports.o-warn): Remove.
+2025-05-21 Iain Sandoe <iain@sandoe.co.uk>
+
+ * coroutines.cc
+ (cp_coroutine_transform::build_ramp_function): Replace ramp
+ cleanup try-catch block with eh-only cleanup statements.
+
+2025-05-21 Iain Sandoe <iain@sandoe.co.uk>
+
+ * coroutines.cc
+ (cp_coroutine_transform::build_ramp_function): Use
+ decltype(auto) to determine the type of the temporary
+ get_return_object.
+
+2025-05-21 Iain Sandoe <iain@sandoe.co.uk>
+
+ PR c++/119916
+ * coroutines.cc
+ (cp_coroutine_transform::wrap_original_function_body): Do not
+ initialise initial_await_resume_called here...
+ (cp_coroutine_transform::build_ramp_function): ... but here.
+ When the coroutine is not void, initialize a GRO object from
+ promise.get_return_object(). Use this as the argument to the
+ return expression. Use a regular cleanup for the GRO, since
+ it is ramp-local.
+
2025-05-20 Nathaniel Shead <nathanieloshead@gmail.com>
PR c++/120349
+2025-05-21 Jeff Law <jlaw@ventanamicro.com>
+
+ PR target/120368
+ * gcc.target/riscv/pr120368.c: New test.
+
+2025-05-21 Pan Li <pan2.li@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: Add asm check
+ for vand.vx combine.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.
+
+2025-05-21 Pan Li <pan2.li@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add test cases
+ for vand vx combine case 0 on GR2VR cost.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
+ data for vand.vx run test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i16.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i32.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i64.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i8.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u16.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u32.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u64.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u8.c: New test.
+
+2025-05-21 Alexandre Oliva <oliva@adacore.com>
+
+ * gcc.dg/vect/vect-simd-clone-16e.c: Expect fewer calls on ia32.
+ * gcc.dg/vect/vect-simd-clone-17e.c: Likewise.
+ * gcc.dg/vect/vect-simd-clone-18e.c: Likewise.
+
+2025-05-21 Alexandre Oliva <oliva@adacore.com>
+
+ * gcc.target/i386/pr31985.c: Add -fomit-frame-pointer.
+
+2025-05-21 Alexandre Oliva <oliva@adacore.com>
+
+ * gcc.target/i386/pr108938-3.c: Add -msse2.
+
+2025-05-21 Alexandre Oliva <oliva@adacore.com>
+
+ * gcc.target/i386/no-callee-saved-16.c: Add -fomit-frame-pointer.
+
+2025-05-21 Alexandre Oliva <oliva@adacore.com>
+
+ * gcc.dg/vect/tsvc/vect-tsvc-s332.c: Require vect_early_break_hw.
+ * gcc.dg/vect/tsvc/vect-tsvc-s481.c: Likewise.
+ * gcc.dg/vect/tsvc/vect-tsvc-s482.c: Likewise.
+
+2025-05-21 Alexandre Oliva <oliva@adacore.com>
+
+ * gcc.dg/tree-ssa/forwprop-41.c: Add -msse on x86.
+
+2025-05-21 Alexandre Oliva <oliva@adacore.com>
+
+ * gcc.dg/strlenopt-80.c: Bump to -msse2.
+
+2025-05-21 Alexandre Oliva <oliva@adacore.com>
+
+ * gcc.dg/memcpy-6.c: Bump to -msse2.
+
+2025-05-21 Alexandre Oliva <oliva@adacore.com>
+
+ * gcc.dg/fold-copysign-1.c: Bump to sse2 on ia32.
+ * gcc.dg/pr55152-2.c: Likewise.
+ * gcc.dg/tree-ssa/abs-4.c: Likewise.
+ * gcc.dg/tree-ssa/backprop-6.c: Likewise.
+
+2025-05-21 Alexandre Oliva <oliva@adacore.com>
+
+ * gcc.target/aarch64/sme/nonlocal_goto_1.c: Match
+ vxworks cache-clearing function as well.
+ * gcc.target/aarch64/sme/nonlocal_goto_2.c: Likewise.
+ * gcc.target/aarch64/sme/nonlocal_goto_3.c: Likewise.
+
+2025-05-21 Alexandre Oliva <oliva@adacore.com>
+
+ * gcc.target/aarch64/acle/rwsr.c: Use uint64_t.
+ * gcc.target/aarch64/acle/rwsr-2.c: Likewise.
+
+2025-05-21 Alexandre Oliva <oliva@adacore.com>
+
+ * c-c++-common/analyzer/strtok-cppreference.c
+ (__STDC_WANT_LIB_EXT1__): Define to 1.
+
+2025-05-21 Alexandre Oliva <oliva@adacore.com>
+
+ * c-c++-common/analyzer/fd-glibc-byte-stream-socket.c: Skip on
+ vxworks with C++ < 11.
+
+2025-05-21 Iain Sandoe <iain@sandoe.co.uk>
+
+ * g++.dg/coroutines/pr115908.C: Count promise construction
+ and destruction. Run the test and XFAIL it.
+
+2025-05-21 Iain Sandoe <iain@sandoe.co.uk>
+
+ PR c++/119916
+ * g++.dg/coroutines/torture/special-termination-00-sync-completion.C:
+ Amend for CWG2563 expected behaviour.
+ * g++.dg/coroutines/torture/special-termination-01-self-destruct.C:
+ Likewise.
+ * g++.dg/coroutines/torture/pr119916.C: New test.
+
+2025-05-21 Andrew Pinski <quic_apinski@quicinc.com>
+
+ PR middle-end/120369
+ * gcc.dg/torture/pr120369-1.c: New test.
+
+2025-05-21 liuhongt <hongtao.liu@intel.com>
+
+ * gcc.target/i386/pr118994-1.c: New test.
+ * gcc.target/i386/pr118994-2.c: New test.
+
2025-05-20 Robert Dubner <rdubner@symas.com>
* cobol.dg/group2/FUNCTION_SQRT__2_.cob: Testcase.
+2025-05-21 Alexandre Oliva <oliva@adacore.com>
+
+ * config/gthr-vxworks-thread.c: Include string.h for memset.
+
2025-05-20 Jakub Jelinek <jakub@redhat.com>
* libgcc-std.ver.in (GCC_14.0.0): Remove bitint related exports
+2025-05-21 Alexandre Oliva <oliva@adacore.com>
+
+ * testsuite/21_strings/basic_string/numeric_conversions/char/stold.cc:
+ Guard non-wide stold calls with conditions for it to be
+ defined.
+ * testsuite/27_io/basic_ostream/inserters_arithmetic/char/hexfloat.cc:
+ Likewise.
+
+2025-05-21 Xℹ Ruoyao <xry111@mengyan1223.wang>
+
+ PR libstdc++/81806
+ * include/ext/pb_ds/detail/bin_search_tree_/split_join_fn_imps.hpp
+ (split_finish): Use maintained size, instead of calling
+ std::distance.
+
+2025-05-21 Xℹ Ruoyao <xry111@mengyan1223.wang>
+
+ * include/ext/pb_ds/detail/rb_tree_map_/node.hpp
+ (rb_tree_node_::size_type): New typedef.
+ (rb_tree_node_::m_subtree_size): New field.
+ * include/ext/pb_ds/detail/splay_tree_/node.hpp
+ (splay_tree_node_::size_type): New typedef.
+ (splay_tree_node_::m_subtree_size): New field.
+ * include/ext/pb_ds/detail/bin_search_tree_/bin_search_tree_.hpp
+ (PB_DS_BIN_TREE_NAME::update_subtree_size): Declare new member
+ function.
+ * include/ext/pb_ds/detail/bin_search_tree_/rotate_fn_imps.hpp
+ (update_subtree_size): Define.
+ (apply_update, update_to_top): Call update_subtree_size.
+
+2025-05-21 Xℹ Ruoyao <xry111@mengyan1223.wang>
+
+ * include/ext/pb_ds/detail/bin_search_tree_/insert_fn_imps.hpp
+ (insert_leaf_new, insert_imp_empty): remove redundant statements.
+
2025-05-20 Tomasz Kamiński <tkaminsk@redhat.com>
* include/bits/chrono_io.h (_ChronoSpec::_M_locale_specific):
projects / thirdparty / gcc.git / commitdiff
