drm/i915/gt: Whitelist COMMON_SLICE_CHICKEN1 for UMD access.

As part of the recommended tuning setting, whitelist COMMON_SLICE_CHICKEN1
for MTL/ARL and DG2.

The UMD will selectively enable or disable specific bits of the
register based on the type of workload and its requirements.

v2: Remove the KMD par of enabling specific bits(Matt R)

Bspec: 68331
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240825121156.2498810-1-dnyaneshwar.bhadane@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index baa609bdf7cb4fe8db3b11da6d066c9282e3f758..e539a656cfc3ae8d833f22efd23aeb601fb780ca 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2071,7 +2071,7 @@ static void dg2_whitelist_build(struct intel_engine_cs *engine)
        case RENDER_CLASS:
                /* Required by recommended tuning setting (not a workaround) */
                whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3);
-
+               whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1);
                break;
        default:
                break;
@@ -2086,7 +2086,7 @@ static void xelpg_whitelist_build(struct intel_engine_cs *engine)
        case RENDER_CLASS:
                /* Required by recommended tuning setting (not a workaround) */
                whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3);
-
+               whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1);
                break;
        default:
                break;