drm/i915/fbc: fix the implementation of wa_18038517565

[ Upstream commit fd56b9c9507f32b16159f9a922e1af5628254567 ]

As per the wa_18038517565, we need to disable FBC compressor
clock gating before enabling FBC and enable after disabling
FBC. Placing the enabling of clock gating in the fbc deactivate
function can make the above wa logic go wrong in case of
frontbuffer rendering FBC mechanism. FBC deactivate can get
called during fb invalidate and then the corresponding FBC
activate can get called without properly disabling the clock
gating and can result in compression stalled. So move the
enable clock gating at the end of one FBC session after FBC
is completely disabled for a pipe.

Bspec: 74212, 72197, 69741, 65555
Fixes: 010363c46189 ("drm/i915/display: implement wa_18038517565")
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20250729124648.288497-1-vinod.govindapillai@intel.com
(cherry picked from commit 82dde0407ab126f8413fd6c51429e5057ced5ba2)
Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index bed2bba20b555cf5a34315d31264c1d073f748f2..6ddbc682ec1cd283236bddff87aebbe2ddc16df4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -550,10 +550,6 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
        if (dpfc_ctl & DPFC_CTL_EN) {
                dpfc_ctl &= ~DPFC_CTL_EN;
                intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
-
-               /* wa_18038517565 Enable DPFC clock gating after FBC disable */
-               if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
-                       fbc_compressor_clkgate_disable_wa(fbc, false);
        }
 }
 
@@ -1708,6 +1704,10 @@ static void __intel_fbc_disable(struct intel_fbc *fbc)
 
        __intel_fbc_cleanup_cfb(fbc);
 
+       /* wa_18038517565 Enable DPFC clock gating after FBC disable */
+       if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
+               fbc_compressor_clkgate_disable_wa(fbc, false);
+
        fbc->state.plane = NULL;
        fbc->flip_pending = false;
        fbc->busy_bits = 0;