arm64: dts: qcom: milos: Add UFS nodes

Add the nodes for the UFS PHY and UFS host controller, along with the
ICE used for UFS.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20260319-milos-ufs-v3-1-b7c60bdd0d48@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index c05308be05bb2925a01589142b48988110063907..67f8ef4d524abbcb0aec6334f15f88de857b7771 100644 (file)
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -799,9 +799,9 @@
                                 <&sleep_clk>,
                                 <0>, /* pcie_0_pipe_clk */
                                 <0>, /* pcie_1_pipe_clk */
-                                <0>, /* ufs_phy_rx_symbol_0_clk */
-                                <0>, /* ufs_phy_rx_symbol_1_clk */
-                                <0>, /* ufs_phy_tx_symbol_0_clk */
+                                <&ufs_mem_phy 0>,
+                                <&ufs_mem_phy 1>,
+                                <&ufs_mem_phy 2>,
                                 <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */
 
                        #clock-cells = <1>;
@@ -1153,6 +1153,129 @@
                        qcom,bcm-voters = <&apps_bcm_voter>;
                };
 
+               ufs_mem_phy: phy@1d80000 {
+                       compatible = "qcom,milos-qmp-ufs-phy";
+                       reg = <0x0 0x01d80000 0x0 0x2000>;
+
+                       clocks = <&rpmhcc RPMH_CXO_CLK>,
+                                <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+                                <&tcsr TCSR_UFS_CLKREF_EN>;
+                       clock-names = "ref",
+                                     "ref_aux",
+                                     "qref";
+
+                       resets = <&ufs_mem_hc 0>;
+                       reset-names = "ufsphy";
+
+                       power-domains = <&gcc UFS_MEM_PHY_GDSC>;
+
+                       #clock-cells = <1>;
+                       #phy-cells = <0>;
+
+                       status = "disabled";
+               };
+
+               ufs_mem_hc: ufshc@1d84000 {
+                       compatible = "qcom,milos-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
+                       reg = <0x0 0x01d84000 0x0 0x3000>;
+
+                       interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
+
+                       clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+                                <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+                                <&gcc GCC_UFS_PHY_AHB_CLK>,
+                                <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+                                <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
+                                <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+                                <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+                                <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+                       clock-names = "core_clk",
+                                     "bus_aggr_clk",
+                                     "iface_clk",
+                                     "core_clk_unipro",
+                                     "ref_clk",
+                                     "tx_lane0_sync_clk",
+                                     "rx_lane0_sync_clk",
+                                     "rx_lane1_sync_clk";
+
+                       resets = <&gcc GCC_UFS_PHY_BCR>;
+                       reset-names = "rst";
+
+                       interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+                                       <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &cnoc_cfg SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+                       interconnect-names = "ufs-ddr",
+                                            "cpu-ufs";
+
+                       power-domains = <&gcc UFS_PHY_GDSC>;
+                       required-opps = <&rpmhpd_opp_nom>;
+
+                       operating-points-v2 = <&ufs_opp_table>;
+
+                       iommus = <&apps_smmu 0x60 0>;
+
+                       dma-coherent;
+
+                       lanes-per-direction = <2>;
+                       qcom,ice = <&ice>;
+
+                       phys = <&ufs_mem_phy>;
+                       phy-names = "ufsphy";
+
+                       #reset-cells = <1>;
+
+                       status = "disabled";
+
+                       ufs_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-75000000 {
+                                       opp-hz = /bits/ 64 <75000000>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <75000000>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                               };
+
+                               opp-150000000 {
+                                       opp-hz = /bits/ 64 <150000000>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <150000000>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>;
+                                       required-opps = <&rpmhpd_opp_svs>;
+                               };
+
+                               opp-300000000 {
+                                       opp-hz = /bits/ 64 <300000000>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <300000000>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>;
+                                       required-opps = <&rpmhpd_opp_nom>;
+                               };
+                       };
+               };
+
+               ice: crypto@1d88000 {
+                       compatible = "qcom,milos-inline-crypto-engine",
+                                    "qcom,inline-crypto-engine";
+                       reg = <0x0 0x01d88000 0x0 0x18000>;
+
+                       clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+               };
+
                tcsr_mutex: hwlock@1f40000 {
                        compatible = "qcom,tcsr-mutex";
                        reg = <0x0 0x01f40000 0x0 0x20000>;