[gcc]

2016-03-11  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/70131
	* config/rs6000/rs6000.md (round32<mode>2_fprs): Do not do the
	optimization if we have direct move.
	(roundu32<mode>2_fprs): Likewise.

[gcc/testsuite]
2016-03-11  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/70131
	* gcc.target/powerpc/ppc-round2.c: New test.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@234155 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ee80171f5b701392043f60a6c8e2cf2d7802e8ff..6fd40f574368f6fd5f6ec50f62f429268cc27ae2 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2016-03-11  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+       PR target/70131
+       * config/rs6000/rs6000.md (round32<mode>2_fprs): Do not do the
+       optimization if we have direct move.
+       (roundu32<mode>2_fprs): Likewise.
+
 2016-03-11  Bernd Schmidt  <bschmidt@redhat.com>
 
        PR target/70123

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 0299a0002af2f99f0167f4d20021595eb4553e86..c92c868a6391f4d2c718280ed3b15c6ed2978701 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5387,10 +5387,12 @@
    xsrdpiz %x0,%x1"
   [(set_attr "type" "fp")])
 
-;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
-;; load to properly sign extend the value, but at least doing a store, load
-;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
-;; if we have 32-bit memory ops
+;; Opitmize converting SF/DFmode to signed SImode and back to SF/DFmode.  This
+;; optimization prevents on ISA 2.06 systems and earlier having to store the
+;; value from the FPR/vector unit to the stack, load the value into a GPR, sign
+;; extend it, store it back on the stack from the GPR, load it back into the
+;; FP/vector unit to do the rounding. If we have direct move (ISA 2.07),
+;; disable using store and load to sign/zero extend the value.
 (define_insn_and_split "*round32<mode>2_fprs"
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
        (float:SFDF
@@ -5399,7 +5401,7 @@
    (clobber (match_scratch:DI 3 "=d"))]
   "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
    && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
-   && can_create_pseudo_p ()"
+   && !TARGET_DIRECT_MOVE && can_create_pseudo_p ()"
   "#"
   ""
   [(pc)]
@@ -5431,7 +5433,7 @@
    (clobber (match_scratch:DI 2 "=d"))
    (clobber (match_scratch:DI 3 "=d"))]
   "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
-   && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
+   && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU && !TARGET_DIRECT_MOVE
    && can_create_pseudo_p ()"
   "#"
   ""

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 9198d81f75977bca366e66b9f7b8d302614ae076..a2eac07f3ec6590ae3ba5b0b951f351e2a5c11ca 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2016-03-11  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+       PR target/70131
+       * gcc.target/powerpc/ppc-round2.c: New test.
+
 2016-03-11  Bernd Schmidt  <bschmidt@redhat.com>
 
        PR target/70123

diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-round2.c b/gcc/testsuite/gcc.target/powerpc/ppc-round2.c
new file mode 100644 (file)
index 0000000..39375a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-round2.c
@@ -0,0 +1,42 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-O2 -mcpu=power8" } */
+/* { dg-final { scan-assembler-times "fcfid "      2 } } */
+/* { dg-final { scan-assembler-times "fcfids "     2 } } */
+/* { dg-final { scan-assembler-times "fctiwuz "    2 } } */
+/* { dg-final { scan-assembler-times "fctiwz "     2 } } */
+/* { dg-final { scan-assembler-times "mfvsrd "     4 } } */
+/* { dg-final { scan-assembler-times "mtvsrwa "    2 } } */
+/* { dg-final { scan-assembler-times "mtvsrwz "    2 } } */
+/* { dg-final { scan-assembler-not   "lwz"           } } */
+/* { dg-final { scan-assembler-not   "lfiwax "       } } */
+/* { dg-final { scan-assembler-not   "lfiwzx "       } } */
+/* { dg-final { scan-assembler-not   "stw"           } } */
+/* { dg-final { scan-assembler-not   "stfiwx "       } } */
+
+/* Make sure we don't have loads/stores to the GPR unit.  */
+double
+round_double_int (double a)
+{
+  return (double)(int)a;
+}
+
+float
+round_float_int (float a)
+{
+  return (float)(int)a;
+}
+
+double
+round_double_uint (double a)
+{
+  return (double)(unsigned int)a;
+}
+
+float
+round_float_uint (float a)
+{
+  return (float)(unsigned int)a;
+}