/ {
/* Introduce a fixed regulator for the new ethernet controller */
- veth: fixedregulator@0 {
+ veth: regulator-veth {
compatible = "regulator-fixed";
regulator-name = "veth";
regulator-min-microvolt = <3300000>;
};
/* The voltage to the MMC card is hardwired at 3.3V */
- vmmc: fixedregulator@0 {
+ vmmc: regulator-vmmc {
compatible = "regulator-fixed";
regulator-name = "vmmc";
regulator-min-microvolt = <3300000>;
clock-frequency = <24000000>;
};
- timclk: timclk@1M {
+ timclk: clock-1000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
};
/* FIXME: this actually hangs off the PLL clocks */
- pclk: pclk@0 {
+ pclk: clock-pclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
clock-frequency = <24000000>;
};
- timclk: timclk@1M {
+ timclk: clock-1000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
};
/* FIXME: this actually hangs off the PLL clocks */
- pclk: pclk@0 {
+ pclk: clock-pclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
clock-frequency = <24000000>;
};
- refclk32khz: refclk32khz {
+ refclk32khz: clock-32768 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
- timclk: timclk@1M {
+ timclk: clock-1000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
};
/* FIXME: this actually hangs off the PLL clocks */
- pclk: pclk@0 {
+ pclk: clock-pclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
clock-frequency = <24000000>;
};
- refclk32khz: refclk32khz {
+ refclk32khz: clock-32768 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
- timclk: timclk@1M {
+ timclk: clock-1000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
};
/* FIXME: this actually hangs off the PLL clocks */
- pclk: pclk@0 {
+ pclk: clock-pclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
/* Also used for the Smart Card Interface SCI */
- impd1_uartclk: clock@1_4 {
+ impd1_uartclk: clock-uart {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <4>;
};
/* For the SSP the clock is divided by 64 */
- impd1_sspclk: clock@1_64 {
+ impd1_sspclk: clock-ssp {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <64>;
};
/* The UART clock is 14.74 MHz divided by an ICS525 */
- uartclk: uartclk@14.74M {
+ uartclk: clock-14745600 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <14745600>;
core-module@10000000 {
/* 24 MHz chrystal on the core module */
- cm24mhz: cm24mhz@24M {
+ cm24mhz: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
*/
/* The codec chrystal operates at 24.576 MHz */
- xtal_codec: xtal24.576@24.576M {
+ xtal_codec: clock-24576000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24576000>;
};
/* The chrystal is divided by 2 by the codec for the AACI bit clock */
- aaci_bitclk: aaci_bitclk@12.288M {
+ aaci_bitclk: clock-12288000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <2>;
};
/* This is a 25MHz chrystal on the base board */
- xtal25mhz: xtal25mhz@25M {
+ xtal25mhz: clock-25000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
/* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
- uartclk: uartclk@14.74M {
+ uartclk: clock-14745600 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <14745600>;
};
/* Actually sysclk I think */
- pclk: pclk@0 {
+ pclk: clock-pclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
core-module@10000000 {
/* 24 MHz chrystal on the core module */
- cm24mhz: cm24mhz@24M {
+ cm24mhz: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
/* The timer clock is the 24 MHz oscillator divided to 1MHz */
- timclk: timclk@1M {
+ timclk: clock-1000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
#address-cells = <1>;
#size-cells = <1>;
- oscclk0: clk-osc0 {
+ oscclk0: clock-50000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
- oscclk1: clk-osc1 {
+ oscclk1: clock-24576000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
- oscclk2: clk-osc2 {
+ oscclk2: clock-25000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
- cfgclk: clk-cfg {
+ cfgclk: clock-5000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <5000000>;
};
- spicfgclk: clk-spicfg {
+ spicfgclk: clock-75000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <75000000>;
clock-mult = <1>;
};
- audmclk: clk-audm {
+ audmclk: clk-12388000 {
compatible = "fixed-factor-clock";
clocks = <&oscclk1>;
#clock-cells = <0>;
clock-mult = <1>;
};
- audsclk: clk-auds {
+ audsclk: clk-3072000 {
compatible = "fixed-factor-clock";
clocks = <&oscclk1>;
#clock-cells = <0>;
reg = <0x0 0x08000000>;
};
- xtal24mhz: xtal24mhz@24M {
+ xtal24mhz: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
/* OSC1 on AB, OSC4 on PB */
- osc1: cm_aux_osc@24M {
+ osc1: clock-osc {
#clock-cells = <0>;
compatible = "arm,versatile-cm-auxosc";
clocks = <&xtal24mhz>;
};
/* The timer clock is the 24 MHz oscillator divided to 1MHz */
- timclk: timclk@1M {
+ timclk: clock-1000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
clocks = <&xtal24mhz>;
};
- pclk: pclk@24M {
+ pclk: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
- v2m_fixed_3v3: fixed-regulator-0 {
+ v2m_fixed_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- v2m_clk24mhz: clk24mhz {
+ v2m_clk24mhz: clock-24000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
- v2m_refclk1mhz: refclk1mhz {
+ v2m_refclk1mhz: clock-1000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
- v2m_refclk32khz: refclk32khz {
+ v2m_refclk32khz: clock-32768 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
- v2m_fixed_3v3: fixed-regulator-0 {
+ v2m_fixed_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-always-on;
};
- v2m_clk24mhz: clk24mhz {
+ v2m_clk24mhz: clock-24000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
- v2m_refclk1mhz: refclk1mhz {
+ v2m_refclk1mhz: clock-1000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
- v2m_refclk32khz: refclk32khz {
+ v2m_refclk32khz: clock-32768 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
- oscclk0 {
+ clock-controller-0 {
/* MCC static memory clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
clock-output-names = "v2m:oscclk0";
};
- v2m_oscclk1: oscclk1 {
+ v2m_oscclk1: clock-controller-1 {
/* CLCD clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
clock-output-names = "v2m:oscclk1";
};
- v2m_oscclk2: oscclk2 {
+ v2m_oscclk2: clock-controller-2 {
/* IO FPGA peripheral clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
clock-output-names = "v2m:oscclk2";
};
- volt-vio {
+ regulator-vio {
/* Logic level voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
- oscclk0 {
+ clock-controller-0 {
/* CPU PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
clock-output-names = "oscclk0";
};
- oscclk4 {
+ clock-controller-4 {
/* Multiplexed AXI master clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
clock-output-names = "oscclk4";
};
- hdlcd_clk: oscclk5 {
+ hdlcd_clk: clock-controller-5 {
/* HDLCD PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 5>;
clock-output-names = "oscclk5";
};
- smbclk: oscclk6 {
+ smbclk: clock-controller-6 {
/* SMB clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 6>;
clock-output-names = "oscclk6";
};
- sys_pll: oscclk7 {
+ sys_pll: clock-controller-7 {
/* SYS PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 7>;
clock-output-names = "oscclk7";
};
- oscclk8 {
+ clock-controller-8 {
/* DDR2 PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 8>;
clock-output-names = "oscclk8";
};
- volt-cores {
+ regulator-cores {
/* CPU core voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
- oscclk0 {
+ clock-controller-0 {
/* A15 PLL 0 reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
clock-output-names = "oscclk0";
};
- oscclk1 {
+ clock-controller-1 {
/* A15 PLL 1 reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
clock-output-names = "oscclk1";
};
- oscclk2 {
+ clock-controller-2 {
/* A7 PLL 0 reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
clock-output-names = "oscclk2";
};
- oscclk3 {
+ clock-controller-3 {
/* A7 PLL 1 reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 3>;
clock-output-names = "oscclk3";
};
- oscclk4 {
+ clock-controller-4 {
/* External AXI master clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
clock-output-names = "oscclk4";
};
- hdlcd_clk: oscclk5 {
+ hdlcd_clk: clock-controller-5 {
/* HDLCD PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 5>;
clock-output-names = "oscclk5";
};
- smbclk: oscclk6 {
+ smbclk: clock-controller-6 {
/* Static memory controller clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 6>;
clock-output-names = "oscclk6";
};
- oscclk7 {
+ clock-controller-7 {
/* SYS PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 7>;
clock-output-names = "oscclk7";
};
- oscclk8 {
+ clock-controller-8 {
/* DDR2 PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 8>;
clock-output-names = "oscclk8";
};
- volt-a15 {
+ regulator-a15 {
/* A15 CPU core voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
label = "A15 Vcore";
};
- volt-a7 {
+ regulator-a7 {
/* A7 CPU core voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 1>;
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
- cpu_clk: oscclk0 {
+ cpu_clk: clock-controller-0 {
/* CPU and internal AXI reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
clock-output-names = "oscclk0";
};
- axi_clk: oscclk1 {
+ axi_clk: clock-controller-1 {
/* Multiplexed AXI master clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
clock-output-names = "oscclk1";
};
- oscclk2 {
+ clock-controller-2 {
/* DDR2 */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
clock-output-names = "oscclk2";
};
- hdlcd_clk: oscclk3 {
+ hdlcd_clk: clock-controller-3 {
/* HDLCD */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 3>;
clock-output-names = "oscclk3";
};
- oscclk4 {
+ clock-controller-4 {
/* Test chip gate configuration */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
clock-output-names = "oscclk4";
};
- smbclk: oscclk5 {
+ smbclk: clock-controller-5 {
/* SMB clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 5>;
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
- oscclk0: extsaxiclk {
+ oscclk0: clock-controller-0 {
/* ACLK clock to the AXI master port on the test chip */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
clock-output-names = "extsaxiclk";
};
- oscclk1: clcdclk {
+ oscclk1: clock-controller-1 {
/* Reference clock for the CLCD */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
clock-output-names = "clcdclk";
};
- smbclk: oscclk2: tcrefclk {
+ smbclk: oscclk2: clock-controller-2 {
/* Reference clock for the test chip internal PLLs */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
clock-output-names = "tcrefclk";
};
- volt-vd10 {
+ regulator-vd10 {
/* Test Chip internal logic voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
label = "VD10";
};
- volt-vd10-s2 {
+ regulator-vd10-s2 {
/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 1>;
label = "VD10_S2";
};
- volt-vd10-s3 {
+ regulator-vd10-s3 {
/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 2>;
label = "VD10_S3";
};
- volt-vcc1v8 {
+ regulator-vcc1v8 {
/* DDR2 SDRAM and Test Chip DDR2 I/O supply */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 3>;
label = "VCC1V8";
};
- volt-ddr2vtt {
+ regulator-ddr2vtt {
/* DDR2 SDRAM VTT termination voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 4>;
label = "DDR2VTT";
};
- volt-vcc3v3 {
+ regulator-vcc3v3 {
/* Local board supply for miscellaneous logic external to the Test Chip */
arm,vexpress-sysreg,func = <2 5>;
compatible = "arm,vexpress-volt";
reg-io-width = <2>;
};
- vmmc_v3_3d: fixed_v3_3d {
+ vmmc_v3_3d: regulator-vmmc {
compatible = "regulator-fixed";
regulator-name = "vmmc_supply";
regulator-min-microvolt = <3300000>;
cache-sets = <1024>;
};
- refclk100mhz: refclk100mhz {
+ refclk100mhz: clock-100000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "apb_pclk";
};
- smbclk: refclk24mhzx2 {
+ smbclk: clock-48000000 {
/* Reference 24MHz clock x 2 */
compatible = "fixed-clock";
#clock-cells = <0>;
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
- uartclk: uartclk {
+ uartclk: clock-50000000 {
/* UART clock - 50MHz */
compatible = "fixed-clock";
#clock-cells = <0>;
timeout-sec = <30>;
};
- v2m_clk24mhz: clk24mhz {
+ v2m_clk24mhz: clock-24000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
- v2m_refclk1mhz: refclk1mhz {
+ v2m_refclk1mhz: clock-1000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
- v2m_refclk32khz: refclk32khz {
+ v2m_refclk32khz: clock-32768 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
*/
/ {
/* SoC fixed clocks */
- soc_uartclk: refclk7372800hz {
+ soc_uartclk: clock-7372800 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <7372800>;
clock-output-names = "juno:uartclk";
};
- soc_usb48mhz: clk48mhz {
+ soc_usb48mhz: clock-48000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
clock-output-names = "clk48mhz";
};
- soc_smc50mhz: clk50mhz {
+ soc_smc50mhz: clock-50000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "smc_clk";
};
- soc_refclk100mhz: refclk100mhz {
+ soc_refclk100mhz: clock-100000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "apb_pclk";
};
- soc_faxiclk: refclk400mhz {
+ soc_faxiclk: clock-400000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <400000000>;
*/
/ {
- mb_clk24mhz: clk24mhz {
+ mb_clk24mhz: clock-24000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "juno_mb:clk24mhz";
};
- mb_clk25mhz: clk25mhz {
+ mb_clk25mhz: clock-25000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "juno_mb:clk25mhz";
};
- v2m_refclk1mhz: refclk1mhz {
+ v2m_refclk1mhz: clock-1000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "juno_mb:refclk1mhz";
};
- v2m_refclk32khz: refclk32khz {
+ v2m_refclk32khz: clock-32768 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "juno_mb:refclk32khz";
};
- mb_fixed_3v3: mcc-sb-3v3 {
+ mb_fixed_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "MCC_SB_3V3";
regulator-min-microvolt = <3300000>;
* VEMotherBoard.lisa
*/
/ {
- v2m_clk24mhz: clk24mhz {
+ v2m_clk24mhz: clock-24000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
- v2m_refclk1mhz: refclk1mhz {
+ v2m_refclk1mhz: clock-1000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
- v2m_refclk32khz: refclk32khz {
+ v2m_refclk32khz: clock-32768 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "v2m:refclk32khz";
};
- v2m_fixed_3v3: v2m-3v3 {
+ v2m_fixed_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
- v2m_oscclk1: oscclk1 {
+ v2m_oscclk1: clock-controller {
/* CLCD clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
- smbclk: smclk {
+ smbclk: clock-controller {
/* SMC clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
clock-output-names = "smclk";
};
- volt-vio {
+ regulator-vio {
/* VIO to expansion board above */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
regulator-always-on;
};
- volt-12v {
+ regulator-12v {
/* 12V from power connector J6 */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 1>;
projects / thirdparty / linux.git / commitdiff
