RISC-V: Make SSAMOSWAP.W available for rv64

Previously we limited SSAMOSWAP.W only available on RV32, but it should
be available on RV64 as well.

See
https://github.com/riscv/riscv-cfi/blob/main/src/cfi_backward.adoc
https://github.com/riscv/riscv-isa-manual/blob/702a3e6e843235a2a13b918ae6938b04f8974ffc/src/unpriv-cfi.adoc#L789

diff --git a/gas/testsuite/gas/riscv/zicfisslp-64.d b/gas/testsuite/gas/riscv/zicfisslp-64.d
index 0eb1b87ab8d46703a44398c262e997441b6a851c..1dba3a62b27d56b1314cc53e210c810257df1ae1 100644 (file)
--- a/gas/testsuite/gas/riscv/zicfisslp-64.d
+++ b/gas/testsuite/gas/riscv/zicfisslp-64.d
@@ -12,6 +12,14 @@ Disassembly of section .text:
 [      ]+[0-9a-f]+:[   ]+cdc0c073[     ]+sspopchk[     ]+ra
 [      ]+[0-9a-f]+:[   ]+cdc2c073[     ]+sspopchk[     ]+t0
 [      ]+[0-9a-f]+:[   ]+cdc04573[     ]+ssrdp[        ]+a0
+[      ]+[0-9a-f]+:[   ]+48a5252f[     ]+ssamoswap.w[  ]+a0,a0,\(a0\)
+[      ]+[0-9a-f]+:[   ]+48a5252f[     ]+ssamoswap.w[  ]+a0,a0,\(a0\)
+[      ]+[0-9a-f]+:[   ]+4ca5252f[     ]+ssamoswap.w.aq[       ]+a0,a0,\(a0\)
+[      ]+[0-9a-f]+:[   ]+4ca5252f[     ]+ssamoswap.w.aq[       ]+a0,a0,\(a0\)
+[      ]+[0-9a-f]+:[   ]+4aa5252f[     ]+ssamoswap.w.rl[       ]+a0,a0,\(a0\)
+[      ]+[0-9a-f]+:[   ]+4aa5252f[     ]+ssamoswap.w.rl[       ]+a0,a0,\(a0\)
+[      ]+[0-9a-f]+:[   ]+4ea5252f[     ]+ssamoswap.w.aqrl[     ]+a0,a0,\(a0\)
+[      ]+[0-9a-f]+:[   ]+4ea5252f[     ]+ssamoswap.w.aqrl[     ]+a0,a0,\(a0\)
 [      ]+[0-9a-f]+:[   ]+48a5352f[     ]+ssamoswap.d[  ]+a0,a0,\(a0\)
 [      ]+[0-9a-f]+:[   ]+48a5352f[     ]+ssamoswap.d[  ]+a0,a0,\(a0\)
 [      ]+[0-9a-f]+:[   ]+4ca5352f[     ]+ssamoswap.d.aq[       ]+a0,a0,\(a0\)

diff --git a/gas/testsuite/gas/riscv/zicfisslp-64.s b/gas/testsuite/gas/riscv/zicfisslp-64.s
index 1199a430c950b7d37ed8dbbb92cb7649cc9f8e32..21ff0e29689ddc33d45590dd313cbe58a327dea7 100644 (file)
--- a/gas/testsuite/gas/riscv/zicfisslp-64.s
+++ b/gas/testsuite/gas/riscv/zicfisslp-64.s
@@ -6,6 +6,14 @@
        sspopchk x1
        sspopchk x5
        ssrdp a0
+       ssamoswap.w     a0,a0,0(a0)
+       ssamoswap.w     a0,a0,(a0)
+       ssamoswap.w.aq  a0,a0,0(a0)
+       ssamoswap.w.aq  a0,a0,(a0)
+       ssamoswap.w.rl  a0,a0,0(a0)
+       ssamoswap.w.rl  a0,a0,(a0)
+       ssamoswap.w.aqrl        a0,a0,0(a0)
+       ssamoswap.w.aqrl        a0,a0,(a0)
        ssamoswap.d       a0, a0, 0(a0)
        ssamoswap.d       a0, a0, (a0)
        ssamoswap.d.aq    a0, a0, 0(a0)

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index ceb94a563e23a8a2569859fd7d525df34263fba9..9e6c2ae45fb78409cbc2e92f6690b0c750ebc698 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1187,10 +1187,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"c.sspush",          0, INSN_CLASS_ZICFISS_AND_ZCMOP, "d", MATCH_C_SSPUSH, MASK_C_SSPUSH, match_rd_x1x5_opcode, 0 },
 {"c.sspopchk",        0, INSN_CLASS_ZICFISS_AND_ZCMOP, "d", MATCH_C_SSPOPCHK, MASK_C_SSPOPCHK, match_rd_x1x5_opcode, 0 },
 {"ssrdp",             0, INSN_CLASS_ZICFISS,           "d", MATCH_SSRDP, MASK_SSRDP, match_opcode, 0 },
-{"ssamoswap.w",      32, INSN_CLASS_ZICFISS,    "d,t,0(s)", MATCH_SSAMOSWAP_W, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"ssamoswap.w.aq",   32, INSN_CLASS_ZICFISS,    "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_AQ, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"ssamoswap.w.rl",   32, INSN_CLASS_ZICFISS,    "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_RL, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"ssamoswap.w.aqrl", 32, INSN_CLASS_ZICFISS,    "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_AQRL, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"ssamoswap.w",       0, INSN_CLASS_ZICFISS,    "d,t,0(s)", MATCH_SSAMOSWAP_W, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"ssamoswap.w.aq",    0, INSN_CLASS_ZICFISS,    "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_AQ, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"ssamoswap.w.rl",    0, INSN_CLASS_ZICFISS,    "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_RL, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"ssamoswap.w.aqrl",  0, INSN_CLASS_ZICFISS,    "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_AQRL, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
 {"ssamoswap.d",      64, INSN_CLASS_ZICFISS,    "d,t,0(s)", MATCH_SSAMOSWAP_D, MASK_SSAMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
 {"ssamoswap.d.aq",   64, INSN_CLASS_ZICFISS,    "d,t,0(s)", MATCH_SSAMOSWAP_D|MASK_AQ, MASK_SSAMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
 {"ssamoswap.d.rl",   64, INSN_CLASS_ZICFISS,    "d,t,0(s)", MATCH_SSAMOSWAP_D|MASK_RL, MASK_SSAMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },