xilinx: common: Fix CONFIG_XILINX_OF_BOARD_DTB_ADDR handling for ZynqMP

Fix bug introduced by commit listed below. It is for cases where Versal or
ZynqMP don't have DDR mapped. Later SPL was also excluded by
commit a672b9871b57 ("xilinx: common: Do not touch
CONFIG_XILINX_OF_BOARD_DTB_ADDR in SPL").

Fixes: 506009fc1022 ("xilinx: common: Change macro handling in board_fdt_blob_setup()")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lists.denx.de/pipermail/u-boot/2021-February/439592.html
State: waiting

diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index df19aeadd0b2936194ce514f093cde0fe290e996..1a259c5785cec506e4fba98f7829f4f06ac95206 100644 (file)
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -326,7 +326,7 @@ void *board_fdt_blob_setup(void)
 
        if (!IS_ENABLED(CONFIG_SPL_BUILD) &&
            !IS_ENABLED(CONFIG_VERSAL_NO_DDR) &&
-           !IS_ENABLED(CONFIG_VERSAL_NO_DDR)) {
+           !IS_ENABLED(CONFIG_ZYNQMP_NO_DDR)) {
                fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
 
                if (fdt_magic(fdt_blob) == FDT_MAGIC)