#...
[a-f0-9]+ <_intel>:
-\s*[a-f0-9]+:\s*c4 a5 78 f8 b4 f5 00 00 00 10\s+t2rpntlvwz0rs tmm6,\[rbp\+r14\*8\+0x10000000\]
-\s*[a-f0-9]+:\s*c4 c5 78 f8 14 21\s+t2rpntlvwz0rs tmm2,\[r9\+riz\*1\]
-\s*[a-f0-9]+:\s*c4 a5 78 f9 b4 f5 00 00 00 10\s+t2rpntlvwz0rst1 tmm6,\[rbp\+r14\*8\+0x10000000\]
-\s*[a-f0-9]+:\s*c4 c5 78 f9 14 21\s+t2rpntlvwz0rst1 tmm2,\[r9\+riz\*1\]
-\s*[a-f0-9]+:\s*c4 a5 79 f8 b4 f5 00 00 00 10\s+t2rpntlvwz1rs tmm6,\[rbp\+r14\*8\+0x10000000\]
-\s*[a-f0-9]+:\s*c4 c5 79 f8 14 21\s+t2rpntlvwz1rs tmm2,\[r9\+riz\*1\]
-\s*[a-f0-9]+:\s*c4 a5 79 f9 b4 f5 00 00 00 10\s+t2rpntlvwz1rst1 tmm6,\[rbp\+r14\*8\+0x10000000\]
-\s*[a-f0-9]+:\s*c4 c5 79 f9 14 21\s+t2rpntlvwz1rst1 tmm2,\[r9\+riz\*1\]
\s*[a-f0-9]+:\s*c4 a2 7b 4a b4 f5 00 00 00 10\s+tileloaddrs tmm6,\[rbp\+r14\*8\+0x10000000\]
\s*[a-f0-9]+:\s*c4 c2 7b 4a 1c 21\s+tileloaddrs tmm3,\[r9\+riz\*1\]
\s*[a-f0-9]+:\s*c4 a2 79 4a b4 f5 00 00 00 10\s+tileloaddrst1 tmm6,\[rbp\+r14\*8\+0x10000000\]
+++ /dev/null
-.* Assembler messages:
-.*:5: Error: `\(%rip\)' cannot be used here
-.*:6: Error: `\(%rip\)' cannot be used here
-.*:7: Error: `\(%rip\)' cannot be used here
-.*:8: Error: `\(%rip\)' cannot be used here
-.*:9: Warning: operand 2 `%tmm1' implicitly denotes `%tmm0' to `%tmm1' group in `t2rpntlvwz0rs'
-.*:10: Warning: operand 2 `%tmm3' implicitly denotes `%tmm2' to `%tmm3' group in `t2rpntlvwz0rst1'
-.*:11: Warning: operand 2 `%tmm5' implicitly denotes `%tmm4' to `%tmm5' group in `t2rpntlvwz1rs'
-.*:12: Warning: operand 2 `%tmm7' implicitly denotes `%tmm6' to `%tmm7' group in `t2rpntlvwz1rst1'
-.*:16: Error: `t2rpntlvwz0rs' is not supported on `x86_64.noamx_transpose'
-.*:17: Error: `t2rpntlvwz0rst1' is not supported on `x86_64.noamx_transpose'
-.*:18: Error: `t2rpntlvwz1rs' is not supported on `x86_64.noamx_transpose'
-.*:19: Error: `t2rpntlvwz1rst1' is not supported on `x86_64.noamx_transpose'
+++ /dev/null
-# Check Invalid 64bit AMX-MOVRS instructions
-
- .text
-_start:
- t2rpntlvwz0rs (%rip), %tmm2
- t2rpntlvwz0rst1 (%rip), %tmm2
- t2rpntlvwz1rs (%rip), %tmm2
- t2rpntlvwz1rst1 (%rip), %tmm2
- t2rpntlvwz0rs (%r9), %tmm1
- t2rpntlvwz0rst1 (%r9), %tmm3
- t2rpntlvwz1rs (%r9), %tmm5
- t2rpntlvwz1rst1 (%r9), %tmm7
-
- .arch .noamx_transpose
-_transpose:
- t2rpntlvwz0rs (%r9), %tmm2
- t2rpntlvwz0rst1 (%r9), %tmm2
- t2rpntlvwz1rs (%r9), %tmm2
- t2rpntlvwz1rst1 (%r9), %tmm2
Disassembly of section \.text:
0+ <_start>:
-\s*[a-f0-9]+:\s*c4 a5 78 f8 b4 f5 00 00 00 10\s+t2rpntlvwz0rs 0x10000000\(%rbp,%r14,8\),%tmm6
-\s*[a-f0-9]+:\s*c4 c5 78 f8 14 21\s+t2rpntlvwz0rs \(%r9,%riz,1\),%tmm2
-\s*[a-f0-9]+:\s*c4 a5 78 f9 b4 f5 00 00 00 10\s+t2rpntlvwz0rst1 0x10000000\(%rbp,%r14,8\),%tmm6
-\s*[a-f0-9]+:\s*c4 c5 78 f9 14 21\s+t2rpntlvwz0rst1 \(%r9,%riz,1\),%tmm2
-\s*[a-f0-9]+:\s*c4 a5 79 f8 b4 f5 00 00 00 10\s+t2rpntlvwz1rs 0x10000000\(%rbp,%r14,8\),%tmm6
-\s*[a-f0-9]+:\s*c4 c5 79 f8 14 21\s+t2rpntlvwz1rs \(%r9,%riz,1\),%tmm2
-\s*[a-f0-9]+:\s*c4 a5 79 f9 b4 f5 00 00 00 10\s+t2rpntlvwz1rst1 0x10000000\(%rbp,%r14,8\),%tmm6
-\s*[a-f0-9]+:\s*c4 c5 79 f9 14 21\s+t2rpntlvwz1rst1 \(%r9,%riz,1\),%tmm2
\s*[a-f0-9]+:\s*c4 a2 7b 4a b4 f5 00 00 00 10\s+tileloaddrs 0x10000000\(%rbp,%r14,8\),%tmm6
\s*[a-f0-9]+:\s*c4 c2 7b 4a 1c 21\s+tileloaddrs \(%r9,%riz,1\),%tmm3
\s*[a-f0-9]+:\s*c4 a2 79 4a b4 f5 00 00 00 10\s+tileloaddrst1 0x10000000\(%rbp,%r14,8\),%tmm6
.text
_start:
- t2rpntlvwz0rs 0x10000000(%rbp, %r14, 8), %tmm6
- t2rpntlvwz0rs (%r9), %tmm2
- t2rpntlvwz0rst1 0x10000000(%rbp, %r14, 8), %tmm6
- t2rpntlvwz0rst1 (%r9), %tmm2
- t2rpntlvwz1rs 0x10000000(%rbp, %r14, 8), %tmm6
- t2rpntlvwz1rs (%r9), %tmm2
- t2rpntlvwz1rst1 0x10000000(%rbp, %r14, 8), %tmm6
- t2rpntlvwz1rst1 (%r9), %tmm2
tileloaddrs 0x10000000(%rbp, %r14, 8), %tmm6
tileloaddrs (%r9), %tmm3
tileloaddrst1 0x10000000(%rbp, %r14, 8), %tmm6
_intel:
.intel_syntax noprefix
- t2rpntlvwz0rs tmm6, [rbp+r14*8+0x10000000]
- t2rpntlvwz0rs tmm2, [r9]
- t2rpntlvwz0rst1 tmm6, [rbp+r14*8+0x10000000]
- t2rpntlvwz0rst1 tmm2, [r9]
- t2rpntlvwz1rs tmm6, [rbp+r14*8+0x10000000]
- t2rpntlvwz1rs tmm2, [r9]
- t2rpntlvwz1rst1 tmm6, [rbp+r14*8+0x10000000]
- t2rpntlvwz1rst1 tmm2, [r9]
tileloaddrs tmm6, [rbp+r14*8+0x10000000]
tileloaddrs tmm3, [r9]
tileloaddrst1 tmm6, [rbp+r14*8+0x10000000]
\s*[a-f0-9]+:\s*c4 e2 71 48 d1\s+tmmultf32ps %tmm1/\(bad\),%tmm1/\(bad\),%tmm2
\s*[a-f0-9]+:\s*c4 e2 69 48 c9\s+tmmultf32ps %tmm2,%tmm1/\(bad\),%tmm1/\(bad\)
\s*[a-f0-9]+:\s*c4 e2 71 48 ca\s+tmmultf32ps %tmm1/\(bad\),%tmm2,%tmm1\/\(bad\)
-\s*[a-f0-9]+:\s*c4 e2 70 48 d1\s+ttmmultf32ps %tmm1/\(bad\),%tmm1/\(bad\),%tmm2
-\s*[a-f0-9]+:\s*c4 e2 68 48 c9\s+ttmmultf32ps %tmm2,%tmm1/\(bad\),%tmm1/\(bad\)
-\s*[a-f0-9]+:\s*c4 e2 70 48 ca\s+ttmmultf32ps %tmm1/\(bad\),%tmm2,%tmm1/\(bad\)
#pass
# tmmultf32ps %tmm2, %tmm1, %tmm1 all tmm registers should be distinct
.insn VEX.128.66.0F38.W0 0x48, %tmm2, %tmm1, %tmm1
-
- # ttmmultf32ps %tmm1, %tmm1, %tmm2 all tmm registers should be distinct
- .insn VEX.128.NP.0F38.W0 0x48, %tmm1, %tmm1, %tmm2
-
- # ttmmultf32ps %tmm1, %tmm2, %tmm1 all tmm registers should be distinct
- .insn VEX.128.NP.0F38.W0 0x48, %tmm1, %tmm2, %tmm1
-
- # ttmmultf32ps %tmm2, %tmm1, %tmm1 all tmm registers should be distinct
- .insn VEX.128.NP.0F38.W0 0x48, %tmm2, %tmm1, %tmm1
[a-f0-9]+ <_intel>:
\s*[a-f0-9]+:\s*c4 e2 59 48 f5\s+tmmultf32ps tmm6,tmm5,tmm4
\s*[a-f0-9]+:\s*c4 e2 71 48 da\s+tmmultf32ps tmm3,tmm2,tmm1
-\s*[a-f0-9]+:\s*c4 e2 58 48 f5\s+ttmmultf32ps tmm6,tmm5,tmm4
-\s*[a-f0-9]+:\s*c4 e2 70 48 da\s+ttmmultf32ps tmm3,tmm2,tmm1
#pass
.*:5: Error: all tmm registers must be distinct for `tmmultf32ps'
.*:6: Error: all tmm registers must be distinct for `tmmultf32ps'
.*:7: Error: all tmm registers must be distinct for `tmmultf32ps'
-.*:8: Error: all tmm registers must be distinct for `ttmmultf32ps'
-.*:9: Error: all tmm registers must be distinct for `ttmmultf32ps'
-.*:10: Error: all tmm registers must be distinct for `ttmmultf32ps'
tmmultf32ps %tmm1, %tmm1, %tmm2
tmmultf32ps %tmm1, %tmm2, %tmm1
tmmultf32ps %tmm2, %tmm1, %tmm1
- ttmmultf32ps %tmm1, %tmm1, %tmm2
- ttmmultf32ps %tmm1, %tmm2, %tmm1
- ttmmultf32ps %tmm2, %tmm1, %tmm1
0+ <_start>:
\s*[a-f0-9]+:\s*c4 e2 59 48 f5\s+tmmultf32ps %tmm4,%tmm5,%tmm6
\s*[a-f0-9]+:\s*c4 e2 71 48 da\s+tmmultf32ps %tmm1,%tmm2,%tmm3
-\s*[a-f0-9]+:\s*c4 e2 58 48 f5\s+ttmmultf32ps %tmm4,%tmm5,%tmm6
-\s*[a-f0-9]+:\s*c4 e2 70 48 da\s+ttmmultf32ps %tmm1,%tmm2,%tmm3
#pass
_start:
tmmultf32ps %tmm4, %tmm5, %tmm6
tmmultf32ps %tmm1, %tmm2, %tmm3
- ttmmultf32ps %tmm4, %tmm5, %tmm6
- ttmmultf32ps %tmm1, %tmm2, %tmm3
_intel:
.intel_syntax noprefix
tmmultf32ps tmm6, tmm5, tmm4
tmmultf32ps tmm3, tmm2, tmm1
- ttmmultf32ps tmm6, tmm5, tmm4
- ttmmultf32ps tmm3, tmm2, tmm1
--- /dev/null
+#objdump: -dw -Mintel
+#name: x86_64 AMX_TRANSPOSE APX_F EVEX-Promoted insns (Intel disassembly)
+#source: x86-64-amx-transpose-apx.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+#...
+[a-f0-9]+ <_intel>:
+[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0 tmm6,\[r31\+rax\*8\+0x123\]
+[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs tmm6,\[r31\+rax\*8\+0x123\]
+[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1 tmm6,\[r31\+rax\*8\+0x123\]
+[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1 tmm6,\[r31\+rax\*8\+0x123\]
+[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1 tmm6,\[r31\+rax\*8\+0x123\]
+[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs tmm6,\[r31\+rax\*8\+0x123\]
+[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1 tmm6,\[r31\+rax\*8\+0x123\]
+[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1 tmm6,\[r31\+rax\*8\+0x123\]
+#pass
--- /dev/null
+#as: -mevexwig=1
+#objdump: -dw
+#name: x86_64 AMX_TRANSPOSE APX_F EVEX-Promoted insns w/ -mevexwig=1
+#source: x86-64-amx-transpose-apx.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6
+[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6
+[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
+[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6
+[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6
+[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6
+[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
+[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6
+#pass
--- /dev/null
+#objdump: -dw
+#name: x86_64 APX_F EVEX-Promoted insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6
+[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6
+[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
+[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6
+[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6
+[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6
+[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
+[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6
+#pass
--- /dev/null
+# Check 64bit AMX-TRANSPOSE APX_F EVEX-Promoted instructions.
+
+ .arch .amx_transpose
+ .text
+_start:
+ t2rpntlvwz0 0x123(%r31,%rax,8),%tmm6
+ t2rpntlvwz0rs 0x123(%r31,%rax,8),%tmm6
+ t2rpntlvwz0rst1 0x123(%r31,%rax,8),%tmm6
+ t2rpntlvwz0t1 0x123(%r31,%rax,8),%tmm6
+ t2rpntlvwz1 0x123(%r31,%rax,8),%tmm6
+ t2rpntlvwz1rs 0x123(%r31,%rax,8),%tmm6
+ t2rpntlvwz1rst1 0x123(%r31,%rax,8),%tmm6
+ t2rpntlvwz1t1 0x123(%r31,%rax,8),%tmm6
+
+_intel:
+ t2rpntlvwz0 tmm6,[r31+rax*8+0x123]
+ t2rpntlvwz0rs tmm6,[r31+rax*8+0x123]
+ t2rpntlvwz0rst1 tmm6,[r31+rax*8+0x123]
+ t2rpntlvwz0t1 tmm6,[r31+rax*8+0x123]
+ t2rpntlvwz1 tmm6,[r31+rax*8+0x123]
+ t2rpntlvwz1rs tmm6,[r31+rax*8+0x123]
+ t2rpntlvwz1rst1 tmm6,[r31+rax*8+0x123]
+ t2rpntlvwz1t1 tmm6,[r31+rax*8+0x123]
\s*[a-f0-9]+:\s*c4 e2 73 6c d1\s+ttdpfp16ps %tmm1/\(bad\),%tmm1/\(bad\),%tmm2
\s*[a-f0-9]+:\s*c4 e2 6b 6c c9\s+ttdpfp16ps %tmm2,%tmm1/\(bad\),%tmm1/\(bad\)
\s*[a-f0-9]+:\s*c4 e2 73 6c ca\s+ttdpfp16ps %tmm1/\(bad\),%tmm2,%tmm1/\(bad\)
+\s*[a-f0-9]+:\s*c4 e2 70 48 d1\s+ttmmultf32ps %tmm1/\(bad\),%tmm1/\(bad\),%tmm2
+\s*[a-f0-9]+:\s*c4 e2 68 48 c9\s+ttmmultf32ps %tmm2,%tmm1/\(bad\),%tmm1/\(bad\)
+\s*[a-f0-9]+:\s*c4 e2 70 48 ca\s+ttmmultf32ps %tmm1/\(bad\),%tmm2,%tmm1/\(bad\)
#pass
# ttdpfp16ps %tmm2, %tmm1, %tmm1 all tmm registers should be distinct
.insn VEX.128.f2.0F38.W0 0x6c, %tmm2, %tmm1, %tmm1
+
+ # ttmmultf32ps %tmm1, %tmm1, %tmm2 all tmm registers should be distinct
+ .insn VEX.128.NP.0F38.W0 0x48, %tmm1, %tmm1, %tmm2
+
+ # ttmmultf32ps %tmm1, %tmm2, %tmm1 all tmm registers should be distinct
+ .insn VEX.128.NP.0F38.W0 0x48, %tmm1, %tmm2, %tmm1
+
+ # ttmmultf32ps %tmm2, %tmm1, %tmm1 all tmm registers should be distinct
+ .insn VEX.128.NP.0F38.W0 0x48, %tmm2, %tmm1, %tmm1
\s*[a-f0-9]+:\s*c4 c2 79 6e 14 21\s+t2rpntlvwz1 tmm2,\[r9\+riz\*1\]
\s*[a-f0-9]+:\s*c4 a2 79 6f b4 f5 00 00 00 10\s+t2rpntlvwz1t1 tmm6,\[rbp\+r14\*8\+0x10000000\]
\s*[a-f0-9]+:\s*c4 c2 79 6f 14 21\s+t2rpntlvwz1t1 tmm2,\[r9\+riz\*1\]
+\s*[a-f0-9]+:\s*c4 a5 78 f8 b4 f5 00 00 00 10\s+t2rpntlvwz0rs tmm6,\[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c5 78 f8 14 21\s+t2rpntlvwz0rs tmm2,\[r9\+riz\*1\]
+\s*[a-f0-9]+:\s*c4 a5 78 f9 b4 f5 00 00 00 10\s+t2rpntlvwz0rst1 tmm6,\[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c5 78 f9 14 21\s+t2rpntlvwz0rst1 tmm2,\[r9\+riz\*1\]
+\s*[a-f0-9]+:\s*c4 a5 79 f8 b4 f5 00 00 00 10\s+t2rpntlvwz1rs tmm6,\[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c5 79 f8 14 21\s+t2rpntlvwz1rs tmm2,\[r9\+riz\*1\]
+\s*[a-f0-9]+:\s*c4 a5 79 f9 b4 f5 00 00 00 10\s+t2rpntlvwz1rst1 tmm6,\[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c5 79 f9 14 21\s+t2rpntlvwz1rst1 tmm2,\[r9\+riz\*1\]
\s*[a-f0-9]+:\s*c4 e2 58 6b f5\s+tconjtcmmimfp16ps tmm6,tmm5,tmm4
\s*[a-f0-9]+:\s*c4 e2 70 6b da\s+tconjtcmmimfp16ps tmm3,tmm2,tmm1
\s*[a-f0-9]+:\s*c4 e2 79 6b f5\s+tconjtfp16 tmm6,tmm5
\s*[a-f0-9]+:\s*c4 e2 73 6b da\s+ttcmmimfp16ps tmm3,tmm2,tmm1
\s*[a-f0-9]+:\s*c4 e2 5a 6b f5\s+ttcmmrlfp16ps tmm6,tmm5,tmm4
\s*[a-f0-9]+:\s*c4 e2 72 6b da\s+ttcmmrlfp16ps tmm3,tmm2,tmm1
+\s*[a-f0-9]+:\s*c4 e2 58 48 f5\s+ttmmultf32ps tmm6,tmm5,tmm4
+\s*[a-f0-9]+:\s*c4 e2 70 48 da\s+ttmmultf32ps tmm3,tmm2,tmm1
#pass
.* Assembler messages:
-.*:5: Error: all tmm registers must be distinct for `ttdpbf16ps'
-.*:6: Error: all tmm registers must be distinct for `ttdpbf16ps'
-.*:7: Error: all tmm registers must be distinct for `ttdpbf16ps'
-.*:8: Error: all tmm registers must be distinct for `ttdpfp16ps'
-.*:9: Error: all tmm registers must be distinct for `ttdpfp16ps'
-.*:10: Error: all tmm registers must be distinct for `ttdpfp16ps'
-.*:11: Error: `\(%rip\)' cannot be used here
-.*:12: Error: `\(%rip\)' cannot be used here
-.*:13: Error: `\(%rip\)' cannot be used here
-.*:14: Error: `\(%rip\)' cannot be used here
-.*:15: Warning: operand 2 `%tmm1' implicitly denotes `%tmm0' to `%tmm1' group in `t2rpntlvwz0'
-.*:16: Warning: operand 2 `%tmm3' implicitly denotes `%tmm2' to `%tmm3' group in `t2rpntlvwz0t1'
-.*:17: Warning: operand 2 `%tmm5' implicitly denotes `%tmm4' to `%tmm5' group in `t2rpntlvwz1'
-.*:18: Warning: operand 2 `%tmm7' implicitly denotes `%tmm6' to `%tmm7' group in `t2rpntlvwz1t1'
+.*:5: Error: `t2rpntlvwz0rs' is not supported on `x86_64'
+.*:6: Error: `t2rpntlvwz0rst1' is not supported on `x86_64'
+.*:7: Error: `t2rpntlvwz1rs' is not supported on `x86_64'
+.*:8: Error: `t2rpntlvwz1rst1' is not supported on `x86_64'
+.*:9: Error: `ttmmultf32ps' is not supported on `x86_64'
+.*:13: Error: all tmm registers must be distinct for `ttdpbf16ps'
+.*:14: Error: all tmm registers must be distinct for `ttdpbf16ps'
+.*:15: Error: all tmm registers must be distinct for `ttdpbf16ps'
+.*:16: Error: all tmm registers must be distinct for `ttdpfp16ps'
+.*:17: Error: all tmm registers must be distinct for `ttdpfp16ps'
+.*:18: Error: all tmm registers must be distinct for `ttdpfp16ps'
+.*:19: Error: all tmm registers must be distinct for `ttmmultf32ps'
+.*:20: Error: all tmm registers must be distinct for `ttmmultf32ps'
+.*:21: Error: all tmm registers must be distinct for `ttmmultf32ps'
+.*:22: Error: `\(%rip\)' cannot be used here
+.*:23: Error: `\(%rip\)' cannot be used here
+.*:24: Error: `\(%rip\)' cannot be used here
+.*:25: Error: `\(%rip\)' cannot be used here
+.*:26: Error: `\(%rip\)' cannot be used here
+.*:27: Error: `\(%rip\)' cannot be used here
+.*:28: Error: `\(%rip\)' cannot be used here
+.*:29: Error: `\(%rip\)' cannot be used here
+.*:30: Warning: operand 2 `%tmm1' implicitly denotes `%tmm0' to `%tmm1' group in `t2rpntlvwz0'
+.*:31: Warning: operand 2 `%tmm3' implicitly denotes `%tmm2' to `%tmm3' group in `t2rpntlvwz0t1'
+.*:32: Warning: operand 2 `%tmm5' implicitly denotes `%tmm4' to `%tmm5' group in `t2rpntlvwz1'
+.*:33: Warning: operand 2 `%tmm7' implicitly denotes `%tmm6' to `%tmm7' group in `t2rpntlvwz1t1'
+.*:34: Warning: operand 2 `%tmm1' implicitly denotes `%tmm0' to `%tmm1' group in `t2rpntlvwz0rs'
+.*:35: Warning: operand 2 `%tmm3' implicitly denotes `%tmm2' to `%tmm3' group in `t2rpntlvwz0rst1'
+.*:36: Warning: operand 2 `%tmm5' implicitly denotes `%tmm4' to `%tmm5' group in `t2rpntlvwz1rs'
+.*:37: Warning: operand 2 `%tmm7' implicitly denotes `%tmm6' to `%tmm7' group in `t2rpntlvwz1rst1'
.text
_start:
+ t2rpntlvwz0rs (%r9), %tmm2
+ t2rpntlvwz0rst1 (%r9), %tmm2
+ t2rpntlvwz1rs (%r9), %tmm2
+ t2rpntlvwz1rst1 (%r9), %tmm2
+ ttmmultf32ps %tmm1, %tmm2, %tmm3
+
+ .arch .amx_transpose
+_transpose:
ttdpbf16ps %tmm1, %tmm1, %tmm2
ttdpbf16ps %tmm1, %tmm2, %tmm1
ttdpbf16ps %tmm2, %tmm1, %tmm1
ttdpfp16ps %tmm1, %tmm1, %tmm2
ttdpfp16ps %tmm1, %tmm2, %tmm1
ttdpfp16ps %tmm2, %tmm1, %tmm1
+ ttmmultf32ps %tmm1, %tmm1, %tmm2
+ ttmmultf32ps %tmm1, %tmm2, %tmm1
+ ttmmultf32ps %tmm2, %tmm1, %tmm1
t2rpntlvwz0 (%rip), %tmm2
t2rpntlvwz0t1 (%rip), %tmm2
t2rpntlvwz1 (%rip), %tmm2
t2rpntlvwz1t1 (%rip), %tmm2
+ t2rpntlvwz0rs (%rip), %tmm2
+ t2rpntlvwz0rst1 (%rip), %tmm2
+ t2rpntlvwz1rs (%rip), %tmm2
+ t2rpntlvwz1rst1 (%rip), %tmm2
t2rpntlvwz0 (%r9), %tmm1
t2rpntlvwz0t1 (%r9), %tmm3
t2rpntlvwz1 (%r9), %tmm5
t2rpntlvwz1t1 (%r9), %tmm7
+ t2rpntlvwz0rs (%r9), %tmm1
+ t2rpntlvwz0rst1 (%r9), %tmm3
+ t2rpntlvwz1rs (%r9), %tmm5
+ t2rpntlvwz1rst1 (%r9), %tmm7
\s*[a-f0-9]+:\s*c4 c2 79 6e 14 21\s+t2rpntlvwz1 \(%r9,%riz,1\),%tmm2
\s*[a-f0-9]+:\s*c4 a2 79 6f b4 f5 00 00 00 10\s+t2rpntlvwz1t1 0x10000000\(%rbp,%r14,8\),%tmm6
\s*[a-f0-9]+:\s*c4 c2 79 6f 14 21\s+t2rpntlvwz1t1 \(%r9,%riz,1\),%tmm2
+\s*[a-f0-9]+:\s*c4 a5 78 f8 b4 f5 00 00 00 10\s+t2rpntlvwz0rs 0x10000000\(%rbp,%r14,8\),%tmm6
+\s*[a-f0-9]+:\s*c4 c5 78 f8 14 21\s+t2rpntlvwz0rs \(%r9,%riz,1\),%tmm2
+\s*[a-f0-9]+:\s*c4 a5 78 f9 b4 f5 00 00 00 10\s+t2rpntlvwz0rst1 0x10000000\(%rbp,%r14,8\),%tmm6
+\s*[a-f0-9]+:\s*c4 c5 78 f9 14 21\s+t2rpntlvwz0rst1 \(%r9,%riz,1\),%tmm2
+\s*[a-f0-9]+:\s*c4 a5 79 f8 b4 f5 00 00 00 10\s+t2rpntlvwz1rs 0x10000000\(%rbp,%r14,8\),%tmm6
+\s*[a-f0-9]+:\s*c4 c5 79 f8 14 21\s+t2rpntlvwz1rs \(%r9,%riz,1\),%tmm2
+\s*[a-f0-9]+:\s*c4 a5 79 f9 b4 f5 00 00 00 10\s+t2rpntlvwz1rst1 0x10000000\(%rbp,%r14,8\),%tmm6
+\s*[a-f0-9]+:\s*c4 c5 79 f9 14 21\s+t2rpntlvwz1rst1 \(%r9,%riz,1\),%tmm2
\s*[a-f0-9]+:\s*c4 e2 58 6b f5\s+tconjtcmmimfp16ps %tmm4,%tmm5,%tmm6
\s*[a-f0-9]+:\s*c4 e2 70 6b da\s+tconjtcmmimfp16ps %tmm1,%tmm2,%tmm3
\s*[a-f0-9]+:\s*c4 e2 79 6b f5\s+tconjtfp16 %tmm5,%tmm6
\s*[a-f0-9]+:\s*c4 e2 73 6b da\s+ttcmmimfp16ps %tmm1,%tmm2,%tmm3
\s*[a-f0-9]+:\s*c4 e2 5a 6b f5\s+ttcmmrlfp16ps %tmm4,%tmm5,%tmm6
\s*[a-f0-9]+:\s*c4 e2 72 6b da\s+ttcmmrlfp16ps %tmm1,%tmm2,%tmm3
+\s*[a-f0-9]+:\s*c4 e2 58 48 f5\s+ttmmultf32ps %tmm4,%tmm5,%tmm6
+\s*[a-f0-9]+:\s*c4 e2 70 48 da\s+ttmmultf32ps %tmm1,%tmm2,%tmm3
#pass
# Check 64bit AMX-TRANSPOSE instructions
+ .arch .amx_transpose
.text
_start:
ttdpbf16ps %tmm4, %tmm5, %tmm6
t2rpntlvwz1 (%r9), %tmm2
t2rpntlvwz1t1 0x10000000(%rbp, %r14, 8), %tmm6
t2rpntlvwz1t1 (%r9), %tmm2
+ t2rpntlvwz0rs 0x10000000(%rbp, %r14, 8), %tmm6
+ t2rpntlvwz0rs (%r9), %tmm2
+ t2rpntlvwz0rst1 0x10000000(%rbp, %r14, 8), %tmm6
+ t2rpntlvwz0rst1 (%r9), %tmm2
+ t2rpntlvwz1rs 0x10000000(%rbp, %r14, 8), %tmm6
+ t2rpntlvwz1rs (%r9), %tmm2
+ t2rpntlvwz1rst1 0x10000000(%rbp, %r14, 8), %tmm6
+ t2rpntlvwz1rst1 (%r9), %tmm2
tconjtcmmimfp16ps %tmm4, %tmm5, %tmm6
tconjtcmmimfp16ps %tmm1, %tmm2, %tmm3
tconjtfp16 %tmm5, %tmm6
ttcmmimfp16ps %tmm1, %tmm2, %tmm3
ttcmmrlfp16ps %tmm4, %tmm5, %tmm6
ttcmmrlfp16ps %tmm1, %tmm2, %tmm3
+ ttmmultf32ps %tmm4, %tmm5, %tmm6
+ ttmmultf32ps %tmm1, %tmm2, %tmm3
_intel:
.intel_syntax noprefix
t2rpntlvwz1 tmm2, [r9]
t2rpntlvwz1t1 tmm6, [rbp+r14*8+0x10000000]
t2rpntlvwz1t1 tmm2, [r9]
+ t2rpntlvwz0rs tmm6, [rbp+r14*8+0x10000000]
+ t2rpntlvwz0rs tmm2, [r9]
+ t2rpntlvwz0rst1 tmm6, [rbp+r14*8+0x10000000]
+ t2rpntlvwz0rst1 tmm2, [r9]
+ t2rpntlvwz1rs tmm6, [rbp+r14*8+0x10000000]
+ t2rpntlvwz1rs tmm2, [r9]
+ t2rpntlvwz1rst1 tmm6, [rbp+r14*8+0x10000000]
+ t2rpntlvwz1rst1 tmm2, [r9]
tconjtcmmimfp16ps tmm6, tmm5, tmm4
tconjtcmmimfp16ps tmm3, tmm2, tmm1
tconjtfp16 tmm6, tmm5
ttcmmimfp16ps tmm3, tmm2, tmm1
ttcmmrlfp16ps tmm6, tmm5, tmm4
ttcmmrlfp16ps tmm3, tmm2, tmm1
+ ttmmultf32ps tmm6, tmm5, tmm4
+ ttmmultf32ps tmm3, tmm2, tmm1
[ ]*[a-f0-9]+:[ ]*62 52 87 00 f7 df[ ]+shrx[ ]+r11,r15,r31
[ ]*[a-f0-9]+:[ ]*62 5a 87 00 f7 bc 87 23 01 00 00[ ]+shrx[ ]+r15,QWORD PTR \[r31\+rax\*4\+0x123\],r31
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+\[r31\+rax\*4\+0x123\]
-[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0 tmm6,\[r31\+rax\*8\+0x123\]
-[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs tmm6,\[r31\+rax\*8\+0x123\]
-[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1 tmm6,\[r31\+rax\*8\+0x123\]
-[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1 tmm6,\[r31\+rax\*8\+0x123\]
-[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1 tmm6,\[r31\+rax\*8\+0x123\]
-[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs tmm6,\[r31\+rax\*8\+0x123\]
-[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1 tmm6,\[r31\+rax\*8\+0x123\]
-[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1 tmm6,\[r31\+rax\*8\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd tmm6,\[r31\+rax\*4\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+tmm6,\[rbp\+r31\*8\+0x10000000\]
[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+tmm3,\[r16\+riz\*1\]
[ ]*[a-f0-9]+:[ ]*62 52 87 00 f7 df[ ]+shrx[ ]+r11,r15,r31
[ ]*[a-f0-9]+:[ ]*62 5a 87 00 f7 bc 87 23 01 00 00[ ]+shrx[ ]+r15,QWORD PTR \[r31\+rax\*4\+0x123\],r31
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+\[r31\+rax\*4\+0x123\]
-[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0 tmm6,\[r31\+rax\*8\+0x123\]
-[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs tmm6,\[r31\+rax\*8\+0x123\]
-[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1 tmm6,\[r31\+rax\*8\+0x123\]
-[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1 tmm6,\[r31\+rax\*8\+0x123\]
-[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1 tmm6,\[r31\+rax\*8\+0x123\]
-[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs tmm6,\[r31\+rax\*8\+0x123\]
-[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1 tmm6,\[r31\+rax\*8\+0x123\]
-[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1 tmm6,\[r31\+rax\*8\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd tmm6,\[r31\+rax\*4\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+tmm6,\[rbp\+r31\*8\+0x10000000\]
[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+tmm3,\[r16\+riz\*1\]
[ ]*[a-f0-9]+:[ ]*62 52 87 00 f7 df[ ]+shrx[ ]+%r31,%r15,%r11
[ ]*[a-f0-9]+:[ ]*62 5a 87 00 f7 bc 87 23 01 00 00[ ]+shrx[ ]+%r31,0x123\(%r31,%rax,4\),%r15
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6
[ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd[ ]+0x123\(%r31,%rax,4\),%tmm6
[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+0x10000000\(%rbp,%r31,8\),%tmm6
[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+\(%r16,%riz,1\),%tmm3
[ ]*[a-f0-9]+:[ ]*62 52 87 00 f7 df[ ]+shrx[ ]+%r31,%r15,%r11
[ ]*[a-f0-9]+:[ ]*62 5a 87 00 f7 bc 87 23 01 00 00[ ]+shrx[ ]+%r31,0x123\(%r31,%rax,4\),%r15
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6
[ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd[ ]+0x123\(%r31,%rax,4\),%tmm6
[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+0x10000000\(%rbp,%r31,8\),%tmm6
[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+\(%r16,%riz,1\),%tmm3
[ ]*[a-f0-9]+:[ ]*62 52 87 00 f7 df[ ]+shrx[ ]+%r31,%r15,%r11
[ ]*[a-f0-9]+:[ ]*62 5a 87 00 f7 bc 87 23 01 00 00[ ]+shrx[ ]+%r31,0x123\(%r31,%rax,4\),%r15
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6
[ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd[ ]+0x123\(%r31,%rax,4\),%tmm6
[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+0x10000000\(%rbp,%r31,8\),%tmm6
[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+\(%r16,%riz,1\),%tmm3
[ ]*[a-f0-9]+:[ ]*62 52 87 00 f7 df[ ]+shrx[ ]+%r31,%r15,%r11
[ ]*[a-f0-9]+:[ ]*62 5a 87 00 f7 bc 87 23 01 00 00[ ]+shrx[ ]+%r31,0x123\(%r31,%rax,4\),%r15
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
-[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6
[ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd[ ]+0x123\(%r31,%rax,4\),%tmm6
[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+0x10000000\(%rbp,%r31,8\),%tmm6
[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+\(%r16,%riz,1\),%tmm3
shrx %r31,%r15,%r11
shrx %r31,0x123(%r31,%rax,4),%r15
sttilecfg 0x123(%r31,%rax,4)
- t2rpntlvwz0 0x123(%r31,%rax,8),%tmm6
- t2rpntlvwz0rs 0x123(%r31,%rax,8),%tmm6
- t2rpntlvwz0rst1 0x123(%r31,%rax,8),%tmm6
- t2rpntlvwz0t1 0x123(%r31,%rax,8),%tmm6
- t2rpntlvwz1 0x123(%r31,%rax,8),%tmm6
- t2rpntlvwz1rs 0x123(%r31,%rax,8),%tmm6
- t2rpntlvwz1rst1 0x123(%r31,%rax,8),%tmm6
- t2rpntlvwz1t1 0x123(%r31,%rax,8),%tmm6
tileloadd 0x123(%r31,%rax,4),%tmm6
tileloaddrs 0x10000000(%rbp, %r31, 8), %tmm6
tileloaddrs (%r16), %tmm3
shrx r11,r15,r31
shrx r15,QWORD PTR [r31+rax*4+0x123],r31
sttilecfg [r31+rax*4+0x123]
- t2rpntlvwz0 tmm6,[r31+rax*8+0x123]
- t2rpntlvwz0rs tmm6,[r31+rax*8+0x123]
- t2rpntlvwz0rst1 tmm6,[r31+rax*8+0x123]
- t2rpntlvwz0t1 tmm6,[r31+rax*8+0x123]
- t2rpntlvwz1 tmm6,[r31+rax*8+0x123]
- t2rpntlvwz1rs tmm6,[r31+rax*8+0x123]
- t2rpntlvwz1rst1 tmm6,[r31+rax*8+0x123]
- t2rpntlvwz1t1 tmm6,[r31+rax*8+0x123]
tileloadd tmm6,[r31+rax*4+0x123]
tileloaddrs tmm6, [rbp+r31*8+0x10000000]
tileloaddrs tmm3, [r16]
run_dump_test "x86-64-amx-fp8-bad"
run_dump_test "x86-64-amx-movrs"
run_dump_test "x86-64-amx-movrs-intel"
-run_list_test "x86-64-amx-movrs-inval"
run_dump_test "x86-64-amx-avx512"
run_dump_test "x86-64-amx-avx512-intel"
run_dump_test "x86-64-movrs"
static const dependency isa_dependencies[] =
{
{ "UNKNOWN",
- "~(IAMCU|MPX)" },
+ "~(IAMCU|MPX|AMX_TRANSPOSE)" },
{ "GENERIC32",
"386" },
{ "GENERIC64",
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 } }
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0 } }
#define CPU_GENERIC32_FLAGS \
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
projects / thirdparty / binutils-gdb.git / commitdiff
