sim: riscv: fix -Wimplicit-fallthrough warnings

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index afdfcf506566973f1f27d63ba6ed895f6226d48f..4d2053453950d3296e43d8f589fcefb23f798615 100644 (file)
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -126,6 +126,7 @@ store_csr (SIM_CPU *cpu, const char *name, int csr, unsigned_word *reg,
     case CSR_INSTRETH:
     case CSR_TIMEH:
       RISCV_ASSERT_RV32 (cpu, "CSR: %s", name);
+      ATTRIBUTE_FALLTHROUGH;
 
     /* All the rest are immutable.  */
     default: