drm/msm/dpu: enable compression bit in cfg2 for DSC

Enable compression bit in cfg2 register for DSC in the DSI case
per hardware version.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/596231/
Link: https://lore.kernel.org/r/20240530-msm-drm-dsc-dsi-video-upstream-4-v6-3-2ab1d334c657@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 041e79410c627f3347a513808d42a722885842d0..ba8878d21cf0e1945a393cca806cb64f03b16640 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -307,7 +307,8 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
 
        spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
        phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
-                       &timing_params, fmt);
+                       &timing_params, fmt,
+                       phys_enc->dpu_kms->catalog->mdss_ver);
        phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
 
        /* setup which pp blk will connect to this intf */

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index f972214232492d354c3a56cdfd1fcd7c527680a2..fa6debda0774e6bc3e16819f3094228743690730 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -98,7 +98,8 @@
 
 static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf,
                const struct dpu_hw_intf_timing_params *p,
-               const struct msm_format *fmt)
+               const struct msm_format *fmt,
+               const struct dpu_mdss_version *mdss_ver)
 {
        struct dpu_hw_blk_reg_map *c = &intf->hw;
        u32 hsync_period, vsync_period;
@@ -177,6 +178,11 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf,
        if (p->wide_bus_en && !dp_intf)
                data_width = p->width >> 1;
 
+       /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */
+       if (p->compression_en && !dp_intf &&
+           mdss_ver->core_major_ver >= 7)
+               intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
+
        hsync_data_start_x = hsync_start_x;
        hsync_data_end_x =  hsync_start_x + data_width - 1;
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index f9015c67a57445978d64f0f9f8dd23925707b3e6..ef947bf77693b973b065f861b0ac9418e875c943 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -81,7 +81,8 @@ struct dpu_hw_intf_cmd_mode_cfg {
 struct dpu_hw_intf_ops {
        void (*setup_timing_gen)(struct dpu_hw_intf *intf,
                        const struct dpu_hw_intf_timing_params *p,
-                       const struct msm_format *fmt);
+                       const struct msm_format *fmt,
+                       const struct dpu_mdss_version *mdss_ver);
 
        void (*setup_prg_fetch)(struct dpu_hw_intf *intf,
                        const struct dpu_hw_intf_prog_fetch *fetch);