--- /dev/null
+From f338bb9f0179cb959977b74e8331b312264d720b Mon Sep 17 00:00:00 2001
+From: George Cherian <george.cherian@marvell.com>
+Date: Mon, 11 Nov 2019 02:43:03 +0000
+Subject: PCI: Apply Cavium ACS quirk to ThunderX2 and ThunderX3
+
+From: George Cherian <george.cherian@marvell.com>
+
+commit f338bb9f0179cb959977b74e8331b312264d720b upstream.
+
+Enhance the ACS quirk for Cavium Processors. Add the root port vendor IDs
+for ThunderX2 and ThunderX3 series of processors.
+
+[bhelgaas: add Fixes: and stable tag]
+Fixes: f2ddaf8dfd4a ("PCI: Apply Cavium ThunderX ACS quirk to more Root Ports")
+Link: https://lore.kernel.org/r/20191111024243.GA11408@dc5-eodlnx05.marvell.com
+Signed-off-by: George Cherian <george.cherian@marvell.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Robert Richter <rrichter@marvell.com>
+Cc: stable@vger.kernel.org # v4.12+
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/quirks.c | 20 +++++++++++++-------
+ 1 file changed, 13 insertions(+), 7 deletions(-)
+
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -4252,15 +4252,21 @@ static int pci_quirk_amd_sb_acs(struct p
+
+ static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
+ {
++ if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
++ return false;
++
++ switch (dev->device) {
+ /*
+- * Effectively selects all downstream ports for whole ThunderX 1
+- * family by 0xf800 mask (which represents 8 SoCs), while the lower
+- * bits of device ID are used to indicate which subdevice is used
+- * within the SoC.
++ * Effectively selects all downstream ports for whole ThunderX1
++ * (which represents 8 SoCs).
+ */
+- return (pci_is_pcie(dev) &&
+- (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&
+- ((dev->device & 0xf800) == 0xa000));
++ case 0xa000 ... 0xa7ff: /* ThunderX1 */
++ case 0xaf84: /* ThunderX2 */
++ case 0xb884: /* ThunderX3 */
++ return true;
++ default:
++ return false;
++ }
+ }
+
+ static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
--- /dev/null
+From d8558ac8c93d429d65d7490b512a3a67e559d0d4 Mon Sep 17 00:00:00 2001
+From: Steffen Liebergeld <steffen.liebergeld@kernkonzept.com>
+Date: Wed, 18 Sep 2019 15:16:52 +0200
+Subject: PCI: Fix Intel ACS quirk UPDCR register address
+
+From: Steffen Liebergeld <steffen.liebergeld@kernkonzept.com>
+
+commit d8558ac8c93d429d65d7490b512a3a67e559d0d4 upstream.
+
+According to documentation [0] the correct offset for the Upstream Peer
+Decode Configuration Register (UPDCR) is 0x1014. It was previously defined
+as 0x1114.
+
+d99321b63b1f ("PCI: Enable quirks for PCIe ACS on Intel PCH root ports")
+intended to enforce isolation between PCI devices allowing them to be put
+into separate IOMMU groups. Due to the wrong register offset the intended
+isolation was not fully enforced. This is fixed with this patch.
+
+Please note that I did not test this patch because I have no hardware that
+implements this register.
+
+[0] https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/4th-gen-core-family-mobile-i-o-datasheet.pdf (page 325)
+Fixes: d99321b63b1f ("PCI: Enable quirks for PCIe ACS on Intel PCH root ports")
+Link: https://lore.kernel.org/r/7a3505df-79ba-8a28-464c-88b83eefffa6@kernkonzept.com
+Signed-off-by: Steffen Liebergeld <steffen.liebergeld@kernkonzept.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Andrew Murray <andrew.murray@arm.com>
+Acked-by: Ashok Raj <ashok.raj@intel.com>
+Cc: stable@vger.kernel.org # v3.15+
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/quirks.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -4600,7 +4600,7 @@ int pci_dev_specific_acs_enabled(struct
+ #define INTEL_BSPR_REG_BPPD (1 << 9)
+
+ /* Upstream Peer Decode Configuration Register */
+-#define INTEL_UPDCR_REG 0x1114
++#define INTEL_UPDCR_REG 0x1014
+ /* 5:0 Peer Decode Enable bits */
+ #define INTEL_UPDCR_REG_MASK 0x3f
+
--- /dev/null
+From e045fa29e89383c717e308609edd19d2fd29e1be Mon Sep 17 00:00:00 2001
+From: Jian-Hong Pan <jian-hong@endlessm.com>
+Date: Tue, 8 Oct 2019 11:42:39 +0800
+Subject: PCI/MSI: Fix incorrect MSI-X masking on resume
+
+From: Jian-Hong Pan <jian-hong@endlessm.com>
+
+commit e045fa29e89383c717e308609edd19d2fd29e1be upstream.
+
+When a driver enables MSI-X, msix_program_entries() reads the MSI-X Vector
+Control register for each vector and saves it in desc->masked. Each
+register is 32 bits and bit 0 is the actual Mask bit.
+
+When we restored these registers during resume, we previously set the Mask
+bit if *any* bit in desc->masked was set instead of when the Mask bit
+itself was set:
+
+ pci_restore_state
+ pci_restore_msi_state
+ __pci_restore_msix_state
+ for_each_pci_msi_entry
+ msix_mask_irq(entry, entry->masked) <-- entire u32 word
+ __pci_msix_desc_mask_irq(desc, flag)
+ mask_bits = desc->masked & ~PCI_MSIX_ENTRY_CTRL_MASKBIT
+ if (flag) <-- testing entire u32, not just bit 0
+ mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT
+ writel(mask_bits, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL)
+
+This means that after resume, MSI-X vectors were masked when they shouldn't
+be, which leads to timeouts like this:
+
+ nvme nvme0: I/O 978 QID 3 timeout, completion polled
+
+On resume, set the Mask bit only when the saved Mask bit from suspend was
+set.
+
+This should remove the need for 19ea025e1d28 ("nvme: Add quirk for Kingston
+NVME SSD running FW E8FK11.T").
+
+[bhelgaas: commit log, move fix to __pci_msix_desc_mask_irq()]
+Link: https://bugzilla.kernel.org/show_bug.cgi?id=204887
+Link: https://lore.kernel.org/r/20191008034238.2503-1-jian-hong@endlessm.com
+Fixes: f2440d9acbe8 ("PCI MSI: Refactor interrupt masking code")
+Signed-off-by: Jian-Hong Pan <jian-hong@endlessm.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/msi.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pci/msi.c
++++ b/drivers/pci/msi.c
+@@ -211,7 +211,7 @@ u32 __pci_msix_desc_mask_irq(struct msi_
+ return 0;
+
+ mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
+- if (flag)
++ if (flag & PCI_MSIX_ENTRY_CTRL_MASKBIT)
+ mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
+ writel(mask_bits, pci_msix_desc_addr(desc) + PCI_MSIX_ENTRY_VECTOR_CTRL);
+
--- /dev/null
+From f2c33ccacb2d4bbeae2a255a7ca0cbfd03017b7c Mon Sep 17 00:00:00 2001
+From: Dexuan Cui <decui@microsoft.com>
+Date: Wed, 14 Aug 2019 01:06:55 +0000
+Subject: PCI/PM: Always return devices to D0 when thawing
+
+From: Dexuan Cui <decui@microsoft.com>
+
+commit f2c33ccacb2d4bbeae2a255a7ca0cbfd03017b7c upstream.
+
+pci_pm_thaw_noirq() is supposed to return the device to D0 and restore its
+configuration registers, but previously it only did that for devices whose
+drivers implemented the new power management ops.
+
+Hibernation, e.g., via "echo disk > /sys/power/state", involves freezing
+devices, creating a hibernation image, thawing devices, writing the image,
+and powering off. The fact that thawing did not return devices with legacy
+power management to D0 caused errors, e.g., in this path:
+
+ pci_pm_thaw_noirq
+ if (pci_has_legacy_pm_support(pci_dev)) # true for Mellanox VF driver
+ return pci_legacy_resume_early(dev) # ... legacy PM skips the rest
+ pci_set_power_state(pci_dev, PCI_D0)
+ pci_restore_state(pci_dev)
+ pci_pm_thaw
+ if (pci_has_legacy_pm_support(pci_dev))
+ pci_legacy_resume
+ drv->resume
+ mlx4_resume
+ ...
+ pci_enable_msix_range
+ ...
+ if (dev->current_state != PCI_D0) # <---
+ return -EINVAL;
+
+which caused these warnings:
+
+ mlx4_core a6d1:00:02.0: INTx is not supported in multi-function mode, aborting
+ PM: dpm_run_callback(): pci_pm_thaw+0x0/0xd7 returns -95
+ PM: Device a6d1:00:02.0 failed to thaw: error -95
+
+Return devices to D0 and restore config registers for all devices, not just
+those whose drivers support new power management.
+
+[bhelgaas: also call pci_restore_state() before pci_legacy_resume_early(),
+update comment, add stable tag, commit log]
+Link: https://lore.kernel.org/r/KU1P153MB016637CAEAD346F0AA8E3801BFAD0@KU1P153MB0166.APCP153.PROD.OUTLOOK.COM
+Signed-off-by: Dexuan Cui <decui@microsoft.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Cc: stable@vger.kernel.org # v4.13+
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/pci-driver.c | 17 +++++++++++------
+ 1 file changed, 11 insertions(+), 6 deletions(-)
+
+--- a/drivers/pci/pci-driver.c
++++ b/drivers/pci/pci-driver.c
+@@ -967,17 +967,22 @@ static int pci_pm_thaw_noirq(struct devi
+ return error;
+ }
+
+- if (pci_has_legacy_pm_support(pci_dev))
+- return pci_legacy_resume_early(dev);
+-
+ /*
+- * pci_restore_state() requires the device to be in D0 (because of MSI
+- * restoration among other things), so force it into D0 in case the
+- * driver's "freeze" callbacks put it into a low-power state directly.
++ * Both the legacy ->resume_early() and the new pm->thaw_noirq()
++ * callbacks assume the device has been returned to D0 and its
++ * config state has been restored.
++ *
++ * In addition, pci_restore_state() restores MSI-X state in MMIO
++ * space, which requires the device to be in D0, so return it to D0
++ * in case the driver's "freeze" callbacks put it into a low-power
++ * state.
+ */
+ pci_set_power_state(pci_dev, PCI_D0);
+ pci_restore_state(pci_dev);
+
++ if (pci_has_legacy_pm_support(pci_dev))
++ return pci_legacy_resume_early(dev);
++
+ if (drv && drv->pm && drv->pm->thaw_noirq)
+ error = drv->pm->thaw_noirq(dev);
+
--- /dev/null
+From 6acdf7e19b37cb3a9258603d0eab315079c19c5e Mon Sep 17 00:00:00 2001
+From: Logan Gunthorpe <logang@deltatee.com>
+Date: Tue, 10 Sep 2019 13:58:33 -0600
+Subject: PCI/switchtec: Read all 64 bits of part_event_bitmap
+
+From: Logan Gunthorpe <logang@deltatee.com>
+
+commit 6acdf7e19b37cb3a9258603d0eab315079c19c5e upstream.
+
+The part_event_bitmap register is 64 bits wide, so read it with ioread64()
+instead of the 32-bit ioread32().
+
+Fixes: 52eabba5bcdb ("switchtec: Add IOCTLs to the Switchtec driver")
+Link: https://lore.kernel.org/r/20190910195833.3891-1-logang@deltatee.com
+Reported-by: Doug Meyer <dmeyer@gigaio.com>
+Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Cc: stable@vger.kernel.org # v4.12+
+Cc: Kelvin Cao <Kelvin.Cao@microchip.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/switch/switchtec.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pci/switch/switchtec.c
++++ b/drivers/pci/switch/switchtec.c
+@@ -898,7 +898,7 @@ static int ioctl_event_summary(struct sw
+ u32 reg;
+
+ s.global = ioread32(&stdev->mmio_sw_event->global_summary);
+- s.part_bitmap = ioread32(&stdev->mmio_sw_event->part_event_bitmap);
++ s.part_bitmap = ioread64(&stdev->mmio_sw_event->part_event_bitmap);
+ s.local_part = ioread32(&stdev->mmio_part_cfg->part_event_summary);
+
+ for (i = 0; i < stdev->partition_count; i++) {
inet-protect-against-too-small-mtu-values.patch
nvme-host-core-fix-precedence-of-ternary-operator.patch
revert-regulator-defer-init-completion-for-a-while-after-late_initcall.patch
+pci-switchtec-read-all-64-bits-of-part_event_bitmap.patch
+pci-pm-always-return-devices-to-d0-when-thawing.patch
+pci-fix-intel-acs-quirk-updcr-register-address.patch
+pci-msi-fix-incorrect-msi-x-masking-on-resume.patch
+pci-apply-cavium-acs-quirk-to-thunderx2-and-thunderx3.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
