drm/i915/cdclk: Extract hsw_ips_min_cdclk()

Pull the whole BDW IPS min CDCLK stuff into the IPS code
so that all the details around IPS are contained in once
place.

Note that while
- min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
vs.
+ min_cdclk = max(DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95), min_cdclk)
may look different, they are in fact the same because
min_cdclk==crtc_state->pixel_rate at this point in
intel_crtc_compute_min_cdclk() on BDW.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241029215217.3697-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index 34c5d28fc8668be1c2842ce3dae47c335074ce4c..405116100d678451f307fc93cb053439017f9c76 100644 (file)
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -188,7 +188,7 @@ bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
        return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
 }
 
-bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
+static bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
 {
        struct intel_display *display = to_intel_display(crtc_state);
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -218,6 +218,20 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
        return true;
 }
 
+int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)
+{
+       struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+
+       if (!IS_BROADWELL(i915))
+               return 0;
+
+       if (!hsw_crtc_state_ips_capable(crtc_state))
+               return 0;
+
+       /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
+       return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95);
+}
+
 int hsw_ips_compute_config(struct intel_atomic_state *state,
                           struct intel_crtc *crtc)
 {

diff --git a/drivers/gpu/drm/i915/display/hsw_ips.h b/drivers/gpu/drm/i915/display/hsw_ips.h
index 35364228e1c1ff0fba37e9cb25e3531f8d7f8ff3..7af12f88a8ce5fae58d3713adfb25f36bcb52921 100644 (file)
--- a/drivers/gpu/drm/i915/display/hsw_ips.h
+++ b/drivers/gpu/drm/i915/display/hsw_ips.h
@@ -19,7 +19,7 @@ bool hsw_ips_pre_update(struct intel_atomic_state *state,
 void hsw_ips_post_update(struct intel_atomic_state *state,
                         struct intel_crtc *crtc);
 bool hsw_crtc_supports_ips(struct intel_crtc *crtc);
-bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
+int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state);
 int hsw_ips_compute_config(struct intel_atomic_state *state,
                           struct intel_crtc *crtc);
 void hsw_ips_get_config(struct intel_crtc_state *crtc_state);
@@ -42,9 +42,9 @@ static inline bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
 {
        return false;
 }
-static inline bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
+static inline int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)
 {
-       return false;
+       return 0;
 }
 static inline int hsw_ips_compute_config(struct intel_atomic_state *state,
                                         struct intel_crtc *crtc)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index e1c0d9dca2fd41e3fff669ccb9616afac4bf95ce..808bebffa1e446f16ba798f6d37f234223c90921 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2857,10 +2857,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
                return 0;
 
        min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
-
-       /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
-       if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
-               min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
+       min_cdclk = max(hsw_ips_min_cdclk(crtc_state), min_cdclk);
 
        /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
         * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else