cond.md (stzx_16): Use register_operand for operand 0.

gcc/
	* config/m32c/cond.md (stzx_16): Use register_operand for operand 0.
	(stzx_24_<mode>): Likewise mra_operand.

From-SVN: r205247

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8f4bdca41a46b8feec8ad4b55485b0294c74f581..b122c3f52c9dd16c9f035ca5dd5013b6c2945570 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2013-11-22  Richard Sandiford  <rdsandiford@googlemail.com>
+
+       * config/m32c/cond.md (stzx_16): Use register_operand for operand 0.
+       (stzx_24_<mode>): Likewise mra_operand.
+
 2013-11-22  Jeff Law  <law@redhat.com>
 
        * tree-ssa-threadupdate.c: Include tree-cfg.h and tree-pass.h

diff --git a/gcc/config/m32c/cond.md b/gcc/config/m32c/cond.md
index 928d7efb289961f6f8ce0cc977a497f9dc436622..1fae01d9836f1beff828e0632e5d444dc4ceab32 100644 (file)
--- a/gcc/config/m32c/cond.md
+++ b/gcc/config/m32c/cond.md
@@ -75,7 +75,7 @@
 )
 
 (define_insn "stzx_16"
-  [(set (match_operand:QI 0 "mrai_operand" "=R0w,R0w,R0w")
+  [(set (match_operand:QI 0 "register_operand" "=R0w,R0w,R0w")
        (if_then_else:QI (eq (reg:CC FLG_REGNO) (const_int 0))
                         (match_operand:QI 1 "const_int_operand" "i,i,0")
                         (match_operand:QI 2 "const_int_operand" "i,0,i")))]
@@ -88,7 +88,7 @@
 )
 
 (define_insn "stzx_24_<mode>"
-  [(set (match_operand:QHI 0 "mrai_operand" "=RraSd,RraSd,RraSd")
+  [(set (match_operand:QHI 0 "mra_operand" "=RraSd,RraSd,RraSd")
        (if_then_else:QHI (eq (reg:CC FLG_REGNO) (const_int 0))
                         (match_operand:QHI 1 "const_int_operand" "i,i,0")
                         (match_operand:QHI 2 "const_int_operand" "i,0,i")))]