drm/amd/display: Various DML2 fixes for FAMS2

- Ensure SubVP stream settings match ODM policy
- Fix MALL size calculations when DCC is enabled
- Fail if any stream fails DRR policy check

Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
index 8c9e95b25eb30055b1b0cd055c64ecfcb21e5f4c..4e12810308a42d4ca02b4ffabd39c8ff94993e0a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c
@@ -85,8 +85,8 @@ void find_pipe_regs_idx(const struct dml2_context *dml_ctx,
 int dml21_find_dc_pipes_for_plane(const struct dc *in_dc,
                struct dc_state *context,
                struct dml2_context *dml_ctx,
-               struct pipe_ctx **dc_main_pipes,
-               struct pipe_ctx **dc_phantom_pipes,
+               struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],
+               struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],
                int dml_plane_idx)
 {
        unsigned int dml_stream_index;
@@ -100,6 +100,9 @@ int dml21_find_dc_pipes_for_plane(const struct dc *in_dc,
        struct dc_plane_state *dc_phantom_plane;
        int num_pipes = 0;
 
+       memset(dc_main_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__);
+       memset(dc_phantom_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__);
+
        dml_stream_index = dml_ctx->v21.mode_programming.programming->plane_programming[dml_plane_idx].plane_descriptor->stream_index;
        main_stream_id = dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_stream_index];
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.h
index 82080397a50ef86047b610b1c6d710538f6b28e5..d5153fbac921ff223c416e16ab39024e6e585e0b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.h
@@ -33,8 +33,8 @@ void find_pipe_regs_idx(const struct dml2_context *dml_ctx,
 int dml21_find_dc_pipes_for_plane(const struct dc *in_dc,
                struct dc_state *context,
                struct dml2_context *dml_ctx,
-               struct pipe_ctx **dc_main_pipes,
-               struct pipe_ctx **dc_phantom_pipes,
+               struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],
+               struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],
                int dml_plane_idx);
 void dml21_program_dc_pipe(struct dml2_context *dml_ctx,
                struct dc_state *context,

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
index 08f001cb61c54b49d4a5021bccc4649776d07442..c4542c3dded9807f817792c5967679525314e54e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
@@ -156,7 +156,7 @@ static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_sta
                for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {
                        dml21_program_dc_pipe(in_ctx, context, dc_main_pipes[dc_pipe_index], pln_prog, stream_prog);
 
-                       if (pln_prog->phantom_plane.valid) {
+                       if (pln_prog->phantom_plane.valid && dc_phantom_pipes[dc_pipe_index]) {
                                dml21_program_dc_pipe(in_ctx, context, dc_phantom_pipes[dc_pipe_index], pln_prog, stream_prog);
                        }
                }
@@ -325,7 +325,7 @@ void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context
                }
 
                /* get config for each phantom pipe */
-               if (pln_prog->phantom_plane.valid) {
+               if (pln_prog->phantom_plane.valid && dc_phantom_pipes[0]) {
                        mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_phantom_prog_idx];
                        memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor));
                        mcache_config->plane_descriptor = pln_prog->plane_descriptor;
@@ -368,7 +368,7 @@ void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context
                }
 
                /* get config for each phantom pipe */
-               if (pln_prog->phantom_plane.valid) {
+               if (pln_prog->phantom_plane.valid && dc_phantom_pipes[0]) {
                        for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {
                                ASSERT(dc_phantom_pipes[dc_pipe_index]);
                                if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index]) {

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
index 4b8691c4352398a9d1f2fdbfb6d66c88271a9fa2..04edcde423a9781419ee15939389494f8f7fb986 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
@@ -235,7 +235,6 @@ static void create_phantom_stream_from_main_stream(struct dml2_stream_parameters
        phantom->timing.v_active = meta->v_active;
        phantom->timing.v_front_porch = meta->v_front_porch;
        phantom->timing.vblank_nom = phantom->timing.v_total - phantom->timing.v_active;
-       phantom->timing.dsc.enable = dml2_dsc_disable;
        phantom->timing.drr_config.enabled = false;
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
index e7e6751f4477789b0fd4f87395b17913b4164e58..85eee5ab54433d1e182f7af15850fdc11471a0be 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
@@ -4501,24 +4501,6 @@ static void CalculateSurfaceSizeInMall(
                                                math_floor2((double)composition->viewport.plane1.y_start + composition->viewport.plane1.height + ReadBlockHeightC[k] - 1, ReadBlockHeightC[k]) -
                                                math_floor2(composition->viewport.plane1.y_start, ReadBlockHeightC[k])) * BytesPerPixelC[k]);
                        }
-                       if (surface->dcc.enable) {
-                               SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] +
-                                       math_min2(math_ceil2(surface->plane0.width, 8 * Read256BytesBlockWidthY[k]),
-                                               math_floor2(composition->viewport.plane0.x_start + composition->viewport.plane0.width + 8 * Read256BytesBlockWidthY[k] - 1, 8 * Read256BytesBlockWidthY[k]) -
-                                               math_floor2(composition->viewport.plane0.x_start, 8 * Read256BytesBlockWidthY[k])) *
-                                       math_min2(math_ceil2(surface->plane0.height, 8 * Read256BytesBlockHeightY[k]),
-                                               math_floor2(composition->viewport.plane0.y_start + composition->viewport.plane0.height + 8 * Read256BytesBlockHeightY[k] - 1, 8 * Read256BytesBlockHeightY[k]) -
-                                               math_floor2(composition->viewport.plane0.y_start, 8 * Read256BytesBlockHeightY[k])) * BytesPerPixelY[k] / 256) + (64 * 1024);
-                               if (Read256BytesBlockWidthC[k] > 0) {
-                                       SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] +
-                                               math_min2(math_ceil2(surface->plane1.width, 8 * Read256BytesBlockWidthC[k]),
-                                                       math_floor2(composition->viewport.plane1.y_start + composition->viewport.plane1.width + 8 * Read256BytesBlockWidthC[k] - 1, 8 * Read256BytesBlockWidthC[k]) -
-                                                       math_floor2(composition->viewport.plane1.y_start, 8 * Read256BytesBlockWidthC[k])) *
-                                               math_min2(math_ceil2(surface->plane1.height, 8 * Read256BytesBlockHeightC[k]),
-                                                       math_floor2(composition->viewport.plane1.y_start + composition->viewport.plane1.height + 8 * Read256BytesBlockHeightC[k] - 1, 8 * Read256BytesBlockHeightC[k]) -
-                                                       math_floor2(composition->viewport.plane1.y_start, 8 * Read256BytesBlockHeightC[k])) * BytesPerPixelC[k] / 256);
-                               }
-                       }
                } else {
                        SurfaceSizeInMALL[k] = (unsigned int)(math_ceil2(math_min2(surface->plane0.width, composition->viewport.plane0.width + ReadBlockWidthY[k] - 1), ReadBlockWidthY[k]) *
                                math_ceil2(math_min2(surface->plane0.height, composition->viewport.plane0.height + ReadBlockHeightY[k] - 1), ReadBlockHeightY[k]) * BytesPerPixelY[k]);
@@ -4527,17 +4509,6 @@ static void CalculateSurfaceSizeInMall(
                                        math_ceil2(math_min2(surface->plane1.width, composition->viewport.plane1.width + ReadBlockWidthC[k] - 1), ReadBlockWidthC[k]) *
                                        math_ceil2(math_min2(surface->plane1.height, composition->viewport.plane1.height + ReadBlockHeightC[k] - 1), ReadBlockHeightC[k]) * BytesPerPixelC[k]);
                        }
-                       if (surface->dcc.enable) {
-                               SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] +
-                                       math_ceil2(math_min2(surface->plane0.width, composition->viewport.plane0.width + 8 * Read256BytesBlockWidthY[k] - 1), 8 * Read256BytesBlockWidthY[k]) *
-                                       math_ceil2(math_min2(surface->plane0.height, composition->viewport.plane0.height + 8 * Read256BytesBlockHeightY[k] - 1), 8 * Read256BytesBlockHeightY[k]) * BytesPerPixelY[k] / 256) + (64 * 1024);
-
-                               if (Read256BytesBlockWidthC[k] > 0) {
-                                       SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] +
-                                               math_ceil2(math_min2(surface->plane1.width, composition->viewport.plane1.width + 8 * Read256BytesBlockWidthC[k] - 1), 8 * Read256BytesBlockWidthC[k]) *
-                                               math_ceil2(math_min2(surface->plane1.height, composition->viewport.plane1.height + 8 * Read256BytesBlockHeightC[k] - 1), 8 * Read256BytesBlockHeightC[k]) * BytesPerPixelC[k] / 256);
-                               }
-                       }
                }
        }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
index 85c64dcefa826fdd5994cc4e008a7dfdffe54407..2e8c836bc63235581b0929d90ce19dd0367e2213 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
@@ -1361,7 +1361,7 @@ static bool validate_pstate_support_strategy_cofunctionality(struct dml2_pmo_ins
                        break;
                }
 
-               strategy_matches_drr_requirements =
+               strategy_matches_drr_requirements &=
                                stream_matches_drr_policy(pmo, display_cfg, per_stream_pstate_strategy[stream_index], stream_index);
 
                if (per_stream_pstate_strategy[stream_index] == dml2_pmo_pstate_strategy_fw_svp ||