5.18-stable patches

added patches:
	arm64-dts-imx8mm-beacon-enable-rts-cts-on-uart3.patch
	arm64-dts-imx8mn-beacon-enable-rts-cts-on-uart3.patch

diff --git a/queue-5.18/arm64-dts-imx8mm-beacon-enable-rts-cts-on-uart3.patch b/queue-5.18/arm64-dts-imx8mm-beacon-enable-rts-cts-on-uart3.patch
new file mode 100644 (file)
index 0000000..b685844
--- /dev/null
+++ b/queue-5.18/arm64-dts-imx8mm-beacon-enable-rts-cts-on-uart3.patch
@@ -0,0 +1,39 @@
+From 4ce01ce36d77137cf60776b320babed89de6bd4c Mon Sep 17 00:00:00 2001
+From: Adam Ford <aford173@gmail.com>
+Date: Tue, 26 Apr 2022 15:51:43 -0500
+Subject: arm64: dts: imx8mm-beacon: Enable RTS-CTS on UART3
+
+From: Adam Ford <aford173@gmail.com>
+
+commit 4ce01ce36d77137cf60776b320babed89de6bd4c upstream.
+
+There is a header for a DB9 serial port, but any attempts to use
+hardware handshaking fail.  Enable RTS and CTS pin muxing and enable
+handshaking in the uart node.
+
+Signed-off-by: Adam Ford <aford173@gmail.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi |    3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
++++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
+@@ -278,6 +278,7 @@
+       pinctrl-0 = <&pinctrl_uart3>;
+       assigned-clocks = <&clk IMX8MM_CLK_UART3>;
+       assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
++      uart-has-rtscts;
+       status = "okay";
+ };
+ 
+@@ -386,6 +387,8 @@
+               fsl,pins = <
+                       MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX   0x40
+                       MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX   0x40
++                      MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B        0x40
++                      MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40
+               >;
+       };
+ 

diff --git a/queue-5.18/arm64-dts-imx8mn-beacon-enable-rts-cts-on-uart3.patch b/queue-5.18/arm64-dts-imx8mn-beacon-enable-rts-cts-on-uart3.patch
new file mode 100644 (file)
index 0000000..6f4473e
--- /dev/null
+++ b/queue-5.18/arm64-dts-imx8mn-beacon-enable-rts-cts-on-uart3.patch
@@ -0,0 +1,39 @@
+From 5446ff1a67160ad92d9aae9530846aa54750be36 Mon Sep 17 00:00:00 2001
+From: Adam Ford <aford173@gmail.com>
+Date: Tue, 26 Apr 2022 15:51:44 -0500
+Subject: arm64: dts: imx8mn-beacon: Enable RTS-CTS on UART3
+
+From: Adam Ford <aford173@gmail.com>
+
+commit 5446ff1a67160ad92d9aae9530846aa54750be36 upstream.
+
+There is a header for a DB9 serial port, but any attempts to use
+hardware handshaking fail.  Enable RTS and CTS pin muxing and enable
+handshaking in the uart node.
+
+Signed-off-by: Adam Ford <aford173@gmail.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi |    3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi
++++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi
+@@ -175,6 +175,7 @@
+       pinctrl-0 = <&pinctrl_uart3>;
+       assigned-clocks = <&clk IMX8MN_CLK_UART3>;
+       assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
++      uart-has-rtscts;
+       status = "okay";
+ };
+ 
+@@ -258,6 +259,8 @@
+               fsl,pins = <
+                       MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX   0x40
+                       MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX   0x40
++                      MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B        0x40
++                      MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40
+               >;
+       };
+ 

diff --git a/queue-5.18/series b/queue-5.18/series
index 30c249d47ae58de79625db0ec842df7459a05e4a..47a249273e34dfa095c053903f11137fcdcbd3ae 100644 (file)
--- a/queue-5.18/series
+++ b/queue-5.18/series
@@ -1 +1,3 @@
 revert-drm-amd-display-fix-dcn3-b0-dp-alt-mapping.patch
+arm64-dts-imx8mm-beacon-enable-rts-cts-on-uart3.patch
+arm64-dts-imx8mn-beacon-enable-rts-cts-on-uart3.patch