--- /dev/null
+From 86be89939d11a84800f66e2a283b915b704bf33d Mon Sep 17 00:00:00 2001
+From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Date: Tue, 16 Jan 2018 11:52:59 +0000
+Subject: alpha/PCI: Fix noname IRQ level detection
+
+From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+
+commit 86be89939d11a84800f66e2a283b915b704bf33d upstream.
+
+The conversion of the alpha architecture PCI host bridge legacy IRQ
+mapping/swizzling to the new PCI host bridge map/swizzle hooks carried
+out through:
+
+commit 0e4c2eeb758a ("alpha/PCI: Replace pci_fixup_irqs() call with
+host bridge IRQ mapping hooks")
+
+implies that IRQ for devices are now allocated through pci_assign_irq()
+function in pci_device_probe() that is called when a driver matching a
+device is found in order to probe the device through the device driver.
+
+Alpha noname platforms required IRQ level programming to be executed
+in sio_fixup_irq_levels(), that is called in noname_init_pci(), a
+platform hook called within a subsys_initcall.
+
+In noname_init_pci(), present IRQs are detected through
+sio_collect_irq_levels() that check the struct pci_dev->irq number
+to detect if an IRQ has been allocated for the device.
+
+By the time sio_collect_irq_levels() is called, some devices may still
+have not a matching driver loaded to match them (eg loadable module)
+therefore their IRQ allocation is still pending - which means that
+sio_collect_irq_levels() does not programme the correct IRQ level for
+those devices, causing their IRQ handling to be broken when the device
+driver is actually loaded and the device is probed.
+
+Fix the issue by adding code in the noname map_irq() function
+(noname_map_irq()) that, whilst mapping/swizzling the IRQ line, it also
+ensures that the correct IRQ level programming is executed at platform
+level, fixing the issue.
+
+Fixes: 0e4c2eeb758a ("alpha/PCI: Replace pci_fixup_irqs() call with
+host bridge IRQ mapping hooks")
+Reported-by: Mikulas Patocka <mpatocka@redhat.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Cc: Bjorn Helgaas <bhelgaas@google.com>
+Cc: Richard Henderson <rth@twiddle.net>
+Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
+Cc: Mikulas Patocka <mpatocka@redhat.com>
+Cc: Meelis Roos <mroos@linux.ee>
+Signed-off-by: Matt Turner <mattst88@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/alpha/kernel/sys_sio.c | 35 +++++++++++++++++++++++++++++------
+ 1 file changed, 29 insertions(+), 6 deletions(-)
+
+--- a/arch/alpha/kernel/sys_sio.c
++++ b/arch/alpha/kernel/sys_sio.c
+@@ -102,6 +102,15 @@ sio_pci_route(void)
+ alpha_mv.sys.sio.route_tab);
+ }
+
++static bool sio_pci_dev_irq_needs_level(const struct pci_dev *dev)
++{
++ if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
++ (dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
++ return false;
++
++ return true;
++}
++
+ static unsigned int __init
+ sio_collect_irq_levels(void)
+ {
+@@ -110,8 +119,7 @@ sio_collect_irq_levels(void)
+
+ /* Iterate through the devices, collecting IRQ levels. */
+ for_each_pci_dev(dev) {
+- if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
+- (dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
++ if (!sio_pci_dev_irq_needs_level(dev))
+ continue;
+
+ if (dev->irq)
+@@ -120,8 +128,7 @@ sio_collect_irq_levels(void)
+ return level_bits;
+ }
+
+-static void __init
+-sio_fixup_irq_levels(unsigned int level_bits)
++static void __sio_fixup_irq_levels(unsigned int level_bits, bool reset)
+ {
+ unsigned int old_level_bits;
+
+@@ -139,12 +146,21 @@ sio_fixup_irq_levels(unsigned int level_
+ */
+ old_level_bits = inb(0x4d0) | (inb(0x4d1) << 8);
+
+- level_bits |= (old_level_bits & 0x71ff);
++ if (reset)
++ old_level_bits &= 0x71ff;
++
++ level_bits |= old_level_bits;
+
+ outb((level_bits >> 0) & 0xff, 0x4d0);
+ outb((level_bits >> 8) & 0xff, 0x4d1);
+ }
+
++static inline void
++sio_fixup_irq_levels(unsigned int level_bits)
++{
++ __sio_fixup_irq_levels(level_bits, true);
++}
++
+ static inline int
+ noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+ {
+@@ -181,7 +197,14 @@ noname_map_irq(const struct pci_dev *dev
+ const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5;
+ int irq = COMMON_TABLE_LOOKUP, tmp;
+ tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
+- return irq >= 0 ? tmp : -1;
++
++ irq = irq >= 0 ? tmp : -1;
++
++ /* Fixup IRQ level if an actual IRQ mapping is detected */
++ if (sio_pci_dev_irq_needs_level(dev) && irq >= 0)
++ __sio_fixup_irq_levels(1 << irq, false);
++
++ return irq;
+ }
+
+ static inline int
--- /dev/null
+From acfb3b883f6d6a4b5d27ad7fdded11f6a09ae6dd Mon Sep 17 00:00:00 2001
+From: Marc Zyngier <marc.zyngier@arm.com>
+Date: Tue, 16 Jan 2018 10:23:47 +0000
+Subject: arm64: KVM: Fix SMCCC handling of unimplemented SMC/HVC calls
+
+From: Marc Zyngier <marc.zyngier@arm.com>
+
+commit acfb3b883f6d6a4b5d27ad7fdded11f6a09ae6dd upstream.
+
+KVM doesn't follow the SMCCC when it comes to unimplemented calls,
+and inject an UNDEF instead of returning an error. Since firmware
+calls are now used for security mitigation, they are becoming more
+common, and the undef is counter productive.
+
+Instead, let's follow the SMCCC which states that -1 must be returned
+to the caller when getting an unknown function number.
+
+Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
+Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm64/kvm/handle_exit.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/kvm/handle_exit.c
++++ b/arch/arm64/kvm/handle_exit.c
+@@ -44,7 +44,7 @@ static int handle_hvc(struct kvm_vcpu *v
+
+ ret = kvm_psci_call(vcpu);
+ if (ret < 0) {
+- kvm_inject_undefined(vcpu);
++ vcpu_set_reg(vcpu, 0, ~0UL);
+ return 1;
+ }
+
+@@ -53,7 +53,7 @@ static int handle_hvc(struct kvm_vcpu *v
+
+ static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
+ {
+- kvm_inject_undefined(vcpu);
++ vcpu_set_reg(vcpu, 0, ~0UL);
+ return 1;
+ }
+
--- /dev/null
+From c507babf10ead4d5c8cca704539b170752a8ac84 Mon Sep 17 00:00:00 2001
+From: Punit Agrawal <punit.agrawal@arm.com>
+Date: Thu, 4 Jan 2018 18:24:33 +0000
+Subject: KVM: arm/arm64: Check pagesize when allocating a hugepage at Stage 2
+
+From: Punit Agrawal <punit.agrawal@arm.com>
+
+commit c507babf10ead4d5c8cca704539b170752a8ac84 upstream.
+
+KVM only supports PMD hugepages at stage 2 but doesn't actually check
+that the provided hugepage memory pagesize is PMD_SIZE before populating
+stage 2 entries.
+
+In cases where the backing hugepage size is smaller than PMD_SIZE (such
+as when using contiguous hugepages), KVM can end up creating stage 2
+mappings that extend beyond the supplied memory.
+
+Fix this by checking for the pagesize of userspace vma before creating
+PMD hugepage at stage 2.
+
+Fixes: 66b3923a1a0f77a ("arm64: hugetlb: add support for PTE contiguous bit")
+Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
+Cc: Marc Zyngier <marc.zyngier@arm.com>
+Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
+Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ virt/kvm/arm/mmu.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/virt/kvm/arm/mmu.c
++++ b/virt/kvm/arm/mmu.c
+@@ -1310,7 +1310,7 @@ static int user_mem_abort(struct kvm_vcp
+ return -EFAULT;
+ }
+
+- if (is_vm_hugetlb_page(vma) && !logging_active) {
++ if (vma_kernel_pagesize(vma) == PMD_SIZE && !logging_active) {
+ hugetlb = true;
+ gfn = (fault_ipa & PMD_MASK) >> PAGE_SHIFT;
+ } else {
--- /dev/null
+From c04de7b1ad645b61c141df8ca903ba0cc03a57f7 Mon Sep 17 00:00:00 2001
+From: James Hogan <jhogan@kernel.org>
+Date: Tue, 5 Dec 2017 22:28:22 +0000
+Subject: MIPS: CM: Drop WARN_ON(vp != 0)
+
+From: James Hogan <jhogan@kernel.org>
+
+commit c04de7b1ad645b61c141df8ca903ba0cc03a57f7 upstream.
+
+Since commit 68923cdc2eb3 ("MIPS: CM: Add cluster & block args to
+mips_cm_lock_other()"), mips_smp_send_ipi_mask() has used
+mips_cm_lock_other_cpu() with each CPU number, rather than
+mips_cm_lock_other() with the first VPE in each core. Prior to r6,
+multicore multithreaded systems such as dual-core dual-thread
+interAptivs with CPU Idle enabled (e.g. MIPS Creator Ci40) results in
+mips_cm_lock_other() repeatedly hitting WARN_ON(vp != 0).
+
+There doesn't appear to be anything fundamentally wrong about passing a
+non-zero VP/VPE number, even if it is a core's region that is locked
+into the other region before r6, so remove that particular WARN_ON().
+
+Fixes: 68923cdc2eb3 ("MIPS: CM: Add cluster & block args to mips_cm_lock_other()")
+Signed-off-by: James Hogan <jhogan@kernel.org>
+Reviewed-by: Paul Burton <paul.burton@mips.com>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/17883/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/mips/kernel/mips-cm.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/arch/mips/kernel/mips-cm.c
++++ b/arch/mips/kernel/mips-cm.c
+@@ -292,7 +292,6 @@ void mips_cm_lock_other(unsigned int clu
+ *this_cpu_ptr(&cm_core_lock_flags));
+ } else {
+ WARN_ON(cluster != 0);
+- WARN_ON(vp != 0);
+ WARN_ON(block != CM_GCR_Cx_OTHER_BLOCK_LOCAL);
+
+ /*
dm-crypt-wipe-kernel-key-copy-after-iv-initialization.patch
dm-crypt-fix-error-return-code-in-crypt_ctr.patch
x86-use-__nostackprotect-for-sme_encrypt_kernel.patch
+alpha-pci-fix-noname-irq-level-detection.patch
+mips-cm-drop-warn_on-vp-0.patch
+kvm-arm-arm64-check-pagesize-when-allocating-a-hugepage-at-stage-2.patch
+arm64-kvm-fix-smccc-handling-of-unimplemented-smc-hvc-calls.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
